From a5538e3431d977ed9face116d3ad835db7b34ce2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Jul 2014 12:28:11 -0600 Subject: [PATCH] SAMA5D3/4: UPLL divisor to generate 48MHz for OHCI is different from the two families. No idea why. --- arch/arm/src/sama5/sam_clockconfig.c | 12 +++++------- arch/arm/src/sama5/sam_ohci.c | 2 +- configs/sama5d3-xplained/include/board_396mhz.h | 6 ++++++ configs/sama5d3-xplained/include/board_528mhz.h | 6 ++++++ configs/sama5d3-xplained/include/board_sdram.h | 6 ++++++ configs/sama5d3x-ek/include/board_396mhz.h | 6 ++++++ configs/sama5d3x-ek/include/board_528mhz.h | 6 ++++++ configs/sama5d3x-ek/include/board_sdram.h | 6 ++++++ configs/sama5d4-ek/include/board_396mhz.h | 1 + configs/sama5d4-ek/include/board_528mhz.h | 1 + configs/sama5d4-ek/include/board_sdram.h | 1 + 11 files changed, 45 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/sama5/sam_clockconfig.c b/arch/arm/src/sama5/sam_clockconfig.c index a561bb9a2f8..d34a07fa084 100644 --- a/arch/arm/src/sama5/sam_clockconfig.c +++ b/arch/arm/src/sama5/sam_clockconfig.c @@ -492,15 +492,13 @@ static inline void sam_usbclockconfig(void) * PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is * selected. * - * REVISIT: The divisor of 10 produces a rate that is too high. Division - * by 5, however, seems to work just fine. No idea why? + * REVISIT: The divisor of 10 produces a rate that is too high with + * SAMA5D3. A divisor of 5, however, seems to work just fine for the + * SAMA5D3. The SAMA5D4, on the other hand, needs the divisor of 10. + * No idea why? Let the board.h file decide which to use. */ -#if 1 /* REVISIT */ - regval |= PMC_USB_USBDIV(4); /* Division by 5 */ -#else - regval |= PMC_USB_USBDIV(9); /* Division by 10 */ -#endif + regval |= PMC_USB_USBDIV(BOARD_UPLL_OHCI_DIV-1); putreg32(regval, SAM_PMC_USB); #else /* BOARD_USE_UPLL */ diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index 84f9ac601d2..cdf040adcad 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -1880,7 +1880,7 @@ static void sam_wdh_bottomhalf(void) /* Invalidate D-cache to force re-reading of the Done Head */ -# if 0 /* Apparently insufficient */ +#if 0 /* Apparently insufficient */ cp15_invalidate_dcache((uintptr_t)&g_hcca.donehead, (uintptr_t)&g_hcca.donehead + sizeof(uint32_t)); #else diff --git a/configs/sama5d3-xplained/include/board_396mhz.h b/configs/sama5d3-xplained/include/board_396mhz.h index 7293956a50e..88369eb4942 100644 --- a/configs/sama5d3-xplained/include/board_396mhz.h +++ b/configs/sama5d3-xplained/include/board_396mhz.h @@ -162,6 +162,12 @@ # define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ + +/* REVISIT: The divisor of 10 produces a rate that is too high. Division + * by 5, however, seems to work just fine. No idea why? + */ + +# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */ #endif /* HSMCI clocking diff --git a/configs/sama5d3-xplained/include/board_528mhz.h b/configs/sama5d3-xplained/include/board_528mhz.h index dc857bee4b1..78be010cabd 100644 --- a/configs/sama5d3-xplained/include/board_528mhz.h +++ b/configs/sama5d3-xplained/include/board_528mhz.h @@ -161,6 +161,12 @@ # define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ + +/* REVISIT: The divisor of 10 produces a rate that is too high. Division + * by 5, however, seems to work just fine. No idea why? + */ + +# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */ #endif /* HSMCI clocking diff --git a/configs/sama5d3-xplained/include/board_sdram.h b/configs/sama5d3-xplained/include/board_sdram.h index 4f2e5f971f1..cd5a5b5dfce 100644 --- a/configs/sama5d3-xplained/include/board_sdram.h +++ b/configs/sama5d3-xplained/include/board_sdram.h @@ -100,6 +100,12 @@ # define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ + +/* REVISIT: The divisor of 10 produces a rate that is too high. Division + * by 5, however, seems to work just fine. No idea why? + */ + +# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */ #endif /* ADC Configuration diff --git a/configs/sama5d3x-ek/include/board_396mhz.h b/configs/sama5d3x-ek/include/board_396mhz.h index ef850fda8fa..3fbe75b17e2 100644 --- a/configs/sama5d3x-ek/include/board_396mhz.h +++ b/configs/sama5d3x-ek/include/board_396mhz.h @@ -162,6 +162,12 @@ # define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ + +/* REVISIT: The divisor of 10 produces a rate that is too high. Division + * by 5, however, seems to work just fine. No idea why? + */ + +# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */ #endif /* HSMCI clocking diff --git a/configs/sama5d3x-ek/include/board_528mhz.h b/configs/sama5d3x-ek/include/board_528mhz.h index 0b2744030d8..08a6fba26b2 100644 --- a/configs/sama5d3x-ek/include/board_528mhz.h +++ b/configs/sama5d3x-ek/include/board_528mhz.h @@ -160,6 +160,12 @@ # define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ + +/* REVISIT: The divisor of 10 produces a rate that is too high. Division + * by 5, however, seems to work just fine. No idea why? + */ + +# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */ #endif /* HSMCI clocking diff --git a/configs/sama5d3x-ek/include/board_sdram.h b/configs/sama5d3x-ek/include/board_sdram.h index 9e4b6046904..990673aaaed 100644 --- a/configs/sama5d3x-ek/include/board_sdram.h +++ b/configs/sama5d3x-ek/include/board_sdram.h @@ -100,6 +100,12 @@ # define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ + +/* REVISIT: The divisor of 10 produces a rate that is too high. Division + * by 5, however, seems to work just fine. No idea why? + */ + +# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */ #endif /* ADC Configuration diff --git a/configs/sama5d4-ek/include/board_396mhz.h b/configs/sama5d4-ek/include/board_396mhz.h index 11af935ed3a..34441910ffe 100644 --- a/configs/sama5d4-ek/include/board_396mhz.h +++ b/configs/sama5d4-ek/include/board_396mhz.h @@ -161,6 +161,7 @@ # define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ +# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */ #endif /* HSMCI clocking diff --git a/configs/sama5d4-ek/include/board_528mhz.h b/configs/sama5d4-ek/include/board_528mhz.h index aa6a336e85d..7b34f09b488 100644 --- a/configs/sama5d4-ek/include/board_528mhz.h +++ b/configs/sama5d4-ek/include/board_528mhz.h @@ -160,6 +160,7 @@ # define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ +# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */ #endif /* HSMCI clocking diff --git a/configs/sama5d4-ek/include/board_sdram.h b/configs/sama5d4-ek/include/board_sdram.h index 5b113d17eed..f86d2827dc7 100644 --- a/configs/sama5d4-ek/include/board_sdram.h +++ b/configs/sama5d4-ek/include/board_sdram.h @@ -101,6 +101,7 @@ # define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ +# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */ #endif /* ADC Configuration