diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_anadig.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_anadig.h index bf4bb09316e..6d963b65f32 100644 --- a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_anadig.h +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_anadig.h @@ -176,6 +176,14 @@ #define IMXRT_ANADIG_OSC_24M_CTRL (IMXRT_ANADIG_OSC_BASE + 0x3320) #define IMXRT_ANADIG_OSC_400M_CTRL1 (IMXRT_ANADIG_OSC_BASE + 0x3350) +#define ANADIG_OSC_24M_CTRL_BYPASS_EN (1u << 1) /* Use external clock on XTALI instead of crystal */ +#define ANADIG_OSC_24M_CTRL_LP_EN (1u << 2) /* 0: High Gain mode, 1: Low-Power mode */ +#define ANADIG_OSC_24M_CTRL_COMP_MODE (1u << 3) /* 0: single-ended (default), 1: differential (test) */ +#define ANADIG_OSC_24M_CTRL_OSC_EN (1u << 4) /* Enable the 24MHz XTALOSC */ +#define ANADIG_OSC_24M_CTRL_GATE (1u << 7) /* 1: output gated (default), 0: output not gated */ +#define ANADIG_OSC_24M_CTRL_STABLE (1u << 30) /* RO: 1 once the OSC stable time has been reached */ +#define ANADIG_OSC_24M_CTRL_CONTROL_MODE (1u << 31) /* 0: software mode (default), 1: GPC mode */ + /* PHY_LDO registers (IMXRT1180RM Ch. 41. Physical: 0x4448_4680). Each * has RW/SET/CLR/TOG aliases. */ diff --git a/arch/arm/src/imxrt/imxrt_clockconfig_ver3.c b/arch/arm/src/imxrt/imxrt_clockconfig_ver3.c index fdcc3de6087..9be4d39593d 100644 --- a/arch/arm/src/imxrt/imxrt_clockconfig_ver3.c +++ b/arch/arm/src/imxrt/imxrt_clockconfig_ver3.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -76,13 +77,6 @@ #define IMXRT_SYS_PLL3_PFD2_HZ (392727272u) /* frac = 22 */ #define IMXRT_SYS_PLL3_PFD3_HZ (392727272u) /* frac = 22 */ -/* ARM_PLL loop divider for 798 MHz with post_div = 2: - * - * Fout = 24 MHz * 133 / (2 * 2) = 798 MHz - */ - -#define ARM_PLL_DIV_SELECT (133) - /* Analog settling delays, expressed as NOP spins because no timer exists * this early. The M33 still runs from OSC_RC_400M/2 (200 MHz), so one * iteration is roughly 5 ns; both values are generously rounded up. @@ -231,14 +225,14 @@ static void imxrt_enable_pll_ldo(void) * ****************************************************************************/ -static void imxrt_init_arm_pll(void) +static void imxrt_init_arm_pll(const struct ccm_arm_pll *config) { uint32_t regval; imxrt_enable_pll_ldo(); - regval = ANADIG_PLL_ARM_DIV_SELECT(ARM_PLL_DIV_SELECT) | - ANADIG_PLL_ARM_POST_DIV_SEL(ANADIG_PLL_ARM_POST_DIV_2); + regval = ANADIG_PLL_ARM_DIV_SELECT(config->loop_div) | + ANADIG_PLL_ARM_POST_DIV_SEL(config->post_div); /* Power the PLL down before touching the dividers, keeping the output * gated so that nothing sees an intermediate frequency. @@ -267,6 +261,71 @@ static void imxrt_init_arm_pll(void) #endif /* CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33 */ +static void imxrt_enable_osc_24m(void) +{ + uint32_t reg; + + /* Check if the 24 MHz crystal oscillator not enabled, is gated + * or is not stable + */ + + reg = getreg32(IMXRT_ANADIG_OSC_24M_CTRL); + + if ((reg & (ANADIG_OSC_24M_CTRL_OSC_EN | + ANADIG_OSC_24M_CTRL_GATE | + ANADIG_OSC_24M_CTRL_STABLE)) != + (ANADIG_OSC_24M_CTRL_OSC_EN | + ANADIG_OSC_24M_CTRL_STABLE)) + { + /* It needs to be enabled */ + + reg |= ANADIG_OSC_24M_CTRL_OSC_EN; + putreg32(reg, IMXRT_ANADIG_OSC_24M_CTRL); + + while ((getreg32(IMXRT_ANADIG_OSC_24M_CTRL) & + ANADIG_OSC_24M_CTRL_STABLE) == 0); + + reg = getreg32(IMXRT_ANADIG_OSC_24M_CTRL); + reg &= ~ANADIG_OSC_24M_CTRL_GATE; + putreg32(reg, IMXRT_ANADIG_OSC_24M_CTRL); + } +} + +static void imxrt_enable_clock_source(int source) +{ + switch (source) + { + /* These sources are expected to be always on */ + + case OSC_RC_24M: + case OSC_RC_400M: + case ARM_PLL_OUT: + case SYS_PLL1_OUT: + case SYS_PLL1_DIV2: + case SYS_PLL1_DIV5: + case SYS_PLL2_OUT: + case SYS_PLL2_PFD0: + case SYS_PLL2_PFD1: + case SYS_PLL2_PFD2: + case SYS_PLL2_PFD3: + case SYS_PLL3_OUT: + case SYS_PLL3_DIV2: + case SYS_PLL3_PFD0: + case SYS_PLL3_PFD1: + case SYS_PLL3_PFD2: + case SYS_PLL3_PFD3: + break; + + case OSC_24M: + imxrt_enable_osc_24m(); + break; + + default: + _err("Enabling source %d is not implemented\n", source); + break; + } +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -310,7 +369,8 @@ int imxrt_ccm_configure_root_clock(int root, int src, uint32_t div) } regval = getreg32(IMXRT_CCM_CR_CTRL(root)); - newval = regval & ~(CCM_CR_CTRL_MUX_MASK | CCM_CR_CTRL_DIV_MASK); + newval = regval & ~(CCM_CR_CTRL_MUX_MASK | CCM_CR_CTRL_DIV_MASK | + CCM_CR_CTRL_OFF); newval |= CCM_CR_CTRL_MUX_SRCSEL(i) | CCM_CR_CTRL_DIV(div); /* Do not reconfigure a root that already has the requested settings. */ @@ -327,6 +387,41 @@ int imxrt_ccm_configure_root_clock(int root, int src, uint32_t div) return OK; } +/**************************************************************************** + * Name: imxrt_ccm_disable_root_clock + ****************************************************************************/ + +static int imxrt_ccm_disable_root_clock(int root) +{ + uint32_t auth; + uint32_t regval; + + if (root >= CCM_CR_COUNT) + { + return -EINVAL; + } + + auth = getreg32(IMXRT_CCM_CR_AUTH(root)); + + if ((auth & CCM_CR_AUTH_DOMAIN(BOARD_CCM_DOMAIN_ID)) == 0) + { + return -EINVAL; + } + + regval = getreg32(IMXRT_CCM_CR_CTRL(root)); + + if ((regval & CCM_CR_CTRL_OFF) != 0) + { + return OK; + } + + putreg32(regval | CCM_CR_CTRL_OFF, IMXRT_CCM_CR_CTRL(root)); + + while (getreg32(IMXRT_CCM_CR_STAT0(root)) & CCM_CR_STAT0_CHANGING); + + return OK; +} + /**************************************************************************** * Name: imxrt_ccm_gate_on ****************************************************************************/ @@ -494,13 +589,14 @@ int imxrt_get_rootclock(uint32_t clkroot, uint32_t *frequency) * Called to initialize the i.MX RT. This does whatever setup is needed to * put the SoC in a usable state. The Cortex-M33 boot ROM has already * started essential PLLs and set the FlexSPI1 clock, so only the roots - * required by NuttX are configured here. CCM_CR_FLEXSPI1 and its LPCG - * MUST NOT be touched while executing XIP from FlexSPI1. + * required by NuttX are configured here. * ****************************************************************************/ void imxrt_clockconfig(void) { + unsigned int i; + #ifdef CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33 /* Raise VDD1P0 to the HSRUN (OverDrive) level. Both cores share this * rail and the M33 is the boot core, so it does this on behalf of both. @@ -518,25 +614,10 @@ void imxrt_clockconfig(void) * ARM_PLL or the M33 root when it later executes this function. */ - imxrt_init_arm_pll(); + imxrt_init_arm_pll(&g_initial_clkconfig.arm_pll); - /* M33 core clock: ARM_PLL (798 MHz) / 3 = 266 MHz. */ - - imxrt_ccm_configure_root_clock(CCM_CR_M33, ARM_PLL_OUT, 3); - - /* Root1 belongs exclusively to the M33 domain. LOCK_LIST makes this - * ownership immutable until the next system reset. - */ - - putreg32(CCM_CR_AUTH_DOMAIN(BOARD_CCM_DOMAIN_ID) | - CCM_CR_AUTH_LOCK_LIST, - IMXRT_CCM_CR_AUTH(CCM_CR_M33)); - -#endif - -#ifdef CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33 - /* Keep both CPU cores in RUN during WFI so core exceptions such as - * SysTick can wake them without requiring a GPC wakeup source. + /* Keep M33 core in RUN during WFI so core exceptions such as + * SysTick can wake it without requiring a GPC wakeup source. */ modifyreg32(IMXRT_GPC_CM33_MODE_CTRL, @@ -546,17 +627,35 @@ void imxrt_clockconfig(void) GPC_CM_MISC_SLEEP_HOLD_EN, 0); #endif - /* AON bus (LPUART1/2 pclk): SYS_PLL2 (528 MHz) / 4 = 132 MHz */ + /* Configure the clock roots required by NuttX. */ - imxrt_ccm_configure_root_clock(CCM_CR_BUS_AON, SYS_PLL2_OUT, 4); + for (i = 0; i < CCM_CR_COUNT; i++) + { + if (g_initial_clkconfig.ccm.clock_root[i].action == + CCM_CLOCK_ROOT_CONFIGURE) + { + imxrt_enable_clock_source( + g_initial_clkconfig.ccm.clock_root[i].mux); + imxrt_ccm_configure_root_clock(i, + g_initial_clkconfig.ccm.clock_root[i].mux, + g_initial_clkconfig.ccm.clock_root[i].div); + } + else if (g_initial_clkconfig.ccm.clock_root[i].action == + CCM_CLOCK_ROOT_ACTION_DISABLE) + { + imxrt_ccm_disable_root_clock(i); + } + } - /* M7 SysTick reference: 24 MHz / 240 = 100 kHz */ +#ifdef CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33 + /* Root1 belongs exclusively to the M33 domain. LOCK_LIST makes this + * ownership immutable until the next system reset. + */ - imxrt_ccm_configure_root_clock(CCM_CR_M7_SYSTICK, OSC_24M, 240); - - /* LPUART1/2 functional clock: SYS_PLL3_DIV2 (240 MHz) / 10 = 24 MHz */ - - imxrt_ccm_configure_root_clock(CCM_CR_LPUART0102, SYS_PLL3_DIV2, 10); + putreg32(CCM_CR_AUTH_DOMAIN(BOARD_CCM_DOMAIN_ID) | + CCM_CR_AUTH_LOCK_LIST, + IMXRT_CCM_CR_AUTH(CCM_CR_M33)); +#endif /* Turn on the LPCGs used by the minimal port */ diff --git a/arch/arm/src/imxrt/imxrt_clockconfig_ver3.h b/arch/arm/src/imxrt/imxrt_clockconfig_ver3.h index 4b1b8c4a38a..56cd41ba6c4 100644 --- a/arch/arm/src/imxrt/imxrt_clockconfig_ver3.h +++ b/arch/arm/src/imxrt/imxrt_clockconfig_ver3.h @@ -34,6 +34,168 @@ #include "hardware/rt118x/imxrt118x_ccm.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CCM_CLOCK_ROOT_DISABLE \ + { .action = CCM_CLOCK_ROOT_ACTION_DISABLE } +#define CCM_CLOCK_ROOT_IGNORE \ + { .action = CCM_CLOCK_ROOT_ACTION_IGNORE } + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum ccm_clock_root_action_e +{ + CCM_CLOCK_ROOT_ACTION_DISABLE = 0, + CCM_CLOCK_ROOT_CONFIGURE, + CCM_CLOCK_ROOT_ACTION_IGNORE +}; + +struct ccm_clock_root +{ + uint8_t action; + uint8_t div; + uint8_t mux; +}; + +struct ccm_clock_root_config_s +{ + union + { + struct + { + struct ccm_clock_root m7_clk_root; + struct ccm_clock_root m33_clk_root; + struct ccm_clock_root edgelock_clk_root; + struct ccm_clock_root bus_aon_clk_root; + struct ccm_clock_root bus_wakeup_clk_root; + struct ccm_clock_root wakeup_axi_clk_root; + struct ccm_clock_root swo_trace_clk_root; + struct ccm_clock_root m33_systick_clk_root; + struct ccm_clock_root m7_systick_clk_root; + struct ccm_clock_root flexio1_clk_root; + struct ccm_clock_root flexio2_clk_root; + struct ccm_clock_root lpit3_clk_root; + struct ccm_clock_root lptimer1_clk_root; + struct ccm_clock_root lptimer2_clk_root; + struct ccm_clock_root lptimer3_clk_root; + struct ccm_clock_root tpm2_clk_root; + struct ccm_clock_root tpm4_clk_root; + struct ccm_clock_root tpm5_clk_root; + struct ccm_clock_root tpm6_clk_root; + struct ccm_clock_root gpt1_clk_root; + struct ccm_clock_root gpt2_clk_root; + struct ccm_clock_root flexspi1_clk_root; + struct ccm_clock_root flexspi2_clk_root; + struct ccm_clock_root flexspi_slv_clk_root; + struct ccm_clock_root can1_clk_root; + struct ccm_clock_root can2_clk_root; + struct ccm_clock_root can3_clk_root; + struct ccm_clock_root lpuart0102_clk_root; + struct ccm_clock_root lpuart0304_clk_root; + struct ccm_clock_root lpuart0506_clk_root; + struct ccm_clock_root lpuart0708_clk_root; + struct ccm_clock_root lpuart0910_clk_root; + struct ccm_clock_root lpuart1112_clk_root; + struct ccm_clock_root lpi2c0102_clk_root; + struct ccm_clock_root lpi2c0304_clk_root; + struct ccm_clock_root lpi2c0506_clk_root; + struct ccm_clock_root lpspi0102_clk_root; + struct ccm_clock_root lpspi0304_clk_root; + struct ccm_clock_root lpspi0506_clk_root; + struct ccm_clock_root i3c1_clk_root; + struct ccm_clock_root i3c2_clk_root; + struct ccm_clock_root usdhc1_clk_root; + struct ccm_clock_root usdhc2_clk_root; + struct ccm_clock_root semc_clk_root; + struct ccm_clock_root adc1_clk_root; + struct ccm_clock_root adc2_clk_root; + struct ccm_clock_root acmp_clk_root; + struct ccm_clock_root ecat_clk_root; + struct ccm_clock_root enet_clk_root; + struct ccm_clock_root tmr_1588_clk_root; + struct ccm_clock_root netc_clk_root; + struct ccm_clock_root mac0_clk_root; + struct ccm_clock_root mac1_clk_root; + struct ccm_clock_root mac2_clk_root; + struct ccm_clock_root mac3_clk_root; + struct ccm_clock_root mac4_clk_root; + struct ccm_clock_root serdes0_clk_root; + struct ccm_clock_root serdes1_clk_root; + struct ccm_clock_root serdes2_clk_root; + struct ccm_clock_root serdes0_1g_clk_root; + struct ccm_clock_root serdes1_1g_clk_root; + struct ccm_clock_root serdes2_1g_clk_root; + struct ccm_clock_root xcelbusx_clk_root; + struct ccm_clock_root xriocu4_clk_root; + struct ccm_clock_root mctrl_clk_root; + struct ccm_clock_root sai1_clk_root; + struct ccm_clock_root sai2_clk_root; + struct ccm_clock_root sai3_clk_root; + struct ccm_clock_root sai4_clk_root; + struct ccm_clock_root spdif_clk_root; + struct ccm_clock_root asrc_clk_root; + struct ccm_clock_root mic_clk_root; + struct ccm_clock_root cko1_clk_root; + struct ccm_clock_root cko2_clk_root; + }; + struct ccm_clock_root clock_root[CCM_CR_COUNT]; + }; +}; + +struct ccm_arm_pll +{ + uint8_t post_div; + uint8_t loop_div; +}; + +struct ccm_sys_pll1 +{ + uint32_t enable; + uint8_t div; + uint32_t num; + uint32_t denom; +}; + +struct ccm_sys_pll2 +{ + uint32_t mfd; + uint32_t ss; + uint8_t ss_enable; + uint16_t ss_stop; + uint16_t ss_step; + uint32_t pfd0; + uint32_t pfd1; + uint32_t pfd2; + uint32_t pfd3; +}; + +struct ccm_sys_pll3 +{ + uint32_t pfd0; + uint32_t pfd1; + uint32_t pfd2; + uint32_t pfd3; +}; + +struct clock_configuration_s +{ + struct ccm_clock_root_config_s ccm; + struct ccm_arm_pll arm_pll; + struct ccm_sys_pll1 sys_pll1; + struct ccm_sys_pll2 sys_pll2; + struct ccm_sys_pll3 sys_pll3; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern const struct clock_configuration_s g_initial_clkconfig; + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/boards/arm/imxrt/imxrt1180-evk/src/Makefile b/boards/arm/imxrt/imxrt1180-evk/src/Makefile index bc6e9e10913..6903eb14fe9 100644 --- a/boards/arm/imxrt/imxrt1180-evk/src/Makefile +++ b/boards/arm/imxrt/imxrt1180-evk/src/Makefile @@ -24,6 +24,12 @@ include $(TOPDIR)/Make.defs CSRCS = imxrt_boot.c imxrt_bringup.c imxrt_appinit.c +ifeq ($(CONFIG_ARCH_CORTEXM33),y) +CSRCS += imxrt_clockconfig_m33.c +else +CSRCS += imxrt_clockconfig_m7.c +endif + # On the M33 target the ROM boots our image directly, so we must supply the # FlexSPI Configuration Block ourselves. The M7 image is a raw XIP payload # and carries no flash headers. diff --git a/boards/arm/imxrt/imxrt1180-evk/src/imxrt_clockconfig_m33.c b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_clockconfig_m33.c new file mode 100644 index 00000000000..fad77df8011 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_clockconfig_m33.c @@ -0,0 +1,225 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/src/imxrt_clockconfig_m33.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The ASF licenses this file to you under the Apache License, Version 2.0 + * (the "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "imxrt_clockconfig.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .ccm = + { + .m7_clk_root = CCM_CLOCK_ROOT_IGNORE, + .m33_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 3, + .mux = ARM_PLL_OUT, + }, + .edgelock_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 2, + .mux = OSC_RC_400M, + }, + .bus_aon_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 4, + .mux = SYS_PLL2_OUT, + }, + .bus_wakeup_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 4, + .mux = SYS_PLL2_OUT, + }, + .wakeup_axi_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 2, + .mux = SYS_PLL3_OUT, + }, + .swo_trace_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 3, + .mux = SYS_PLL3_DIV2, + }, + .m33_systick_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 240, + .mux = OSC_24M, + }, + .m7_systick_clk_root = CCM_CLOCK_ROOT_IGNORE, + .flexio1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .flexio2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpit3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lptimer1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lptimer2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lptimer3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tpm2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tpm4_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tpm5_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tpm6_clk_root = CCM_CLOCK_ROOT_DISABLE, + .gpt1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .gpt2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .flexspi1_clk_root = CCM_CLOCK_ROOT_IGNORE, + .flexspi2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .flexspi_slv_clk_root = CCM_CLOCK_ROOT_DISABLE, + .can1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .can2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .can3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart0102_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 10, + .mux = SYS_PLL3_DIV2, + }, + .lpuart0304_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart0506_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart0708_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart0910_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart1112_clk_root = CCM_CLOCK_ROOT_DISABLE, +#ifndef CONFIG_IMXRT1180_EVK_BOOTLOADER + .lpi2c0102_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 10, + .mux = SYS_PLL3_DIV2, + }, + .lpi2c0304_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 10, + .mux = SYS_PLL3_DIV2, + }, + .lpi2c0506_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 10, + .mux = SYS_PLL3_DIV2, + }, + .lpspi0102_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 8, + .mux = SYS_PLL2_OUT, + }, + .lpspi0304_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 8, + .mux = SYS_PLL2_OUT, + }, + .lpspi0506_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 8, + .mux = SYS_PLL2_OUT, + }, +#else + .lpi2c0102_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpi2c0304_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpi2c0506_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpspi0102_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpspi0304_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpspi0506_clk_root = CCM_CLOCK_ROOT_DISABLE, +#endif + .i3c1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .i3c2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .usdhc1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .usdhc2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .semc_clk_root = CCM_CLOCK_ROOT_IGNORE, + .adc1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .adc2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .acmp_clk_root = CCM_CLOCK_ROOT_DISABLE, + .ecat_clk_root = CCM_CLOCK_ROOT_DISABLE, + .enet_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tmr_1588_clk_root = CCM_CLOCK_ROOT_DISABLE, + .netc_clk_root = CCM_CLOCK_ROOT_IGNORE, + .mac0_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mac1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mac2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mac3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mac4_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes0_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes0_1g_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes1_1g_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes2_1g_clk_root = CCM_CLOCK_ROOT_DISABLE, + .xcelbusx_clk_root = CCM_CLOCK_ROOT_DISABLE, + .xriocu4_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mctrl_clk_root = CCM_CLOCK_ROOT_DISABLE, + .sai1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .sai2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .sai3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .sai4_clk_root = CCM_CLOCK_ROOT_DISABLE, + .spdif_clk_root = CCM_CLOCK_ROOT_DISABLE, + .asrc_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mic_clk_root = CCM_CLOCK_ROOT_DISABLE, + .cko1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .cko2_clk_root = CCM_CLOCK_ROOT_DISABLE, + }, + .arm_pll = + { + .post_div = 0, + .loop_div = 133, + }, + .sys_pll1 = + { + .enable = 1, + .div = 41, + .num = 178956970, + .denom = 268435455, + }, + .sys_pll2 = + { + .mfd = 268435455, + .ss_enable = 0, + .pfd0 = 27, + .pfd1 = 16, + .pfd2 = 24, + .pfd3 = 32, + }, + .sys_pll3 = + { + .pfd0 = 22, + .pfd1 = 33, + .pfd2 = 22, + .pfd3 = 18, + }, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/imxrt/imxrt1180-evk/src/imxrt_clockconfig_m7.c b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_clockconfig_m7.c new file mode 100644 index 00000000000..28ee4be5b31 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_clockconfig_m7.c @@ -0,0 +1,216 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/src/imxrt_clockconfig_m7.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. + * The ASF licenses this file to you under the Apache License, Version 2.0 + * (the "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "imxrt_clockconfig.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .ccm = + { + .m7_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 1, + .mux = ARM_PLL_OUT, + }, + .m33_clk_root = CCM_CLOCK_ROOT_IGNORE, + .edgelock_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 2, + .mux = OSC_RC_400M, + }, + .bus_aon_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 4, + .mux = SYS_PLL2_OUT, + }, + .bus_wakeup_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 4, + .mux = SYS_PLL2_OUT, + }, + .wakeup_axi_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 2, + .mux = SYS_PLL3_OUT, + }, + .swo_trace_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 3, + .mux = SYS_PLL3_DIV2, + }, + .m33_systick_clk_root = CCM_CLOCK_ROOT_IGNORE, + .m7_systick_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 240, + .mux = OSC_24M, + }, + .flexio1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .flexio2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpit3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lptimer1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lptimer2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lptimer3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tpm2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tpm4_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tpm5_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tpm6_clk_root = CCM_CLOCK_ROOT_DISABLE, + .gpt1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .gpt2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .flexspi1_clk_root = CCM_CLOCK_ROOT_IGNORE, + .flexspi2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .flexspi_slv_clk_root = CCM_CLOCK_ROOT_DISABLE, + .can1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .can2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .can3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart0102_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 10, + .mux = SYS_PLL3_DIV2, + }, + .lpuart0304_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart0506_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart0708_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart0910_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpuart1112_clk_root = CCM_CLOCK_ROOT_DISABLE, + .lpi2c0102_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 10, + .mux = SYS_PLL3_DIV2, + }, + .lpi2c0304_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 10, + .mux = SYS_PLL3_DIV2, + }, + .lpi2c0506_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 10, + .mux = SYS_PLL3_DIV2, + }, + .lpspi0102_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 8, + .mux = SYS_PLL2_OUT, + }, + .lpspi0304_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 8, + .mux = SYS_PLL2_OUT, + }, + .lpspi0506_clk_root = + { + .action = CCM_CLOCK_ROOT_CONFIGURE, + .div = 8, + .mux = SYS_PLL2_OUT, + }, + .i3c1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .i3c2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .usdhc1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .usdhc2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .semc_clk_root = CCM_CLOCK_ROOT_IGNORE, + .adc1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .adc2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .acmp_clk_root = CCM_CLOCK_ROOT_DISABLE, + .ecat_clk_root = CCM_CLOCK_ROOT_DISABLE, + .enet_clk_root = CCM_CLOCK_ROOT_DISABLE, + .tmr_1588_clk_root = CCM_CLOCK_ROOT_DISABLE, + .netc_clk_root = CCM_CLOCK_ROOT_IGNORE, + .mac0_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mac1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mac2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mac3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mac4_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes0_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes0_1g_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes1_1g_clk_root = CCM_CLOCK_ROOT_DISABLE, + .serdes2_1g_clk_root = CCM_CLOCK_ROOT_DISABLE, + .xcelbusx_clk_root = CCM_CLOCK_ROOT_DISABLE, + .xriocu4_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mctrl_clk_root = CCM_CLOCK_ROOT_DISABLE, + .sai1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .sai2_clk_root = CCM_CLOCK_ROOT_DISABLE, + .sai3_clk_root = CCM_CLOCK_ROOT_DISABLE, + .sai4_clk_root = CCM_CLOCK_ROOT_DISABLE, + .spdif_clk_root = CCM_CLOCK_ROOT_DISABLE, + .asrc_clk_root = CCM_CLOCK_ROOT_DISABLE, + .mic_clk_root = CCM_CLOCK_ROOT_DISABLE, + .cko1_clk_root = CCM_CLOCK_ROOT_DISABLE, + .cko2_clk_root = CCM_CLOCK_ROOT_DISABLE, + }, + .arm_pll = + { + .post_div = 0, + .loop_div = 133, + }, + .sys_pll1 = + { + .enable = 1, + .div = 41, + .num = 178956970, + .denom = 268435455, + }, + .sys_pll2 = + { + .mfd = 268435455, + .ss_enable = 0, + .pfd0 = 27, + .pfd1 = 16, + .pfd2 = 24, + .pfd3 = 32, + }, + .sys_pll3 = + { + .pfd0 = 22, + .pfd1 = 33, + .pfd2 = 22, + .pfd3 = 18, + }, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/