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risc-v/esp32c3: Refactor and rename linker scripts

Browse source 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei 2022-12-07 15:29:32 -03:00 • committed by Xiang Xiao
parent ffd2eb5b14
commit 9af5dca7dc
23 changed files with 99 additions and 2506 deletions
Download patch file Download diff file Expand all files Collapse all files

6
arch/risc-v/src/esp32c3/esp32c3_allocateheap.c
View file

@ -86,8 +86,8 @@ void up_allocate_heap(void **heap_start, size_t *heap_size)
*/
#else
/* These values come from the linker scripts (esp32c3.ld and
* flat.template.ld).
/* These values come from the linker scripts
* (<legacy/mcuboot>_sections.ld and flat_memory.ld).
* Check boards/risc-v/esp32c3.
*/
@ -119,7 +119,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size)
void up_allocate_kheap(void **heap_start, size_t *heap_size)
{
/* These values come from the linker scripts (kernel-space.ld and
* protected.template.ld).
* protected_memory.ld).
* Check boards/risc-v/esp32c3.
*/

4
arch/risc-v/src/esp32c3/esp32c3_rtcheap.c
View file

@ -53,8 +53,8 @@ void esp32c3_rtcheap_initialize(void)
void *start;
size_t size;
/* These values come from the linker scripts (esp32c3.ld and
* flat.template.ld).
/* These values come from the linker scripts
* (<legacy/mcuboot>_sections.ld and flat_memory.ld).
* Check boards/risc-v/esp32c3.
*/

13
boards/risc-v/esp32c3/common/Kconfig Normal file
View file

@ -0,0 +1,13 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
config ESP32C3_MERGE_BINS
bool "Merge raw binary files into a single file"
default n
---help---
Merge the raw binary files into a single file for flashing to the
device.
This is only useful when the path to binary files (e.g. bootloader)
is provided via the ESPTOOL_BINDIR variable.

33
boards/risc-v/esp32c3/common/Makefile Normal file
View file

@ -0,0 +1,33 @@
#############################################################################
# boards/risc-v/esp32c3/common/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
#############################################################################
include $(TOPDIR)/Make.defs
include board/Make.defs
include src/Make.defs
DEPPATH += --dep-path board
DEPPATH += --dep-path src
include $(TOPDIR)/boards/Board.mk
ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
BOARDDIR = $(ARCHSRCDIR)$(DELIM)board
CFLAGS += $(shell $(INCDIR) "$(CC)" $(BOARDDIR)$(DELIM)include)

1
boards/risc-v/esp32c3/common/scripts/.gitignore vendored Normal file
View file

@ -0,0 +1 @@
/*.ld.tmp

2
boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_aliases.ld → boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_aliases.ld
* boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

6
boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_rom.ld → boards/risc-v/esp32c3/common/scripts/esp32c3_rom.ld
View file

@ -1,4 +1,8 @@
/* ROM function interface esp32c3.rom.ld for esp32c3
/****************************************************************************
* boards/risc-v/esp32c3/common/scripts/esp32c3_rom.ld
****************************************************************************/
/* ROM function interface esp32c3_rom.ld for esp32c3
*
*
* Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208

10
boards/risc-v/esp32c3/esp32c3-devkit/scripts/flat.template.ld → boards/risc-v/esp32c3/common/scripts/flat_memory.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/risc-v/esp32c3/esp32c3-devkit/scripts/flat.template.ld
* boards/risc-v/esp32c3/common/scripts/flat_memory.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -72,8 +72,8 @@ MEMORY
*/
metadata (RX) : org = CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE, len = 0x20
ROM (RX) : org = CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE + 0x20,
len = FLASH_SIZE - (CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE + 0x20)
ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata),
len = FLASH_SIZE - ORIGIN(ROM)
#endif
/* Below values assume the flash cache is on, and have the blocks this
@ -119,8 +119,8 @@ MEMORY
* be equal.
*/
drom0_0_seg (R) : org = 0x3c000000 + (CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE + 0x20),
len = FLASH_SIZE - (CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE + 0x20)
drom0_0_seg (R) : org = 0x3c000000 + ORIGIN(ROM),
len = FLASH_SIZE - ORIGIN(ROM)
#else
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip

0
boards/risc-v/esp32c3/esp32c3-devkit/scripts/kernel-space.ld → boards/risc-v/esp32c3/common/scripts/kernel-space.ld
View file

2
boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.ld → boards/risc-v/esp32c3/common/scripts/legacy_sections.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3.ld
* boards/risc-v/esp32c3/common/scripts/legacy_sections.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

2
boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_mcuboot.ld → boards/risc-v/esp32c3/common/scripts/mcuboot_sections.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/risc-v/esp32c3/esp32c3-devkit/scripts/esp32c3_mcuboot.ld
* boards/risc-v/esp32c3/common/scripts/mcuboot_sections.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

13
boards/risc-v/esp32c3/esp32c3-devkit/scripts/protected.template.ld → boards/risc-v/esp32c3/common/scripts/protected_memory.ld
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/risc-v/esp32c3/esp32c3-devkit/scripts/protected.template.ld
* boards/risc-v/esp32c3/common/scripts/protected_memory.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -19,6 +19,8 @@
****************************************************************************/
/****************************************************************************
* ESP32-C3 Linker Script Memory Layout for Protected Mode
*
* This file describes the memory layout (memory blocks) as virtual
* memory addresses.
*
@ -26,10 +28,6 @@
* output into these memory blocks for the Kernel and User images,
* respectively.
*
* NOTE: That this is not the actual linker script but rather a "template"
* for the esp32c3_out.ld script. This template script is passed through
* the C preprocessor to include selected configuration options.
*
****************************************************************************/
#include <nuttx/config.h>
@ -57,7 +55,8 @@
MEMORY
{
metadata (RX) : org = 0x0, len = 0x18
ROM (RX) : org = 0x18, len = 0x100000
ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata),
len = 0x100000 - ORIGIN(ROM)
/* Below values assume the flash cache is on, and have the blocks this
* uses subtracted from the length of the various regions. The 'data access
@ -98,5 +97,5 @@ MEMORY
*/
KDROM (R) : org = 0x3c000020, len = 0x80000 - 0x20
UDROM (R) : org = 0x3c080018, len = 0x180000 - 0x18
UDROM (R) : org = 0x3c080018, len = 0x180000 - ORIGIN(ROM)
}

0
boards/risc-v/esp32c3/esp32c3-devkit/scripts/user-space.ld → boards/risc-v/esp32c3/common/scripts/user-space.ld
View file

1
boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/.gitignore vendored
View file

@ -1 +0,0 @@
/esp32c3_out.ld

20
boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/Make.defs
View file

@ -23,9 +23,23 @@ include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/tools/esp32c3/Config.mk
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32c3_out.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32c3.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld
# Pick the linker scripts from the board level if they exist, if not
# pick the common linker scripts.
ifeq ($(CONFIG_BUILD_PROTECTED),y)
ARCHSCRIPT += $(call FINDSCRIPT,protected_memory.ld)
ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
endif
ARCHPICFLAGS = -fpic

260
boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/esp32c3.ld
View file

@ -1,260 +0,0 @@
/****************************************************************************
* boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/esp32c3.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Default entry point: */
ENTRY(__start);
SECTIONS
{
.iram0.text :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to start of IRAM */
KEEP(*(.exception_vectors.text));
. = ALIGN(4);
*(.iram1)
*(.iram1.*)
*libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*)
*(.wifi0iram .wifi0iram.*)
*(.wifirxiram .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
} >iram0_0_seg
/* This section is required to skip .iram0.text area because iram0_0_seg
* and dram0_0_seg reflect the same address space on different buses.
*/
.dram0.dummy (NOLOAD):
{
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
} >dram0_0_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_sbss = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.share.mem)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_ebss = ABSOLUTE(.);
} >dram0_0_seg
.noinit (NOLOAD):
{
/* This section contains data that is not initialized during load,
* or during the application's initialization sequence.
*/
*(.noinit)
*(.noinit.*)
} >dram0_0_seg
.dram0.data :
{
_sdata = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
__global_pointer$ = . + 0x800;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
*(.dram1)
*(.dram1.*)
. = ALIGN(4);
_edata = ABSOLUTE(.);
/* Heap starts at the end of .data */
_sheap = ABSOLUTE(.);
} >dram0_0_seg
.flash.text :
{
_stext = .;
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
_etext = .;
/* Similar to _iram_start, this symbol goes here so it is
* resolved by addr2line in preference to the first symbol in
* the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} >default_code_seg
.flash_rodata_dummy (NOLOAD):
{
. = SIZEOF(.flash.text);
. = ALIGN(0x10000) + 0x20;
} >drom0_0_seg
.flash.rodata : ALIGN(0x10)
{
_srodata = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.srodata.*)
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
. = (. + 3) & ~ 3;
__eh_frame = ABSOLUTE(.);
KEEP(*(.eh_frame))
. = (. + 7) & ~ 3;
/* C++ constructor and destructor tables:
* RISC-V GCC is configured with --enable-initfini-array so it emits an
* .init_array section instead.
*/
_sinit = ABSOLUTE(.);
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
_einit = ABSOLUTE(.);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_erodata = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
} >default_rodata_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
. = ALIGN (16);
} >iram0_0_seg
.iram0.data :
{
. = ALIGN(16);
*(.iram.data)
*(.iram.data*)
} >iram0_0_seg
.iram0.bss (NOLOAD) :
{
. = ALIGN(16);
*(.iram.bss)
*(.iram.bss*)
. = ALIGN(16);
_iram_end = ABSOLUTE(.);
} >iram0_0_seg
/* RTC fast memory holds RTC wake stub code !*/
.rtc.text :
{
. = ALIGN(4);
*(.rtc.literal .rtc.text)
} >rtc_seg
/* This section is required to skip rtc.text area because the text and
* data segments reflect the same address space on different buses.
*/
.rtc.dummy :
{
. = SIZEOF(.rtc.text);
} >rtc_seg
/* RTC BSS section. */
.rtc.bss (NOLOAD) :
{
*(.rtc.bss)
} >rtc_seg
/* RTC data section holds RTC wake stub data/rodata. */
.rtc.data :
{
*(.rtc.data)
*(.rtc.rodata)
/* Whatever is left from the RTC memory is used as a special heap. */
_srtcheap = ABSOLUTE(.);
} >rtc_seg
}

2036
boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/esp32c3_rom.ld
View file

File diff suppressed because it is too large Load diff

148
boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/flat.template.ld
View file

@ -1,148 +0,0 @@
/****************************************************************************
* boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/flat.template.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* This file describes the memory layout (memory blocks) as virtual
* memory addresses.
*
* NOTE: That this is not the actual linker script but rather a "template"
* for the esp32c3_out.ld script. This template script is passed through
* the C preprocessor to include selected configuration options.
*
****************************************************************************/
#include <nuttx/config.h>
#define SRAM_IRAM_START 0x4037c000
#define SRAM_DRAM_START 0x3fc7c000
/* ICache size is fixed to 16KB on ESP32-C3 */
#define ICACHE_SIZE 0x4000
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
/* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_DRAM_END 0x403d0000 - I_D_SRAM_OFFSET
#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE)
#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
#ifdef CONFIG_ESP32C3_FLASH_2M
# define FLASH_SIZE 0x200000
#elif defined (CONFIG_ESP32C3_FLASH_4M)
# define FLASH_SIZE 0x400000
#elif defined (CONFIG_ESP32C3_FLASH_8M)
# define FLASH_SIZE 0x800000
#elif defined (CONFIG_ESP32C3_FLASH_16M)
# define FLASH_SIZE 0x1000000
#endif
MEMORY
{
#ifdef CONFIG_ESP32C3_APP_FORMAT_MCUBOOT
/* The origin values for "metadata" and "ROM" memory regions are the actual
* load addresses.
*
* NOTE: The memory region starting from 0x0 with length represented by
* CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE is reserved for the MCUboot header,
* which will be prepended to the binary file by the "imgtool" during the
* signing of firmware image.
*/
metadata (RX) : org = CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE, len = 0x20
ROM (RX) : org = CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE + 0x20,
len = FLASH_SIZE - (CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE + 0x20)
#endif
/* Below values assume the flash cache is on, and have the blocks this
* uses subtracted from the length of the various regions. The 'data access
* port' dram/drom regions map to the same iram/irom regions but are
* connected to the data port of the CPU and e.g. allow bytewise access.
*/
iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
/* Flash mapped instruction data. */
#ifdef CONFIG_ESP32C3_APP_FORMAT_MCUBOOT
irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE
#else
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20
#endif
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */
dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE
/* Flash mapped constant data */
#ifdef CONFIG_ESP32C3_APP_FORMAT_MCUBOOT
/* The DROM segment origin is offset by 0x40 for mirroring the actual ROM
* image layout:
* 0x0 - 0x1F : MCUboot header
* 0x20 - 0x3F : Application image metadata section
* 0x40 onwards: ROM code and data
* This is required to meet the following constraint from the external
* flash MMU:
* VMA % 64KB == LMA % 64KB
* i.e. the lower 16 bits of both the virtual address (address seen by the
* CPU) and the load address (physical address of the external flash) must
* be equal.
*/
drom0_0_seg (R) : org = 0x3c000000 + (CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE + 0x20),
len = FLASH_SIZE - (CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE + 0x20)
#else
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20
#endif
/* RTC fast memory. Persists over deep sleep. */
rtc_seg(RWX) : org = 0x50000000, len = 0x2000
}
#if CONFIG_ESP32C3_DEVKIT_RUST1_RUN_IRAM
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
REGION_ALIAS("default_code_seg", iram0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
REGION_ALIAS("default_code_seg", irom0_0_seg);
#endif /* CONFIG_ESP32C3_DEVKIT_RUST1_RUN_IRAM */
/* Mark the end of the RTC heap (top of the RTC region) */
_ertcheap = 0x50001fff;

13
boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/Makefile
View file

@ -53,17 +53,4 @@ ifeq ($(CONFIG_LCD_APA102),y)
CSRCS += esp32c3_apa102.c
endif
SCRIPTIN = $(SCRIPTDIR)$(DELIM)flat.template.ld
SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32c3_out.ld
.PHONY = context distclean
$(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE)
$(Q) $(CC) -isystem $(TOPDIR)/include -I $(BOARD_DIR)/scripts -C -P -x c -E $(SCRIPTIN) -o $@
context:: $(SCRIPTOUT)
distclean::
$(call DELFILE, $(SCRIPTOUT))
include $(TOPDIR)/boards/Board.mk

1
boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig
View file

@ -10,6 +10,7 @@
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="esp32c3-devkit"
CONFIG_ARCH_BOARD_COMMON=y
CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y
CONFIG_ARCH_CHIP="esp32c3"
CONFIG_ARCH_CHIP_ESP32C3=y

1
boards/risc-v/esp32c3/esp32c3-devkit/scripts/.gitignore vendored
View file

@ -1 +0,0 @@
/esp32c3_out.ld

16
boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs
View file

@ -23,20 +23,24 @@ include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/tools/esp32c3/Config.mk
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32c3_out.ld
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld
# Pick the linker scripts from the board level if they exist, if not
# pick the common linker scripts.
ifeq ($(CONFIG_BUILD_PROTECTED),y)
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld
ARCHSCRIPT += $(call FINDSCRIPT,protected_memory.ld)
ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32c3_mcuboot.ld
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32c3.ld
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
endif
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld
ARCHPICFLAGS = -fpic
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror

17
boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile
View file

@ -113,21 +113,4 @@ ifneq ($(CONFIG_NSH_CUSTOMROMFS),y)
endif
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
SCRIPTIN = $(SCRIPTDIR)$(DELIM)protected.template.ld
else
SCRIPTIN = $(SCRIPTDIR)$(DELIM)flat.template.ld
endif
SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32c3_out.ld
.PHONY = context distclean
$(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE)
$(Q) $(CC) -isystem $(TOPDIR)/include -I $(BOARD_DIR)/scripts -C -P -x c -E $(SCRIPTIN) -o $@
context:: $(SCRIPTOUT)
distclean::
$(call DELFILE, $(SCRIPTOUT))
include $(TOPDIR)/boards/Board.mk