From 95cdd306f0ac3a5108b18637c71b95be07f17a9d Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 20 Sep 2026 16:16:42 +0200 Subject: [PATCH] arm/nrf54l: add initial nrf54l support add initial nrf54l support (Cortex-M33 only) Assisted-by: Codex:GPT-6 Signed-off-by: raiden00pl --- Documentation/platforms/arm/nrf54l/index.rst | 57 + arch/arm/Kconfig | 14 + arch/arm/include/nrf54l/chip.h | 35 + arch/arm/include/nrf54l/irq.h | 67 + arch/arm/include/nrf54l/nrf54l_irq.h | 121 ++ arch/arm/src/nrf54l/CMakeLists.txt | 46 + arch/arm/src/nrf54l/Kconfig | 122 ++ arch/arm/src/nrf54l/Make.defs | 43 + arch/arm/src/nrf54l/chip.h | 51 + arch/arm/src/nrf54l/hardware/nrf54l_clock.h | 221 +++ arch/arm/src/nrf54l/hardware/nrf54l_ficr.h | 99 ++ arch/arm/src/nrf54l/hardware/nrf54l_gpio.h | 136 ++ arch/arm/src/nrf54l/hardware/nrf54l_kmu.h | 84 ++ .../src/nrf54l/hardware/nrf54l_memorymap.h | 175 +++ arch/arm/src/nrf54l/hardware/nrf54l_osc.h | 84 ++ arch/arm/src/nrf54l/hardware/nrf54l_tampc.h | 61 + arch/arm/src/nrf54l/hardware/nrf54l_uarte.h | 827 +++++++++++ arch/arm/src/nrf54l/nrf54l_allocateheap.c | 195 +++ arch/arm/src/nrf54l/nrf54l_clockconfig.c | 169 +++ arch/arm/src/nrf54l/nrf54l_clockconfig.h | 40 + arch/arm/src/nrf54l/nrf54l_config.h | 71 + arch/arm/src/nrf54l/nrf54l_gpio.c | 500 +++++++ arch/arm/src/nrf54l/nrf54l_gpio.h | 230 +++ arch/arm/src/nrf54l/nrf54l_idle.c | 91 ++ arch/arm/src/nrf54l/nrf54l_irq.c | 511 +++++++ arch/arm/src/nrf54l/nrf54l_irq.h | 47 + arch/arm/src/nrf54l/nrf54l_lowputc.c | 540 +++++++ arch/arm/src/nrf54l/nrf54l_lowputc.h | 119 ++ arch/arm/src/nrf54l/nrf54l_oscconfig.c | 93 ++ arch/arm/src/nrf54l/nrf54l_oscconfig.h | 63 + arch/arm/src/nrf54l/nrf54l_pminitialize.c | 59 + arch/arm/src/nrf54l/nrf54l_serial.c | 1249 +++++++++++++++++ arch/arm/src/nrf54l/nrf54l_serial.h | 50 + arch/arm/src/nrf54l/nrf54l_start.c | 133 ++ arch/arm/src/nrf54l/nrf54l_start.h | 49 + arch/arm/src/nrf54l/nrf54l_systick.c | 55 + arch/arm/src/nrf54l/nrf54l_uid.c | 59 + arch/arm/src/nrf54l/nrf54l_uid.h | 38 + 38 files changed, 6604 insertions(+) create mode 100644 Documentation/platforms/arm/nrf54l/index.rst create mode 100644 arch/arm/include/nrf54l/chip.h create mode 100644 arch/arm/include/nrf54l/irq.h create mode 100644 arch/arm/include/nrf54l/nrf54l_irq.h create mode 100644 arch/arm/src/nrf54l/CMakeLists.txt create mode 100644 arch/arm/src/nrf54l/Kconfig create mode 100644 arch/arm/src/nrf54l/Make.defs create mode 100644 arch/arm/src/nrf54l/chip.h create mode 100644 arch/arm/src/nrf54l/hardware/nrf54l_clock.h create mode 100644 arch/arm/src/nrf54l/hardware/nrf54l_ficr.h create mode 100644 arch/arm/src/nrf54l/hardware/nrf54l_gpio.h create mode 100644 arch/arm/src/nrf54l/hardware/nrf54l_kmu.h create mode 100644 arch/arm/src/nrf54l/hardware/nrf54l_memorymap.h create mode 100644 arch/arm/src/nrf54l/hardware/nrf54l_osc.h create mode 100644 arch/arm/src/nrf54l/hardware/nrf54l_tampc.h create mode 100644 arch/arm/src/nrf54l/hardware/nrf54l_uarte.h create mode 100644 arch/arm/src/nrf54l/nrf54l_allocateheap.c create mode 100644 arch/arm/src/nrf54l/nrf54l_clockconfig.c create mode 100644 arch/arm/src/nrf54l/nrf54l_clockconfig.h create mode 100644 arch/arm/src/nrf54l/nrf54l_config.h create mode 100644 arch/arm/src/nrf54l/nrf54l_gpio.c create mode 100644 arch/arm/src/nrf54l/nrf54l_gpio.h create mode 100644 arch/arm/src/nrf54l/nrf54l_idle.c create mode 100644 arch/arm/src/nrf54l/nrf54l_irq.c create mode 100644 arch/arm/src/nrf54l/nrf54l_irq.h create mode 100644 arch/arm/src/nrf54l/nrf54l_lowputc.c create mode 100644 arch/arm/src/nrf54l/nrf54l_lowputc.h create mode 100644 arch/arm/src/nrf54l/nrf54l_oscconfig.c create mode 100644 arch/arm/src/nrf54l/nrf54l_oscconfig.h create mode 100644 arch/arm/src/nrf54l/nrf54l_pminitialize.c create mode 100644 arch/arm/src/nrf54l/nrf54l_serial.c create mode 100644 arch/arm/src/nrf54l/nrf54l_serial.h create mode 100644 arch/arm/src/nrf54l/nrf54l_start.c create mode 100644 arch/arm/src/nrf54l/nrf54l_start.h create mode 100644 arch/arm/src/nrf54l/nrf54l_systick.c create mode 100644 arch/arm/src/nrf54l/nrf54l_uid.c create mode 100644 arch/arm/src/nrf54l/nrf54l_uid.h diff --git a/Documentation/platforms/arm/nrf54l/index.rst b/Documentation/platforms/arm/nrf54l/index.rst new file mode 100644 index 00000000000..366763f5cb1 --- /dev/null +++ b/Documentation/platforms/arm/nrf54l/index.rst @@ -0,0 +1,57 @@ +============= +Nordic nRF54L +============= + +The nRF54L series from Nordic Semiconductor is based on an ARM Cortex-M33 +application core. NuttX supports nRF54L15 and nRF54LM20A/B as standalone +secure images, with a 128 MHz CPU clock and SysTick scheduling. + +Peripheral Support +================== + +The following list indicates peripherals supported in NuttX: + +========== ======= ===================================== +Peripheral Support Notes +========== ======= ===================================== +GPIO Yes +GPIOTE No +GRTC No +PWM No +QDEC No +RADIO No +RRAMC No +SAADC No +SPIM No +TIMER No +TWIM No +UARTE Yes No hardware flow control +USBHS No +WDT No +========== ======= ===================================== + +GPIO +---- + +Pins can be configured and operated using ``nrf54l_gpio_*`` functions. + +UARTE +----- + +UART0 through UART4 correspond to UARTE20, UARTE21, UARTE22, UARTE30 and +UARTE00. nRF54LM20 also provides UART5 and UART6 using UARTE23 and UARTE24. +Each enabled UART requires ``BOARD_UARTn_TX_PIN`` and ``BOARD_UARTn_RX_PIN`` +definitions. Any enabled UART can be selected as the serial console. +UART4 requires the dedicated UARTE00 TXD and RXD pins listed in the chip's +pin assignment table. + +``CONFIG_SERIAL_TERMIOS`` enables runtime baud rate, data bits, parity and +stop bit configuration. A format change returns ``-EBUSY`` while a byte is +being transmitted or DMA error recovery is in progress. + +Power Management +================ + +With SysTick selected, the CPU remains awake so its clock keeps running. +``CONFIG_PM`` initializes the NuttX power management framework. System OFF +is not supported. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0b9bcdfd7bd..e6dabd07e9f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -341,6 +341,16 @@ config ARCH_CHIP_NRF53 ---help--- Nordic nRF53 architectures (ARM dual Cortex-M33). +config ARCH_CHIP_NRF54L + bool "Nordic nRF54L" + select ARCH_CORTEXM33 + select ARCH_HAVE_FPU + select ARCH_HAVE_SERIAL_TERMIOS + select ARM_HAVE_DSP + select ARCH_DMA_NO_FLASH_TRANSFER + ---help--- + Nordic nRF54L application Cortex-M33, standalone secure image. + config ARCH_CHIP_NRF91 bool "Nordic nRF91" select ARCH_CORTEXM33 @@ -1344,6 +1354,7 @@ config ARCH_CHIP default "n32h7" if ARCH_CHIP_N32H7 default "nrf52" if ARCH_CHIP_NRF52 default "nrf53" if ARCH_CHIP_NRF53 + default "nrf54l" if ARCH_CHIP_NRF54L default "nrf91" if ARCH_CHIP_NRF91 default "nuc1xx" if ARCH_CHIP_NUC1XX default "ra4" if ARCH_CHIP_RA4 @@ -1846,6 +1857,9 @@ endif if ARCH_CHIP_NRF53 source "arch/arm/src/nrf53/Kconfig" endif +if ARCH_CHIP_NRF54L +source "arch/arm/src/nrf54l/Kconfig" +endif if ARCH_CHIP_NRF91 source "arch/arm/src/nrf91/Kconfig" endif diff --git a/arch/arm/include/nrf54l/chip.h b/arch/arm/include/nrf54l/chip.h new file mode 100644 index 00000000000..c05788d8f09 --- /dev/null +++ b/arch/arm/include/nrf54l/chip.h @@ -0,0 +1,35 @@ +/**************************************************************************** + * arch/arm/include/nrf54l/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_NRF54L_CHIP_H +#define __ARCH_ARM_INCLUDE_NRF54L_CHIP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 +#define NVIC_SYSH_PRIORITY_MAX 0x00 +#define NVIC_SYSH_PRIORITY_STEP 0x20 + +#endif /* __ARCH_ARM_INCLUDE_NRF54L_CHIP_H */ diff --git a/arch/arm/include/nrf54l/irq.h b/arch/arm/include/nrf54l/irq.h new file mode 100644 index 00000000000..9e86f14df48 --- /dev/null +++ b/arch/arm/include/nrf54l/irq.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/arm/include/nrf54l/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_NRF54L_IRQ_H +#define __ARCH_ARM_INCLUDE_NRF54L_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NRF54L_IRQ_RESERVED 0 +#define NRF54L_IRQ_NMI 2 +#define NRF54L_IRQ_HARDFAULT 3 +#define NRF54L_IRQ_MEMFAULT 4 +#define NRF54L_IRQ_BUSFAULT 5 +#define NRF54L_IRQ_USAGEFAULT 6 +#define NRF54L_IRQ_SECUREFAULT 7 +#define NRF54L_IRQ_SVCALL 11 +#define NRF54L_IRQ_DBGMONITOR 12 +#define NRF54L_IRQ_PENDSV 14 +#define NRF54L_IRQ_SYSTICK 15 +#define NRF54L_IRQ_EXTINT 16 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*vic_vector_t)(uint32_t *regs); +#endif + +#endif /* __ARCH_ARM_INCLUDE_NRF54L_IRQ_H */ diff --git a/arch/arm/include/nrf54l/nrf54l_irq.h b/arch/arm/include/nrf54l/nrf54l_irq.h new file mode 100644 index 00000000000..90b8ed97788 --- /dev/null +++ b/arch/arm/include/nrf54l/nrf54l_irq.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * arch/arm/include/nrf54l/nrf54l_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_NRF54L_NRF54L_IRQ_H +#define __ARCH_ARM_INCLUDE_NRF54L_NRF54L_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Cortex-M33 external interrupts (vectors >= 16) */ + +#define NRF54L_IRQ_SWI00 (NRF54L_IRQ_EXTINT + 28) +#define NRF54L_IRQ_SWI01 (NRF54L_IRQ_EXTINT + 29) +#define NRF54L_IRQ_SWI02 (NRF54L_IRQ_EXTINT + 30) +#define NRF54L_IRQ_SWI03 (NRF54L_IRQ_EXTINT + 31) +#define NRF54L_IRQ_SPU00 (NRF54L_IRQ_EXTINT + 64) +#define NRF54L_IRQ_MPC00 (NRF54L_IRQ_EXTINT + 65) +#define NRF54L_IRQ_VPR00 (NRF54L_IRQ_EXTINT + 76) +#define NRF54L_IRQ_CTRLAP (NRF54L_IRQ_EXTINT + 82) +#define NRF54L_IRQ_CM33SS (NRF54L_IRQ_EXTINT + 84) +#define NRF54L_IRQ_TIMER00 (NRF54L_IRQ_EXTINT + 85) +#define NRF54L_IRQ_AXONS (NRF54L_IRQ_EXTINT + 86) +#define NRF54L_IRQ_EGU00 (NRF54L_IRQ_EXTINT + 88) +#define NRF54L_IRQ_USBHS (NRF54L_IRQ_EXTINT + 90) +#define NRF54L_IRQ_SPU10 (NRF54L_IRQ_EXTINT + 128) +#define NRF54L_IRQ_TIMER10 (NRF54L_IRQ_EXTINT + 133) +#define NRF54L_IRQ_EGU10 (NRF54L_IRQ_EXTINT + 135) +#define NRF54L_IRQ_RADIO_0 (NRF54L_IRQ_EXTINT + 138) +#define NRF54L_IRQ_RADIO_1 (NRF54L_IRQ_EXTINT + 139) +#define NRF54L_IRQ_SPU20 (NRF54L_IRQ_EXTINT + 192) +#define NRF54L_IRQ_SERIAL20 (NRF54L_IRQ_EXTINT + 198) +#define NRF54L_IRQ_SERIAL21 (NRF54L_IRQ_EXTINT + 199) +#define NRF54L_IRQ_SERIAL22 (NRF54L_IRQ_EXTINT + 200) +#define NRF54L_IRQ_EGU20 (NRF54L_IRQ_EXTINT + 201) +#define NRF54L_IRQ_TIMER20 (NRF54L_IRQ_EXTINT + 202) +#define NRF54L_IRQ_TIMER21 (NRF54L_IRQ_EXTINT + 203) +#define NRF54L_IRQ_TIMER22 (NRF54L_IRQ_EXTINT + 204) +#define NRF54L_IRQ_TIMER23 (NRF54L_IRQ_EXTINT + 205) +#define NRF54L_IRQ_TIMER24 (NRF54L_IRQ_EXTINT + 206) +#define NRF54L_IRQ_PDM20 (NRF54L_IRQ_EXTINT + 208) +#define NRF54L_IRQ_PDM21 (NRF54L_IRQ_EXTINT + 209) +#define NRF54L_IRQ_PWM20 (NRF54L_IRQ_EXTINT + 210) +#define NRF54L_IRQ_PWM21 (NRF54L_IRQ_EXTINT + 211) +#define NRF54L_IRQ_PWM22 (NRF54L_IRQ_EXTINT + 212) +#define NRF54L_IRQ_SAADC (NRF54L_IRQ_EXTINT + 213) +#define NRF54L_IRQ_NFCT (NRF54L_IRQ_EXTINT + 214) +#define NRF54L_IRQ_TEMP (NRF54L_IRQ_EXTINT + 215) +#define NRF54L_IRQ_GPIOTE20_0 (NRF54L_IRQ_EXTINT + 218) +#define NRF54L_IRQ_GPIOTE20_1 (NRF54L_IRQ_EXTINT + 219) +#define NRF54L_IRQ_I2S20 (NRF54L_IRQ_EXTINT + 221) +#define NRF54L_IRQ_QDEC20 (NRF54L_IRQ_EXTINT + 224) +#define NRF54L_IRQ_QDEC21 (NRF54L_IRQ_EXTINT + 225) +#define NRF54L_IRQ_GRTC_0 (NRF54L_IRQ_EXTINT + 226) +#define NRF54L_IRQ_GRTC_1 (NRF54L_IRQ_EXTINT + 227) +#define NRF54L_IRQ_GRTC_2 (NRF54L_IRQ_EXTINT + 228) +#define NRF54L_IRQ_GRTC_3 (NRF54L_IRQ_EXTINT + 229) +#define NRF54L_IRQ_TDM (NRF54L_IRQ_EXTINT + 232) +#define NRF54L_IRQ_SERIAL23 (NRF54L_IRQ_EXTINT + 237) +#define NRF54L_IRQ_SERIAL24 (NRF54L_IRQ_EXTINT + 238) +#define NRF54L_IRQ_SPU30 (NRF54L_IRQ_EXTINT + 256) +#define NRF54L_IRQ_SERIAL30 (NRF54L_IRQ_EXTINT + 260) +#define NRF54L_IRQ_COMP_LPCOMP (NRF54L_IRQ_EXTINT + 262) +#define NRF54L_IRQ_WDT30 (NRF54L_IRQ_EXTINT + 264) +#define NRF54L_IRQ_WDT31 (NRF54L_IRQ_EXTINT + 265) +#define NRF54L_IRQ_GPIOTE30_0 (NRF54L_IRQ_EXTINT + 268) +#define NRF54L_IRQ_GPIOTE30_1 (NRF54L_IRQ_EXTINT + 269) +#define NRF54L_IRQ_VREGUSB (NRF54L_IRQ_EXTINT + 289) + +#ifdef CONFIG_ARCH_CHIP_NRF54L15 +# define NRF54L_IRQ_AAR00_CCM00 (NRF54L_IRQ_EXTINT + 70) +# define NRF54L_IRQ_ECB00 (NRF54L_IRQ_EXTINT + 71) +# define NRF54L_IRQ_CRACEN (NRF54L_IRQ_EXTINT + 72) +# define NRF54L_IRQ_SERIAL00 (NRF54L_IRQ_EXTINT + 74) +# define NRF54L_IRQ_RRAMC (NRF54L_IRQ_EXTINT + 75) +# define NRF54L_IRQ_TAMPC (NRF54L_IRQ_EXTINT + 220) +# define NRF54L_IRQ_CLOCK_POWER (NRF54L_IRQ_EXTINT + 261) +# define NRF54L_IRQ_NEXTINT (270) +#else +# define NRF54L_IRQ_AAR00_CCM00 (NRF54L_IRQ_EXTINT + 74) +# define NRF54L_IRQ_ECB00 (NRF54L_IRQ_EXTINT + 75) +# define NRF54L_IRQ_SERIAL00 (NRF54L_IRQ_EXTINT + 77) +# define NRF54L_IRQ_RRAMC (NRF54L_IRQ_EXTINT + 78) +# define NRF54L_IRQ_CRACEN (NRF54L_IRQ_EXTINT + 89) +# define NRF54L_IRQ_TAMPC (NRF54L_IRQ_EXTINT + 239) +# define NRF54L_IRQ_CLOCK_POWER (NRF54L_IRQ_EXTINT + 270) +# define NRF54L_IRQ_NEXTINT (290) +#endif + +#define NRF54L_IRQ_NIRQS (NRF54L_IRQ_EXTINT + NRF54L_IRQ_NEXTINT) + +/* Total number of IRQ numbers */ + +#define NR_IRQS NRF54L_IRQ_NIRQS + +#endif /* __ARCH_ARM_INCLUDE_NRF54L_NRF54L_IRQ_H */ diff --git a/arch/arm/src/nrf54l/CMakeLists.txt b/arch/arm/src/nrf54l/CMakeLists.txt new file mode 100644 index 00000000000..a3d56b07470 --- /dev/null +++ b/arch/arm/src/nrf54l/CMakeLists.txt @@ -0,0 +1,46 @@ +# ############################################################################## +# arch/arm/src/nrf54l/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS + nrf54l_start.c + nrf54l_clockconfig.c + nrf54l_oscconfig.c + nrf54l_irq.c + nrf54l_allocateheap.c + nrf54l_gpio.c + nrf54l_lowputc.c + nrf54l_uid.c) + +if(CONFIG_NRF54L_SYSTIMER_SYSTICK) + list(APPEND SRCS nrf54l_systick.c) +endif() +if(CONFIG_NRF54L_UART) + list(APPEND SRCS nrf54l_serial.c) +endif() +if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS nrf54l_idle.c) +endif() +if(CONFIG_PM) + list(APPEND SRCS nrf54l_pminitialize.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/nrf54l/Kconfig b/arch/arm/src/nrf54l/Kconfig new file mode 100644 index 00000000000..15b6a08318b --- /dev/null +++ b/arch/arm/src/nrf54l/Kconfig @@ -0,0 +1,122 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "nRF54L Configuration Options" + +# nRF54L Families + +choice + prompt "nRF54L Chip Selection" + default ARCH_CHIP_NRF54L15 + depends on ARCH_CHIP_NRF54L + +config ARCH_CHIP_NRF54L15 + bool "nRF54L15" + +config ARCH_CHIP_NRF54LM20A + bool "nRF54LM20A" + +config ARCH_CHIP_NRF54LM20B + bool "nRF54LM20B" + +endchoice # nRF54L Chip Selection + +# Peripheral Selection + +config NRF54L_UART + bool + default n + +menu "nRF54L Peripheral Selection" + +config NRF54L_UART0 + bool "UART0" + default n + select UART0_SERIALDRIVER + select NRF54L_UART + ---help--- + Enable UART0 (UARTE20). The board must provide + BOARD_UART0_TX_PIN and BOARD_UART0_RX_PIN. + +config NRF54L_UART1 + bool "UART1" + default n + select UART1_SERIALDRIVER + select NRF54L_UART + ---help--- + Enable UART1 (UARTE21). The board must provide + BOARD_UART1_TX_PIN and BOARD_UART1_RX_PIN. + +config NRF54L_UART2 + bool "UART2" + default n + select UART2_SERIALDRIVER + select NRF54L_UART + ---help--- + Enable UART2 (UARTE22). The board must provide + BOARD_UART2_TX_PIN and BOARD_UART2_RX_PIN. + +config NRF54L_UART3 + bool "UART3" + default n + select UART3_SERIALDRIVER + select NRF54L_UART + ---help--- + Enable UART3 (UARTE30). The board must provide + BOARD_UART3_TX_PIN and BOARD_UART3_RX_PIN. + +config NRF54L_UART4 + bool "UART4" + default n + select UART4_SERIALDRIVER + select NRF54L_UART + ---help--- + Enable UART4 (UARTE00). The board must provide + BOARD_UART4_TX_PIN and BOARD_UART4_RX_PIN. + +config NRF54L_UART5 + bool "UART5" + default n + depends on ARCH_CHIP_NRF54LM20A || ARCH_CHIP_NRF54LM20B + select UART5_SERIALDRIVER + select NRF54L_UART + ---help--- + Enable UART5 (UARTE23). The board must provide + BOARD_UART5_TX_PIN and BOARD_UART5_RX_PIN. + +config NRF54L_UART6 + bool "UART6" + default n + depends on ARCH_CHIP_NRF54LM20A || ARCH_CHIP_NRF54LM20B + select UART6_SERIALDRIVER + select NRF54L_UART + ---help--- + Enable UART6 (UARTE24). The board must provide + BOARD_UART6_TX_PIN and BOARD_UART6_RX_PIN. + +endmenu # nRF54L Peripheral Selection + +menu "System Timer" + +choice + prompt "System Timer Source" + default NRF54L_SYSTIMER_SYSTICK + +config NRF54L_SYSTIMER_SYSTICK + bool "SysTick" + select TIMER + select TIMER_ARCH + select ARMV8M_SYSTICK + +endchoice # System Timer Source + +endmenu # System Timer + +config NRF54L_DEBUG_ACCESS + bool "Keep firmware-controlled debug access open" + default y + ---help--- + Open unlocked TAMPC debug signals for SWD/RTT development. + Signals locked by an earlier boot stage are left unchanged. diff --git a/arch/arm/src/nrf54l/Make.defs b/arch/arm/src/nrf54l/Make.defs new file mode 100644 index 00000000000..79d3db769f7 --- /dev/null +++ b/arch/arm/src/nrf54l/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# arch/arm/src/nrf54l/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv8-m/Make.defs + +CHIP_CSRCS += nrf54l_start.c nrf54l_clockconfig.c nrf54l_oscconfig.c nrf54l_irq.c +CHIP_CSRCS += nrf54l_allocateheap.c nrf54l_gpio.c nrf54l_lowputc.c +CHIP_CSRCS += nrf54l_uid.c + +ifeq ($(CONFIG_NRF54L_SYSTIMER_SYSTICK),y) +CHIP_CSRCS += nrf54l_systick.c +endif + +ifeq ($(CONFIG_NRF54L_UART),y) +CHIP_CSRCS += nrf54l_serial.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += nrf54l_idle.c +endif + +ifeq ($(CONFIG_PM),y) +CHIP_CSRCS += nrf54l_pminitialize.c +endif diff --git a/arch/arm/src/nrf54l/chip.h b/arch/arm/src/nrf54l/chip.h new file mode 100644 index 00000000000..4748b5d3f8f --- /dev/null +++ b/arch/arm/src/nrf54l/chip.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_CHIP_H +#define __ARCH_ARM_SRC_NRF54L_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "hardware/nrf54l_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ARMV8M_PERIPHERAL_INTERRUPTS NRF54L_IRQ_NEXTINT + +#ifdef CONFIG_ARCH_CHIP_NRF54L15 +# define NRF54L_GPIO_NPORTS 3 +# define NRF54L_GPIO_PIN_COUNTS {7, 17, 11} +#else +# define NRF54L_GPIO_NPORTS 4 +# define NRF54L_GPIO_PIN_COUNTS {10, 32, 11, 13} +#endif + +#endif /* __ARCH_ARM_SRC_NRF54L_CHIP_H */ diff --git a/arch/arm/src/nrf54l/hardware/nrf54l_clock.h b/arch/arm/src/nrf54l/hardware/nrf54l_clock.h new file mode 100644 index 00000000000..b9d1d40bd59 --- /dev/null +++ b/arch/arm/src/nrf54l/hardware/nrf54l_clock.h @@ -0,0 +1,221 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/hardware/nrf54l_clock.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_CLOCK_H +#define __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_CLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf54l_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define NRF54L_CLOCK_TASKS_XOSTART_OFFSET 0x0000 /* Start HFXO */ +#define NRF54L_CLOCK_TASKS_XOSTOP_OFFSET 0x0004 /* Release HFXO request */ +#define NRF54L_CLOCK_TASKS_PLLSTART_OFFSET 0x0008 /* Start PLL */ +#define NRF54L_CLOCK_TASKS_PLLSTOP_OFFSET 0x000c /* Release PLL request */ +#define NRF54L_CLOCK_TASKS_LFCLKSTART_OFFSET 0x0010 /* Start LFCLK */ +#define NRF54L_CLOCK_TASKS_LFCLKSTOP_OFFSET 0x0014 /* Stop LFCLK */ +#define NRF54L_CLOCK_TASKS_CAL_OFFSET 0x0018 /* Calibrate LFRC */ +#define NRF54L_CLOCK_TASKS_XOTUNE_OFFSET 0x001c /* Tune HFXO */ +#define NRF54L_CLOCK_TASKS_XOTUNEABORT_OFFSET 0x0020 /* Abort HFXO tuning */ +#define NRF54L_CLOCK_TASKS_XO24MSTART_OFFSET 0x0024 /* Start 24 MHz clock */ +#define NRF54L_CLOCK_TASKS_XO24MSTOP_OFFSET 0x0028 /* Stop 24 MHz clock */ +#define NRF54L_CLOCK_SUBSCRIBE_XOSTART_OFFSET 0x0080 /* Subscribe to XOSTART task */ +#define NRF54L_CLOCK_SUBSCRIBE_XOSTOP_OFFSET 0x0084 /* Subscribe to XOSTOP task */ +#define NRF54L_CLOCK_SUBSCRIBE_PLLSTART_OFFSET 0x0088 /* Subscribe to PLLSTART task */ +#define NRF54L_CLOCK_SUBSCRIBE_PLLSTOP_OFFSET 0x008c /* Subscribe to PLLSTOP task */ +#define NRF54L_CLOCK_SUBSCRIBE_LFCLKSTART_OFFSET 0x0090 /* Subscribe to LFCLKSTART task */ +#define NRF54L_CLOCK_SUBSCRIBE_LFCLKSTOP_OFFSET 0x0094 /* Subscribe to LFCLKSTOP task */ +#define NRF54L_CLOCK_SUBSCRIBE_CAL_OFFSET 0x0098 /* Subscribe to CAL task */ +#define NRF54L_CLOCK_SUBSCRIBE_XOTUNE_OFFSET 0x009c /* Subscribe to XOTUNE task */ +#define NRF54L_CLOCK_SUBSCRIBE_XOTUNEABORT_OFFSET 0x00a0 /* Subscribe to XOTUNEABORT task */ +#define NRF54L_CLOCK_SUBSCRIBE_XO24MSTART_OFFSET 0x00a4 /* Subscribe to XO24MSTART task */ +#define NRF54L_CLOCK_SUBSCRIBE_XO24MSTOP_OFFSET 0x00a8 /* Subscribe to XO24MSTOP task */ +#define NRF54L_CLOCK_EVENTS_XOSTARTED_OFFSET 0x0100 /* HFXO started */ +#define NRF54L_CLOCK_EVENTS_PLLSTARTED_OFFSET 0x0104 /* PLL started */ +#define NRF54L_CLOCK_EVENTS_LFCLKSTARTED_OFFSET 0x0108 /* LFCLK started */ +#define NRF54L_CLOCK_EVENTS_DONE_OFFSET 0x010c /* LFRC calibration completed */ +#define NRF54L_CLOCK_EVENTS_XOTUNED_OFFSET 0x0110 /* HFXO tuning completed */ +#define NRF54L_CLOCK_EVENTS_XOTUNEERROR_OFFSET 0x0114 /* HFXO requires tuning */ +#define NRF54L_CLOCK_EVENTS_XOTUNEFAILED_OFFSET 0x0118 /* HFXO tuning failed */ +#define NRF54L_CLOCK_EVENTS_XO24MSTARTED_OFFSET 0x011c /* 24 MHz clock started */ +#define NRF54L_CLOCK_PUBLISH_XOSTARTED_OFFSET 0x0180 /* Publish XOSTARTED event */ +#define NRF54L_CLOCK_PUBLISH_PLLSTARTED_OFFSET 0x0184 /* Publish PLLSTARTED event */ +#define NRF54L_CLOCK_PUBLISH_LFCLKSTARTED_OFFSET 0x0188 /* Publish LFCLKSTARTED event */ +#define NRF54L_CLOCK_PUBLISH_DONE_OFFSET 0x018c /* Publish DONE event */ +#define NRF54L_CLOCK_PUBLISH_XOTUNED_OFFSET 0x0190 /* Publish XOTUNED event */ +#define NRF54L_CLOCK_PUBLISH_XOTUNEERROR_OFFSET 0x0194 /* Publish XOTUNEERROR event */ +#define NRF54L_CLOCK_PUBLISH_XOTUNEFAILED_OFFSET 0x0198 /* Publish XOTUNEFAILED event */ +#define NRF54L_CLOCK_PUBLISH_XO24MSTARTED_OFFSET 0x019c /* Publish XO24MSTARTED event */ +#define NRF54L_CLOCK_INTEN_OFFSET 0x0300 /* Enable or disable interrupts */ +#define NRF54L_CLOCK_INTENSET_OFFSET 0x0304 /* Enable interrupts */ +#define NRF54L_CLOCK_INTENCLR_OFFSET 0x0308 /* Disable interrupts */ +#define NRF54L_CLOCK_INTPEND_OFFSET 0x030c /* Pending interrupts */ +#define NRF54L_CLOCK_XO_RUN_OFFSET 0x0408 /* HFXO start request status */ +#define NRF54L_CLOCK_XO_STAT_OFFSET 0x040c /* HFXO clock status */ +#define NRF54L_CLOCK_PLL_RUN_OFFSET 0x0428 /* PLL start request status */ +#define NRF54L_CLOCK_PLL_STAT_OFFSET 0x042c /* PLL clock status */ +#define NRF54L_CLOCK_LFCLK_SRC_OFFSET 0x0440 /* LFCLK source selection */ +#define NRF54L_CLOCK_LFCLK_RUN_OFFSET 0x0448 /* LFCLK start request status */ +#define NRF54L_CLOCK_LFCLK_STAT_OFFSET 0x044c /* LFCLK clock status */ +#define NRF54L_CLOCK_LFCLK_SRCCOPY_OFFSET 0x0450 /* LFCLK source latched at start */ +#define NRF54L_CLOCK_PLL24M_RUN_OFFSET 0x0468 /* 24 MHz clock start request status */ +#define NRF54L_CLOCK_PLL24M_STAT_OFFSET 0x046c /* 24 MHz clock status */ + +/* Register addresses *******************************************************/ + +#define NRF54L_CLOCK_TASKS_XOSTART (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_XOSTART_OFFSET) +#define NRF54L_CLOCK_TASKS_XOSTOP (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_XOSTOP_OFFSET) +#define NRF54L_CLOCK_TASKS_PLLSTART (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_PLLSTART_OFFSET) +#define NRF54L_CLOCK_TASKS_PLLSTOP (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_PLLSTOP_OFFSET) +#define NRF54L_CLOCK_TASKS_LFCLKSTART (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_LFCLKSTART_OFFSET) +#define NRF54L_CLOCK_TASKS_LFCLKSTOP (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_LFCLKSTOP_OFFSET) +#define NRF54L_CLOCK_TASKS_CAL (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_CAL_OFFSET) +#define NRF54L_CLOCK_TASKS_XOTUNE (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_XOTUNE_OFFSET) +#define NRF54L_CLOCK_TASKS_XOTUNEABORT (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_XOTUNEABORT_OFFSET) +#define NRF54L_CLOCK_TASKS_XO24MSTART (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_XO24MSTART_OFFSET) +#define NRF54L_CLOCK_TASKS_XO24MSTOP (NRF54L_CLOCK_BASE + NRF54L_CLOCK_TASKS_XO24MSTOP_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_XOSTART (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_XOSTART_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_XOSTOP (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_XOSTOP_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_PLLSTART (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_PLLSTART_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_PLLSTOP (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_PLLSTOP_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_LFCLKSTART (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_LFCLKSTART_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_LFCLKSTOP (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_LFCLKSTOP_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_CAL (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_CAL_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_XOTUNE (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_XOTUNE_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_XOTUNEABORT (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_XOTUNEABORT_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_XO24MSTART (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_XO24MSTART_OFFSET) +#define NRF54L_CLOCK_SUBSCRIBE_XO24MSTOP (NRF54L_CLOCK_BASE + NRF54L_CLOCK_SUBSCRIBE_XO24MSTOP_OFFSET) +#define NRF54L_CLOCK_EVENTS_XOSTARTED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_EVENTS_XOSTARTED_OFFSET) +#define NRF54L_CLOCK_EVENTS_PLLSTARTED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_EVENTS_PLLSTARTED_OFFSET) +#define NRF54L_CLOCK_EVENTS_LFCLKSTARTED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_EVENTS_LFCLKSTARTED_OFFSET) +#define NRF54L_CLOCK_EVENTS_DONE (NRF54L_CLOCK_BASE + NRF54L_CLOCK_EVENTS_DONE_OFFSET) +#define NRF54L_CLOCK_EVENTS_XOTUNED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_EVENTS_XOTUNED_OFFSET) +#define NRF54L_CLOCK_EVENTS_XOTUNEERROR (NRF54L_CLOCK_BASE + NRF54L_CLOCK_EVENTS_XOTUNEERROR_OFFSET) +#define NRF54L_CLOCK_EVENTS_XOTUNEFAILED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_EVENTS_XOTUNEFAILED_OFFSET) +#define NRF54L_CLOCK_EVENTS_XO24MSTARTED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_EVENTS_XO24MSTARTED_OFFSET) +#define NRF54L_CLOCK_PUBLISH_XOSTARTED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PUBLISH_XOSTARTED_OFFSET) +#define NRF54L_CLOCK_PUBLISH_PLLSTARTED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PUBLISH_PLLSTARTED_OFFSET) +#define NRF54L_CLOCK_PUBLISH_LFCLKSTARTED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PUBLISH_LFCLKSTARTED_OFFSET) +#define NRF54L_CLOCK_PUBLISH_DONE (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PUBLISH_DONE_OFFSET) +#define NRF54L_CLOCK_PUBLISH_XOTUNED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PUBLISH_XOTUNED_OFFSET) +#define NRF54L_CLOCK_PUBLISH_XOTUNEERROR (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PUBLISH_XOTUNEERROR_OFFSET) +#define NRF54L_CLOCK_PUBLISH_XOTUNEFAILED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PUBLISH_XOTUNEFAILED_OFFSET) +#define NRF54L_CLOCK_PUBLISH_XO24MSTARTED (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PUBLISH_XO24MSTARTED_OFFSET) +#define NRF54L_CLOCK_INTEN (NRF54L_CLOCK_BASE + NRF54L_CLOCK_INTEN_OFFSET) +#define NRF54L_CLOCK_INTENSET (NRF54L_CLOCK_BASE + NRF54L_CLOCK_INTENSET_OFFSET) +#define NRF54L_CLOCK_INTENCLR (NRF54L_CLOCK_BASE + NRF54L_CLOCK_INTENCLR_OFFSET) +#define NRF54L_CLOCK_INTPEND (NRF54L_CLOCK_BASE + NRF54L_CLOCK_INTPEND_OFFSET) +#define NRF54L_CLOCK_XO_RUN (NRF54L_CLOCK_BASE + NRF54L_CLOCK_XO_RUN_OFFSET) +#define NRF54L_CLOCK_XO_STAT (NRF54L_CLOCK_BASE + NRF54L_CLOCK_XO_STAT_OFFSET) +#define NRF54L_CLOCK_PLL_RUN (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PLL_RUN_OFFSET) +#define NRF54L_CLOCK_PLL_STAT (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PLL_STAT_OFFSET) +#define NRF54L_CLOCK_LFCLK_SRC (NRF54L_CLOCK_BASE + NRF54L_CLOCK_LFCLK_SRC_OFFSET) +#define NRF54L_CLOCK_LFCLK_RUN (NRF54L_CLOCK_BASE + NRF54L_CLOCK_LFCLK_RUN_OFFSET) +#define NRF54L_CLOCK_LFCLK_STAT (NRF54L_CLOCK_BASE + NRF54L_CLOCK_LFCLK_STAT_OFFSET) +#define NRF54L_CLOCK_LFCLK_SRCCOPY (NRF54L_CLOCK_BASE + NRF54L_CLOCK_LFCLK_SRCCOPY_OFFSET) +#define NRF54L_CLOCK_PLL24M_RUN (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PLL24M_RUN_OFFSET) +#define NRF54L_CLOCK_PLL24M_STAT (NRF54L_CLOCK_BASE + NRF54L_CLOCK_PLL24M_STAT_OFFSET) + +/* Register bit definitions *************************************************/ + +/* INTEN/INTENSET/INTENCLR/INTPEND Registers */ + +#define CLOCK_INT_XOSTARTED (1 << 0) +#define CLOCK_INT_PLLSTARTED (1 << 1) +#define CLOCK_INT_LFCLKSTARTED (1 << 2) +#define CLOCK_INT_DONE (1 << 3) +#define CLOCK_INT_XOTUNED (1 << 4) +#define CLOCK_INT_XOTUNEERROR (1 << 5) +#define CLOCK_INT_XOTUNEFAILED (1 << 6) +#define CLOCK_INT_XO24MSTARTED (1 << 7) + +/* XO_RUN Register */ + +#define CLOCK_XO_RUN_STATUS (1 << 0) + +/* XO_STAT Register */ + +#define CLOCK_XO_STAT_STATE (1 << 16) + +/* PLL_RUN Register */ + +#define CLOCK_PLL_RUN_STATUS (1 << 0) + +/* PLL_STAT Register */ + +#define CLOCK_PLL_STAT_STATE (1 << 16) + +/* LFCLK_SRC Register */ + +#define CLOCK_LFCLK_SRC_SRC_SHIFT (0) +#define CLOCK_LFCLK_SRC_SRC_MASK (0x3 << CLOCK_LFCLK_SRC_SRC_SHIFT) +# define CLOCK_LFCLK_SRC_SRC_LFRC (0 << CLOCK_LFCLK_SRC_SRC_SHIFT) +# define CLOCK_LFCLK_SRC_SRC_LFXO (1 << CLOCK_LFCLK_SRC_SRC_SHIFT) +# define CLOCK_LFCLK_SRC_SRC_LFSYNT (2 << CLOCK_LFCLK_SRC_SRC_SHIFT) + +/* LFCLK_RUN Register */ + +#define CLOCK_LFCLK_RUN_STATUS (1 << 0) + +/* LFCLK_STAT Register */ + +#define CLOCK_LFCLK_STAT_SRC_SHIFT (0) +#define CLOCK_LFCLK_STAT_SRC_MASK (0x3 << CLOCK_LFCLK_STAT_SRC_SHIFT) +# define CLOCK_LFCLK_STAT_SRC_LFRC (0 << CLOCK_LFCLK_STAT_SRC_SHIFT) +# define CLOCK_LFCLK_STAT_SRC_LFXO (1 << CLOCK_LFCLK_STAT_SRC_SHIFT) +# define CLOCK_LFCLK_STAT_SRC_LFSYNT (2 << CLOCK_LFCLK_STAT_SRC_SHIFT) +#define CLOCK_LFCLK_STAT_ALWAYSRUNNING (1 << 4) +#define CLOCK_LFCLK_STAT_STATE (1 << 16) + +/* LFCLK_SRCCOPY Register */ + +#define CLOCK_LFCLK_SRCCOPY_SRC_SHIFT (0) +#define CLOCK_LFCLK_SRCCOPY_SRC_MASK (0x3 << CLOCK_LFCLK_SRCCOPY_SRC_SHIFT) +# define CLOCK_LFCLK_SRCCOPY_SRC_LFRC (0 << CLOCK_LFCLK_SRCCOPY_SRC_SHIFT) +# define CLOCK_LFCLK_SRCCOPY_SRC_LFXO (1 << CLOCK_LFCLK_SRCCOPY_SRC_SHIFT) +# define CLOCK_LFCLK_SRCCOPY_SRC_LFSYNT (2 << CLOCK_LFCLK_SRCCOPY_SRC_SHIFT) + +/* PLL24M_RUN Register */ + +#define CLOCK_PLL24M_RUN_STATUS (1 << 0) + +/* PLL24M_STAT Register */ + +#define CLOCK_PLL24M_STAT_STATE (1 << 16) + +/* SUBSCRIBE/PUBLISH Registers */ + +#define CLOCK_DPPI_CHIDX_SHIFT (0) +#define CLOCK_DPPI_CHIDX_MASK (0xff << CLOCK_DPPI_CHIDX_SHIFT) +#define CLOCK_DPPI_ENABLE (1 << 31) + +#endif /* __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_CLOCK_H */ diff --git a/arch/arm/src/nrf54l/hardware/nrf54l_ficr.h b/arch/arm/src/nrf54l/hardware/nrf54l_ficr.h new file mode 100644 index 00000000000..8fb05541516 --- /dev/null +++ b/arch/arm/src/nrf54l/hardware/nrf54l_ficr.h @@ -0,0 +1,99 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/hardware/nrf54l_ficr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_FICR_H +#define __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_FICR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf54l_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define NRF54L_FICR_INFO_CONFIGID_OFFSET 0x0300 /* Device configuration identifier */ +#define NRF54L_FICR_INFO_DEVICEID_OFFSET(n) (0x0304 + ((n) << 2)) /* Device identifier word n */ +#define NRF54L_FICR_INFO_UUID_OFFSET(n) (0x030c + ((n) << 2)) /* UUID word n */ +#define NRF54L_FICR_INFO_PART_OFFSET 0x031c /* Part number */ +#define NRF54L_FICR_INFO_VARIANT_OFFSET 0x0320 /* Part variant */ +#define NRF54L_FICR_INFO_PACKAGE_OFFSET 0x0324 /* Package variant */ +#define NRF54L_FICR_INFO_RAM_OFFSET 0x0328 /* RAM size in KiB */ +#define NRF54L_FICR_INFO_RRAM_OFFSET 0x032c /* RRAM size in KiB */ +#define NRF54L_FICR_ER_OFFSET(n) (0x0380 + ((n) << 2)) /* Encryption root word n */ +#define NRF54L_FICR_IR_OFFSET(n) (0x0390 + ((n) << 2)) /* Identity root word n */ +#define NRF54L_FICR_DEVICEADDRTYPE_OFFSET 0x03a0 /* Device address type */ +#define NRF54L_FICR_DEVICEADDR_OFFSET(n) (0x03a4 + ((n) << 2)) /* Device address word n */ +#define NRF54L_FICR_TRIM_ADDR_OFFSET(n) (0x0400 + ((n) << 3)) /* Factory trim destination n */ +#define NRF54L_FICR_TRIM_DATA_OFFSET(n) (0x0404 + ((n) << 3)) /* Factory trim value n */ +#define NRF54L_FICR_NFC_TAGHEADER_OFFSET(n) (0x0600 + ((n) << 2)) /* NFC tag header word n */ +#define NRF54L_FICR_XOSC32MTRIM_OFFSET 0x0620 /* HFXO capacitance trim */ +#define NRF54L_FICR_XOSC32KTRIM_OFFSET 0x0624 /* LFXO capacitance trim */ + +/* Silicon identification used by the startup errata */ + +#define NRF54L_FICR_PART_OFFSET 0x0340 /* Silicon part identifier */ +#define NRF54L_FICR_VARIANT_OFFSET 0x0344 /* Silicon revision identifier */ + +/* Register addresses *******************************************************/ + +#define NRF54L_FICR_INFO_CONFIGID (NRF54L_FICR_BASE + NRF54L_FICR_INFO_CONFIGID_OFFSET) +#define NRF54L_FICR_INFO_DEVICEID(n) (NRF54L_FICR_BASE + NRF54L_FICR_INFO_DEVICEID_OFFSET(n)) +#define NRF54L_FICR_INFO_UUID(n) (NRF54L_FICR_BASE + NRF54L_FICR_INFO_UUID_OFFSET(n)) +#define NRF54L_FICR_INFO_PART (NRF54L_FICR_BASE + NRF54L_FICR_INFO_PART_OFFSET) +#define NRF54L_FICR_INFO_VARIANT (NRF54L_FICR_BASE + NRF54L_FICR_INFO_VARIANT_OFFSET) +#define NRF54L_FICR_INFO_PACKAGE (NRF54L_FICR_BASE + NRF54L_FICR_INFO_PACKAGE_OFFSET) +#define NRF54L_FICR_INFO_RAM (NRF54L_FICR_BASE + NRF54L_FICR_INFO_RAM_OFFSET) +#define NRF54L_FICR_INFO_RRAM (NRF54L_FICR_BASE + NRF54L_FICR_INFO_RRAM_OFFSET) +#define NRF54L_FICR_PART (NRF54L_FICR_BASE + NRF54L_FICR_PART_OFFSET) +#define NRF54L_FICR_VARIANT (NRF54L_FICR_BASE + NRF54L_FICR_VARIANT_OFFSET) +#define NRF54L_FICR_ER(n) (NRF54L_FICR_BASE + NRF54L_FICR_ER_OFFSET(n)) +#define NRF54L_FICR_IR(n) (NRF54L_FICR_BASE + NRF54L_FICR_IR_OFFSET(n)) +#define NRF54L_FICR_DEVICEADDRTYPE (NRF54L_FICR_BASE + NRF54L_FICR_DEVICEADDRTYPE_OFFSET) +#define NRF54L_FICR_DEVICEADDR(n) (NRF54L_FICR_BASE + NRF54L_FICR_DEVICEADDR_OFFSET(n)) +#define NRF54L_FICR_TRIM_ADDR(n) (NRF54L_FICR_BASE + NRF54L_FICR_TRIM_ADDR_OFFSET(n)) +#define NRF54L_FICR_TRIM_DATA(n) (NRF54L_FICR_BASE + NRF54L_FICR_TRIM_DATA_OFFSET(n)) +#define NRF54L_FICR_NFC_TAGHEADER(n) (NRF54L_FICR_BASE + NRF54L_FICR_NFC_TAGHEADER_OFFSET(n)) +#define NRF54L_FICR_XOSC32MTRIM (NRF54L_FICR_BASE + NRF54L_FICR_XOSC32MTRIM_OFFSET) +#define NRF54L_FICR_XOSC32KTRIM (NRF54L_FICR_BASE + NRF54L_FICR_XOSC32KTRIM_OFFSET) + +/* Register bit definitions *************************************************/ + +#define FICR_DEVICEADDRTYPE_RANDOM (1 << 0) + +#define FICR_XOSC32MTRIM_SLOPE_SHIFT (0) +#define FICR_XOSC32MTRIM_SLOPE_MASK (0x1ff << FICR_XOSC32MTRIM_SLOPE_SHIFT) +#define FICR_XOSC32MTRIM_OFFSET_SHIFT (16) +#define FICR_XOSC32MTRIM_OFFSET_MASK (0x3ff << FICR_XOSC32MTRIM_OFFSET_SHIFT) + +#define FICR_XOSC32KTRIM_SLOPE_SHIFT (0) +#define FICR_XOSC32KTRIM_SLOPE_MASK (0x1ff << FICR_XOSC32KTRIM_SLOPE_SHIFT) +#define FICR_XOSC32KTRIM_OFFSET_SHIFT (16) +#define FICR_XOSC32KTRIM_OFFSET_MASK (0x3ff << FICR_XOSC32KTRIM_OFFSET_SHIFT) + +#endif /* __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_FICR_H */ diff --git a/arch/arm/src/nrf54l/hardware/nrf54l_gpio.h b/arch/arm/src/nrf54l/hardware/nrf54l_gpio.h new file mode 100644 index 00000000000..90b57448f23 --- /dev/null +++ b/arch/arm/src/nrf54l/hardware/nrf54l_gpio.h @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/hardware/nrf54l_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_GPIO_H +#define __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf54l_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define NRF54L_GPIO_OUT_OFFSET 0x0000 /* Write GPIO port */ +#define NRF54L_GPIO_OUTSET_OFFSET 0x0004 /* Set output pins */ +#define NRF54L_GPIO_OUTCLR_OFFSET 0x0008 /* Clear output pins */ +#define NRF54L_GPIO_IN_OFFSET 0x000c /* Read GPIO port */ +#define NRF54L_GPIO_DIR_OFFSET 0x0010 /* Pin direction */ +#define NRF54L_GPIO_DIRSET_OFFSET 0x0014 /* Set pins as outputs */ +#define NRF54L_GPIO_DIRCLR_OFFSET 0x0018 /* Set pins as inputs */ +#define NRF54L_GPIO_LATCH_OFFSET 0x0020 /* Latched pin detection */ +#define NRF54L_GPIO_DETECTMODE_OFFSET 0x0024 /* Select DETECT signal behavior */ +#define NRF54L_GPIO_PIN_CNF_OFFSET(n) (0x0080 + 4 * (n)) /* Pin n configuration */ + +/* Register addresses *******************************************************/ + +#define NRF54L_GPIO0_OUT (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_OUT_OFFSET) +#define NRF54L_GPIO0_OUTSET (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_OUTSET_OFFSET) +#define NRF54L_GPIO0_OUTCLR (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_OUTCLR_OFFSET) +#define NRF54L_GPIO0_IN (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_IN_OFFSET) +#define NRF54L_GPIO0_DIR (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_DIR_OFFSET) +#define NRF54L_GPIO0_DIRSET (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_DIRSET_OFFSET) +#define NRF54L_GPIO0_DIRCLR (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_DIRCLR_OFFSET) +#define NRF54L_GPIO0_LATCH (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_LATCH_OFFSET) +#define NRF54L_GPIO0_DETECTMODE (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_DETECTMODE_OFFSET) +#define NRF54L_GPIO0_CNF(n) (NRF54L_GPIO_P0_BASE + NRF54L_GPIO_PIN_CNF_OFFSET(n)) + +#define NRF54L_GPIO1_OUT (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_OUT_OFFSET) +#define NRF54L_GPIO1_OUTSET (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_OUTSET_OFFSET) +#define NRF54L_GPIO1_OUTCLR (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_OUTCLR_OFFSET) +#define NRF54L_GPIO1_IN (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_IN_OFFSET) +#define NRF54L_GPIO1_DIR (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_DIR_OFFSET) +#define NRF54L_GPIO1_DIRSET (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_DIRSET_OFFSET) +#define NRF54L_GPIO1_DIRCLR (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_DIRCLR_OFFSET) +#define NRF54L_GPIO1_LATCH (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_LATCH_OFFSET) +#define NRF54L_GPIO1_DETECTMODE (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_DETECTMODE_OFFSET) +#define NRF54L_GPIO1_CNF(n) (NRF54L_GPIO_P1_BASE + NRF54L_GPIO_PIN_CNF_OFFSET(n)) + +#define NRF54L_GPIO2_OUT (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_OUT_OFFSET) +#define NRF54L_GPIO2_OUTSET (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_OUTSET_OFFSET) +#define NRF54L_GPIO2_OUTCLR (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_OUTCLR_OFFSET) +#define NRF54L_GPIO2_IN (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_IN_OFFSET) +#define NRF54L_GPIO2_DIR (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_DIR_OFFSET) +#define NRF54L_GPIO2_DIRSET (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_DIRSET_OFFSET) +#define NRF54L_GPIO2_DIRCLR (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_DIRCLR_OFFSET) +#define NRF54L_GPIO2_LATCH (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_LATCH_OFFSET) +#define NRF54L_GPIO2_DETECTMODE (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_DETECTMODE_OFFSET) +#define NRF54L_GPIO2_CNF(n) (NRF54L_GPIO_P2_BASE + NRF54L_GPIO_PIN_CNF_OFFSET(n)) + +#define NRF54L_GPIO3_OUT (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_OUT_OFFSET) +#define NRF54L_GPIO3_OUTSET (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_OUTSET_OFFSET) +#define NRF54L_GPIO3_OUTCLR (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_OUTCLR_OFFSET) +#define NRF54L_GPIO3_IN (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_IN_OFFSET) +#define NRF54L_GPIO3_DIR (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_DIR_OFFSET) +#define NRF54L_GPIO3_DIRSET (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_DIRSET_OFFSET) +#define NRF54L_GPIO3_DIRCLR (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_DIRCLR_OFFSET) +#define NRF54L_GPIO3_LATCH (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_LATCH_OFFSET) +#define NRF54L_GPIO3_DETECTMODE (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_DETECTMODE_OFFSET) +#define NRF54L_GPIO3_CNF(n) (NRF54L_GPIO_P3_BASE + NRF54L_GPIO_PIN_CNF_OFFSET(n)) + +/* Register bit definitions *************************************************/ + +/* DETECTMODE register */ + +#define GPIO_DETECTMODE_DEFAULT (0) +#define GPIO_DETECTMODE_LDETECT (1) + +/* PIN_CNF register */ + +#define GPIO_CNF_DIR (1 << 0) +#define GPIO_CNF_INPUT (1 << 1) +#define GPIO_CNF_PULL_SHIFT (2) +#define GPIO_CNF_PULL_MASK (3 << GPIO_CNF_PULL_SHIFT) +# define GPIO_CNF_PULL_DISABLED (0 << GPIO_CNF_PULL_SHIFT) +# define GPIO_CNF_PULL_DOWN (1 << GPIO_CNF_PULL_SHIFT) +# define GPIO_CNF_PULL_UP (3 << GPIO_CNF_PULL_SHIFT) +#define GPIO_CNF_DRIVE0_SHIFT (8) +#define GPIO_CNF_DRIVE0_MASK (3 << GPIO_CNF_DRIVE0_SHIFT) +# define GPIO_CNF_DRIVE0_STANDARD (0 << GPIO_CNF_DRIVE0_SHIFT) +# define GPIO_CNF_DRIVE0_HIGH (1 << GPIO_CNF_DRIVE0_SHIFT) +# define GPIO_CNF_DRIVE0_DISCONNECT (2 << GPIO_CNF_DRIVE0_SHIFT) +# define GPIO_CNF_DRIVE0_EXTRA (3 << GPIO_CNF_DRIVE0_SHIFT) +#define GPIO_CNF_DRIVE1_SHIFT (10) +#define GPIO_CNF_DRIVE1_MASK (3 << GPIO_CNF_DRIVE1_SHIFT) +# define GPIO_CNF_DRIVE1_STANDARD (0 << GPIO_CNF_DRIVE1_SHIFT) +# define GPIO_CNF_DRIVE1_HIGH (1 << GPIO_CNF_DRIVE1_SHIFT) +# define GPIO_CNF_DRIVE1_DISCONNECT (2 << GPIO_CNF_DRIVE1_SHIFT) +# define GPIO_CNF_DRIVE1_EXTRA (3 << GPIO_CNF_DRIVE1_SHIFT) +#define GPIO_CNF_SENSE_SHIFT (16) +#define GPIO_CNF_SENSE_MASK (3 << GPIO_CNF_SENSE_SHIFT) +# define GPIO_CNF_SENSE_DISABLED (0 << GPIO_CNF_SENSE_SHIFT) +# define GPIO_CNF_SENSE_HIGH (2 << GPIO_CNF_SENSE_SHIFT) +# define GPIO_CNF_SENSE_LOW (3 << GPIO_CNF_SENSE_SHIFT) +#define GPIO_CNF_CTRLSEL_SHIFT (28) +#define GPIO_CNF_CTRLSEL_MASK (7 << GPIO_CNF_CTRLSEL_SHIFT) +# define GPIO_CNF_CTRLSEL_GPIO (0 << GPIO_CNF_CTRLSEL_SHIFT) +# define GPIO_CNF_CTRLSEL_VPR (1 << GPIO_CNF_CTRLSEL_SHIFT) +# define GPIO_CNF_CTRLSEL_GRTC (4 << GPIO_CNF_CTRLSEL_SHIFT) + +#endif /* __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_GPIO_H */ diff --git a/arch/arm/src/nrf54l/hardware/nrf54l_kmu.h b/arch/arm/src/nrf54l/hardware/nrf54l_kmu.h new file mode 100644 index 00000000000..a17ef182f96 --- /dev/null +++ b/arch/arm/src/nrf54l/hardware/nrf54l_kmu.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/hardware/nrf54l_kmu.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_KMU_H +#define __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_KMU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf54l_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define NRF54L_KMU_TASKS_PROVISION_OFFSET 0x0000 /* Provision a key slot */ +#define NRF54L_KMU_TASKS_PUSH_OFFSET 0x0004 /* Push a key slot */ +#define NRF54L_KMU_TASKS_REVOKE_OFFSET 0x0008 /* Revoke a key slot */ +#define NRF54L_KMU_TASKS_READMETADATA_OFFSET 0x000c /* Read key metadata */ +#define NRF54L_KMU_TASKS_PUSHBLOCK_OFFSET 0x0010 /* Block key push */ +#define NRF54L_KMU_TASKS_BLOCK_OFFSET 0x0014 /* Block key operations */ +#define NRF54L_KMU_EVENTS_PROVISIONED_OFFSET 0x0100 /* Key provisioned */ +#define NRF54L_KMU_EVENTS_PUSHED_OFFSET 0x0104 /* Key pushed */ +#define NRF54L_KMU_EVENTS_REVOKED_OFFSET 0x0108 /* Key revoked */ +#define NRF54L_KMU_EVENTS_ERROR_OFFSET 0x010c /* Operation failed */ +#define NRF54L_KMU_EVENTS_METADATAREAD_OFFSET 0x0110 /* Metadata available */ +#define NRF54L_KMU_EVENTS_PUSHBLOCKED_OFFSET 0x0114 /* Key push blocked */ +#define NRF54L_KMU_EVENTS_BLOCKED_OFFSET 0x0118 /* Key operations blocked */ +#define NRF54L_KMU_STATUS_OFFSET 0x0400 /* Preparation status */ +#define NRF54L_KMU_KEYSLOT_OFFSET 0x0500 /* Selected key slot */ +#define NRF54L_KMU_SRC_OFFSET 0x0504 /* Provisioning source */ +#define NRF54L_KMU_METADATA_OFFSET 0x0508 /* Key metadata */ + +/* Register addresses *******************************************************/ + +#define NRF54L_KMU_TASKS_PROVISION (NRF54L_KMU_BASE + NRF54L_KMU_TASKS_PROVISION_OFFSET) +#define NRF54L_KMU_TASKS_PUSH (NRF54L_KMU_BASE + NRF54L_KMU_TASKS_PUSH_OFFSET) +#define NRF54L_KMU_TASKS_REVOKE (NRF54L_KMU_BASE + NRF54L_KMU_TASKS_REVOKE_OFFSET) +#define NRF54L_KMU_TASKS_READMETADATA (NRF54L_KMU_BASE + NRF54L_KMU_TASKS_READMETADATA_OFFSET) +#define NRF54L_KMU_TASKS_PUSHBLOCK (NRF54L_KMU_BASE + NRF54L_KMU_TASKS_PUSHBLOCK_OFFSET) +#define NRF54L_KMU_TASKS_BLOCK (NRF54L_KMU_BASE + NRF54L_KMU_TASKS_BLOCK_OFFSET) +#define NRF54L_KMU_EVENTS_PROVISIONED (NRF54L_KMU_BASE + NRF54L_KMU_EVENTS_PROVISIONED_OFFSET) +#define NRF54L_KMU_EVENTS_PUSHED (NRF54L_KMU_BASE + NRF54L_KMU_EVENTS_PUSHED_OFFSET) +#define NRF54L_KMU_EVENTS_REVOKED (NRF54L_KMU_BASE + NRF54L_KMU_EVENTS_REVOKED_OFFSET) +#define NRF54L_KMU_EVENTS_ERROR (NRF54L_KMU_BASE + NRF54L_KMU_EVENTS_ERROR_OFFSET) +#define NRF54L_KMU_EVENTS_METADATAREAD (NRF54L_KMU_BASE + NRF54L_KMU_EVENTS_METADATAREAD_OFFSET) +#define NRF54L_KMU_EVENTS_PUSHBLOCKED (NRF54L_KMU_BASE + NRF54L_KMU_EVENTS_PUSHBLOCKED_OFFSET) +#define NRF54L_KMU_EVENTS_BLOCKED (NRF54L_KMU_BASE + NRF54L_KMU_EVENTS_BLOCKED_OFFSET) +#define NRF54L_KMU_STATUS (NRF54L_KMU_BASE + NRF54L_KMU_STATUS_OFFSET) +#define NRF54L_KMU_KEYSLOT (NRF54L_KMU_BASE + NRF54L_KMU_KEYSLOT_OFFSET) +#define NRF54L_KMU_SRC (NRF54L_KMU_BASE + NRF54L_KMU_SRC_OFFSET) +#define NRF54L_KMU_METADATA (NRF54L_KMU_BASE + NRF54L_KMU_METADATA_OFFSET) + +/* Register bit definitions *************************************************/ + +#define KMU_STATUS_BUSY (1 << 0) +#define KMU_KEYSLOT_ID_SHIFT (0) +#define KMU_KEYSLOT_ID_MASK (0xff << KMU_KEYSLOT_ID_SHIFT) + +#endif /* __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_KMU_H */ diff --git a/arch/arm/src/nrf54l/hardware/nrf54l_memorymap.h b/arch/arm/src/nrf54l/hardware/nrf54l_memorymap.h new file mode 100644 index 00000000000..fa73b46e029 --- /dev/null +++ b/arch/arm/src/nrf54l/hardware/nrf54l_memorymap.h @@ -0,0 +1,175 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/hardware/nrf54l_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_MEMORYMAP_H +#define __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Memory */ + +#define NRF54L_RRAM_BASE 0x00000000 +#define NRF54L_ICACHE_BASE 0xe0082000 +#define NRF54L_SRAM_BASE 0x20000000 + +/* Peripheral bases */ + +#define NRF54L_FICR_BASE 0x00ffc000 +#define NRF54L_UICR_BASE 0x00ffd000 +#define NRF54L_SICR_BASE 0x00ffe000 +#define NRF54L_USBHSCORE_BASE 0x50020000 +#define NRF54L_SPU00_BASE 0x50040000 +#define NRF54L_MPC00_BASE 0x50041000 +#define NRF54L_DPPIC00_BASE 0x50042000 +#define NRF54L_VPR00_BASE 0x5004c000 +#define NRF54L_GPIOHSPADCTRL_BASE 0x50050400 +#define NRF54L_GPIO_P2_BASE 0x50050400 +#define NRF54L_CTRLAP_BASE 0x50052000 +#define NRF54L_TAD_BASE 0x50053000 +#define NRF54L_TIMER00_BASE 0x50055000 +#define NRF54L_AXONS_BASE 0x50056000 +#define NRF54L_EGU00_BASE 0x50058000 +#define NRF54L_USBHS_BASE 0x5005a000 +#define NRF54L_SPU10_BASE 0x50080000 +#define NRF54L_DPPIC10_BASE 0x50082000 +#define NRF54L_PPIB10_BASE 0x50083000 +#define NRF54L_PPIB11_BASE 0x50084000 +#define NRF54L_TIMER10_BASE 0x50085000 +#define NRF54L_EGU10_BASE 0x50087000 +#define NRF54L_RADIO_BASE 0x5008a000 +#define NRF54L_SPU20_BASE 0x500c0000 +#define NRF54L_DPPIC20_BASE 0x500c2000 +#define NRF54L_PPIB20_BASE 0x500c3000 +#define NRF54L_PPIB21_BASE 0x500c4000 +#define NRF54L_PPIB22_BASE 0x500c5000 +#define NRF54L_SPIM20_BASE 0x500c6000 +#define NRF54L_SPIS20_BASE 0x500c6000 +#define NRF54L_TWIM20_BASE 0x500c6000 +#define NRF54L_TWIS20_BASE 0x500c6000 +#define NRF54L_UART0_BASE 0x500c6000 +#define NRF54L_SPIM21_BASE 0x500c7000 +#define NRF54L_SPIS21_BASE 0x500c7000 +#define NRF54L_TWIM21_BASE 0x500c7000 +#define NRF54L_TWIS21_BASE 0x500c7000 +#define NRF54L_UART1_BASE 0x500c7000 +#define NRF54L_SPIM22_BASE 0x500c8000 +#define NRF54L_SPIS22_BASE 0x500c8000 +#define NRF54L_TWIM22_BASE 0x500c8000 +#define NRF54L_TWIS22_BASE 0x500c8000 +#define NRF54L_UART2_BASE 0x500c8000 +#define NRF54L_EGU20_BASE 0x500c9000 +#define NRF54L_TIMER20_BASE 0x500ca000 +#define NRF54L_TIMER21_BASE 0x500cb000 +#define NRF54L_TIMER22_BASE 0x500cc000 +#define NRF54L_TIMER23_BASE 0x500cd000 +#define NRF54L_TIMER24_BASE 0x500ce000 +#define NRF54L_MEMCONF_BASE 0x500cf000 +#define NRF54L_PDM20_BASE 0x500d0000 +#define NRF54L_PDM21_BASE 0x500d1000 +#define NRF54L_PWM20_BASE 0x500d2000 +#define NRF54L_PWM21_BASE 0x500d3000 +#define NRF54L_PWM22_BASE 0x500d4000 +#define NRF54L_SAADC_BASE 0x500d5000 +#define NRF54L_NFCT_BASE 0x500d6000 +#define NRF54L_TEMP_BASE 0x500d7000 +#define NRF54L_GPIO_P1_BASE 0x500d8200 +#define NRF54L_GPIO_P3_BASE 0x500d8600 +#define NRF54L_GPIOTE20_BASE 0x500da000 +#define NRF54L_I2S20_BASE 0x500dd000 +#define NRF54L_QDEC20_BASE 0x500e0000 +#define NRF54L_QDEC21_BASE 0x500e1000 +#define NRF54L_GRTC_BASE 0x500e2000 +#define NRF54L_TDM_BASE 0x500e8000 +#define NRF54L_SPIM23_BASE 0x500ed000 +#define NRF54L_SPIS23_BASE 0x500ed000 +#define NRF54L_TWIM23_BASE 0x500ed000 +#define NRF54L_TWIS23_BASE 0x500ed000 +#define NRF54L_UART5_BASE 0x500ed000 +#define NRF54L_SPIM24_BASE 0x500ee000 +#define NRF54L_SPIS24_BASE 0x500ee000 +#define NRF54L_TWIM24_BASE 0x500ee000 +#define NRF54L_TWIS24_BASE 0x500ee000 +#define NRF54L_UART6_BASE 0x500ee000 +#define NRF54L_SPU30_BASE 0x50100000 +#define NRF54L_DPPIC30_BASE 0x50102000 +#define NRF54L_PPIB30_BASE 0x50103000 +#define NRF54L_SPIM30_BASE 0x50104000 +#define NRF54L_SPIS30_BASE 0x50104000 +#define NRF54L_TWIM30_BASE 0x50104000 +#define NRF54L_TWIS30_BASE 0x50104000 +#define NRF54L_UART3_BASE 0x50104000 +#define NRF54L_COMP_BASE 0x50106000 +#define NRF54L_LPCOMP_BASE 0x50106000 +#define NRF54L_WDT30_BASE 0x50108000 +#define NRF54L_WDT31_BASE 0x50109000 +#define NRF54L_GPIO_P0_BASE 0x5010a000 +#define NRF54L_GPIOTE30_BASE 0x5010c000 +#define NRF54L_CLOCK_BASE 0x5010e000 +#define NRF54L_POWER_BASE 0x5010e000 +#define NRF54L_RESET_BASE 0x5010e000 +#define NRF54L_OSCILLATORS_BASE 0x50120000 +#define NRF54L_REGULATORS_BASE 0x50120000 +#define NRF54L_VREGUSB_BASE 0x50121000 + +/* Peripheral bases that differ between L15 and LM20 */ + +#ifdef CONFIG_ARCH_CHIP_NRF54L15 +# define NRF54L_AAR00_BASE 0x50046000 +# define NRF54L_CCM00_BASE 0x50046000 +# define NRF54L_CRACEN_BASE 0x50048000 +# define NRF54L_CRACENCORE_BASE 0x51800000 +# define NRF54L_ECB00_BASE 0x50047000 +# define NRF54L_GLITCHDET_BASE 0x5004b000 +# define NRF54L_KMU_BASE 0x50045000 +# define NRF54L_PPIB00_BASE 0x50043000 +# define NRF54L_PPIB01_BASE 0x50044000 +# define NRF54L_RRAMC_BASE 0x5004b000 +# define NRF54L_SPIM00_BASE 0x5004a000 +# define NRF54L_SPIS00_BASE 0x5004a000 +# define NRF54L_TAMPC_BASE 0x500dc000 +# define NRF54L_UART4_BASE 0x5004a000 +#else +# define NRF54L_AAR00_BASE 0x5004a000 +# define NRF54L_CCM00_BASE 0x5004a000 +# define NRF54L_CRACEN_BASE 0x50059000 +# define NRF54L_CRACENCORE_BASE 0x50010000 +# define NRF54L_ECB00_BASE 0x5004b000 +# define NRF54L_GLITCHDET_BASE 0x5004e000 +# define NRF54L_KMU_BASE 0x50049000 +# define NRF54L_PPIB00_BASE 0x50044000 +# define NRF54L_PPIB01_BASE 0x50045000 +# define NRF54L_RRAMC_BASE 0x5004e000 +# define NRF54L_SPIM00_BASE 0x5004d000 +# define NRF54L_SPIS00_BASE 0x5004d000 +# define NRF54L_TAMPC_BASE 0x500ef000 +# define NRF54L_UART4_BASE 0x5004d000 +#endif + +#endif /* __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_MEMORYMAP_H */ diff --git a/arch/arm/src/nrf54l/hardware/nrf54l_osc.h b/arch/arm/src/nrf54l/hardware/nrf54l_osc.h new file mode 100644 index 00000000000..1227c1c07a9 --- /dev/null +++ b/arch/arm/src/nrf54l/hardware/nrf54l_osc.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/hardware/nrf54l_osc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_OSC_H +#define __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_OSC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf54l_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define NRF54L_OSC_XOSC32M_INTCAP_OFFSET 0x071c /* HFXO load capacitance */ +#define NRF54L_OSC_PLL_FREQ_OFFSET 0x0800 /* Requested MCU clock */ +#define NRF54L_OSC_PLL_CURRENTFREQ_OFFSET 0x0804 /* Current MCU clock */ +#define NRF54L_OSC_XOSC32KI_BYPASS_OFFSET 0x0900 /* LFXO external clock */ +#define NRF54L_OSC_XOSC32KI_INTCAP_OFFSET 0x0904 /* LFXO load capacitance */ +#define NRF54L_OSC_XOSC32KI_STATUS_OFFSET 0x0914 /* LFXO status */ + +/* Register addresses *******************************************************/ + +#define NRF54L_OSC_XOSC32M_INTCAP (NRF54L_OSCILLATORS_BASE + NRF54L_OSC_XOSC32M_INTCAP_OFFSET) +#define NRF54L_OSC_PLL_FREQ (NRF54L_OSCILLATORS_BASE + NRF54L_OSC_PLL_FREQ_OFFSET) +#define NRF54L_OSC_PLL_CURRENTFREQ (NRF54L_OSCILLATORS_BASE + NRF54L_OSC_PLL_CURRENTFREQ_OFFSET) +#define NRF54L_OSC_XOSC32KI_BYPASS (NRF54L_OSCILLATORS_BASE + NRF54L_OSC_XOSC32KI_BYPASS_OFFSET) +#define NRF54L_OSC_XOSC32KI_INTCAP (NRF54L_OSCILLATORS_BASE + NRF54L_OSC_XOSC32KI_INTCAP_OFFSET) +#define NRF54L_OSC_XOSC32KI_STATUS (NRF54L_OSCILLATORS_BASE + NRF54L_OSC_XOSC32KI_STATUS_OFFSET) + +/* Register bit definitions *************************************************/ + +/* XOSC32M_INTCAP Register */ + +#define OSC_XOSC32M_INTCAP_SHIFT (0) +#define OSC_XOSC32M_INTCAP_MASK (0x3f << OSC_XOSC32M_INTCAP_SHIFT) + +/* PLL_FREQ Register */ + +#define OSC_PLL_FREQ_SHIFT (0) +#define OSC_PLL_FREQ_MASK (0x3 << OSC_PLL_FREQ_SHIFT) +# define OSC_PLL_FREQ_128M (1 << OSC_PLL_FREQ_SHIFT) +# define OSC_PLL_FREQ_64M (3 << OSC_PLL_FREQ_SHIFT) + +/* PLL_CURRENTFREQ Register */ + +#define OSC_PLL_CURRENTFREQ_SHIFT (0) +#define OSC_PLL_CURRENTFREQ_MASK (0x3 << OSC_PLL_CURRENTFREQ_SHIFT) +# define OSC_PLL_CURRENTFREQ_128M (1 << OSC_PLL_CURRENTFREQ_SHIFT) +# define OSC_PLL_CURRENTFREQ_64M (3 << OSC_PLL_CURRENTFREQ_SHIFT) + +/* XOSC32KI Registers */ + +#define OSC_XOSC32KI_BYPASS (1 << 0) +#define OSC_XOSC32KI_INTCAP_SHIFT (0) +#define OSC_XOSC32KI_INTCAP_MASK (0x1f << OSC_XOSC32KI_INTCAP_SHIFT) +#define OSC_XOSC32KI_STATUS_RUNNING (1 << 2) + +#endif /* __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_OSC_H */ diff --git a/arch/arm/src/nrf54l/hardware/nrf54l_tampc.h b/arch/arm/src/nrf54l/hardware/nrf54l_tampc.h new file mode 100644 index 00000000000..5530bdb4307 --- /dev/null +++ b/arch/arm/src/nrf54l/hardware/nrf54l_tampc.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/hardware/nrf54l_tampc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_TAMPC_H +#define __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_TAMPC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf54l_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define NRF54L_TAMPC_DBGEN_OFFSET 0x0500 /* Invasive debug protection */ +#define NRF54L_TAMPC_NIDEN_OFFSET 0x0508 /* Non-invasive debug protection */ +#define NRF54L_TAMPC_SPIDEN_OFFSET 0x0510 /* Secure invasive debug protection */ +#define NRF54L_TAMPC_SPNIDEN_OFFSET 0x0518 /* Secure non-invasive debug protection */ +#define NRF54L_TAMPC_AP_DBGEN_OFFSET 0x0700 /* Access port debug protection */ + +/* Register addresses *******************************************************/ + +#define NRF54L_TAMPC_DBGEN (NRF54L_TAMPC_BASE + NRF54L_TAMPC_DBGEN_OFFSET) +#define NRF54L_TAMPC_NIDEN (NRF54L_TAMPC_BASE + NRF54L_TAMPC_NIDEN_OFFSET) +#define NRF54L_TAMPC_SPIDEN (NRF54L_TAMPC_BASE + NRF54L_TAMPC_SPIDEN_OFFSET) +#define NRF54L_TAMPC_SPNIDEN (NRF54L_TAMPC_BASE + NRF54L_TAMPC_SPNIDEN_OFFSET) +#define NRF54L_TAMPC_AP_DBGEN (NRF54L_TAMPC_BASE + NRF54L_TAMPC_AP_DBGEN_OFFSET) + +/* Register bit definitions *************************************************/ + +#define TAMPC_KEY (0x50fa0000) +#define TAMPC_UNLOCK (TAMPC_KEY | 0xf0) +#define TAMPC_OPEN (TAMPC_KEY | 1) +#define TAMPC_LOCKED (1 << 1) + +#endif /* __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_TAMPC_H */ diff --git a/arch/arm/src/nrf54l/hardware/nrf54l_uarte.h b/arch/arm/src/nrf54l/hardware/nrf54l_uarte.h new file mode 100644 index 00000000000..815054e4907 --- /dev/null +++ b/arch/arm/src/nrf54l/hardware/nrf54l_uarte.h @@ -0,0 +1,827 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/hardware/nrf54l_uarte.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_UARTE_H +#define __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_UARTE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf54l_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define NRF54L_UARTE_TASKS_FLUSHRX_OFFSET 0x001c /* Flush RX FIFO to DMA buffer */ +#define NRF54L_UARTE_TASKS_STARTRX_OFFSET 0x0028 /* Start reception */ +#define NRF54L_UARTE_TASKS_STOPRX_OFFSET 0x002c /* Stop reception */ +#define NRF54L_UARTE_TASKS_DMA_RX_ENABLEMATCH_OFFSET(n) (0x0030 + 4 * (n)) /* Enable RX match event n */ +#define NRF54L_UARTE_TASKS_DMA_RX_DISABLEMATCH_OFFSET(n) (0x0040 + 4 * (n)) /* Disable RX match event n */ +#define NRF54L_UARTE_TASKS_STARTTX_OFFSET 0x0050 /* Start transmission */ +#define NRF54L_UARTE_TASKS_STOPTX_OFFSET 0x0054 /* Stop transmission */ +#define NRF54L_UARTE_SUBSCRIBE_FLUSHRX_OFFSET 0x009c /* Subscribe to FLUSHRX task */ +#define NRF54L_UARTE_SUBSCRIBE_DMA_RX_START_OFFSET 0x00a8 /* Subscribe to RX START task */ +#define NRF54L_UARTE_SUBSCRIBE_DMA_RX_STOP_OFFSET 0x00ac /* Subscribe to RX STOP task */ +#define NRF54L_UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_OFFSET(n) (0x00b0 + 4 * (n)) /* Subscribe to RX ENABLEMATCH task n */ +#define NRF54L_UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_OFFSET(n) (0x00c0 + 4 * (n)) /* Subscribe to RX DISABLEMATCH task n */ +#define NRF54L_UARTE_SUBSCRIBE_DMA_TX_START_OFFSET 0x00d0 /* Subscribe to TX START task */ +#define NRF54L_UARTE_SUBSCRIBE_DMA_TX_STOP_OFFSET 0x00d4 /* Subscribe to TX STOP task */ +#define NRF54L_UARTE_EVENTS_CTS_OFFSET 0x0100 /* CTS asserted */ +#define NRF54L_UARTE_EVENTS_NCTS_OFFSET 0x0104 /* CTS deasserted */ +#define NRF54L_UARTE_EVENTS_TXDRDY_OFFSET 0x010c /* Byte transmitted */ +#define NRF54L_UARTE_EVENTS_RXDRDY_OFFSET 0x0110 /* Byte received */ +#define NRF54L_UARTE_EVENTS_ERROR_OFFSET 0x0114 /* Receive error */ +#define NRF54L_UARTE_EVENTS_RXTO_OFFSET 0x0124 /* Receiver stopped */ +#define NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET 0x0130 /* Transmitter stopped */ +#define NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET 0x014c /* RX DMA buffer completed */ +#define NRF54L_UARTE_EVENTS_DMA_RX_READY_OFFSET 0x0150 /* RX DMA buffer prepared */ +#define NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET 0x0154 /* RX DMA bus error */ +#define NRF54L_UARTE_EVENTS_DMA_RX_MATCH_OFFSET(n) (0x0158 + 4 * (n)) /* RX data matched candidate n */ +#define NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET 0x0168 /* TX DMA buffer completed */ +#define NRF54L_UARTE_EVENTS_DMA_TX_READY_OFFSET 0x016c /* TX DMA buffer prepared */ +#define NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET 0x0170 /* TX DMA bus error */ +#define NRF54L_UARTE_EVENTS_FRAMETIMEOUT_OFFSET 0x0174 /* Receive frame timed out */ +#define NRF54L_UARTE_PUBLISH_CTS_OFFSET 0x0180 /* Publish CTS event */ +#define NRF54L_UARTE_PUBLISH_NCTS_OFFSET 0x0184 /* Publish NCTS event */ +#define NRF54L_UARTE_PUBLISH_TXDRDY_OFFSET 0x018c /* Publish TXDRDY event */ +#define NRF54L_UARTE_PUBLISH_RXDRDY_OFFSET 0x0190 /* Publish RXDRDY event */ +#define NRF54L_UARTE_PUBLISH_ERROR_OFFSET 0x0194 /* Publish ERROR event */ +#define NRF54L_UARTE_PUBLISH_RXTO_OFFSET 0x01a4 /* Publish RXTO event */ +#define NRF54L_UARTE_PUBLISH_TXSTOPPED_OFFSET 0x01b0 /* Publish TXSTOPPED event */ +#define NRF54L_UARTE_PUBLISH_DMA_RX_END_OFFSET 0x01cc /* Publish RX END event */ +#define NRF54L_UARTE_PUBLISH_DMA_RX_READY_OFFSET 0x01d0 /* Publish RX READY event */ +#define NRF54L_UARTE_PUBLISH_DMA_RX_BUSERROR_OFFSET 0x01d4 /* Publish RX BUSERROR event */ +#define NRF54L_UARTE_PUBLISH_DMA_RX_MATCH_OFFSET(n) (0x01d8 + 4 * (n)) /* Publish RX MATCH event n */ +#define NRF54L_UARTE_PUBLISH_DMA_TX_END_OFFSET 0x01e8 /* Publish TX END event */ +#define NRF54L_UARTE_PUBLISH_DMA_TX_READY_OFFSET 0x01ec /* Publish TX READY event */ +#define NRF54L_UARTE_PUBLISH_DMA_TX_BUSERROR_OFFSET 0x01f0 /* Publish TX BUSERROR event */ +#define NRF54L_UARTE_PUBLISH_FRAMETIMEOUT_OFFSET 0x01f4 /* Publish FRAMETIMEOUT event */ +#define NRF54L_UARTE_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */ +#define NRF54L_UARTE_INTEN_OFFSET 0x0300 /* Enable or disable interrupts */ +#define NRF54L_UARTE_INTENSET_OFFSET 0x0304 /* Enable interrupts */ +#define NRF54L_UARTE_INTENCLR_OFFSET 0x0308 /* Disable interrupts */ +#define NRF54L_UARTE_ERRORSRC_OFFSET 0x0480 /* Receive error source */ +#define NRF54L_UARTE_ENABLE_OFFSET 0x0500 /* Enable UARTE */ +#define NRF54L_UARTE_BAUDRATE_OFFSET 0x0524 /* Baud rate */ +#define NRF54L_UARTE_CONFIG_OFFSET 0x056c /* Frame and flow control configuration */ +#define NRF54L_UARTE_ADDRESS_OFFSET 0x0574 /* Address match configuration */ +#define NRF54L_UARTE_FRAMETIMEOUT_OFFSET 0x0578 /* Receive frame timeout */ +#define NRF54L_UARTE_PSEL_TXD_OFFSET 0x0604 /* Pin select for TXD */ +#define NRF54L_UARTE_PSEL_CTS_OFFSET 0x0608 /* Pin select for CTS */ +#define NRF54L_UARTE_PSEL_RXD_OFFSET 0x060c /* Pin select for RXD */ +#define NRF54L_UARTE_PSEL_RTS_OFFSET 0x0610 /* Pin select for RTS */ +#define NRF54L_UARTE_DMA_RX_PTR_OFFSET 0x0704 /* RX DMA buffer address */ +#define NRF54L_UARTE_DMA_RX_MAXCNT_OFFSET 0x0708 /* RX DMA buffer size in bytes */ +#define NRF54L_UARTE_DMA_RX_AMOUNT_OFFSET 0x070c /* Number of bytes received by DMA */ +#define NRF54L_UARTE_DMA_RX_LIST_OFFSET 0x0714 /* RX DMA list type */ +#define NRF54L_UARTE_DMA_RX_TERMINATEONBUSERROR_OFFSET 0x071c /* Terminate RX DMA on bus error */ +#define NRF54L_UARTE_DMA_RX_BUSERRORADDRESS_OFFSET 0x0720 /* Address of last RX DMA bus error */ +#define NRF54L_UARTE_DMA_RX_MATCH_CONFIG_OFFSET 0x0724 /* RX DMA match configuration */ +#define NRF54L_UARTE_DMA_RX_MATCH_CANDIDATE_OFFSET(n) (0x0728 + 4 * (n)) /* RX DMA match candidate n */ +#define NRF54L_UARTE_DMA_TX_PTR_OFFSET 0x073c /* TX DMA buffer address */ +#define NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET 0x0740 /* TX DMA buffer size in bytes */ +#define NRF54L_UARTE_DMA_TX_AMOUNT_OFFSET 0x0744 /* Number of bytes transmitted by DMA */ +#define NRF54L_UARTE_DMA_TX_LIST_OFFSET 0x074c /* TX DMA list type */ +#define NRF54L_UARTE_DMA_TX_TERMINATEONBUSERROR_OFFSET 0x0754 /* Terminate TX DMA on bus error */ +#define NRF54L_UARTE_DMA_TX_BUSERRORADDRESS_OFFSET 0x0758 /* Address of last TX DMA bus error */ + +/* Register addresses *******************************************************/ + +#define NRF54L_UART0_TASKS_FLUSHRX (NRF54L_UART0_BASE + NRF54L_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF54L_UART0_TASKS_STARTRX (NRF54L_UART0_BASE + NRF54L_UARTE_TASKS_STARTRX_OFFSET) +#define NRF54L_UART0_TASKS_STOPRX (NRF54L_UART0_BASE + NRF54L_UARTE_TASKS_STOPRX_OFFSET) +#define NRF54L_UART0_TASKS_DMA_RX_ENABLEMATCH(n) (NRF54L_UART0_BASE + NRF54L_UARTE_TASKS_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART0_TASKS_DMA_RX_DISABLEMATCH(n) (NRF54L_UART0_BASE + NRF54L_UARTE_TASKS_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART0_TASKS_STARTTX (NRF54L_UART0_BASE + NRF54L_UARTE_TASKS_STARTTX_OFFSET) +#define NRF54L_UART0_TASKS_STOPTX (NRF54L_UART0_BASE + NRF54L_UARTE_TASKS_STOPTX_OFFSET) +#define NRF54L_UART0_SUBSCRIBE_FLUSHRX (NRF54L_UART0_BASE + NRF54L_UARTE_SUBSCRIBE_FLUSHRX_OFFSET) +#define NRF54L_UART0_SUBSCRIBE_DMA_RX_START (NRF54L_UART0_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_START_OFFSET) +#define NRF54L_UART0_SUBSCRIBE_DMA_RX_STOP (NRF54L_UART0_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_STOP_OFFSET) +#define NRF54L_UART0_SUBSCRIBE_DMA_RX_ENABLEMATCH(n) (NRF54L_UART0_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART0_SUBSCRIBE_DMA_RX_DISABLEMATCH(n) (NRF54L_UART0_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART0_SUBSCRIBE_DMA_TX_START (NRF54L_UART0_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_START_OFFSET) +#define NRF54L_UART0_SUBSCRIBE_DMA_TX_STOP (NRF54L_UART0_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_STOP_OFFSET) +#define NRF54L_UART0_EVENTS_CTS (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_CTS_OFFSET) +#define NRF54L_UART0_EVENTS_NCTS (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_NCTS_OFFSET) +#define NRF54L_UART0_EVENTS_TXDRDY (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF54L_UART0_EVENTS_RXDRDY (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF54L_UART0_EVENTS_ERROR (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_ERROR_OFFSET) +#define NRF54L_UART0_EVENTS_RXTO (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_RXTO_OFFSET) +#define NRF54L_UART0_EVENTS_TXSTOPPED (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF54L_UART0_EVENTS_DMA_RX_END (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET) +#define NRF54L_UART0_EVENTS_DMA_RX_READY (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_DMA_RX_READY_OFFSET) +#define NRF54L_UART0_EVENTS_DMA_RX_BUSERROR (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART0_EVENTS_DMA_RX_MATCH(n) (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART0_EVENTS_DMA_TX_END (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET) +#define NRF54L_UART0_EVENTS_DMA_TX_READY (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_DMA_TX_READY_OFFSET) +#define NRF54L_UART0_EVENTS_DMA_TX_BUSERROR (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART0_EVENTS_FRAMETIMEOUT (NRF54L_UART0_BASE + NRF54L_UARTE_EVENTS_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART0_PUBLISH_CTS (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_CTS_OFFSET) +#define NRF54L_UART0_PUBLISH_NCTS (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_NCTS_OFFSET) +#define NRF54L_UART0_PUBLISH_TXDRDY (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_TXDRDY_OFFSET) +#define NRF54L_UART0_PUBLISH_RXDRDY (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_RXDRDY_OFFSET) +#define NRF54L_UART0_PUBLISH_ERROR (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_ERROR_OFFSET) +#define NRF54L_UART0_PUBLISH_RXTO (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_RXTO_OFFSET) +#define NRF54L_UART0_PUBLISH_TXSTOPPED (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_TXSTOPPED_OFFSET) +#define NRF54L_UART0_PUBLISH_DMA_RX_END (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_END_OFFSET) +#define NRF54L_UART0_PUBLISH_DMA_RX_READY (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_READY_OFFSET) +#define NRF54L_UART0_PUBLISH_DMA_RX_BUSERROR (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART0_PUBLISH_DMA_RX_MATCH(n) (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART0_PUBLISH_DMA_TX_END (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_END_OFFSET) +#define NRF54L_UART0_PUBLISH_DMA_TX_READY (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_READY_OFFSET) +#define NRF54L_UART0_PUBLISH_DMA_TX_BUSERROR (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART0_PUBLISH_FRAMETIMEOUT (NRF54L_UART0_BASE + NRF54L_UARTE_PUBLISH_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART0_SHORTS (NRF54L_UART0_BASE + NRF54L_UARTE_SHORTS_OFFSET) +#define NRF54L_UART0_INTEN (NRF54L_UART0_BASE + NRF54L_UARTE_INTEN_OFFSET) +#define NRF54L_UART0_INTENSET (NRF54L_UART0_BASE + NRF54L_UARTE_INTENSET_OFFSET) +#define NRF54L_UART0_INTENCLR (NRF54L_UART0_BASE + NRF54L_UARTE_INTENCLR_OFFSET) +#define NRF54L_UART0_ERRORSRC (NRF54L_UART0_BASE + NRF54L_UARTE_ERRORSRC_OFFSET) +#define NRF54L_UART0_ENABLE (NRF54L_UART0_BASE + NRF54L_UARTE_ENABLE_OFFSET) +#define NRF54L_UART0_BAUDRATE (NRF54L_UART0_BASE + NRF54L_UARTE_BAUDRATE_OFFSET) +#define NRF54L_UART0_CONFIG (NRF54L_UART0_BASE + NRF54L_UARTE_CONFIG_OFFSET) +#define NRF54L_UART0_ADDRESS (NRF54L_UART0_BASE + NRF54L_UARTE_ADDRESS_OFFSET) +#define NRF54L_UART0_FRAMETIMEOUT (NRF54L_UART0_BASE + NRF54L_UARTE_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART0_PSEL_TXD (NRF54L_UART0_BASE + NRF54L_UARTE_PSEL_TXD_OFFSET) +#define NRF54L_UART0_PSEL_CTS (NRF54L_UART0_BASE + NRF54L_UARTE_PSEL_CTS_OFFSET) +#define NRF54L_UART0_PSEL_RXD (NRF54L_UART0_BASE + NRF54L_UARTE_PSEL_RXD_OFFSET) +#define NRF54L_UART0_PSEL_RTS (NRF54L_UART0_BASE + NRF54L_UARTE_PSEL_RTS_OFFSET) +#define NRF54L_UART0_DMA_RX_PTR (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_RX_PTR_OFFSET) +#define NRF54L_UART0_DMA_RX_MAXCNT (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_RX_MAXCNT_OFFSET) +#define NRF54L_UART0_DMA_RX_AMOUNT (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_RX_AMOUNT_OFFSET) +#define NRF54L_UART0_DMA_RX_LIST (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_RX_LIST_OFFSET) +#define NRF54L_UART0_DMA_RX_TERMINATEONBUSERROR (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_RX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART0_DMA_RX_BUSERRORADDRESS (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_RX_BUSERRORADDRESS_OFFSET) +#define NRF54L_UART0_DMA_RX_MATCH_CONFIG (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_RX_MATCH_CONFIG_OFFSET) +#define NRF54L_UART0_DMA_RX_MATCH_CANDIDATE(n) (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_RX_MATCH_CANDIDATE_OFFSET(n)) +#define NRF54L_UART0_DMA_TX_PTR (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_TX_PTR_OFFSET) +#define NRF54L_UART0_DMA_TX_MAXCNT (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET) +#define NRF54L_UART0_DMA_TX_AMOUNT (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_TX_AMOUNT_OFFSET) +#define NRF54L_UART0_DMA_TX_LIST (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_TX_LIST_OFFSET) +#define NRF54L_UART0_DMA_TX_TERMINATEONBUSERROR (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_TX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART0_DMA_TX_BUSERRORADDRESS (NRF54L_UART0_BASE + NRF54L_UARTE_DMA_TX_BUSERRORADDRESS_OFFSET) + +#define NRF54L_UART1_TASKS_FLUSHRX (NRF54L_UART1_BASE + NRF54L_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF54L_UART1_TASKS_STARTRX (NRF54L_UART1_BASE + NRF54L_UARTE_TASKS_STARTRX_OFFSET) +#define NRF54L_UART1_TASKS_STOPRX (NRF54L_UART1_BASE + NRF54L_UARTE_TASKS_STOPRX_OFFSET) +#define NRF54L_UART1_TASKS_DMA_RX_ENABLEMATCH(n) (NRF54L_UART1_BASE + NRF54L_UARTE_TASKS_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART1_TASKS_DMA_RX_DISABLEMATCH(n) (NRF54L_UART1_BASE + NRF54L_UARTE_TASKS_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART1_TASKS_STARTTX (NRF54L_UART1_BASE + NRF54L_UARTE_TASKS_STARTTX_OFFSET) +#define NRF54L_UART1_TASKS_STOPTX (NRF54L_UART1_BASE + NRF54L_UARTE_TASKS_STOPTX_OFFSET) +#define NRF54L_UART1_SUBSCRIBE_FLUSHRX (NRF54L_UART1_BASE + NRF54L_UARTE_SUBSCRIBE_FLUSHRX_OFFSET) +#define NRF54L_UART1_SUBSCRIBE_DMA_RX_START (NRF54L_UART1_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_START_OFFSET) +#define NRF54L_UART1_SUBSCRIBE_DMA_RX_STOP (NRF54L_UART1_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_STOP_OFFSET) +#define NRF54L_UART1_SUBSCRIBE_DMA_RX_ENABLEMATCH(n) (NRF54L_UART1_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART1_SUBSCRIBE_DMA_RX_DISABLEMATCH(n) (NRF54L_UART1_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART1_SUBSCRIBE_DMA_TX_START (NRF54L_UART1_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_START_OFFSET) +#define NRF54L_UART1_SUBSCRIBE_DMA_TX_STOP (NRF54L_UART1_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_STOP_OFFSET) +#define NRF54L_UART1_EVENTS_CTS (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_CTS_OFFSET) +#define NRF54L_UART1_EVENTS_NCTS (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_NCTS_OFFSET) +#define NRF54L_UART1_EVENTS_TXDRDY (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF54L_UART1_EVENTS_RXDRDY (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF54L_UART1_EVENTS_ERROR (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_ERROR_OFFSET) +#define NRF54L_UART1_EVENTS_RXTO (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_RXTO_OFFSET) +#define NRF54L_UART1_EVENTS_TXSTOPPED (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF54L_UART1_EVENTS_DMA_RX_END (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET) +#define NRF54L_UART1_EVENTS_DMA_RX_READY (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_DMA_RX_READY_OFFSET) +#define NRF54L_UART1_EVENTS_DMA_RX_BUSERROR (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART1_EVENTS_DMA_RX_MATCH(n) (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART1_EVENTS_DMA_TX_END (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET) +#define NRF54L_UART1_EVENTS_DMA_TX_READY (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_DMA_TX_READY_OFFSET) +#define NRF54L_UART1_EVENTS_DMA_TX_BUSERROR (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART1_EVENTS_FRAMETIMEOUT (NRF54L_UART1_BASE + NRF54L_UARTE_EVENTS_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART1_PUBLISH_CTS (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_CTS_OFFSET) +#define NRF54L_UART1_PUBLISH_NCTS (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_NCTS_OFFSET) +#define NRF54L_UART1_PUBLISH_TXDRDY (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_TXDRDY_OFFSET) +#define NRF54L_UART1_PUBLISH_RXDRDY (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_RXDRDY_OFFSET) +#define NRF54L_UART1_PUBLISH_ERROR (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_ERROR_OFFSET) +#define NRF54L_UART1_PUBLISH_RXTO (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_RXTO_OFFSET) +#define NRF54L_UART1_PUBLISH_TXSTOPPED (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_TXSTOPPED_OFFSET) +#define NRF54L_UART1_PUBLISH_DMA_RX_END (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_END_OFFSET) +#define NRF54L_UART1_PUBLISH_DMA_RX_READY (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_READY_OFFSET) +#define NRF54L_UART1_PUBLISH_DMA_RX_BUSERROR (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART1_PUBLISH_DMA_RX_MATCH(n) (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART1_PUBLISH_DMA_TX_END (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_END_OFFSET) +#define NRF54L_UART1_PUBLISH_DMA_TX_READY (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_READY_OFFSET) +#define NRF54L_UART1_PUBLISH_DMA_TX_BUSERROR (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART1_PUBLISH_FRAMETIMEOUT (NRF54L_UART1_BASE + NRF54L_UARTE_PUBLISH_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART1_SHORTS (NRF54L_UART1_BASE + NRF54L_UARTE_SHORTS_OFFSET) +#define NRF54L_UART1_INTEN (NRF54L_UART1_BASE + NRF54L_UARTE_INTEN_OFFSET) +#define NRF54L_UART1_INTENSET (NRF54L_UART1_BASE + NRF54L_UARTE_INTENSET_OFFSET) +#define NRF54L_UART1_INTENCLR (NRF54L_UART1_BASE + NRF54L_UARTE_INTENCLR_OFFSET) +#define NRF54L_UART1_ERRORSRC (NRF54L_UART1_BASE + NRF54L_UARTE_ERRORSRC_OFFSET) +#define NRF54L_UART1_ENABLE (NRF54L_UART1_BASE + NRF54L_UARTE_ENABLE_OFFSET) +#define NRF54L_UART1_BAUDRATE (NRF54L_UART1_BASE + NRF54L_UARTE_BAUDRATE_OFFSET) +#define NRF54L_UART1_CONFIG (NRF54L_UART1_BASE + NRF54L_UARTE_CONFIG_OFFSET) +#define NRF54L_UART1_ADDRESS (NRF54L_UART1_BASE + NRF54L_UARTE_ADDRESS_OFFSET) +#define NRF54L_UART1_FRAMETIMEOUT (NRF54L_UART1_BASE + NRF54L_UARTE_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART1_PSEL_TXD (NRF54L_UART1_BASE + NRF54L_UARTE_PSEL_TXD_OFFSET) +#define NRF54L_UART1_PSEL_CTS (NRF54L_UART1_BASE + NRF54L_UARTE_PSEL_CTS_OFFSET) +#define NRF54L_UART1_PSEL_RXD (NRF54L_UART1_BASE + NRF54L_UARTE_PSEL_RXD_OFFSET) +#define NRF54L_UART1_PSEL_RTS (NRF54L_UART1_BASE + NRF54L_UARTE_PSEL_RTS_OFFSET) +#define NRF54L_UART1_DMA_RX_PTR (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_RX_PTR_OFFSET) +#define NRF54L_UART1_DMA_RX_MAXCNT (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_RX_MAXCNT_OFFSET) +#define NRF54L_UART1_DMA_RX_AMOUNT (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_RX_AMOUNT_OFFSET) +#define NRF54L_UART1_DMA_RX_LIST (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_RX_LIST_OFFSET) +#define NRF54L_UART1_DMA_RX_TERMINATEONBUSERROR (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_RX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART1_DMA_RX_BUSERRORADDRESS (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_RX_BUSERRORADDRESS_OFFSET) +#define NRF54L_UART1_DMA_RX_MATCH_CONFIG (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_RX_MATCH_CONFIG_OFFSET) +#define NRF54L_UART1_DMA_RX_MATCH_CANDIDATE(n) (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_RX_MATCH_CANDIDATE_OFFSET(n)) +#define NRF54L_UART1_DMA_TX_PTR (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_TX_PTR_OFFSET) +#define NRF54L_UART1_DMA_TX_MAXCNT (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET) +#define NRF54L_UART1_DMA_TX_AMOUNT (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_TX_AMOUNT_OFFSET) +#define NRF54L_UART1_DMA_TX_LIST (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_TX_LIST_OFFSET) +#define NRF54L_UART1_DMA_TX_TERMINATEONBUSERROR (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_TX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART1_DMA_TX_BUSERRORADDRESS (NRF54L_UART1_BASE + NRF54L_UARTE_DMA_TX_BUSERRORADDRESS_OFFSET) + +#define NRF54L_UART2_TASKS_FLUSHRX (NRF54L_UART2_BASE + NRF54L_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF54L_UART2_TASKS_STARTRX (NRF54L_UART2_BASE + NRF54L_UARTE_TASKS_STARTRX_OFFSET) +#define NRF54L_UART2_TASKS_STOPRX (NRF54L_UART2_BASE + NRF54L_UARTE_TASKS_STOPRX_OFFSET) +#define NRF54L_UART2_TASKS_DMA_RX_ENABLEMATCH(n) (NRF54L_UART2_BASE + NRF54L_UARTE_TASKS_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART2_TASKS_DMA_RX_DISABLEMATCH(n) (NRF54L_UART2_BASE + NRF54L_UARTE_TASKS_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART2_TASKS_STARTTX (NRF54L_UART2_BASE + NRF54L_UARTE_TASKS_STARTTX_OFFSET) +#define NRF54L_UART2_TASKS_STOPTX (NRF54L_UART2_BASE + NRF54L_UARTE_TASKS_STOPTX_OFFSET) +#define NRF54L_UART2_SUBSCRIBE_FLUSHRX (NRF54L_UART2_BASE + NRF54L_UARTE_SUBSCRIBE_FLUSHRX_OFFSET) +#define NRF54L_UART2_SUBSCRIBE_DMA_RX_START (NRF54L_UART2_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_START_OFFSET) +#define NRF54L_UART2_SUBSCRIBE_DMA_RX_STOP (NRF54L_UART2_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_STOP_OFFSET) +#define NRF54L_UART2_SUBSCRIBE_DMA_RX_ENABLEMATCH(n) (NRF54L_UART2_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART2_SUBSCRIBE_DMA_RX_DISABLEMATCH(n) (NRF54L_UART2_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART2_SUBSCRIBE_DMA_TX_START (NRF54L_UART2_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_START_OFFSET) +#define NRF54L_UART2_SUBSCRIBE_DMA_TX_STOP (NRF54L_UART2_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_STOP_OFFSET) +#define NRF54L_UART2_EVENTS_CTS (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_CTS_OFFSET) +#define NRF54L_UART2_EVENTS_NCTS (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_NCTS_OFFSET) +#define NRF54L_UART2_EVENTS_TXDRDY (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF54L_UART2_EVENTS_RXDRDY (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF54L_UART2_EVENTS_ERROR (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_ERROR_OFFSET) +#define NRF54L_UART2_EVENTS_RXTO (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_RXTO_OFFSET) +#define NRF54L_UART2_EVENTS_TXSTOPPED (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF54L_UART2_EVENTS_DMA_RX_END (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET) +#define NRF54L_UART2_EVENTS_DMA_RX_READY (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_DMA_RX_READY_OFFSET) +#define NRF54L_UART2_EVENTS_DMA_RX_BUSERROR (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART2_EVENTS_DMA_RX_MATCH(n) (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART2_EVENTS_DMA_TX_END (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET) +#define NRF54L_UART2_EVENTS_DMA_TX_READY (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_DMA_TX_READY_OFFSET) +#define NRF54L_UART2_EVENTS_DMA_TX_BUSERROR (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART2_EVENTS_FRAMETIMEOUT (NRF54L_UART2_BASE + NRF54L_UARTE_EVENTS_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART2_PUBLISH_CTS (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_CTS_OFFSET) +#define NRF54L_UART2_PUBLISH_NCTS (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_NCTS_OFFSET) +#define NRF54L_UART2_PUBLISH_TXDRDY (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_TXDRDY_OFFSET) +#define NRF54L_UART2_PUBLISH_RXDRDY (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_RXDRDY_OFFSET) +#define NRF54L_UART2_PUBLISH_ERROR (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_ERROR_OFFSET) +#define NRF54L_UART2_PUBLISH_RXTO (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_RXTO_OFFSET) +#define NRF54L_UART2_PUBLISH_TXSTOPPED (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_TXSTOPPED_OFFSET) +#define NRF54L_UART2_PUBLISH_DMA_RX_END (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_END_OFFSET) +#define NRF54L_UART2_PUBLISH_DMA_RX_READY (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_READY_OFFSET) +#define NRF54L_UART2_PUBLISH_DMA_RX_BUSERROR (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART2_PUBLISH_DMA_RX_MATCH(n) (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART2_PUBLISH_DMA_TX_END (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_END_OFFSET) +#define NRF54L_UART2_PUBLISH_DMA_TX_READY (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_READY_OFFSET) +#define NRF54L_UART2_PUBLISH_DMA_TX_BUSERROR (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART2_PUBLISH_FRAMETIMEOUT (NRF54L_UART2_BASE + NRF54L_UARTE_PUBLISH_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART2_SHORTS (NRF54L_UART2_BASE + NRF54L_UARTE_SHORTS_OFFSET) +#define NRF54L_UART2_INTEN (NRF54L_UART2_BASE + NRF54L_UARTE_INTEN_OFFSET) +#define NRF54L_UART2_INTENSET (NRF54L_UART2_BASE + NRF54L_UARTE_INTENSET_OFFSET) +#define NRF54L_UART2_INTENCLR (NRF54L_UART2_BASE + NRF54L_UARTE_INTENCLR_OFFSET) +#define NRF54L_UART2_ERRORSRC (NRF54L_UART2_BASE + NRF54L_UARTE_ERRORSRC_OFFSET) +#define NRF54L_UART2_ENABLE (NRF54L_UART2_BASE + NRF54L_UARTE_ENABLE_OFFSET) +#define NRF54L_UART2_BAUDRATE (NRF54L_UART2_BASE + NRF54L_UARTE_BAUDRATE_OFFSET) +#define NRF54L_UART2_CONFIG (NRF54L_UART2_BASE + NRF54L_UARTE_CONFIG_OFFSET) +#define NRF54L_UART2_ADDRESS (NRF54L_UART2_BASE + NRF54L_UARTE_ADDRESS_OFFSET) +#define NRF54L_UART2_FRAMETIMEOUT (NRF54L_UART2_BASE + NRF54L_UARTE_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART2_PSEL_TXD (NRF54L_UART2_BASE + NRF54L_UARTE_PSEL_TXD_OFFSET) +#define NRF54L_UART2_PSEL_CTS (NRF54L_UART2_BASE + NRF54L_UARTE_PSEL_CTS_OFFSET) +#define NRF54L_UART2_PSEL_RXD (NRF54L_UART2_BASE + NRF54L_UARTE_PSEL_RXD_OFFSET) +#define NRF54L_UART2_PSEL_RTS (NRF54L_UART2_BASE + NRF54L_UARTE_PSEL_RTS_OFFSET) +#define NRF54L_UART2_DMA_RX_PTR (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_RX_PTR_OFFSET) +#define NRF54L_UART2_DMA_RX_MAXCNT (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_RX_MAXCNT_OFFSET) +#define NRF54L_UART2_DMA_RX_AMOUNT (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_RX_AMOUNT_OFFSET) +#define NRF54L_UART2_DMA_RX_LIST (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_RX_LIST_OFFSET) +#define NRF54L_UART2_DMA_RX_TERMINATEONBUSERROR (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_RX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART2_DMA_RX_BUSERRORADDRESS (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_RX_BUSERRORADDRESS_OFFSET) +#define NRF54L_UART2_DMA_RX_MATCH_CONFIG (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_RX_MATCH_CONFIG_OFFSET) +#define NRF54L_UART2_DMA_RX_MATCH_CANDIDATE(n) (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_RX_MATCH_CANDIDATE_OFFSET(n)) +#define NRF54L_UART2_DMA_TX_PTR (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_TX_PTR_OFFSET) +#define NRF54L_UART2_DMA_TX_MAXCNT (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET) +#define NRF54L_UART2_DMA_TX_AMOUNT (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_TX_AMOUNT_OFFSET) +#define NRF54L_UART2_DMA_TX_LIST (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_TX_LIST_OFFSET) +#define NRF54L_UART2_DMA_TX_TERMINATEONBUSERROR (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_TX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART2_DMA_TX_BUSERRORADDRESS (NRF54L_UART2_BASE + NRF54L_UARTE_DMA_TX_BUSERRORADDRESS_OFFSET) + +#define NRF54L_UART3_TASKS_FLUSHRX (NRF54L_UART3_BASE + NRF54L_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF54L_UART3_TASKS_STARTRX (NRF54L_UART3_BASE + NRF54L_UARTE_TASKS_STARTRX_OFFSET) +#define NRF54L_UART3_TASKS_STOPRX (NRF54L_UART3_BASE + NRF54L_UARTE_TASKS_STOPRX_OFFSET) +#define NRF54L_UART3_TASKS_DMA_RX_ENABLEMATCH(n) (NRF54L_UART3_BASE + NRF54L_UARTE_TASKS_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART3_TASKS_DMA_RX_DISABLEMATCH(n) (NRF54L_UART3_BASE + NRF54L_UARTE_TASKS_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART3_TASKS_STARTTX (NRF54L_UART3_BASE + NRF54L_UARTE_TASKS_STARTTX_OFFSET) +#define NRF54L_UART3_TASKS_STOPTX (NRF54L_UART3_BASE + NRF54L_UARTE_TASKS_STOPTX_OFFSET) +#define NRF54L_UART3_SUBSCRIBE_FLUSHRX (NRF54L_UART3_BASE + NRF54L_UARTE_SUBSCRIBE_FLUSHRX_OFFSET) +#define NRF54L_UART3_SUBSCRIBE_DMA_RX_START (NRF54L_UART3_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_START_OFFSET) +#define NRF54L_UART3_SUBSCRIBE_DMA_RX_STOP (NRF54L_UART3_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_STOP_OFFSET) +#define NRF54L_UART3_SUBSCRIBE_DMA_RX_ENABLEMATCH(n) (NRF54L_UART3_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART3_SUBSCRIBE_DMA_RX_DISABLEMATCH(n) (NRF54L_UART3_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART3_SUBSCRIBE_DMA_TX_START (NRF54L_UART3_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_START_OFFSET) +#define NRF54L_UART3_SUBSCRIBE_DMA_TX_STOP (NRF54L_UART3_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_STOP_OFFSET) +#define NRF54L_UART3_EVENTS_CTS (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_CTS_OFFSET) +#define NRF54L_UART3_EVENTS_NCTS (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_NCTS_OFFSET) +#define NRF54L_UART3_EVENTS_TXDRDY (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF54L_UART3_EVENTS_RXDRDY (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF54L_UART3_EVENTS_ERROR (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_ERROR_OFFSET) +#define NRF54L_UART3_EVENTS_RXTO (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_RXTO_OFFSET) +#define NRF54L_UART3_EVENTS_TXSTOPPED (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF54L_UART3_EVENTS_DMA_RX_END (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET) +#define NRF54L_UART3_EVENTS_DMA_RX_READY (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_DMA_RX_READY_OFFSET) +#define NRF54L_UART3_EVENTS_DMA_RX_BUSERROR (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART3_EVENTS_DMA_RX_MATCH(n) (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART3_EVENTS_DMA_TX_END (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET) +#define NRF54L_UART3_EVENTS_DMA_TX_READY (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_DMA_TX_READY_OFFSET) +#define NRF54L_UART3_EVENTS_DMA_TX_BUSERROR (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART3_EVENTS_FRAMETIMEOUT (NRF54L_UART3_BASE + NRF54L_UARTE_EVENTS_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART3_PUBLISH_CTS (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_CTS_OFFSET) +#define NRF54L_UART3_PUBLISH_NCTS (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_NCTS_OFFSET) +#define NRF54L_UART3_PUBLISH_TXDRDY (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_TXDRDY_OFFSET) +#define NRF54L_UART3_PUBLISH_RXDRDY (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_RXDRDY_OFFSET) +#define NRF54L_UART3_PUBLISH_ERROR (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_ERROR_OFFSET) +#define NRF54L_UART3_PUBLISH_RXTO (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_RXTO_OFFSET) +#define NRF54L_UART3_PUBLISH_TXSTOPPED (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_TXSTOPPED_OFFSET) +#define NRF54L_UART3_PUBLISH_DMA_RX_END (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_END_OFFSET) +#define NRF54L_UART3_PUBLISH_DMA_RX_READY (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_READY_OFFSET) +#define NRF54L_UART3_PUBLISH_DMA_RX_BUSERROR (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART3_PUBLISH_DMA_RX_MATCH(n) (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART3_PUBLISH_DMA_TX_END (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_END_OFFSET) +#define NRF54L_UART3_PUBLISH_DMA_TX_READY (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_READY_OFFSET) +#define NRF54L_UART3_PUBLISH_DMA_TX_BUSERROR (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART3_PUBLISH_FRAMETIMEOUT (NRF54L_UART3_BASE + NRF54L_UARTE_PUBLISH_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART3_SHORTS (NRF54L_UART3_BASE + NRF54L_UARTE_SHORTS_OFFSET) +#define NRF54L_UART3_INTEN (NRF54L_UART3_BASE + NRF54L_UARTE_INTEN_OFFSET) +#define NRF54L_UART3_INTENSET (NRF54L_UART3_BASE + NRF54L_UARTE_INTENSET_OFFSET) +#define NRF54L_UART3_INTENCLR (NRF54L_UART3_BASE + NRF54L_UARTE_INTENCLR_OFFSET) +#define NRF54L_UART3_ERRORSRC (NRF54L_UART3_BASE + NRF54L_UARTE_ERRORSRC_OFFSET) +#define NRF54L_UART3_ENABLE (NRF54L_UART3_BASE + NRF54L_UARTE_ENABLE_OFFSET) +#define NRF54L_UART3_BAUDRATE (NRF54L_UART3_BASE + NRF54L_UARTE_BAUDRATE_OFFSET) +#define NRF54L_UART3_CONFIG (NRF54L_UART3_BASE + NRF54L_UARTE_CONFIG_OFFSET) +#define NRF54L_UART3_ADDRESS (NRF54L_UART3_BASE + NRF54L_UARTE_ADDRESS_OFFSET) +#define NRF54L_UART3_FRAMETIMEOUT (NRF54L_UART3_BASE + NRF54L_UARTE_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART3_PSEL_TXD (NRF54L_UART3_BASE + NRF54L_UARTE_PSEL_TXD_OFFSET) +#define NRF54L_UART3_PSEL_CTS (NRF54L_UART3_BASE + NRF54L_UARTE_PSEL_CTS_OFFSET) +#define NRF54L_UART3_PSEL_RXD (NRF54L_UART3_BASE + NRF54L_UARTE_PSEL_RXD_OFFSET) +#define NRF54L_UART3_PSEL_RTS (NRF54L_UART3_BASE + NRF54L_UARTE_PSEL_RTS_OFFSET) +#define NRF54L_UART3_DMA_RX_PTR (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_RX_PTR_OFFSET) +#define NRF54L_UART3_DMA_RX_MAXCNT (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_RX_MAXCNT_OFFSET) +#define NRF54L_UART3_DMA_RX_AMOUNT (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_RX_AMOUNT_OFFSET) +#define NRF54L_UART3_DMA_RX_LIST (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_RX_LIST_OFFSET) +#define NRF54L_UART3_DMA_RX_TERMINATEONBUSERROR (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_RX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART3_DMA_RX_BUSERRORADDRESS (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_RX_BUSERRORADDRESS_OFFSET) +#define NRF54L_UART3_DMA_RX_MATCH_CONFIG (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_RX_MATCH_CONFIG_OFFSET) +#define NRF54L_UART3_DMA_RX_MATCH_CANDIDATE(n) (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_RX_MATCH_CANDIDATE_OFFSET(n)) +#define NRF54L_UART3_DMA_TX_PTR (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_TX_PTR_OFFSET) +#define NRF54L_UART3_DMA_TX_MAXCNT (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET) +#define NRF54L_UART3_DMA_TX_AMOUNT (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_TX_AMOUNT_OFFSET) +#define NRF54L_UART3_DMA_TX_LIST (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_TX_LIST_OFFSET) +#define NRF54L_UART3_DMA_TX_TERMINATEONBUSERROR (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_TX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART3_DMA_TX_BUSERRORADDRESS (NRF54L_UART3_BASE + NRF54L_UARTE_DMA_TX_BUSERRORADDRESS_OFFSET) + +#define NRF54L_UART4_TASKS_FLUSHRX (NRF54L_UART4_BASE + NRF54L_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF54L_UART4_TASKS_STARTRX (NRF54L_UART4_BASE + NRF54L_UARTE_TASKS_STARTRX_OFFSET) +#define NRF54L_UART4_TASKS_STOPRX (NRF54L_UART4_BASE + NRF54L_UARTE_TASKS_STOPRX_OFFSET) +#define NRF54L_UART4_TASKS_DMA_RX_ENABLEMATCH(n) (NRF54L_UART4_BASE + NRF54L_UARTE_TASKS_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART4_TASKS_DMA_RX_DISABLEMATCH(n) (NRF54L_UART4_BASE + NRF54L_UARTE_TASKS_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART4_TASKS_STARTTX (NRF54L_UART4_BASE + NRF54L_UARTE_TASKS_STARTTX_OFFSET) +#define NRF54L_UART4_TASKS_STOPTX (NRF54L_UART4_BASE + NRF54L_UARTE_TASKS_STOPTX_OFFSET) +#define NRF54L_UART4_SUBSCRIBE_FLUSHRX (NRF54L_UART4_BASE + NRF54L_UARTE_SUBSCRIBE_FLUSHRX_OFFSET) +#define NRF54L_UART4_SUBSCRIBE_DMA_RX_START (NRF54L_UART4_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_START_OFFSET) +#define NRF54L_UART4_SUBSCRIBE_DMA_RX_STOP (NRF54L_UART4_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_STOP_OFFSET) +#define NRF54L_UART4_SUBSCRIBE_DMA_RX_ENABLEMATCH(n) (NRF54L_UART4_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART4_SUBSCRIBE_DMA_RX_DISABLEMATCH(n) (NRF54L_UART4_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART4_SUBSCRIBE_DMA_TX_START (NRF54L_UART4_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_START_OFFSET) +#define NRF54L_UART4_SUBSCRIBE_DMA_TX_STOP (NRF54L_UART4_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_STOP_OFFSET) +#define NRF54L_UART4_EVENTS_CTS (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_CTS_OFFSET) +#define NRF54L_UART4_EVENTS_NCTS (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_NCTS_OFFSET) +#define NRF54L_UART4_EVENTS_TXDRDY (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF54L_UART4_EVENTS_RXDRDY (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF54L_UART4_EVENTS_ERROR (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_ERROR_OFFSET) +#define NRF54L_UART4_EVENTS_RXTO (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_RXTO_OFFSET) +#define NRF54L_UART4_EVENTS_TXSTOPPED (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF54L_UART4_EVENTS_DMA_RX_END (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET) +#define NRF54L_UART4_EVENTS_DMA_RX_READY (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_DMA_RX_READY_OFFSET) +#define NRF54L_UART4_EVENTS_DMA_RX_BUSERROR (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART4_EVENTS_DMA_RX_MATCH(n) (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART4_EVENTS_DMA_TX_END (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET) +#define NRF54L_UART4_EVENTS_DMA_TX_READY (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_DMA_TX_READY_OFFSET) +#define NRF54L_UART4_EVENTS_DMA_TX_BUSERROR (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART4_EVENTS_FRAMETIMEOUT (NRF54L_UART4_BASE + NRF54L_UARTE_EVENTS_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART4_PUBLISH_CTS (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_CTS_OFFSET) +#define NRF54L_UART4_PUBLISH_NCTS (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_NCTS_OFFSET) +#define NRF54L_UART4_PUBLISH_TXDRDY (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_TXDRDY_OFFSET) +#define NRF54L_UART4_PUBLISH_RXDRDY (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_RXDRDY_OFFSET) +#define NRF54L_UART4_PUBLISH_ERROR (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_ERROR_OFFSET) +#define NRF54L_UART4_PUBLISH_RXTO (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_RXTO_OFFSET) +#define NRF54L_UART4_PUBLISH_TXSTOPPED (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_TXSTOPPED_OFFSET) +#define NRF54L_UART4_PUBLISH_DMA_RX_END (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_END_OFFSET) +#define NRF54L_UART4_PUBLISH_DMA_RX_READY (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_READY_OFFSET) +#define NRF54L_UART4_PUBLISH_DMA_RX_BUSERROR (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART4_PUBLISH_DMA_RX_MATCH(n) (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART4_PUBLISH_DMA_TX_END (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_END_OFFSET) +#define NRF54L_UART4_PUBLISH_DMA_TX_READY (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_READY_OFFSET) +#define NRF54L_UART4_PUBLISH_DMA_TX_BUSERROR (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART4_PUBLISH_FRAMETIMEOUT (NRF54L_UART4_BASE + NRF54L_UARTE_PUBLISH_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART4_SHORTS (NRF54L_UART4_BASE + NRF54L_UARTE_SHORTS_OFFSET) +#define NRF54L_UART4_INTEN (NRF54L_UART4_BASE + NRF54L_UARTE_INTEN_OFFSET) +#define NRF54L_UART4_INTENSET (NRF54L_UART4_BASE + NRF54L_UARTE_INTENSET_OFFSET) +#define NRF54L_UART4_INTENCLR (NRF54L_UART4_BASE + NRF54L_UARTE_INTENCLR_OFFSET) +#define NRF54L_UART4_ERRORSRC (NRF54L_UART4_BASE + NRF54L_UARTE_ERRORSRC_OFFSET) +#define NRF54L_UART4_ENABLE (NRF54L_UART4_BASE + NRF54L_UARTE_ENABLE_OFFSET) +#define NRF54L_UART4_BAUDRATE (NRF54L_UART4_BASE + NRF54L_UARTE_BAUDRATE_OFFSET) +#define NRF54L_UART4_CONFIG (NRF54L_UART4_BASE + NRF54L_UARTE_CONFIG_OFFSET) +#define NRF54L_UART4_ADDRESS (NRF54L_UART4_BASE + NRF54L_UARTE_ADDRESS_OFFSET) +#define NRF54L_UART4_FRAMETIMEOUT (NRF54L_UART4_BASE + NRF54L_UARTE_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART4_PSEL_TXD (NRF54L_UART4_BASE + NRF54L_UARTE_PSEL_TXD_OFFSET) +#define NRF54L_UART4_PSEL_CTS (NRF54L_UART4_BASE + NRF54L_UARTE_PSEL_CTS_OFFSET) +#define NRF54L_UART4_PSEL_RXD (NRF54L_UART4_BASE + NRF54L_UARTE_PSEL_RXD_OFFSET) +#define NRF54L_UART4_PSEL_RTS (NRF54L_UART4_BASE + NRF54L_UARTE_PSEL_RTS_OFFSET) +#define NRF54L_UART4_DMA_RX_PTR (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_RX_PTR_OFFSET) +#define NRF54L_UART4_DMA_RX_MAXCNT (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_RX_MAXCNT_OFFSET) +#define NRF54L_UART4_DMA_RX_AMOUNT (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_RX_AMOUNT_OFFSET) +#define NRF54L_UART4_DMA_RX_LIST (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_RX_LIST_OFFSET) +#define NRF54L_UART4_DMA_RX_TERMINATEONBUSERROR (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_RX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART4_DMA_RX_BUSERRORADDRESS (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_RX_BUSERRORADDRESS_OFFSET) +#define NRF54L_UART4_DMA_RX_MATCH_CONFIG (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_RX_MATCH_CONFIG_OFFSET) +#define NRF54L_UART4_DMA_RX_MATCH_CANDIDATE(n) (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_RX_MATCH_CANDIDATE_OFFSET(n)) +#define NRF54L_UART4_DMA_TX_PTR (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_TX_PTR_OFFSET) +#define NRF54L_UART4_DMA_TX_MAXCNT (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET) +#define NRF54L_UART4_DMA_TX_AMOUNT (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_TX_AMOUNT_OFFSET) +#define NRF54L_UART4_DMA_TX_LIST (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_TX_LIST_OFFSET) +#define NRF54L_UART4_DMA_TX_TERMINATEONBUSERROR (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_TX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART4_DMA_TX_BUSERRORADDRESS (NRF54L_UART4_BASE + NRF54L_UARTE_DMA_TX_BUSERRORADDRESS_OFFSET) + +#define NRF54L_UART5_TASKS_FLUSHRX (NRF54L_UART5_BASE + NRF54L_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF54L_UART5_TASKS_STARTRX (NRF54L_UART5_BASE + NRF54L_UARTE_TASKS_STARTRX_OFFSET) +#define NRF54L_UART5_TASKS_STOPRX (NRF54L_UART5_BASE + NRF54L_UARTE_TASKS_STOPRX_OFFSET) +#define NRF54L_UART5_TASKS_DMA_RX_ENABLEMATCH(n) (NRF54L_UART5_BASE + NRF54L_UARTE_TASKS_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART5_TASKS_DMA_RX_DISABLEMATCH(n) (NRF54L_UART5_BASE + NRF54L_UARTE_TASKS_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART5_TASKS_STARTTX (NRF54L_UART5_BASE + NRF54L_UARTE_TASKS_STARTTX_OFFSET) +#define NRF54L_UART5_TASKS_STOPTX (NRF54L_UART5_BASE + NRF54L_UARTE_TASKS_STOPTX_OFFSET) +#define NRF54L_UART5_SUBSCRIBE_FLUSHRX (NRF54L_UART5_BASE + NRF54L_UARTE_SUBSCRIBE_FLUSHRX_OFFSET) +#define NRF54L_UART5_SUBSCRIBE_DMA_RX_START (NRF54L_UART5_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_START_OFFSET) +#define NRF54L_UART5_SUBSCRIBE_DMA_RX_STOP (NRF54L_UART5_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_STOP_OFFSET) +#define NRF54L_UART5_SUBSCRIBE_DMA_RX_ENABLEMATCH(n) (NRF54L_UART5_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART5_SUBSCRIBE_DMA_RX_DISABLEMATCH(n) (NRF54L_UART5_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART5_SUBSCRIBE_DMA_TX_START (NRF54L_UART5_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_START_OFFSET) +#define NRF54L_UART5_SUBSCRIBE_DMA_TX_STOP (NRF54L_UART5_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_STOP_OFFSET) +#define NRF54L_UART5_EVENTS_CTS (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_CTS_OFFSET) +#define NRF54L_UART5_EVENTS_NCTS (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_NCTS_OFFSET) +#define NRF54L_UART5_EVENTS_TXDRDY (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF54L_UART5_EVENTS_RXDRDY (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF54L_UART5_EVENTS_ERROR (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_ERROR_OFFSET) +#define NRF54L_UART5_EVENTS_RXTO (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_RXTO_OFFSET) +#define NRF54L_UART5_EVENTS_TXSTOPPED (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF54L_UART5_EVENTS_DMA_RX_END (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET) +#define NRF54L_UART5_EVENTS_DMA_RX_READY (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_DMA_RX_READY_OFFSET) +#define NRF54L_UART5_EVENTS_DMA_RX_BUSERROR (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART5_EVENTS_DMA_RX_MATCH(n) (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART5_EVENTS_DMA_TX_END (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET) +#define NRF54L_UART5_EVENTS_DMA_TX_READY (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_DMA_TX_READY_OFFSET) +#define NRF54L_UART5_EVENTS_DMA_TX_BUSERROR (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART5_EVENTS_FRAMETIMEOUT (NRF54L_UART5_BASE + NRF54L_UARTE_EVENTS_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART5_PUBLISH_CTS (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_CTS_OFFSET) +#define NRF54L_UART5_PUBLISH_NCTS (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_NCTS_OFFSET) +#define NRF54L_UART5_PUBLISH_TXDRDY (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_TXDRDY_OFFSET) +#define NRF54L_UART5_PUBLISH_RXDRDY (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_RXDRDY_OFFSET) +#define NRF54L_UART5_PUBLISH_ERROR (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_ERROR_OFFSET) +#define NRF54L_UART5_PUBLISH_RXTO (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_RXTO_OFFSET) +#define NRF54L_UART5_PUBLISH_TXSTOPPED (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_TXSTOPPED_OFFSET) +#define NRF54L_UART5_PUBLISH_DMA_RX_END (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_END_OFFSET) +#define NRF54L_UART5_PUBLISH_DMA_RX_READY (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_READY_OFFSET) +#define NRF54L_UART5_PUBLISH_DMA_RX_BUSERROR (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART5_PUBLISH_DMA_RX_MATCH(n) (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART5_PUBLISH_DMA_TX_END (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_END_OFFSET) +#define NRF54L_UART5_PUBLISH_DMA_TX_READY (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_READY_OFFSET) +#define NRF54L_UART5_PUBLISH_DMA_TX_BUSERROR (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART5_PUBLISH_FRAMETIMEOUT (NRF54L_UART5_BASE + NRF54L_UARTE_PUBLISH_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART5_SHORTS (NRF54L_UART5_BASE + NRF54L_UARTE_SHORTS_OFFSET) +#define NRF54L_UART5_INTEN (NRF54L_UART5_BASE + NRF54L_UARTE_INTEN_OFFSET) +#define NRF54L_UART5_INTENSET (NRF54L_UART5_BASE + NRF54L_UARTE_INTENSET_OFFSET) +#define NRF54L_UART5_INTENCLR (NRF54L_UART5_BASE + NRF54L_UARTE_INTENCLR_OFFSET) +#define NRF54L_UART5_ERRORSRC (NRF54L_UART5_BASE + NRF54L_UARTE_ERRORSRC_OFFSET) +#define NRF54L_UART5_ENABLE (NRF54L_UART5_BASE + NRF54L_UARTE_ENABLE_OFFSET) +#define NRF54L_UART5_BAUDRATE (NRF54L_UART5_BASE + NRF54L_UARTE_BAUDRATE_OFFSET) +#define NRF54L_UART5_CONFIG (NRF54L_UART5_BASE + NRF54L_UARTE_CONFIG_OFFSET) +#define NRF54L_UART5_ADDRESS (NRF54L_UART5_BASE + NRF54L_UARTE_ADDRESS_OFFSET) +#define NRF54L_UART5_FRAMETIMEOUT (NRF54L_UART5_BASE + NRF54L_UARTE_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART5_PSEL_TXD (NRF54L_UART5_BASE + NRF54L_UARTE_PSEL_TXD_OFFSET) +#define NRF54L_UART5_PSEL_CTS (NRF54L_UART5_BASE + NRF54L_UARTE_PSEL_CTS_OFFSET) +#define NRF54L_UART5_PSEL_RXD (NRF54L_UART5_BASE + NRF54L_UARTE_PSEL_RXD_OFFSET) +#define NRF54L_UART5_PSEL_RTS (NRF54L_UART5_BASE + NRF54L_UARTE_PSEL_RTS_OFFSET) +#define NRF54L_UART5_DMA_RX_PTR (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_RX_PTR_OFFSET) +#define NRF54L_UART5_DMA_RX_MAXCNT (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_RX_MAXCNT_OFFSET) +#define NRF54L_UART5_DMA_RX_AMOUNT (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_RX_AMOUNT_OFFSET) +#define NRF54L_UART5_DMA_RX_LIST (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_RX_LIST_OFFSET) +#define NRF54L_UART5_DMA_RX_TERMINATEONBUSERROR (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_RX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART5_DMA_RX_BUSERRORADDRESS (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_RX_BUSERRORADDRESS_OFFSET) +#define NRF54L_UART5_DMA_RX_MATCH_CONFIG (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_RX_MATCH_CONFIG_OFFSET) +#define NRF54L_UART5_DMA_RX_MATCH_CANDIDATE(n) (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_RX_MATCH_CANDIDATE_OFFSET(n)) +#define NRF54L_UART5_DMA_TX_PTR (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_TX_PTR_OFFSET) +#define NRF54L_UART5_DMA_TX_MAXCNT (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET) +#define NRF54L_UART5_DMA_TX_AMOUNT (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_TX_AMOUNT_OFFSET) +#define NRF54L_UART5_DMA_TX_LIST (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_TX_LIST_OFFSET) +#define NRF54L_UART5_DMA_TX_TERMINATEONBUSERROR (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_TX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART5_DMA_TX_BUSERRORADDRESS (NRF54L_UART5_BASE + NRF54L_UARTE_DMA_TX_BUSERRORADDRESS_OFFSET) + +#define NRF54L_UART6_TASKS_FLUSHRX (NRF54L_UART6_BASE + NRF54L_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF54L_UART6_TASKS_STARTRX (NRF54L_UART6_BASE + NRF54L_UARTE_TASKS_STARTRX_OFFSET) +#define NRF54L_UART6_TASKS_STOPRX (NRF54L_UART6_BASE + NRF54L_UARTE_TASKS_STOPRX_OFFSET) +#define NRF54L_UART6_TASKS_DMA_RX_ENABLEMATCH(n) (NRF54L_UART6_BASE + NRF54L_UARTE_TASKS_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART6_TASKS_DMA_RX_DISABLEMATCH(n) (NRF54L_UART6_BASE + NRF54L_UARTE_TASKS_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART6_TASKS_STARTTX (NRF54L_UART6_BASE + NRF54L_UARTE_TASKS_STARTTX_OFFSET) +#define NRF54L_UART6_TASKS_STOPTX (NRF54L_UART6_BASE + NRF54L_UARTE_TASKS_STOPTX_OFFSET) +#define NRF54L_UART6_SUBSCRIBE_FLUSHRX (NRF54L_UART6_BASE + NRF54L_UARTE_SUBSCRIBE_FLUSHRX_OFFSET) +#define NRF54L_UART6_SUBSCRIBE_DMA_RX_START (NRF54L_UART6_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_START_OFFSET) +#define NRF54L_UART6_SUBSCRIBE_DMA_RX_STOP (NRF54L_UART6_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_STOP_OFFSET) +#define NRF54L_UART6_SUBSCRIBE_DMA_RX_ENABLEMATCH(n) (NRF54L_UART6_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_OFFSET(n)) +#define NRF54L_UART6_SUBSCRIBE_DMA_RX_DISABLEMATCH(n) (NRF54L_UART6_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_OFFSET(n)) +#define NRF54L_UART6_SUBSCRIBE_DMA_TX_START (NRF54L_UART6_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_START_OFFSET) +#define NRF54L_UART6_SUBSCRIBE_DMA_TX_STOP (NRF54L_UART6_BASE + NRF54L_UARTE_SUBSCRIBE_DMA_TX_STOP_OFFSET) +#define NRF54L_UART6_EVENTS_CTS (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_CTS_OFFSET) +#define NRF54L_UART6_EVENTS_NCTS (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_NCTS_OFFSET) +#define NRF54L_UART6_EVENTS_TXDRDY (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF54L_UART6_EVENTS_RXDRDY (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF54L_UART6_EVENTS_ERROR (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_ERROR_OFFSET) +#define NRF54L_UART6_EVENTS_RXTO (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_RXTO_OFFSET) +#define NRF54L_UART6_EVENTS_TXSTOPPED (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF54L_UART6_EVENTS_DMA_RX_END (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET) +#define NRF54L_UART6_EVENTS_DMA_RX_READY (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_DMA_RX_READY_OFFSET) +#define NRF54L_UART6_EVENTS_DMA_RX_BUSERROR (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART6_EVENTS_DMA_RX_MATCH(n) (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART6_EVENTS_DMA_TX_END (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET) +#define NRF54L_UART6_EVENTS_DMA_TX_READY (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_DMA_TX_READY_OFFSET) +#define NRF54L_UART6_EVENTS_DMA_TX_BUSERROR (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART6_EVENTS_FRAMETIMEOUT (NRF54L_UART6_BASE + NRF54L_UARTE_EVENTS_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART6_PUBLISH_CTS (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_CTS_OFFSET) +#define NRF54L_UART6_PUBLISH_NCTS (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_NCTS_OFFSET) +#define NRF54L_UART6_PUBLISH_TXDRDY (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_TXDRDY_OFFSET) +#define NRF54L_UART6_PUBLISH_RXDRDY (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_RXDRDY_OFFSET) +#define NRF54L_UART6_PUBLISH_ERROR (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_ERROR_OFFSET) +#define NRF54L_UART6_PUBLISH_RXTO (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_RXTO_OFFSET) +#define NRF54L_UART6_PUBLISH_TXSTOPPED (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_TXSTOPPED_OFFSET) +#define NRF54L_UART6_PUBLISH_DMA_RX_END (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_END_OFFSET) +#define NRF54L_UART6_PUBLISH_DMA_RX_READY (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_READY_OFFSET) +#define NRF54L_UART6_PUBLISH_DMA_RX_BUSERROR (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_BUSERROR_OFFSET) +#define NRF54L_UART6_PUBLISH_DMA_RX_MATCH(n) (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_DMA_RX_MATCH_OFFSET(n)) +#define NRF54L_UART6_PUBLISH_DMA_TX_END (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_END_OFFSET) +#define NRF54L_UART6_PUBLISH_DMA_TX_READY (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_READY_OFFSET) +#define NRF54L_UART6_PUBLISH_DMA_TX_BUSERROR (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_DMA_TX_BUSERROR_OFFSET) +#define NRF54L_UART6_PUBLISH_FRAMETIMEOUT (NRF54L_UART6_BASE + NRF54L_UARTE_PUBLISH_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART6_SHORTS (NRF54L_UART6_BASE + NRF54L_UARTE_SHORTS_OFFSET) +#define NRF54L_UART6_INTEN (NRF54L_UART6_BASE + NRF54L_UARTE_INTEN_OFFSET) +#define NRF54L_UART6_INTENSET (NRF54L_UART6_BASE + NRF54L_UARTE_INTENSET_OFFSET) +#define NRF54L_UART6_INTENCLR (NRF54L_UART6_BASE + NRF54L_UARTE_INTENCLR_OFFSET) +#define NRF54L_UART6_ERRORSRC (NRF54L_UART6_BASE + NRF54L_UARTE_ERRORSRC_OFFSET) +#define NRF54L_UART6_ENABLE (NRF54L_UART6_BASE + NRF54L_UARTE_ENABLE_OFFSET) +#define NRF54L_UART6_BAUDRATE (NRF54L_UART6_BASE + NRF54L_UARTE_BAUDRATE_OFFSET) +#define NRF54L_UART6_CONFIG (NRF54L_UART6_BASE + NRF54L_UARTE_CONFIG_OFFSET) +#define NRF54L_UART6_ADDRESS (NRF54L_UART6_BASE + NRF54L_UARTE_ADDRESS_OFFSET) +#define NRF54L_UART6_FRAMETIMEOUT (NRF54L_UART6_BASE + NRF54L_UARTE_FRAMETIMEOUT_OFFSET) +#define NRF54L_UART6_PSEL_TXD (NRF54L_UART6_BASE + NRF54L_UARTE_PSEL_TXD_OFFSET) +#define NRF54L_UART6_PSEL_CTS (NRF54L_UART6_BASE + NRF54L_UARTE_PSEL_CTS_OFFSET) +#define NRF54L_UART6_PSEL_RXD (NRF54L_UART6_BASE + NRF54L_UARTE_PSEL_RXD_OFFSET) +#define NRF54L_UART6_PSEL_RTS (NRF54L_UART6_BASE + NRF54L_UARTE_PSEL_RTS_OFFSET) +#define NRF54L_UART6_DMA_RX_PTR (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_RX_PTR_OFFSET) +#define NRF54L_UART6_DMA_RX_MAXCNT (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_RX_MAXCNT_OFFSET) +#define NRF54L_UART6_DMA_RX_AMOUNT (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_RX_AMOUNT_OFFSET) +#define NRF54L_UART6_DMA_RX_LIST (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_RX_LIST_OFFSET) +#define NRF54L_UART6_DMA_RX_TERMINATEONBUSERROR (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_RX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART6_DMA_RX_BUSERRORADDRESS (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_RX_BUSERRORADDRESS_OFFSET) +#define NRF54L_UART6_DMA_RX_MATCH_CONFIG (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_RX_MATCH_CONFIG_OFFSET) +#define NRF54L_UART6_DMA_RX_MATCH_CANDIDATE(n) (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_RX_MATCH_CANDIDATE_OFFSET(n)) +#define NRF54L_UART6_DMA_TX_PTR (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_TX_PTR_OFFSET) +#define NRF54L_UART6_DMA_TX_MAXCNT (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET) +#define NRF54L_UART6_DMA_TX_AMOUNT (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_TX_AMOUNT_OFFSET) +#define NRF54L_UART6_DMA_TX_LIST (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_TX_LIST_OFFSET) +#define NRF54L_UART6_DMA_TX_TERMINATEONBUSERROR (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_TX_TERMINATEONBUSERROR_OFFSET) +#define NRF54L_UART6_DMA_TX_BUSERRORADDRESS (NRF54L_UART6_BASE + NRF54L_UARTE_DMA_TX_BUSERRORADDRESS_OFFSET) + +/* Register bit definitions *************************************************/ + +/* SHORTS Register */ + +#define UARTE_SHORTS_DMA_RX_END_START (1 << 5) +#define UARTE_SHORTS_DMA_RX_END_STOP (1 << 6) +#define UARTE_SHORTS_DMA_TX_END_STOP (1 << 18) +#define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 (1 << 21) +#define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 (1 << 22) +#define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 (1 << 23) +#define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 (1 << 24) +#define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 (1 << 25) +#define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 (1 << 26) +#define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 (1 << 27) +#define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 (1 << 28) +#define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP (1 << 29) + +/* INTEN/INTENSET/INTENCLR Register */ + +#define UARTE_INT_CTS (1 << 0) +#define UARTE_INT_NCTS (1 << 1) +#define UARTE_INT_TXDRDY (1 << 3) +#define UARTE_INT_RXDRDY (1 << 4) +#define UARTE_INT_ERROR (1 << 5) +#define UARTE_INT_RXTO (1 << 9) +#define UARTE_INT_TXSTOPPED (1 << 12) +#define UARTE_INT_DMA_RX_END (1 << 19) +#define UARTE_INT_DMA_RX_READY (1 << 20) +#define UARTE_INT_DMA_RX_BUSERROR (1 << 21) +#define UARTE_INT_DMA_RX_MATCH0 (1 << 22) +#define UARTE_INT_DMA_RX_MATCH1 (1 << 23) +#define UARTE_INT_DMA_RX_MATCH2 (1 << 24) +#define UARTE_INT_DMA_RX_MATCH3 (1 << 25) +#define UARTE_INT_DMA_TX_END (1 << 26) +#define UARTE_INT_DMA_TX_READY (1 << 27) +#define UARTE_INT_DMA_TX_BUSERROR (1 << 28) +#define UARTE_INT_FRAMETIMEOUT (1 << 29) + +/* ERRORSRC Register */ + +#define UARTE_ERRORSRC_OVERRUN (1 << 0) +#define UARTE_ERRORSRC_PARITY (1 << 1) +#define UARTE_ERRORSRC_FRAMING (1 << 2) +#define UARTE_ERRORSRC_BREAK (1 << 3) + +/* ENABLE Register */ + +#define UARTE_ENABLE_DISABLE (0) +#define UARTE_ENABLE_ENABLE (8) + +/* BAUDRATE Register */ + +#define UARTE_BAUDRATE_1200 (0x0004f000) +#define UARTE_BAUDRATE_2400 (0x0009d000) +#define UARTE_BAUDRATE_4800 (0x0013b000) +#define UARTE_BAUDRATE_9600 (0x00275000) +#define UARTE_BAUDRATE_14400 (0x003af000) +#define UARTE_BAUDRATE_19200 (0x004ea000) +#define UARTE_BAUDRATE_28800 (0x0075c000) +#define UARTE_BAUDRATE_31250 (0x00800000) +#define UARTE_BAUDRATE_38400 (0x009d0000) +#define UARTE_BAUDRATE_56000 (0x00e50000) +#define UARTE_BAUDRATE_57600 (0x00eb0000) +#define UARTE_BAUDRATE_76800 (0x013a9000) +#define UARTE_BAUDRATE_115200 (0x01d60000) +#define UARTE_BAUDRATE_230400 (0x03b00000) +#define UARTE_BAUDRATE_250000 (0x04000000) +#define UARTE_BAUDRATE_460800 (0x07400000) +#define UARTE_BAUDRATE_921600 (0x0f000000) +#define UARTE_BAUDRATE_1000000 (0x10000000) + +/* CONFIG Register */ + +#define UARTE_CONFIG_HWFC (1 << 0) +#define UARTE_CONFIG_PARITY_SHIFT (1) +#define UARTE_CONFIG_PARITY_MASK (7 << UARTE_CONFIG_PARITY_SHIFT) +# define UARTE_CONFIG_PARITY_EXCLUDED (0 << UARTE_CONFIG_PARITY_SHIFT) +# define UARTE_CONFIG_PARITY_INCLUDED (7 << UARTE_CONFIG_PARITY_SHIFT) +#define UARTE_CONFIG_STOP (1 << 4) +#define UARTE_CONFIG_PARITYTYPE (1 << 8) +#define UARTE_CONFIG_FRAMESIZE_SHIFT (9) +#define UARTE_CONFIG_FRAMESIZE_MASK (0xf << UARTE_CONFIG_FRAMESIZE_SHIFT) +# define UARTE_CONFIG_FRAMESIZE_4BIT (4 << UARTE_CONFIG_FRAMESIZE_SHIFT) +# define UARTE_CONFIG_FRAMESIZE_5BIT (5 << UARTE_CONFIG_FRAMESIZE_SHIFT) +# define UARTE_CONFIG_FRAMESIZE_6BIT (6 << UARTE_CONFIG_FRAMESIZE_SHIFT) +# define UARTE_CONFIG_FRAMESIZE_7BIT (7 << UARTE_CONFIG_FRAMESIZE_SHIFT) +# define UARTE_CONFIG_FRAMESIZE_8BIT (8 << UARTE_CONFIG_FRAMESIZE_SHIFT) +# define UARTE_CONFIG_FRAMESIZE_9BIT (9 << UARTE_CONFIG_FRAMESIZE_SHIFT) +#define UARTE_CONFIG_ENDIAN (1 << 13) +#define UARTE_CONFIG_FRAMETIMEOUT (1 << 14) + +/* ADDRESS Register */ + +#define UARTE_ADDRESS_SHIFT (0) +#define UARTE_ADDRESS_MASK (0xff << UARTE_ADDRESS_SHIFT) + +/* FRAMETIMEOUT Register */ + +#define UARTE_FRAMETIMEOUT_SHIFT (0) +#define UARTE_FRAMETIMEOUT_MASK (0x3ff << UARTE_FRAMETIMEOUT_SHIFT) + +/* PSEL_TXD Register */ + +#define UARTE_PSEL_TXD_PIN_SHIFT (0) +#define UARTE_PSEL_TXD_PIN_MASK (0x1f << UARTE_PSEL_TXD_PIN_SHIFT) +#define UARTE_PSEL_TXD_PORT_SHIFT (5) +#define UARTE_PSEL_TXD_PORT_MASK (7 << UARTE_PSEL_TXD_PORT_SHIFT) +#define UARTE_PSEL_TXD_CONNECT (1 << 31) +#define UARTE_PSEL_TXD_RESET (0xffffffff) + +/* PSEL_RXD Register */ + +#define UARTE_PSEL_RXD_PIN_SHIFT (0) +#define UARTE_PSEL_RXD_PIN_MASK (0x1f << UARTE_PSEL_RXD_PIN_SHIFT) +#define UARTE_PSEL_RXD_PORT_SHIFT (5) +#define UARTE_PSEL_RXD_PORT_MASK (7 << UARTE_PSEL_RXD_PORT_SHIFT) +#define UARTE_PSEL_RXD_CONNECT (1 << 31) +#define UARTE_PSEL_RXD_RESET (0xffffffff) + +/* PSEL_CTS Register */ + +#define UARTE_PSEL_CTS_PIN_SHIFT (0) +#define UARTE_PSEL_CTS_PIN_MASK (0x1f << UARTE_PSEL_CTS_PIN_SHIFT) +#define UARTE_PSEL_CTS_PORT_SHIFT (5) +#define UARTE_PSEL_CTS_PORT_MASK (7 << UARTE_PSEL_CTS_PORT_SHIFT) +#define UARTE_PSEL_CTS_CONNECT (1 << 31) +#define UARTE_PSEL_CTS_RESET (0xffffffff) + +/* PSEL_RTS Register */ + +#define UARTE_PSEL_RTS_PIN_SHIFT (0) +#define UARTE_PSEL_RTS_PIN_MASK (0x1f << UARTE_PSEL_RTS_PIN_SHIFT) +#define UARTE_PSEL_RTS_PORT_SHIFT (5) +#define UARTE_PSEL_RTS_PORT_MASK (7 << UARTE_PSEL_RTS_PORT_SHIFT) +#define UARTE_PSEL_RTS_CONNECT (1 << 31) +#define UARTE_PSEL_RTS_RESET (0xffffffff) + +/* DMA_RX_MAXCNT Register */ + +#define UARTE_DMA_RX_MAXCNT_SHIFT (0) +#define UARTE_DMA_RX_MAXCNT_MASK (0xffff << UARTE_DMA_RX_MAXCNT_SHIFT) + +/* DMA_RX_AMOUNT Register */ + +#define UARTE_DMA_RX_AMOUNT_SHIFT (0) +#define UARTE_DMA_RX_AMOUNT_MASK (0xffff << UARTE_DMA_RX_AMOUNT_SHIFT) + +/* DMA_RX_LIST Register */ + +#define UARTE_DMA_RX_LIST_TYPE_SHIFT (0) +#define UARTE_DMA_RX_LIST_TYPE_MASK (7 << UARTE_DMA_RX_LIST_TYPE_SHIFT) +# define UARTE_DMA_RX_LIST_TYPE_DISABLED (0 << UARTE_DMA_RX_LIST_TYPE_SHIFT) +# define UARTE_DMA_RX_LIST_TYPE_ARRAYLIST (1 << UARTE_DMA_RX_LIST_TYPE_SHIFT) + +/* DMA_RX_TERMINATEONBUSERROR Register */ + +#define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE (1 << 0) + +/* DMA_TX_MAXCNT Register */ + +#define UARTE_DMA_TX_MAXCNT_SHIFT (0) +#define UARTE_DMA_TX_MAXCNT_MASK (0xffff << UARTE_DMA_TX_MAXCNT_SHIFT) + +/* DMA_TX_AMOUNT Register */ + +#define UARTE_DMA_TX_AMOUNT_SHIFT (0) +#define UARTE_DMA_TX_AMOUNT_MASK (0xffff << UARTE_DMA_TX_AMOUNT_SHIFT) + +/* DMA_TX_LIST Register */ + +#define UARTE_DMA_TX_LIST_TYPE_SHIFT (0) +#define UARTE_DMA_TX_LIST_TYPE_MASK (7 << UARTE_DMA_TX_LIST_TYPE_SHIFT) +# define UARTE_DMA_TX_LIST_TYPE_DISABLED (0 << UARTE_DMA_TX_LIST_TYPE_SHIFT) +# define UARTE_DMA_TX_LIST_TYPE_ARRAYLIST (1 << UARTE_DMA_TX_LIST_TYPE_SHIFT) + +/* DMA_TX_TERMINATEONBUSERROR Register */ + +#define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE (1 << 0) + +/* DMA_RX_MATCH_CONFIG Register */ + +#define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0 (1 << 0) +#define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1 (1 << 1) +#define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2 (1 << 2) +#define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3 (1 << 3) +#define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0 (1 << 16) +#define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1 (1 << 17) +#define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2 (1 << 18) +#define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3 (1 << 19) + +/* DMA_RX_MATCH_CANDIDATE Register */ + +#define UARTE_DMA_RX_MATCH_CANDIDATE_DATA_SHIFT (0) +#define UARTE_DMA_RX_MATCH_CANDIDATE_DATA_MASK (0xff << UARTE_DMA_RX_MATCH_CANDIDATE_DATA_SHIFT) + +/* SUBSCRIBE/PUBLISH Registers */ + +#define UARTE_DPPI_CHIDX_SHIFT (0) +#define UARTE_DPPI_CHIDX_MASK (0xff << UARTE_DPPI_CHIDX_SHIFT) +#define UARTE_DPPI_ENABLE (1 << 31) + +#endif /* __ARCH_ARM_SRC_NRF54L_HARDWARE_NRF54L_UARTE_H */ diff --git a/arch/arm/src/nrf54l/nrf54l_allocateheap.c b/arch/arm/src/nrf54l/nrf54l_allocateheap.c new file mode 100644 index 00000000000..d2a4bfa27fb --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_allocateheap.c @@ -0,0 +1,195 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_allocateheap.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* .bss and .data is always positioned in internal SRAM. The remaining SRAM + * after the static .bss, .data, and IDLE stack allocations are always added + * to the heap. + */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* _sbss is the start of the BSS region (see the linker script) _ebss is the + * end of the BSS region (see the linker script). The idle task stack starts + * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE + * thread is the thread that the system boots on and, eventually, becomes the + * idle, do nothing task that runs only when there is nothing else to run. + * The heap continues from there until the configured end of memory. + * g_idle_topstack is the beginning of this heap region (not necessarily + * aligned). + */ + +const uintptr_t g_idle_topstack = (uintptr_t)_ebss + + CONFIG_IDLETHREAD_STACKSIZE; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap/up_allocate_kheap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * - For the normal "flat" build, this function returns the size of the + * single heap. + * - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function + * provides the size of the unprotected, user-space heap. + * - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides + * the size of the protected, kernel-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated by an analogous up_allocate_kheap(). A custom version of this + * file is needed if memory protection of the kernel heap is required. + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +void up_allocate_kheap(void **heap_start, size_t *heap_size) +#else +void up_allocate_heap(void **heap_start, size_t *heap_size) +#endif +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)ubase; + *heap_size = usize; +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * the kernel-space heap. A custom version of this function is needed if + * memory protection of the kernel heap is required. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif + +/**************************************************************************** + * Name: arm_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void arm_addregion(void) +{ +} +#endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/arch/arm/src/nrf54l/nrf54l_clockconfig.c b/arch/arm/src/nrf54l/nrf54l_clockconfig.c new file mode 100644 index 00000000000..0bb851268fc --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_clockconfig.c @@ -0,0 +1,169 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_clockconfig.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/nrf54l_clock.h" +#include "hardware/nrf54l_ficr.h" +#include "hardware/nrf54l_kmu.h" +#include "hardware/nrf54l_osc.h" +#include "hardware/nrf54l_tampc.h" +#include "nrf54l_clockconfig.h" +#include "nrf54l_oscconfig.h" + +/* Factory trim and startup errata follow Nordic's system_nrf54l.c. + * See the port documentation for the exact reference revision. + */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_NRF54L_DEBUG_ACCESS +/**************************************************************************** + * Name: nrf54l_debug_open + * + * Description: + * Enable debug access unless an earlier boot stage locked protection. + * + ****************************************************************************/ + +static void nrf54l_debug_open(uintptr_t addr) +{ + /* Respect a protection signal already locked by an earlier boot stage. */ + + if ((getreg32(addr) & TAMPC_LOCKED) == 0) + { + putreg32(TAMPC_UNLOCK, addr); + putreg32(TAMPC_OPEN, addr); + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_clockconfig + * + * Description: + * Apply factory trim and startup errata, then start the high-speed clock. + * + ****************************************************************************/ + +void nrf54l_clockconfig(void) +{ + uint32_t addr; + uint32_t part; + uint32_t variant; + unsigned int i; + +#ifndef CONFIG_ARCH_CHIP_NRF54L15 + /* Start the LM20 KMU boot preparation before applying factory trim. */ + + (void)getreg32(NRF54L_KMU_STATUS); +#endif + + part = getreg32(NRF54L_FICR_PART); + variant = getreg32(NRF54L_FICR_VARIANT); + + /* Anomaly 37 applies to L15 and LM20A, and LM20B revision 1 onward. */ + + if (part == 0x1c || part == 0x29 || (part == 0x33 && variant != 0)) + { + putreg32(1, NRF54L_TAD_BASE + 0x040c); + } + +#ifdef CONFIG_NRF54L_DEBUG_ACCESS + nrf54l_debug_open(NRF54L_TAMPC_DBGEN); + nrf54l_debug_open(NRF54L_TAMPC_NIDEN); + nrf54l_debug_open(NRF54L_TAMPC_SPIDEN); + nrf54l_debug_open(NRF54L_TAMPC_SPNIDEN); + nrf54l_debug_open(NRF54L_TAMPC_AP_DBGEN); +#endif + + for (i = 0; i < 64; i++) + { + addr = getreg32(NRF54L_FICR_TRIM_ADDR(i)); + if (addr == UINT32_MAX || addr == 0) + { + break; + } + + putreg32(getreg32(NRF54L_FICR_TRIM_DATA(i)), addr); + } + + /* L15 revision 1 startup anomalies 31, 32 and 40. */ + + if (part == 0x1c && variant == 1) + { + putreg32(0x040a0078, 0x5008a7ac); + putreg32(20 | (1 << 5), 0x50120624); + modifyreg32(0x5012063c, 1 << 19, 0); + if (getreg32(NRF54L_FICR_BASE + 0x334) <= 0x180a1d00) + { + putreg32(0x1ea9e040, 0x50120640); + } + } + + /* Configure oscillators */ + + nrf54l_oscconfig(); + + putreg32(OSC_PLL_FREQ_128M, NRF54L_OSC_PLL_FREQ); + putreg32(0, NRF54L_CLOCK_EVENTS_XOSTARTED); + putreg32(1, NRF54L_CLOCK_TASKS_XOSTART); + + for (i = 0; i < 10000000; i++) + { + if (getreg32(NRF54L_CLOCK_EVENTS_XOSTARTED) != 0) + { + break; + } + } + + if (i == 10000000) + { + PANIC(); + } + +#ifndef CONFIG_ARCH_CHIP_NRF54L15 + for (i = 0; i < 10000000 && getreg32(NRF54L_KMU_STATUS) == 1; i++) + { + } + + if (i == 10000000) + { + PANIC(); + } +#endif +} diff --git a/arch/arm/src/nrf54l/nrf54l_clockconfig.h b/arch/arm/src/nrf54l/nrf54l_clockconfig.h new file mode 100644 index 00000000000..d8fe359a608 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_clockconfig.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_clockconfig.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_NRF54L_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_NRF54L_NRF54L_CLOCKCONFIG_H + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_clockconfig + * + * Description: + * Apply factory trim and configure the high-speed system clock. + * + ****************************************************************************/ + +void nrf54l_clockconfig(void); + +#endif /* __ARCH_ARM_SRC_NRF54L_NRF54L_CLOCKCONFIG_H */ diff --git a/arch/arm/src/nrf54l/nrf54l_config.h b/arch/arm/src/nrf54l/nrf54l_config.h new file mode 100644 index 00000000000..66b7c0e0110 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_config.h @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_config.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_NRF54L_CONFIG_H +#define __ARCH_ARM_SRC_NRF54L_NRF54L_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* UART configuration *******************************************************/ + +#undef HAVE_UART_DEVICE +#undef HAVE_UART_CONSOLE + +#ifdef CONFIG_NRF54L_UART +# define HAVE_UART_DEVICE 1 +#endif + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && \ + defined(CONFIG_NRF54L_UART0) +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && \ + defined(CONFIG_NRF54L_UART1) +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && \ + defined(CONFIG_NRF54L_UART2) +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && \ + defined(CONFIG_NRF54L_UART3) +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && \ + defined(CONFIG_NRF54L_UART4) +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && \ + defined(CONFIG_NRF54L_UART5) +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART6_SERIAL_CONSOLE) && \ + defined(CONFIG_NRF54L_UART6) +# define HAVE_UART_CONSOLE 1 +#endif + +#endif /* __ARCH_ARM_SRC_NRF54L_NRF54L_CONFIG_H */ diff --git a/arch/arm/src/nrf54l/nrf54l_gpio.c b/arch/arm/src/nrf54l/nrf54l_gpio.c new file mode 100644 index 00000000000..c81c9ae5e26 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_gpio.c @@ -0,0 +1,500 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/nrf54l_gpio.h" +#include "nrf54l_gpio.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_nrf54l_gpio_lock = SP_UNLOCKED; + +static const uint8_t g_gpiopins[NRF54L_GPIO_NPORTS] = NRF54L_GPIO_PIN_COUNTS; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_gpio_regget + * + * Description: + * Get a register address for given GPIO port and register offset + * + ****************************************************************************/ + +static inline uint32_t nrf54l_gpio_regget(int port, uint32_t offset) +{ + uint32_t base = 0; + + /* Get base address for port */ + + if (port == 0) + { + base = NRF54L_GPIO_P0_BASE; + } + else if (port == 1) + { + base = NRF54L_GPIO_P1_BASE; + } + else if (port == 2) + { + base = NRF54L_GPIO_P2_BASE; + } + else if (port == 3) + { + base = NRF54L_GPIO_P3_BASE; + } + + return (base + offset); +} + +/**************************************************************************** + * Name: nrf54l_gpio_input + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void nrf54l_gpio_input(unsigned int port, unsigned int pin) +{ + uint32_t offset; + + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_DIRCLR_OFFSET); + + /* Configure the pin as an input */ + + putreg32(1 << pin, offset); + + /* Enable input buffer */ + + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_PIN_CNF_OFFSET(pin)); + modifyreg32(offset, GPIO_CNF_INPUT | GPIO_CNF_CTRLSEL_MASK, 0); +} + +/**************************************************************************** + * Name: nrf54l_gpio_output + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void nrf54l_gpio_output(nrf54l_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t offset; + + /* Disable input buffer */ + + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_PIN_CNF_OFFSET(pin)); + modifyreg32(offset, 0, GPIO_CNF_INPUT); + + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_DIRSET_OFFSET); + + nrf54l_gpio_write(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); + + /* Configure the pin as an output */ + + putreg32(1 << pin, offset); +} + +/**************************************************************************** + * Name: nrf54l_gpio_mode + * + * Description: + * Configure a GPIO mode based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void nrf54l_gpio_mode(nrf54l_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t mode; + uint32_t regval; + uint32_t offset; + + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_PIN_CNF_OFFSET(pin)); + + mode = cfgset & GPIO_MODE_MASK; + + regval = getreg32(offset); + regval &= ~GPIO_CNF_PULL_MASK; + + if (mode == GPIO_PULLUP) + { + regval |= GPIO_CNF_PULL_UP; + } + else if (mode == GPIO_PULLDOWN) + { + regval |= GPIO_CNF_PULL_DOWN; + } + + putreg32(regval, offset); +} + +/**************************************************************************** + * Name: nrf54l_gpio_sense + * + * Description: + * Set SENSE configuration for an input pin + * + ****************************************************************************/ + +static inline void nrf54l_gpio_sense(nrf54l_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t mode; + uint32_t regval; + uint32_t offset; + + mode = cfgset & GPIO_SENSE_MASK; + + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_PIN_CNF_OFFSET(pin)); + regval = getreg32(offset); + + regval &= ~GPIO_CNF_SENSE_MASK; + + if (mode == GPIO_SENSE_HIGH) + { + regval |= GPIO_CNF_SENSE_HIGH; + } + else if (mode == GPIO_SENSE_LOW) + { + regval |= GPIO_CNF_SENSE_LOW; + } + + putreg32(regval, offset); +} + +/**************************************************************************** + * Name: nrf54l_gpio_drive + * + * Description: + * Set DRIVE configuration for a pin + * + ****************************************************************************/ + +static inline void nrf54l_gpio_drive(nrf54l_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t drive; + uint32_t regval; + uint32_t offset; + + drive = cfgset & GPIO_DRIVE_MASK; + + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_PIN_CNF_OFFSET(pin)); + regval = getreg32(offset); + + regval &= ~(GPIO_CNF_DRIVE0_MASK | GPIO_CNF_DRIVE1_MASK); + + switch (drive) + { + case GPIO_DRIVE_S0S1: + regval |= GPIO_CNF_DRIVE0_STANDARD | GPIO_CNF_DRIVE1_STANDARD; + break; + case GPIO_DRIVE_S0H1: + regval |= GPIO_CNF_DRIVE0_STANDARD | GPIO_CNF_DRIVE1_HIGH; + break; + case GPIO_DRIVE_S0D1: + regval |= GPIO_CNF_DRIVE0_STANDARD | GPIO_CNF_DRIVE1_DISCONNECT; + break; + case GPIO_DRIVE_H0D1: + regval |= GPIO_CNF_DRIVE0_HIGH | GPIO_CNF_DRIVE1_DISCONNECT; + break; + case GPIO_DRIVE_H0H1: + regval |= GPIO_CNF_DRIVE0_HIGH | GPIO_CNF_DRIVE1_HIGH; + break; + case GPIO_DRIVE_H0S1: + regval |= GPIO_CNF_DRIVE0_HIGH | GPIO_CNF_DRIVE1_STANDARD; + break; + case GPIO_DRIVE_D0H1: + regval |= GPIO_CNF_DRIVE0_DISCONNECT | GPIO_CNF_DRIVE1_HIGH; + break; + case GPIO_DRIVE_D0S1: + regval |= GPIO_CNF_DRIVE0_DISCONNECT | GPIO_CNF_DRIVE1_STANDARD; + break; + case GPIO_DRIVE_EOS1: + regval |= GPIO_CNF_DRIVE0_EXTRA | GPIO_CNF_DRIVE1_STANDARD; + break; + case GPIO_DRIVE_SOE1: + regval |= GPIO_CNF_DRIVE0_STANDARD | GPIO_CNF_DRIVE1_EXTRA; + break; + case GPIO_DRIVE_EOE1: + regval |= GPIO_CNF_DRIVE0_EXTRA | GPIO_CNF_DRIVE1_EXTRA; + break; + case GPIO_DRIVE_DOE1: + regval |= GPIO_CNF_DRIVE0_DISCONNECT | GPIO_CNF_DRIVE1_EXTRA; + break; + case GPIO_DRIVE_EOD1: + regval |= GPIO_CNF_DRIVE0_EXTRA | GPIO_CNF_DRIVE1_DISCONNECT; + break; + } + + putreg32(regval, offset); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int nrf54l_gpio_config(nrf54l_pinset_t cfgset) +{ + unsigned int port = 0; + unsigned int pin; + irqstate_t flags; + int ret = OK; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pin = GPIO_PIN_DECODE(cfgset); + + if (port >= NRF54L_GPIO_NPORTS || pin >= g_gpiopins[port] || + (cfgset & GPIO_DRIVE_MASK) > GPIO_DRIVE_EOD1 || + (cfgset & GPIO_FUNC_MASK) > GPIO_OUTPUT || + (port == 2 && (cfgset & GPIO_SENSE_MASK) != GPIO_SENSE_NONE)) + { + return -EINVAL; + } + + if (port < NRF54L_GPIO_NPORTS) + { + /* Get the pin number and select the port configuration register for + * that pin. + */ + + pin = GPIO_PIN_DECODE(cfgset); + + flags = spin_lock_irqsave(&g_nrf54l_gpio_lock); + + /* First, configure the port as a generic input so that we have a + * known starting point and consistent behavior during the re- + * configuration. + */ + + nrf54l_gpio_input(port, pin); + + /* Set the mode bits */ + + nrf54l_gpio_mode(cfgset, port, pin); + + /* Set the drive bits (needed also for input pins + * for some peripherals). + */ + + nrf54l_gpio_drive(cfgset, port, pin); + + /* Handle according to pin function */ + + switch (cfgset & GPIO_FUNC_MASK) + { + case GPIO_INPUT: /* GPIO input pin */ + nrf54l_gpio_sense(cfgset, port, pin); + break; + + case GPIO_OUTPUT: /* GPIO output pin */ + nrf54l_gpio_sense(cfgset & ~GPIO_SENSE_MASK, port, pin); + nrf54l_gpio_output(cfgset, port, pin); + break; + + default: + ret = -EINVAL; + } + + spin_unlock_irqrestore(&g_nrf54l_gpio_lock, flags); + } + else + { + ret = -EINVAL; + } + + return ret; +} + +/**************************************************************************** + * Name: nrf54l_gpio_unconfig + * + * Description: + * Unconfigure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int nrf54l_gpio_unconfig(nrf54l_pinset_t cfgset) +{ + unsigned int pin; + unsigned int port = 0; + uint32_t offset; + + /* Get port and pin number */ + + pin = GPIO_PIN_DECODE(cfgset); + port = GPIO_PORT_DECODE(cfgset); + + if (port >= NRF54L_GPIO_NPORTS || pin >= g_gpiopins[port]) + { + return -EINVAL; + } + + /* Get address offset */ + + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_PIN_CNF_OFFSET(pin)); + + /* Configure as input and disconnect input buffer */ + + putreg32(GPIO_CNF_INPUT, offset); + + return OK; +} + +/**************************************************************************** + * Name: nrf54l_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void nrf54l_gpio_write(nrf54l_pinset_t pinset, bool value) +{ + unsigned int pin; + unsigned int port = 0; + uint32_t offset; + + /* Get port and pin number */ + + pin = GPIO_PIN_DECODE(pinset); + port = GPIO_PORT_DECODE(pinset); + + if (port >= NRF54L_GPIO_NPORTS || pin >= g_gpiopins[port]) + { + return; + } + + /* Get register address */ + + if (value) + { + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_OUTSET_OFFSET); + } + else + { + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_OUTCLR_OFFSET); + } + + /* Put register value */ + + putreg32(1 << pin, offset); +} + +/**************************************************************************** + * Name: nrf54l_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool nrf54l_gpio_read(nrf54l_pinset_t pinset) +{ + unsigned int port; + unsigned int pin; + uint32_t regval; + uint32_t offset; + + /* Get port and pin number */ + + pin = GPIO_PIN_DECODE(pinset); + port = GPIO_PORT_DECODE(pinset); + + if (port >= NRF54L_GPIO_NPORTS || pin >= g_gpiopins[port]) + { + return false; + } + + /* Get register address */ + + if ((pinset & GPIO_FUNC_MASK) == GPIO_OUTPUT) + { + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_OUT_OFFSET); + } + else + { + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_IN_OFFSET); + } + + /* Get register value */ + + regval = getreg32(offset); + + return (regval >> pin) & 1; +} + +/**************************************************************************** + * Name: nrf54l_gpio_detectmode + * + * Description: + * Set DETECTMODE to either default or latched + * + ****************************************************************************/ + +void nrf54l_gpio_detectmode(int port, enum nrf54l_gpio_detectmode_e mode) +{ + uint32_t offset; + + if (port < 0 || port >= NRF54L_GPIO_NPORTS || port == 2) + { + return; + } + + offset = nrf54l_gpio_regget(port, NRF54L_GPIO_DETECTMODE_OFFSET); + + putreg32(mode == NRF54L_GPIO_DETECTMODE_DETECT ? + GPIO_DETECTMODE_DEFAULT : + GPIO_DETECTMODE_LDETECT, offset); +} diff --git a/arch/arm/src/nrf54l/nrf54l_gpio.h b/arch/arm/src/nrf54l/nrf54l_gpio.h new file mode 100644 index 00000000000..87337420829 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_gpio.h @@ -0,0 +1,230 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_NRF54L_GPIO_H +#define __ARCH_ARM_SRC_NRF54L_NRF54L_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#include "chip.h" +#include "hardware/nrf54l_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Bit-encoded input to nrf54l_gpio_config() ********************************/ + +/* 32-bit encoding: + * + * Bits 0-4: Pin number (0-31) + * Bits 5-6: Port number (0-3) + * Bit 7: Initial output value + * Bits 8-9: Pull configuration + * Bits 10-13: Drive configuration + * Bits 14-15: Sense configuration + * Bits 16-17: Input/output function + */ + +#define GPIO_FUNC_SHIFT (16) /* Bits 16-17: GPIO mode */ +#define GPIO_FUNC_MASK (0x03 << GPIO_FUNC_SHIFT) +# define GPIO_INPUT (0x00 << GPIO_FUNC_SHIFT) /* GPIO input pin */ +# define GPIO_OUTPUT (0x01 << GPIO_FUNC_SHIFT) /* GPIO output pin */ + +#define GPIO_SENSE_SHIFT (14) /* Bits 14-15: Pin sense mode */ +#define GPIO_SENSE_MASK (0x3 << GPIO_SENSE_SHIFT) +# define GPIO_SENSE_NONE (0 << GPIO_SENSE_SHIFT) +# define GPIO_SENSE_HIGH (2 << GPIO_SENSE_SHIFT) +# define GPIO_SENSE_LOW (3 << GPIO_SENSE_SHIFT) + +#define GPIO_DRIVE_SHIFT (10) /* Bits 10-13: Pin drive mode */ +#define GPIO_DRIVE_MASK (0xf << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_S0S1 (0 << GPIO_DRIVE_SHIFT) /* Standard '0', standard '1' */ +# define GPIO_DRIVE_H0S1 (1 << GPIO_DRIVE_SHIFT) /* High drive '0', standard '1' */ +# define GPIO_DRIVE_S0H1 (2 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_H0H1 (3 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_D0S1 (4 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_D0H1 (5 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_S0D1 (6 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_H0D1 (7 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_EOS1 (8 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_SOE1 (9 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_EOE1 (10 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_DOE1 (11 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_EOD1 (12 << GPIO_DRIVE_SHIFT) + +#define GPIO_MODE_SHIFT (8) /* Bits 8-9: Pin pull-up mode */ +#define GPIO_MODE_MASK (0x3 << GPIO_MODE_SHIFT) +# define GPIO_FLOAT (0 << GPIO_MODE_SHIFT) /* Neither pull-up nor -down */ +# define GPIO_PULLDOWN (1 << GPIO_MODE_SHIFT) /* Pull-down resistor enabled */ +# define GPIO_PULLUP (2 << GPIO_MODE_SHIFT) /* Pull-up resistor enabled */ + +#define GPIO_VALUE (1 << 7) /* Bit 7: Initial GPIO output value */ +# define GPIO_VALUE_ONE GPIO_VALUE +# define GPIO_VALUE_ZERO (0) + +#define GPIO_PORT_SHIFT (5) /* Bits 5-6: Port number */ +#define GPIO_PORT_MASK (0x3 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) +# define GPIO_PIN(n) ((n) << GPIO_PIN_SHIFT) + +/* Helper macros */ + +#define GPIO_PIN_DECODE(p) (((p) & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT) + +#define GPIO_PORT_DECODE(p) (((p) & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef uint32_t nrf54l_pinset_t; + +enum nrf54l_gpio_detectmode_e +{ + NRF54L_GPIO_DETECTMODE_DETECT, + NRF54L_GPIO_DETECTMODE_LDETECT, +}; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int nrf54l_gpio_config(nrf54l_pinset_t cfgset); + +/**************************************************************************** + * Name: nrf54l_gpio_unconfig + * + * Description: + * Unconfigure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int nrf54l_gpio_unconfig(nrf54l_pinset_t cfgset); + +/**************************************************************************** + * Name: nrf54l_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void nrf54l_gpio_write(nrf54l_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: nrf54l_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool nrf54l_gpio_read(nrf54l_pinset_t pinset); + +/**************************************************************************** + * Name: nrf54l_gpio_detectmode + * + * Description: + * Select normal or latched pin detection for a GPIO port. + * + ****************************************************************************/ + +void nrf54l_gpio_detectmode(int port, enum nrf54l_gpio_detectmode_e mode); + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_NRF54L_NRF54L_GPIO_H */ diff --git a/arch/arm/src/nrf54l/nrf54l_idle.c b/arch/arm/src/nrf54l/nrf54l_idle.c new file mode 100644 index 00000000000..c4557fabb5c --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_idle.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when there is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* The SysTick's clock will only tick when the CPU is + * running (not in WFE/WFI) or when the system is in debug interface mode. + */ + +#endif +} diff --git a/arch/arm/src/nrf54l/nrf54l_irq.c b/arch/arm/src/nrf54l/nrf54l_irq.c new file mode 100644 index 00000000000..54606350e50 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_irq.c @@ -0,0 +1,511 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_irq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "chip.h" +#include "nvic.h" +#include "ram_vectors.h" +#include "arm_internal.h" +#include "nrf54l_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void nrf54l_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), + getreg32(NVIC_SYSHCON_BUSFAULTENA)); + irqinfo(" USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_USGFAULTENA), + getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + irqinfo(" IRQ ENABLE: %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), + getreg32(NVIC_IRQ32_63_ENABLE)); + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), + getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), + getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), + getreg32(NVIC_IRQ12_15_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), + getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), + getreg32(NVIC_IRQ28_31_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), + getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), + getreg32(NVIC_IRQ44_47_PRIORITY)); + irqinfo(" %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), + getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY)); + + leave_critical_section(flags); +} +#else +# define nrf54l_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: nrf54l_nmi, nrf54l_pendsv, nrf54l_pendsv, nrf54l_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int nrf54l_nmi(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int nrf54l_pendsv(int irq, void *context, void *arg) +{ + /* ARMv8-M uses PendSV to finish a context switch requested by a direct + * interrupt. arm_doirq() performs the switch after this callback. + */ + + return 0; +} + +static int nrf54l_reserved(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: nrf54l_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +static inline void nrf54l_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} + +/**************************************************************************** + * Name: nrf54l_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int nrf54l_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + int n; + + DEBUGASSERT(irq >= NRF54L_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= NRF54L_IRQ_EXTINT) + { + n = irq - NRF54L_IRQ_EXTINT; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + *bit = (uint32_t)1 << (n & 0x1f); + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == NRF54L_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == NRF54L_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == NRF54L_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == NRF54L_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + * + * Description: + * Complete initialization of the interrupt system and enable normal, + * interrupt processing. + * + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; + int num_priority_registers; + int i; + + /* Disable all interrupts */ + + for (i = 0; i < NRF54L_IRQ_NEXTINT; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } + + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + arm_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* The NVIC ICTR register (bits 0-4) holds the number of interrupt + * lines that the NVIC supports: + * + * 0 -> 32 interrupt lines, 8 priority registers + * 1 -> 64 " " " ", 16 priority registers + * 2 -> 96 " " " ", 32 priority registers + * ... + */ + + num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; + + /* Now set all of the interrupt lines to the default priority */ + + regaddr = NVIC_IRQ0_3_PRIORITY; + while (num_priority_registers--) + { + putreg32(DEFPRIORITY32, regaddr); + regaddr += 4; + } + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(NRF54L_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(NRF54L_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO +# if 0 + up_prioritize_irq(NRF54L_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); +# endif +#endif + + nrf54l_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + +#ifdef CONFIG_ARM_MPU + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + + irq_attach(NRF54L_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(NRF54L_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(NRF54L_IRQ_NMI, nrf54l_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(NRF54L_IRQ_MEMFAULT, arm_memfault, NULL); +#endif + irq_attach(NRF54L_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(NRF54L_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(NRF54L_IRQ_PENDSV, nrf54l_pendsv, NULL); + arm_enable_dbgmonitor(); + irq_attach(NRF54L_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(NRF54L_IRQ_RESERVED, nrf54l_reserved, NULL); +#endif + + nrf54l_dumpnvic("initial", NRF54L_IRQ_NIRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And finally, enable interrupts */ + + arm_color_intstack(); + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (nrf54l_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= NRF54L_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } + + nrf54l_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (nrf54l_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= NRF54L_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } + + nrf54l_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ + nrf54l_clrpend(irq); +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= NRF54L_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < NRF54L_IRQ_EXTINT) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= NRF54L_IRQ_EXTINT; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + nrf54l_dumpnvic("prioritize", irq); + return OK; +} +#endif + +/**************************************************************************** + * Name: nrf54l_clrpend + * + * Description: + * Clear any external interrupt, including the extended nRF54L banks. + ****************************************************************************/ + +void nrf54l_clrpend(int irq) +{ + if (irq >= NRF54L_IRQ_EXTINT && irq < NR_IRQS) + { + unsigned int n = irq - NRF54L_IRQ_EXTINT; + + putreg32(1 << (n & 31), NVIC_IRQ0_31_CLRPEND + 4 * (n >> 5)); + } +} diff --git a/arch/arm/src/nrf54l/nrf54l_irq.h b/arch/arm/src/nrf54l/nrf54l_irq.h new file mode 100644 index 00000000000..25731e2eaf5 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_irq.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_NRF54L_IRQ_H +#define __ARCH_ARM_SRC_NRF54L_NRF54L_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. + * + ****************************************************************************/ + +void nrf54l_clrpend(int irq); + +#endif /* __ARCH_ARM_SRC_NRF54L_NRF54L_IRQ_H */ diff --git a/arch/arm/src/nrf54l/nrf54l_lowputc.c b/arch/arm/src/nrf54l/nrf54l_lowputc.c new file mode 100644 index 00000000000..f5a4d906420 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_lowputc.c @@ -0,0 +1,540 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_lowputc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/nrf54l_memorymap.h" +#include "hardware/nrf54l_uarte.h" + +#include "nrf54l_config.h" +#include "nrf54l_clockconfig.h" +#include "nrf54l_gpio.h" +#include "nrf54l_lowputc.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef HAVE_UART_CONSOLE + +#ifdef CONFIG_UART0_SERIAL_CONSOLE +# define CONSOLE_BASE NRF54L_UART0_BASE +# define CONSOLE_BAUD CONFIG_UART0_BAUD +# define CONSOLE_BITS CONFIG_UART0_BITS +# define CONSOLE_PARITY CONFIG_UART0_PARITY +# define CONSOLE_2STOP CONFIG_UART0_2STOP +# define CONSOLE_TX_PIN BOARD_UART0_TX_PIN +# define CONSOLE_RX_PIN BOARD_UART0_RX_PIN +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_BASE NRF54L_UART1_BASE +# define CONSOLE_BAUD CONFIG_UART1_BAUD +# define CONSOLE_BITS CONFIG_UART1_BITS +# define CONSOLE_PARITY CONFIG_UART1_PARITY +# define CONSOLE_2STOP CONFIG_UART1_2STOP +# define CONSOLE_TX_PIN BOARD_UART1_TX_PIN +# define CONSOLE_RX_PIN BOARD_UART1_RX_PIN +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_BASE NRF54L_UART2_BASE +# define CONSOLE_BAUD CONFIG_UART2_BAUD +# define CONSOLE_BITS CONFIG_UART2_BITS +# define CONSOLE_PARITY CONFIG_UART2_PARITY +# define CONSOLE_2STOP CONFIG_UART2_2STOP +# define CONSOLE_TX_PIN BOARD_UART2_TX_PIN +# define CONSOLE_RX_PIN BOARD_UART2_RX_PIN +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_BASE NRF54L_UART3_BASE +# define CONSOLE_BAUD CONFIG_UART3_BAUD +# define CONSOLE_BITS CONFIG_UART3_BITS +# define CONSOLE_PARITY CONFIG_UART3_PARITY +# define CONSOLE_2STOP CONFIG_UART3_2STOP +# define CONSOLE_TX_PIN BOARD_UART3_TX_PIN +# define CONSOLE_RX_PIN BOARD_UART3_RX_PIN +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_BASE NRF54L_UART4_BASE +# define CONSOLE_BAUD CONFIG_UART4_BAUD +# define CONSOLE_BITS CONFIG_UART4_BITS +# define CONSOLE_PARITY CONFIG_UART4_PARITY +# define CONSOLE_2STOP CONFIG_UART4_2STOP +# define CONSOLE_TX_PIN BOARD_UART4_TX_PIN +# define CONSOLE_RX_PIN BOARD_UART4_RX_PIN +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define CONSOLE_BASE NRF54L_UART5_BASE +# define CONSOLE_BAUD CONFIG_UART5_BAUD +# define CONSOLE_BITS CONFIG_UART5_BITS +# define CONSOLE_PARITY CONFIG_UART5_PARITY +# define CONSOLE_2STOP CONFIG_UART5_2STOP +# define CONSOLE_TX_PIN BOARD_UART5_TX_PIN +# define CONSOLE_RX_PIN BOARD_UART5_RX_PIN +#elif defined(CONFIG_UART6_SERIAL_CONSOLE) +# define CONSOLE_BASE NRF54L_UART6_BASE +# define CONSOLE_BAUD CONFIG_UART6_BAUD +# define CONSOLE_BITS CONFIG_UART6_BITS +# define CONSOLE_PARITY CONFIG_UART6_PARITY +# define CONSOLE_2STOP CONFIG_UART6_2STOP +# define CONSOLE_TX_PIN BOARD_UART6_TX_PIN +# define CONSOLE_RX_PIN BOARD_UART6_RX_PIN +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* UART console configuration */ + +static const struct uart_config_s g_console_config = +{ + .baud = CONSOLE_BAUD, + .parity = CONSOLE_PARITY, + .bits = CONSOLE_BITS, + .stopbits2 = CONSOLE_2STOP, + .txpin = CONSOLE_TX_PIN, + .rxpin = CONSOLE_RX_PIN, +}; + +/* EasyDMA requires its source byte to be in RAM. */ + +static uint8_t g_console_tx; +#endif /* HAVE_UART_CONSOLE */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_setbaud + * + * Description: + * Configure the UART BAUD. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +static int nrf54l_setbaud(uintptr_t base, const struct uart_config_s *config) +{ + uint32_t br = 0; + + switch (config->baud) + { + case 1200: + { + br = UARTE_BAUDRATE_1200; + break; + } + + case 2400: + { + br = UARTE_BAUDRATE_2400; + break; + } + + case 4800: + { + br = UARTE_BAUDRATE_4800; + break; + } + + case 9600: + { + br = UARTE_BAUDRATE_9600; + break; + } + + case 14400: + { + br = UARTE_BAUDRATE_14400; + break; + } + + case 19200: + { + br = UARTE_BAUDRATE_19200; + break; + } + + case 28800: + { + br = UARTE_BAUDRATE_28800; + break; + } + + case 31250: + { + br = UARTE_BAUDRATE_31250; + break; + } + + case 38400: + { + br = UARTE_BAUDRATE_38400; + break; + } + + case 56000: + { + br = UARTE_BAUDRATE_56000; + break; + } + + case 57600: + { + br = UARTE_BAUDRATE_57600; + break; + } + + case 76800: + { + br = UARTE_BAUDRATE_76800; + break; + } + + case 115200: + { + br = UARTE_BAUDRATE_115200; + break; + } + + case 230400: + { + br = UARTE_BAUDRATE_230400; + break; + } + + case 250000: + { + br = UARTE_BAUDRATE_250000; + break; + } + + case 460800: + { + br = UARTE_BAUDRATE_460800; + break; + } + + case 921600: + { + br = UARTE_BAUDRATE_921600; + break; + } + + case 1000000: + { + br = UARTE_BAUDRATE_1000000; + break; + } + + default: + { + return -EINVAL; + } + } + + /* UARTE00 runs from the 128 MHz peripheral clock. The baud generator + * ignores the low 12 bits, so round after scaling the 16 MHz value. + */ + + if (base == NRF54L_UART4_BASE) + { + br = ((br / 8) + 0x800) & ~0xfff; + } + + putreg32(br, base + NRF54L_UARTE_BAUDRATE_OFFSET); + return OK; +} + +/**************************************************************************** + * Name: nrf54l_setparity + ****************************************************************************/ + +static void nrf54l_setparity(uintptr_t base, + const struct uart_config_s *config) +{ + uint32_t regval = 0; + + regval = getreg32(base + NRF54L_UARTE_CONFIG_OFFSET); + + regval &= ~(UARTE_CONFIG_PARITY_MASK | UARTE_CONFIG_PARITYTYPE); + + if (config->parity != 0) + { + /* Include the selected parity */ + + regval |= UARTE_CONFIG_PARITY_INCLUDED; + if (config->parity == 1) + { + regval |= UARTE_CONFIG_PARITYTYPE; + } + } + + putreg32(regval, base + NRF54L_UARTE_CONFIG_OFFSET); +} + +/**************************************************************************** + * Name: nrf54l_setstops + ****************************************************************************/ + +static void nrf54l_setstops(uintptr_t base, + const struct uart_config_s *config) +{ + uint32_t regval = 0; + + regval = getreg32(base + NRF54L_UARTE_CONFIG_OFFSET); + + if (config->stopbits2 == true) + { + regval |= UARTE_CONFIG_STOP; + } + else + { + regval &= ~UARTE_CONFIG_STOP; + } + + putreg32(regval, base + NRF54L_UARTE_CONFIG_OFFSET); +} + +/**************************************************************************** + * Name: nrf54l_sethwflow + ****************************************************************************/ + +static void nrf54l_sethwflow(uintptr_t base, + const struct uart_config_s *config) +{ + modifyreg32(base + NRF54L_UARTE_CONFIG_OFFSET, UARTE_CONFIG_HWFC, 0); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. + * This UART initialization is done early so that the serial console is + * available for debugging very early in the boot sequence. + * + ****************************************************************************/ + +void nrf54l_lowsetup(void) +{ +#ifdef HAVE_UART_DEVICE +#if defined(HAVE_UART_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Configure the console UART (if any) */ + + nrf54l_usart_configure(CONSOLE_BASE, &g_console_config); + +#endif /* HAVE_UART_CONSOLE */ +#endif /* HAVE_UART_DEVICE */ +} + +/**************************************************************************** + * Name: nrf54l_usart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +int nrf54l_usart_configure(uintptr_t base, + const struct uart_config_s *config) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t pin = 0; + uint32_t port = 0; + uint32_t regval = 0; + int ret; + + putreg32(0xffffffff, base + NRF54L_UARTE_INTENCLR_OFFSET); + putreg32(0, base + NRF54L_UARTE_ENABLE_OFFSET); + + /* Set UART format */ + + ret = nrf54l_usart_setformat(base, config); + if (ret < 0) + { + return ret; + } + + /* Config GPIO pins for uart */ + + ret = nrf54l_gpio_config(config->txpin); + if (ret < 0) + { + return ret; + } + + ret = nrf54l_gpio_config(config->rxpin); + if (ret < 0) + { + nrf54l_gpio_unconfig(config->txpin); + return ret; + } + + /* Select TX pins for UART */ + + pin = GPIO_PIN_DECODE(config->txpin); + port = GPIO_PORT_DECODE(config->txpin); + + regval = (pin << UARTE_PSEL_TXD_PIN_SHIFT); + regval |= (port << UARTE_PSEL_TXD_PORT_SHIFT); + putreg32(regval, base + NRF54L_UARTE_PSEL_TXD_OFFSET); + + /* Select RX pins for UART */ + + pin = GPIO_PIN_DECODE(config->rxpin); + port = GPIO_PORT_DECODE(config->rxpin); + + regval = (pin << UARTE_PSEL_RXD_PIN_SHIFT); + regval |= (port << UARTE_PSEL_RXD_PORT_SHIFT); + putreg32(regval, base + NRF54L_UARTE_PSEL_RXD_OFFSET); + putreg32(0xffffffff, base + NRF54L_UARTE_PSEL_CTS_OFFSET); + putreg32(0xffffffff, base + NRF54L_UARTE_PSEL_RTS_OFFSET); + + /* Stop each DMA transmission after the last byte leaves the UART. */ + + putreg32(UARTE_SHORTS_DMA_TX_END_STOP, base + NRF54L_UARTE_SHORTS_OFFSET); + + /* Enable UART */ + + putreg32(UARTE_ENABLE_ENABLE, base + NRF54L_UARTE_ENABLE_OFFSET); +#endif + return OK; +} + +/**************************************************************************** + * Name: nrf54l_usart_disable + * + * Description: + * Disable a UART. it will be necessary to again call + * nrf54l_usart_configure() in order to use this UART channel again. + * + ****************************************************************************/ + +void nrf54l_usart_disable(uintptr_t base, const struct uart_config_s *config) +{ + /* Disable the UART */ + + putreg32(0, base + NRF54L_UARTE_ENABLE_OFFSET); + + putreg32(0xffffffff, base + NRF54L_UARTE_PSEL_TXD_OFFSET); + putreg32(0xffffffff, base + NRF54L_UARTE_PSEL_RXD_OFFSET); + + /* Unconfigure GPIO */ + + nrf54l_gpio_unconfig(config->rxpin); + nrf54l_gpio_unconfig(config->txpin); +} + +/**************************************************************************** + * Name: nrf54l_usart_setformat + * + * Description: + * Set the USART line format and speed. + * + ****************************************************************************/ + +int nrf54l_usart_setformat(uintptr_t base, + const struct uart_config_s *config) +{ + int ret; + + if (config->bits < 5 || config->bits > 8 || config->parity > 2) + { + return -EINVAL; + } + + /* Configure baud */ + + ret = nrf54l_setbaud(base, config); + if (ret < 0) + { + return ret; + } + + modifyreg32(base + NRF54L_UARTE_CONFIG_OFFSET, + UARTE_CONFIG_FRAMESIZE_MASK, + config->bits << UARTE_CONFIG_FRAMESIZE_SHIFT); + + /* Configure polarity */ + + nrf54l_setparity(base, config); + + /* Configure STOP bits */ + + nrf54l_setstops(base, config); + + /* Configure hardware flow control */ + + nrf54l_sethwflow(base, config); + return OK; +} +#endif + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef HAVE_UART_CONSOLE + g_console_tx = ch; + + putreg32(0, CONSOLE_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET); + (void)getreg32(CONSOLE_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET); + + putreg32(0, CONSOLE_BASE + NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET); + (void)getreg32(CONSOLE_BASE + NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET); + + putreg32((uintptr_t)&g_console_tx, + CONSOLE_BASE + NRF54L_UARTE_DMA_TX_PTR_OFFSET); + + putreg32(1, CONSOLE_BASE + NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET); + + UP_DMB(); + + putreg32(1, CONSOLE_BASE + NRF54L_UARTE_TASKS_STARTTX_OFFSET); + + while (getreg32(CONSOLE_BASE + NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET) == 0) + { + } + +#endif +} diff --git a/arch/arm/src/nrf54l/nrf54l_lowputc.h b/arch/arm/src/nrf54l/nrf54l_lowputc.h new file mode 100644 index 00000000000..42f222ffa54 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_lowputc.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_lowputc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_NRF54L_LOWPUTC_H +#define __ARCH_ARM_SRC_NRF54L_NRF54L_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nrf54l_gpio.h" +#include "nrf54l_config.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-8) */ + bool stopbits2; /* Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; /* Input flow control supported */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; /* Output flow control supported. */ +#endif + nrf54l_pinset_t txpin; /* TX pin */ + nrf54l_pinset_t rxpin; /* RX pin */ +}; +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART + * initialization is done early so that the serial console is available + * for debugging very early in the boot sequence. + * + ****************************************************************************/ + +void nrf54l_lowsetup(void); + +/**************************************************************************** + * Name: nrf54l_usart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +int nrf54l_usart_configure(uintptr_t base, + const struct uart_config_s *config); +#endif + +/**************************************************************************** + * Name: nrf54l_usart_disable + * + * Description: + * Disable a UART. it will be necessary to again call + * nrf54l_usart_configure() in order to use this UART channel again. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void nrf54l_usart_disable(uintptr_t base, + const struct uart_config_s *config); +#endif + +/**************************************************************************** + * Name: nrf54l_usart_setformat + * + * Description: + * Set the USART line format and speed. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +int nrf54l_usart_setformat(uintptr_t base, + const struct uart_config_s *config); +#endif + +#endif /* __ARCH_ARM_SRC_NRF54L_NRF54L_LOWPUTC_H */ diff --git a/arch/arm/src/nrf54l/nrf54l_oscconfig.c b/arch/arm/src/nrf54l/nrf54l_oscconfig.c new file mode 100644 index 00000000000..98842042c00 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_oscconfig.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_oscconfig.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "nrf54l_oscconfig.h" +#include "hardware/nrf54l_osc.h" +#include "hardware/nrf54l_ficr.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_hfxo_intcap + * + * Description: + * Configure HFXO load capacitance using the signed factory trim. + * + ****************************************************************************/ + +static void nrf54l_hfxo_intcap(void) +{ + int32_t slope; + int32_t offset; + int32_t capvalue; + uint32_t trim; + + trim = getreg32(NRF54L_FICR_XOSC32MTRIM); + if (trim == UINT32_MAX) + { + return; + } + + slope = (int32_t)((trim & 0x1ff) ^ 0x100) - 0x100; + offset = (trim >> 16) & 0x3ff; + + /* Board capacitance is expressed in femtofarads to avoid floating point. + */ + + capvalue = ((BOARD_HFXO_CAPACITANCE - 5500) * (slope + 791) + + 4000 * offset + 128000) / 256000; + if (capvalue < 0 || capvalue > 63) + { + PANIC(); + } + + putreg32(capvalue, NRF54L_OSC_XOSC32M_INTCAP); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_oscconfig + ****************************************************************************/ + +void nrf54l_oscconfig(void) +{ + /* Configure internal capacitors for HFXO */ + + nrf54l_hfxo_intcap(); +} diff --git a/arch/arm/src/nrf54l/nrf54l_oscconfig.h b/arch/arm/src/nrf54l/nrf54l_oscconfig.h new file mode 100644 index 00000000000..bacf34033ec --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_oscconfig.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_oscconfig.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_NRF54L_OSCCONFIG_H +#define __ARCH_ARM_SRC_NRF54L_NRF54L_OSCCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_oscconfig + ****************************************************************************/ + +void nrf54l_oscconfig(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_NRF54L_NRF54L_OSCCONFIG_H */ diff --git a/arch/arm/src/nrf54l/nrf54l_pminitialize.c b/arch/arm/src/nrf54l/nrf54l_pminitialize.c new file mode 100644 index 00000000000..ef12caf5f05 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_pminitialize.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_pminitialize.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); +} diff --git a/arch/arm/src/nrf54l/nrf54l_serial.c b/arch/arm/src/nrf54l/nrf54l_serial.c new file mode 100644 index 00000000000..4dae865e936 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_serial.c @@ -0,0 +1,1249 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_serial.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "nrf54l_config.h" +#include "nrf54l_lowputc.h" +#include "nrf54l_serial.h" +#include "hardware/nrf54l_uarte.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of UART instances */ + +#define NRF54L_NUART 7 + +#if defined(HAVE_UART_DEVICE) && defined(USE_SERIALDRIVER) + +/* The console is always ttyS0. */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port +# define TTYS0_DEV g_uart0port +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port +# define TTYS0_DEV g_uart1port +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port +# define TTYS0_DEV g_uart2port +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port +# define TTYS0_DEV g_uart3port +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart4port +# define TTYS0_DEV g_uart4port +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart5port +# define TTYS0_DEV g_uart5port +#elif defined(CONFIG_UART6_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart6port +# define TTYS0_DEV g_uart6port +#endif + +#define RX_INTERRUPTS (UARTE_INT_DMA_RX_END | UARTE_INT_ERROR | \ + UARTE_INT_DMA_RX_BUSERROR | UARTE_INT_RXTO) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* State of one UART device */ + +struct nrf54l_dev_s +{ + uintptr_t uartbase; /* Base address of UART registers */ + uint16_t irq; /* IRQ associated with this UART */ + uint8_t rxdma; /* Receive DMA buffer */ + uint8_t txdma; /* Transmit DMA buffer */ + uint8_t rxchar; /* Completed receive byte */ + uint32_t rxstatus; /* Receive error status */ + bool rxvalid; /* Receive byte available */ + bool rxenabled; /* Upper-half reception enabled */ + bool rxrecover; /* Receiver stopping after a DMA error */ + bool rxactive; /* Receiver started */ + bool txenabled; /* Upper-half transmission enabled */ + volatile bool txbusy; /* DMA transmitter owns txdma */ + + /* UART configuration */ + + struct uart_config_s config; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int nrf54l_setup(struct uart_dev_s *dev); +static void nrf54l_shutdown(struct uart_dev_s *dev); +static int nrf54l_attach(struct uart_dev_s *dev); +static void nrf54l_detach(struct uart_dev_s *dev); +static int nrf54l_interrupt(int irq, void *context, void *arg); +static int nrf54l_ioctl(struct file *filep, int cmd, unsigned long arg); +static int nrf54l_receive(struct uart_dev_s *dev, unsigned int *status); +static void nrf54l_rxint(struct uart_dev_s *dev, bool enable); +static bool nrf54l_rxavailable(struct uart_dev_s *dev); +static void nrf54l_send(struct uart_dev_s *dev, int ch); +static void nrf54l_txint(struct uart_dev_s *dev, bool enable); +static bool nrf54l_txready(struct uart_dev_s *dev); +static bool nrf54l_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = nrf54l_setup, + .shutdown = nrf54l_shutdown, + .attach = nrf54l_attach, + .detach = nrf54l_detach, + .ioctl = nrf54l_ioctl, + .receive = nrf54l_receive, + .rxint = nrf54l_rxint, + .rxavailable = nrf54l_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = nrf54l_send, + .txint = nrf54l_txint, + .txready = nrf54l_txready, + .txempty = nrf54l_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_NRF54L_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif + +#ifdef CONFIG_NRF54L_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif + +#ifdef CONFIG_NRF54L_UART2 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif + +#ifdef CONFIG_NRF54L_UART3 +static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; +#endif + +#ifdef CONFIG_NRF54L_UART4 +static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; +#endif + +#ifdef CONFIG_NRF54L_UART5 +static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; +static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; +#endif + +#ifdef CONFIG_NRF54L_UART6 +static char g_uart6rxbuffer[CONFIG_UART6_RXBUFSIZE]; +static char g_uart6txbuffer[CONFIG_UART6_TXBUFSIZE]; +#endif + +/* This describes the state of the NRF54L UART0 port. */ + +#ifdef CONFIG_NRF54L_UART0 +static struct nrf54l_dev_s g_uart0priv = +{ + .uartbase = NRF54L_UART0_BASE, + .irq = NRF54L_IRQ_SERIAL20, + .config = + { + .baud = CONFIG_UART0_BAUD, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, + .txpin = BOARD_UART0_TX_PIN, + .rxpin = BOARD_UART0_RX_PIN, + }, +}; + +static struct uart_dev_s g_uart0port = +{ + .recv = + { + .size = sizeof(g_uart0rxbuffer), + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = sizeof(g_uart0txbuffer), + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; + +#endif + +/* This describes the state of the NRF54L UART1 port. */ + +#ifdef CONFIG_NRF54L_UART1 +static struct nrf54l_dev_s g_uart1priv = +{ + .uartbase = NRF54L_UART1_BASE, + .irq = NRF54L_IRQ_SERIAL21, + .config = + { + .baud = CONFIG_UART1_BAUD, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, + .txpin = BOARD_UART1_TX_PIN, + .rxpin = BOARD_UART1_RX_PIN, + }, +}; + +static struct uart_dev_s g_uart1port = +{ + .recv = + { + .size = sizeof(g_uart1rxbuffer), + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = sizeof(g_uart1txbuffer), + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; + +#endif + +/* This describes the state of the NRF54L UART2 port. */ + +#ifdef CONFIG_NRF54L_UART2 +static struct nrf54l_dev_s g_uart2priv = +{ + .uartbase = NRF54L_UART2_BASE, + .irq = NRF54L_IRQ_SERIAL22, + .config = + { + .baud = CONFIG_UART2_BAUD, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, + .txpin = BOARD_UART2_TX_PIN, + .rxpin = BOARD_UART2_RX_PIN, + }, +}; + +static struct uart_dev_s g_uart2port = +{ + .recv = + { + .size = sizeof(g_uart2rxbuffer), + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = sizeof(g_uart2txbuffer), + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; + +#endif + +/* This describes the state of the NRF54L UART3 port. */ + +#ifdef CONFIG_NRF54L_UART3 +static struct nrf54l_dev_s g_uart3priv = +{ + .uartbase = NRF54L_UART3_BASE, + .irq = NRF54L_IRQ_SERIAL30, + .config = + { + .baud = CONFIG_UART3_BAUD, + .parity = CONFIG_UART3_PARITY, + .bits = CONFIG_UART3_BITS, + .stopbits2 = CONFIG_UART3_2STOP, + .txpin = BOARD_UART3_TX_PIN, + .rxpin = BOARD_UART3_RX_PIN, + }, +}; + +static struct uart_dev_s g_uart3port = +{ + .recv = + { + .size = sizeof(g_uart3rxbuffer), + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = sizeof(g_uart3txbuffer), + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; + +#endif + +/* This describes the state of the NRF54L UART4 port. */ + +#ifdef CONFIG_NRF54L_UART4 +static struct nrf54l_dev_s g_uart4priv = +{ + .uartbase = NRF54L_UART4_BASE, + .irq = NRF54L_IRQ_SERIAL00, + .config = + { + .baud = CONFIG_UART4_BAUD, + .parity = CONFIG_UART4_PARITY, + .bits = CONFIG_UART4_BITS, + .stopbits2 = CONFIG_UART4_2STOP, + .txpin = BOARD_UART4_TX_PIN, + .rxpin = BOARD_UART4_RX_PIN, + }, +}; + +static struct uart_dev_s g_uart4port = +{ + .recv = + { + .size = sizeof(g_uart4rxbuffer), + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = sizeof(g_uart4txbuffer), + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; + +#endif + +/* This describes the state of the NRF54L UART5 port. */ + +#ifdef CONFIG_NRF54L_UART5 +static struct nrf54l_dev_s g_uart5priv = +{ + .uartbase = NRF54L_UART5_BASE, + .irq = NRF54L_IRQ_SERIAL23, + .config = + { + .baud = CONFIG_UART5_BAUD, + .parity = CONFIG_UART5_PARITY, + .bits = CONFIG_UART5_BITS, + .stopbits2 = CONFIG_UART5_2STOP, + .txpin = BOARD_UART5_TX_PIN, + .rxpin = BOARD_UART5_RX_PIN, + }, +}; + +static struct uart_dev_s g_uart5port = +{ + .recv = + { + .size = sizeof(g_uart5rxbuffer), + .buffer = g_uart5rxbuffer, + }, + .xmit = + { + .size = sizeof(g_uart5txbuffer), + .buffer = g_uart5txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart5priv, +}; + +#endif + +/* This describes the state of the NRF54L UART6 port. */ + +#ifdef CONFIG_NRF54L_UART6 +static struct nrf54l_dev_s g_uart6priv = +{ + .uartbase = NRF54L_UART6_BASE, + .irq = NRF54L_IRQ_SERIAL24, + .config = + { + .baud = CONFIG_UART6_BAUD, + .parity = CONFIG_UART6_PARITY, + .bits = CONFIG_UART6_BITS, + .stopbits2 = CONFIG_UART6_2STOP, + .txpin = BOARD_UART6_TX_PIN, + .rxpin = BOARD_UART6_RX_PIN, + }, +}; + +static struct uart_dev_s g_uart6port = +{ + .recv = + { + .size = sizeof(g_uart6rxbuffer), + .buffer = g_uart6rxbuffer, + }, + .xmit = + { + .size = sizeof(g_uart6txbuffer), + .buffer = g_uart6txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart6priv, +}; + +#endif + +/* This table lets us iterate over the configured UARTs */ + +static struct uart_dev_s * const g_uart_devs[NRF54L_NUART] = +{ +#ifdef CONFIG_NRF54L_UART0 + [0] = &g_uart0port, +#endif +#ifdef CONFIG_NRF54L_UART1 + [1] = &g_uart1port, +#endif +#ifdef CONFIG_NRF54L_UART2 + [2] = &g_uart2port, +#endif +#ifdef CONFIG_NRF54L_UART3 + [3] = &g_uart3port, +#endif +#ifdef CONFIG_NRF54L_UART4 + [4] = &g_uart4port, +#endif +#ifdef CONFIG_NRF54L_UART5 + [5] = &g_uart5port, +#endif +#ifdef CONFIG_NRF54L_UART6 + [6] = &g_uart6port, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_uart_putreg + * + * Description: + * Write a UART register. + * + ****************************************************************************/ + +static inline void nrf54l_uart_putreg(struct nrf54l_dev_s *priv, + uint32_t offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: nrf54l_uart_getreg + * + * Description: + * Read a UART register. + * + ****************************************************************************/ + +static inline uint32_t nrf54l_uart_getreg(struct nrf54l_dev_s *priv, + uint32_t offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: nrf54l_uart_clrevent + * + * Description: + * Clear a UARTE event and read it back before returning. + * + ****************************************************************************/ + +static void nrf54l_uart_clrevent(struct nrf54l_dev_s *priv, uint32_t event) +{ + nrf54l_uart_putreg(priv, event, 0); + (void)nrf54l_uart_getreg(priv, event); +} + +/**************************************************************************** + * Name: nrf54l_rxstart + * + * Description: + * Start reception and queue the first one-byte DMA buffer. + * + ****************************************************************************/ + +static void nrf54l_rxstart(struct nrf54l_dev_s *priv) +{ + priv->rxactive = true; + priv->rxvalid = false; + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET); + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_DMA_RX_READY_OFFSET); + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_RXTO_OFFSET); + nrf54l_uart_putreg(priv, NRF54L_UARTE_DMA_RX_PTR_OFFSET, + (uintptr_t)&priv->rxdma); + nrf54l_uart_putreg(priv, NRF54L_UARTE_DMA_RX_MAXCNT_OFFSET, 1); + nrf54l_uart_putreg(priv, NRF54L_UARTE_SHORTS_OFFSET, + UARTE_SHORTS_DMA_TX_END_STOP); + UP_DMB(); + nrf54l_uart_putreg(priv, NRF54L_UARTE_TASKS_STARTRX_OFFSET, 1); +} + +/**************************************************************************** + * Name: nrf54l_txstart + * + * Description: + * Start a one-byte DMA transfer. The caller must serialize access. + * + ****************************************************************************/ + +static void nrf54l_txstart(struct nrf54l_dev_s *priv, int ch) +{ + priv->txdma = ch; + priv->txbusy = true; + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_DMA_TX_END_OFFSET); + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET); + nrf54l_uart_putreg(priv, NRF54L_UARTE_DMA_TX_PTR_OFFSET, + (uintptr_t)&priv->txdma); + nrf54l_uart_putreg(priv, NRF54L_UARTE_DMA_TX_MAXCNT_OFFSET, 1); + UP_DMB(); + nrf54l_uart_putreg(priv, NRF54L_UARTE_TASKS_STARTTX_OFFSET, 1); +} + +/**************************************************************************** + * Name: nrf54l_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int nrf54l_setup(struct uart_dev_s *dev) +{ + struct nrf54l_dev_s *priv = dev->priv; + + return nrf54l_usart_configure(priv->uartbase, &priv->config); +} + +/**************************************************************************** + * Name: nrf54l_shutdown + * + * Description: + * Disable the UART. This method is not called for the serial console. + * + ****************************************************************************/ + +static void nrf54l_shutdown(struct uart_dev_s *dev) +{ + struct nrf54l_dev_s *priv = dev->priv; + + nrf54l_usart_disable(priv->uartbase, &priv->config); +} + +/**************************************************************************** + * Name: nrf54l_attach + * + * Description: + * Configure the UART to operate in interrupt driven mode. This method + * is called when the serial port is opened, normally just after setup. + * DMA completion interrupts release buffers even when delivery to the + * upper half is disabled by the rxint() and txint() methods. + * + ****************************************************************************/ + +static int nrf54l_attach(struct uart_dev_s *dev) +{ + struct nrf54l_dev_s *priv = (struct nrf54l_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, nrf54l_interrupt, dev); + if (ret == OK) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + nrf54l_uart_putreg(priv, NRF54L_UARTE_INTENSET_OFFSET, RX_INTERRUPTS | + UARTE_INT_TXSTOPPED | UARTE_INT_DMA_TX_BUSERROR); + up_enable_irq(priv->irq); + nrf54l_rxstart(priv); +#endif + } + + return ret; +} + +/**************************************************************************** + * Name: nrf54l_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. + * The exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void nrf54l_detach(struct uart_dev_s *dev) +{ + struct nrf54l_dev_s *priv = (struct nrf54l_dev_s *)dev->priv; + + /* Stop DMA before detaching the interrupt handler */ + + nrf54l_uart_putreg(priv, NRF54L_UARTE_INTENCLR_OFFSET, UINT32_MAX); + nrf54l_uart_putreg(priv, NRF54L_UARTE_SHORTS_OFFSET, + UARTE_SHORTS_DMA_TX_END_STOP); + if (priv->rxactive) + { + /* Wait until the DMA buffer is released before a subsequent attach. */ + + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_RXTO_OFFSET); + nrf54l_uart_putreg(priv, NRF54L_UARTE_TASKS_STOPRX_OFFSET, 1); + while (!nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_RXTO_OFFSET)) + { + } + + priv->rxactive = false; + priv->rxrecover = false; + } + + if (priv->txbusy) + { + while (!nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET)) + { + } + + priv->txbusy = false; + } + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: nrf54l_interrupt + * + * Description: + * Handle receive buffers, transfer completion and DMA errors. + * + ****************************************************************************/ + +static int nrf54l_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = arg; + struct nrf54l_dev_s *priv = dev->priv; + + if (nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_ERROR_OFFSET)) + { + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_ERROR_OFFSET); + priv->rxstatus |= + nrf54l_uart_getreg(priv, NRF54L_UARTE_ERRORSRC_OFFSET); + nrf54l_uart_putreg(priv, NRF54L_UARTE_ERRORSRC_OFFSET, priv->rxstatus); + } + + if (nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET)) + { + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET); + priv->rxrecover = true; + nrf54l_uart_putreg(priv, NRF54L_UARTE_SHORTS_OFFSET, + UARTE_SHORTS_DMA_TX_END_STOP); + nrf54l_uart_putreg(priv, NRF54L_UARTE_TASKS_STOPRX_OFFSET, 1); + } + + if (priv->rxrecover) + { + if (nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_RXTO_OFFSET)) + { + priv->rxrecover = false; + nrf54l_rxstart(priv); + } + } + else + { + /* Copy the completed byte before restarting DMA. Automatic END-to- + * START would let DMA overwrite a buffer before the interrupt handler + * consumes it. The UART FIFO holds incoming bytes between transfers. + */ + + if (nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET)) + { + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_DMA_RX_END_OFFSET); + UP_DMB(); + priv->rxchar = priv->rxdma; + priv->rxvalid = true; + UP_DMB(); + nrf54l_uart_putreg(priv, NRF54L_UARTE_TASKS_STARTRX_OFFSET, 1); + } + + if (priv->rxvalid && priv->rxenabled) + { + uart_recvchars(dev); + } + + priv->rxvalid = false; + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_RXTO_OFFSET); + } + + if (nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET)) + { + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_DMA_TX_BUSERROR_OFFSET); + nrf54l_uart_putreg(priv, NRF54L_UARTE_TASKS_STOPTX_OFFSET, 1); + } + + if (nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET)) + { + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET); + priv->txbusy = false; + if (priv->txenabled) + { + uart_xmitchars(dev); + } + } + + return OK; +} + +/**************************************************************************** + * Name: nrf54l_set_format + * + * Description: + * Set the serial line format and speed with DMA stopped. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_TERMIOS +static int nrf54l_set_format(struct uart_dev_s *dev, + const struct uart_config_s *config) +{ + struct nrf54l_dev_s *priv = dev->priv; + irqstate_t flags; + uint32_t enabled; + int ret; + + flags = enter_critical_section(); + + /* Do not change the format of a byte still being transmitted or + * interrupt DMA error recovery. + */ + + if (priv->txbusy || priv->rxrecover) + { + leave_critical_section(flags); + return -EBUSY; + } + + if (priv->rxactive) + { + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_RXTO_OFFSET); + nrf54l_uart_putreg(priv, NRF54L_UARTE_TASKS_STOPRX_OFFSET, 1); + while (!nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_RXTO_OFFSET)) + { + } + + /* STOP also generates END for an empty buffer. Deliver a completed + * byte before restarting DMA, but never deliver an empty buffer. + */ + + if (nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_ERROR_OFFSET)) + { + nrf54l_uart_clrevent(priv, NRF54L_UARTE_EVENTS_ERROR_OFFSET); + priv->rxstatus |= + nrf54l_uart_getreg(priv, NRF54L_UARTE_ERRORSRC_OFFSET); + nrf54l_uart_putreg(priv, NRF54L_UARTE_ERRORSRC_OFFSET, + priv->rxstatus); + } + + if (nrf54l_uart_getreg(priv, NRF54L_UARTE_DMA_RX_AMOUNT_OFFSET) != 0 && + !nrf54l_uart_getreg(priv, + NRF54L_UARTE_EVENTS_DMA_RX_BUSERROR_OFFSET)) + { + UP_DMB(); + priv->rxchar = priv->rxdma; + priv->rxvalid = true; + if (priv->rxenabled) + { + uart_recvchars(dev); + } + } + } + + enabled = nrf54l_uart_getreg(priv, NRF54L_UARTE_ENABLE_OFFSET); + nrf54l_uart_putreg(priv, NRF54L_UARTE_ENABLE_OFFSET, 0); + ret = nrf54l_usart_setformat(priv->uartbase, config); + if (ret == OK) + { + priv->config = *config; + } + + nrf54l_uart_putreg(priv, NRF54L_UARTE_ENABLE_OFFSET, enabled); + if (priv->rxactive) + { + nrf54l_rxstart(priv); + } + + leave_critical_section(flags); + return ret; +} +#endif + +/**************************************************************************** + * Name: nrf54l_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int nrf54l_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#ifdef CONFIG_SERIAL_TERMIOS + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + struct nrf54l_dev_s *priv = dev->priv; + struct uart_config_s config; + irqstate_t flags; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + flags = enter_critical_section(); + config = priv->config; + leave_critical_section(flags); + + termiosp->c_cflag = ((config.parity != 0) ? PARENB : 0) + | ((config.parity == 1) ? PARODD : 0) + | ((config.stopbits2) ? CSTOPB : 0); + + switch (config.bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + termiosp->c_cflag |= CS8; + break; + } + + cfsetispeed(termiosp, config.baud); + break; + } + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Hardware flow control is not supported. */ + + if ((termiosp->c_cflag & (CCTS_OFLOW | CRTS_IFLOW)) != 0) + { + ret = -EINVAL; + break; + } + + flags = enter_critical_section(); + config = priv->config; + leave_critical_section(flags); + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + config.bits = 5; + break; + + case CS6: + config.bits = 6; + break; + + case CS7: + config.bits = 7; + break; + + case CS8: + config.bits = 8; + break; + + default: + return -EINVAL; + } + + /* Parity */ + + if (termiosp->c_cflag & PARENB) + { + config.parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + config.parity = 0; + } + + /* Stop bits */ + + config.stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Note that only cfgetispeed is used because we have knowledge + * that only one speed is supported. + */ + + config.baud = cfgetispeed(termiosp); + + /* Effect the changes */ + + ret = nrf54l_set_format(dev, &config); + break; + } +#endif + + default: + { + ret = -ENOTTY; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: nrf54l_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int nrf54l_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct nrf54l_dev_s *priv = dev->priv; + + if (status) + { + *status = priv->rxstatus; + } + + priv->rxstatus = 0; + priv->rxvalid = false; + return priv->rxchar; +} + +/**************************************************************************** + * Name: nrf54l_rxint + * + * Description: + * Enable or disable delivery of received characters to the upper half. + * + ****************************************************************************/ + +static void nrf54l_rxint(struct uart_dev_s *dev, bool enable) +{ + struct nrf54l_dev_s *priv = dev->priv; + +#ifdef CONFIG_SUPPRESS_SERIAL_INTS + priv->rxenabled = false; +#else + priv->rxenabled = enable; +#endif +} + +/**************************************************************************** + * Name: nrf54l_rxavailable + * + * Description: + * Report whether a received character is waiting for the upper half. + * + ****************************************************************************/ + +static bool nrf54l_rxavailable(struct uart_dev_s *dev) +{ + struct nrf54l_dev_s *priv = dev->priv; + + return priv->rxvalid; +} + +/**************************************************************************** + * Name: nrf54l_send + * + * Description: + * Start transmitting the character supplied by the upper half. + * + ****************************************************************************/ + +static void nrf54l_send(struct uart_dev_s *dev, int ch) +{ + struct nrf54l_dev_s *priv = dev->priv; + irqstate_t flags = enter_critical_section(); + + nrf54l_txstart(priv, ch); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: nrf54l_txint + * + * Description: + * Enable or disable transmission from the upper-half transmit buffer. + * + ****************************************************************************/ + +static void nrf54l_txint(struct uart_dev_s *dev, bool enable) +{ + struct nrf54l_dev_s *priv = dev->priv; + irqstate_t flags = enter_critical_section(); + +#ifdef CONFIG_SUPPRESS_SERIAL_INTS + enable = false; +#endif + + priv->txenabled = enable; + if (enable) + { + uart_xmitchars(dev); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: nrf54l_txready + * + * Description: + * Report whether the transmitter can accept another character. + * + ****************************************************************************/ + +static bool nrf54l_txready(struct uart_dev_s *dev) +{ + struct nrf54l_dev_s *priv = dev->priv; + + return !priv->txbusy; +} + +/**************************************************************************** + * Name: nrf54l_txempty + * + * Description: + * Return true if the transmit data register is empty + * + ****************************************************************************/ + +static bool nrf54l_txempty(struct uart_dev_s *dev) +{ + struct nrf54l_dev_s *priv = dev->priv; + + return !priv->txbusy; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during boot up. This must be called + * before arm_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in nrf54l_lowsetup() and main clock + * initialization performed in nrf54l_clockconfig(). + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void nrf54l_earlyserialinit(void) +{ + /* Configure whichever one is the console */ + +#ifdef HAVE_UART_CONSOLE + CONSOLE_DEV.isconsole = true; + nrf54l_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that nrf54l_earlyserialinit was called previously. + * + * Input Parameters: + * None + * + * Returns Value: + * None + * + ****************************************************************************/ + +void arm_serialinit(void) +{ + unsigned minor = 0; + unsigned i = 0; + char devname[16]; + +#ifdef HAVE_UART_CONSOLE + /* Register the serial console */ + + CONSOLE_DEV.isconsole = true; + uart_register("/dev/console", &CONSOLE_DEV); + uart_register("/dev/ttyS0", &TTYS0_DEV); + minor = 1; +#endif + + /* Register all remaining UARTs */ + + strlcpy(devname, "/dev/ttySx", sizeof(devname)); + + for (i = 0; i < NRF54L_NUART; i++) + { + /* Don't create a device for non-configured ports. */ + + if (g_uart_devs[i] == NULL) + { + continue; + } + + /* Don't create a device for the console - we did that above */ + + if (g_uart_devs[i]->isconsole) + { + continue; + } + + /* Register USARTs as devices in increasing order */ + + devname[9] = '0' + minor++; + uart_register(devname, g_uart_devs[i]); + } +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes. + * + ****************************************************************************/ + +void up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + struct nrf54l_dev_s *priv = CONSOLE_DEV.priv; + irqstate_t flags = enter_critical_section(); + + /* Serialize polled debug output with the interrupt-driven transmitter. + * TXSTOPPED, rather than DMA END, guarantees the pin is idle before reuse. + */ + + if (priv->txbusy) + { + while (!nrf54l_uart_getreg(priv, NRF54L_UARTE_EVENTS_TXSTOPPED_OFFSET)) + { + } + } + + arm_lowputc(ch); + priv->txbusy = false; + leave_critical_section(flags); +#endif +} + +#else /* HAVE_UART_DEVICE && USE_SERIALDRIVER */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes. + * + ****************************************************************************/ + +void up_putc(int ch) +{ + arm_lowputc(ch); +} + +#endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER */ diff --git a/arch/arm/src/nrf54l/nrf54l_serial.h b/arch/arm/src/nrf54l/nrf54l_serial.h new file mode 100644 index 00000000000..326dff61756 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_serial.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_serial.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_NRF54L_SERIAL_H +#define __ARCH_ARM_SRC_NRF54L_NRF54L_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +/**************************************************************************** + * Name: nrf54l_earlyserialinit + * + * Description: + * Initialize the serial console before device registration. + * + ****************************************************************************/ + +void nrf54l_earlyserialinit(void); +#endif + +#endif /* __ARCH_ARM_SRC_NRF54L_NRF54L_SERIAL_H */ diff --git a/arch/arm/src/nrf54l/nrf54l_start.c b/arch/arm/src/nrf54l/nrf54l_start.c new file mode 100644 index 00000000000..524989f4152 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_start.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "nrf54l_start.h" +#include "nrf54l_clockconfig.h" +#include "nrf54l_lowputc.h" +#include "nrf54l_serial.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) arm_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void __start(void) noinstrument_function; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * Initialize memory and chip hardware before starting NuttX. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + +#ifdef CONFIG_ARMV8M_STACKCHECK + /* Set the stack limit before calling instrumented functions. */ + + __asm__ volatile("sub r10, sp, %0" : : + "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); +#endif + + /* Keep interrupts masked until up_irqinitialize() installs the handlers. */ + + __asm__ volatile("cpsid i" : : : "memory"); + + for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } + + for (src = (const uint32_t *)_eronly, dest = (uint32_t *)_sdata; + dest < (uint32_t *)_edata; + ) + { + *dest++ = *src++; + } + +#ifdef CONFIG_ARMV8M_STACKCHECK + arm_stack_check_init(); +#endif + +#ifdef CONFIG_ARCH_FPU + arm_fpuconfig(); +#endif + + nrf54l_clockconfig(); + + nrf54l_lowsetup(); + showprogress('A'); + +#ifdef CONFIG_ARCH_PERF_EVENTS + up_perf_init((void *)BOARD_SYSTICK_CLOCK); +#endif + +#if defined(CONFIG_NRF54L_UART) && defined(USE_EARLYSERIALINIT) + nrf54l_earlyserialinit(); +#endif + + showprogress('B'); + + nrf54l_board_initialize(); + showprogress('C'); + + showprogress('\r'); + showprogress('\n'); + nx_start(); +} diff --git a/arch/arm/src/nrf54l/nrf54l_start.h b/arch/arm/src/nrf54l/nrf54l_start.h new file mode 100644 index 00000000000..da92d63af46 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_start.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_start.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_NRF54L_START_H +#define __ARCH_ARM_SRC_NRF54L_NRF54L_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_board_initialize + * + * Description: + * Initialize board hardware before starting the operating system. + * + ****************************************************************************/ + +void nrf54l_board_initialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_NRF54L_NRF54L_START_H */ diff --git a/arch/arm/src/nrf54l/nrf54l_systick.c b/arch/arm/src/nrf54l/nrf54l_systick.c new file mode 100644 index 00000000000..650304562b1 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_systick.c @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_systick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "systick.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * Initialize the Cortex-M SysTick timer used by the scheduler. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + /* Use SysTick to drive system timer */ + + up_timer_set_lowerhalf(systick_initialize(true, BOARD_SYSTICK_CLOCK, -1)); +} diff --git a/arch/arm/src/nrf54l/nrf54l_uid.c b/arch/arm/src/nrf54l/nrf54l_uid.c new file mode 100644 index 00000000000..fb70aa55d29 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_uid.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_uid.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm_internal.h" +#include "nrf54l_uid.h" + +#include "hardware/nrf54l_ficr.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf54l_get_uniqueid + * + * Description: + * Read the 64-bit factory device identifier in little-endian byte order. + * + ****************************************************************************/ + +void nrf54l_get_uniqueid(uint8_t uniqueid[8]) +{ + uint32_t uid0 = getreg32(NRF54L_FICR_INFO_DEVICEID(0)); + uint32_t uid1 = getreg32(NRF54L_FICR_INFO_DEVICEID(1)); + + uniqueid[0] = (uint8_t)((uid0 >> 0) & 0xff); + uniqueid[1] = (uint8_t)((uid0 >> 8) & 0xff); + uniqueid[2] = (uint8_t)((uid0 >> 16) & 0xff); + uniqueid[3] = (uint8_t)((uid0 >> 24) & 0xff); + uniqueid[4] = (uint8_t)((uid1 >> 0) & 0xff); + uniqueid[5] = (uint8_t)((uid1 >> 8) & 0xff); + uniqueid[6] = (uint8_t)((uid1 >> 16) & 0xff); + uniqueid[7] = (uint8_t)((uid1 >> 24) & 0xff); +} diff --git a/arch/arm/src/nrf54l/nrf54l_uid.h b/arch/arm/src/nrf54l/nrf54l_uid.h new file mode 100644 index 00000000000..c62b520ec46 --- /dev/null +++ b/arch/arm/src/nrf54l/nrf54l_uid.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/nrf54l/nrf54l_uid.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF54L_NRF54L_UID_H +#define __ARCH_ARM_SRC_NRF54L_NRF54L_UID_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void nrf54l_get_uniqueid(uint8_t uniqueid[8]); + +#endif /* __ARCH_ARM_SRC_NRF54L_NRF54L_UID_H */