diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 935d1a97512..cdf4df2bb13 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -85,6 +85,15 @@ config ARCH_CHIP_AM335X ---help--- TI AM335X family: AM3356, AM3357, AM3358, AM3359 (ARM Cortex-A8) +config ARCH_CHIP_AM67 + bool "AM67" + select ARCH_CORTEXR5 + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_LOWVECTORS + select ARCH_HAVE_TICKLESS + ---help--- + TI AM67 family + config ARCH_CHIP_FVP_ARMV8R_AARCH32 bool "ARM FVP virt platform (ARMv8r AARCH32)" select ARCH_CORTEXR52 @@ -1165,6 +1174,7 @@ config ARCH_CHIP string default "a1x" if ARCH_CHIP_A1X default "am335x" if ARCH_CHIP_AM335X + default "am67" if ARCH_CHIP_AM67 default "fvp-v8r-aarch32" if ARCH_CHIP_FVP_ARMV8R_AARCH32 default "c5471" if ARCH_CHIP_C5471 default "dm320" if ARCH_CHIP_DM320 @@ -1592,6 +1602,9 @@ endif if ARCH_CHIP_AM335X source "arch/arm/src/am335x/Kconfig" endif +if ARCH_CHIP_AM67 +source "arch/arm/src/am67/Kconfig" +endif if ARCH_CHIP_FVP_ARMV8R_AARCH32 source "arch/arm/src/fvp-v8r-aarch32/Kconfig" endif diff --git a/arch/arm/include/am67/irq.h b/arch/arm/include/am67/irq.h new file mode 100644 index 00000000000..2b32acd7e06 --- /dev/null +++ b/arch/arm/include/am67/irq.h @@ -0,0 +1,319 @@ +/**************************************************************************** + * arch/arm/include/am67/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_AM67_IRQ_H +#define __ARCH_ARM_INCLUDE_AM67_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CSLR_R5FSS0_CORE0_INTR_SMS0_AESEIP38T_0_AES_SINTREQUEST_P_0 (1U) +#define CSLR_R5FSS0_CORE0_INTR_SMS0_AESEIP38T_0_AES_SINTREQUEST_S_0 (2U) +#define CSLR_R5FSS0_CORE0_INTR_R5FSS0_CORE0_EXP_INTR_0 (4U) +#define CSLR_R5FSS0_CORE0_INTR_DMPAC0_DMPAC_LEVEL_0 (5U) +#define CSLR_R5FSS0_CORE0_INTR_DMPAC0_DMPAC_LEVEL_1 (6U) +#define CSLR_R5FSS0_CORE0_INTR_SA3_SS0_INTAGGR_0_INTAGGR_VINTR_7 (7U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_32 (8U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_33 (9U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_34 (10U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_35 (11U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_36 (12U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_37 (13U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_38 (14U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_39 (15U) +#define CSLR_R5FSS0_CORE0_INTR_SA3_SS0_SA_UL_0_SA_UL_PKA_0 (16U) +#define CSLR_R5FSS0_CORE0_INTR_SA3_SS0_SA_UL_0_SA_UL_TRNG_0 (17U) +#define CSLR_R5FSS0_CORE0_INTR_SMS0_TIFS_CBASS_0_FW_EXCEPTION_INTR_0 (19U) +#define CSLR_R5FSS0_CORE0_INTR_SMS0_COMMON_0_COMBINED_SEC_IN_0 (20U) +#define CSLR_R5FSS0_CORE0_INTR_SMS0_HSM_CBASS_0_FW_EXCEPTION_INTR_0 (21U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_GPU_GPIO_REQACK_GLUE_GPU_GPIO_ACKINT_LVL_0 (22U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_GPU_GPIO_REQACK_GLUE_GPU_GPIO_REQINT_LVL_0 (23U) +#define CSLR_R5FSS0_CORE0_INTR_TIMER0_INTR_PEND_0 (24U) +#define CSLR_R5FSS0_CORE0_INTR_TIMER1_INTR_PEND_0 (25U) +#define CSLR_R5FSS0_CORE0_INTR_TIMER2_INTR_PEND_0 (26U) +#define CSLR_R5FSS0_CORE0_INTR_TIMER3_INTR_PEND_0 (27U) +#define CSLR_R5FSS0_CORE0_INTR_TIMER4_INTR_PEND_0 (28U) +#define CSLR_R5FSS0_CORE0_INTR_TIMER5_INTR_PEND_0 (29U) +#define CSLR_R5FSS0_CORE0_INTR_RTI8_INTR_WWD_0 (30U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_MCU_CBASS_INTR_OR_GLUE_OUT_0 (31U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_12 (32U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_13 (33U) +#define CSLR_R5FSS0_CORE0_INTR_TIMER6_INTR_PEND_0 (34U) +#define CSLR_R5FSS0_CORE0_INTR_TIMER7_INTR_PEND_0 (35U) +#define CSLR_R5FSS0_CORE0_INTR_EPWM0_EPWM_ETINT_0 (36U) +#define CSLR_R5FSS0_CORE0_INTR_EPWM1_EPWM_ETINT_0 (37U) +#define CSLR_R5FSS0_CORE0_INTR_EPWM2_EPWM_ETINT_0 (38U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_MCU_ACCESS_ERR_INTR_GLUE_OUT_0 (39U) +#define CSLR_R5FSS0_CORE0_INTR_DSS0_DISPC_INTR_REQ_0_0 (40U) +#define CSLR_R5FSS0_CORE0_INTR_DSS0_DISPC_INTR_REQ_1_0 (41U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 (42U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_MCAN0_MCANSS_MCAN_LVL_INT_0 (43U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_MCAN0_MCANSS_MCAN_LVL_INT_1 (44U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 (45U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_MCAN1_MCANSS_MCAN_LVL_INT_0 (46U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_MCAN1_MCANSS_MCAN_LVL_INT_1 (47U) +#define CSLR_R5FSS0_CORE0_INTR_CPSW0_CPTS_COMP_0 (48U) +#define CSLR_R5FSS0_CORE0_INTR_PCIE0_PCIE_CPTS_COMP_0 (49U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_TX_IF0_CSI_INTERRUPT_0 (50U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_TX_IF0_CSI_LEVEL_0 (51U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_OTGIRQ_0 (52U) +#define CSLR_R5FSS0_CORE0_INTR_PCIE0_PCIE_CPTS_PEND_0 (53U) +#define CSLR_R5FSS0_CORE0_INTR_PCIE0_PCIE_PWR_STATE_PULSE_0 (54U) +#define CSLR_R5FSS0_CORE0_INTR_PCIE0_PCIE_HOT_RESET_PULSE_0 (55U) +#define CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_20 (56U) +#define CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_21 (57U) +#define CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_32 (58U) +#define CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_33 (59U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_14 (60U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_15 (61U) +#define CSLR_R5FSS0_CORE0_INTR_MCAN1_MCANSS_MCAN_LVL_INT_1 (63U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_152 (64U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_153 (65U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_154 (66U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_155 (67U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_156 (68U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_157 (69U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_158 (70U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_159 (71U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_160 (72U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_161 (73U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_162 (74U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_163 (75U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_164 (76U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_165 (77U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_166 (78U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_167 (79U) +#define CSLR_R5FSS0_CORE0_INTR_EPWM0_EPWM_TRIPZINT_0 (80U) +#define CSLR_R5FSS0_CORE0_INTR_EPWM1_EPWM_TRIPZINT_0 (81U) +#define CSLR_R5FSS0_CORE0_INTR_EPWM2_EPWM_TRIPZINT_0 (82U) +#define CSLR_R5FSS0_CORE0_INTR_ECAP0_ECAP_INT_0 (83U) +#define CSLR_R5FSS0_CORE0_INTR_ECAP1_ECAP_INT_0 (84U) +#define CSLR_R5FSS0_CORE0_INTR_ECAP2_ECAP_INT_0 (85U) +#define CSLR_R5FSS0_CORE0_INTR_EQEP0_EQEP_INT_0 (86U) +#define CSLR_R5FSS0_CORE0_INTR_EQEP1_EQEP_INT_0 (87U) +#define CSLR_R5FSS0_CORE0_INTR_EQEP2_EQEP_INT_0 (88U) +#define CSLR_R5FSS0_CORE0_INTR_R5FSS0_COMMON0_COMMRX_LEVEL_0_0 (90U) +#define CSLR_R5FSS0_CORE0_INTR_R5FSS0_COMMON0_COMMTX_LEVEL_0_0 (91U) +#define CSLR_R5FSS0_CORE0_INTR_DSS1_DISPC_INTR_REQ_0_0 (92U) +#define CSLR_R5FSS0_CORE0_INTR_DSS1_DISPC_INTR_REQ_1_0 (93U) +#define CSLR_R5FSS0_CORE0_INTR_R5FSS0_CORE0_PMU_0 (94U) +#define CSLR_R5FSS0_CORE0_INTR_R5FSS0_CORE0_VALFIQ_0 (95U) +#define CSLR_R5FSS0_CORE0_INTR_R5FSS0_CORE0_VALIRQ_0 (96U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_RTCSS0_RTC_EVENT_PEND_0 (97U) +#define CSLR_R5FSS0_CORE0_INTR_PCIE0_PCIE_DOWNSTREAM_PULSE_0 (99U) +#define CSLR_R5FSS0_CORE0_INTR_JPGENC0_IRQ_0 (100U) +#define CSLR_R5FSS0_CORE0_INTR_GPMC0_GPMC_SINTERRUPT_0 (103U) +#define CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_16 (104U) +#define CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_17 (105U) +#define CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_18 (106U) +#define CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_19 (107U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_DCC0_INTR_DONE_LEVEL_0 (108U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_MAIN_DCC_DONE_GLUE_DCC_DONE_0 (109U) +#define CSLR_R5FSS0_CORE0_INTR_MCAN1_MCANSS_MCAN_LVL_INT_0 (110U) +#define CSLR_R5FSS0_CORE0_INTR_SMS0_RAT_1_EXP_INTR_0 (111U) +#define CSLR_R5FSS0_CORE0_INTR_SMS0_RAT_0_EXP_INTR_0 (112U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGICN_MAIN_PBIST_CPU_GLUE_OUT_0 (113U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_WKUP_PBIST_CPUINTR_OUT_0 (114U) +#define CSLR_R5FSS0_CORE0_INTR_MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_3 (115U) +#define CSLR_R5FSS0_CORE0_INTR_MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_3 (116U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP3_XMIT_INTR_PEND_0 (117U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP3_REC_INTR_PEND_0 (118U) +#define CSLR_R5FSS0_CORE0_INTR_MCRC64_0_INT_MCRC_0 (119U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP0_REC_INTR_PEND_0 (120U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP0_XMIT_INTR_PEND_0 (121U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP1_REC_INTR_PEND_0 (122U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP1_XMIT_INTR_PEND_0 (123U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP2_REC_INTR_PEND_0 (124U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP2_XMIT_INTR_PEND_0 (125U) +#define CSLR_R5FSS0_CORE0_INTR_PCIE0_PCIE_DPA_PULSE_0 (126U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_SOC_ACCESS_ERR_INTR_GLUE_OUT_0 (128U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_24 (129U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_25 (130U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_26 (131U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_27 (132U) +#define CSLR_R5FSS0_CORE0_INTR_CODEC0_VPU_WAVE521CL_INTR_0 (133U) +#define CSLR_R5FSS0_CORE0_INTR_CPSW0_EVNT_PEND_0 (134U) +#define CSLR_R5FSS0_CORE0_INTR_CPSW0_MDIO_PEND_0 (135U) +#define CSLR_R5FSS0_CORE0_INTR_CPSW0_STAT_PEND_0 (136U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_DCC1_INTR_DONE_LEVEL_0 (137U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_28 (138U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_29 (139U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_CFG_LVL_0 (140U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_HI_LVL_0 (141U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_LOW_LVL_0 (142U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_30 (143U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_31 (144U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_PSC0_PSC_ALLINT_0 (145U) +#define CSLR_R5FSS0_CORE0_INTR_PSC0_PSC_ALLINT_0 (146U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_SOC_CBASS_ERR_INTR_GLUE_MAIN_CBASS_AGG_ERR_INTR_0 (147U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_PBIST0_DFT_PBIST_CPU_0 (149U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_23 (150U) +#define CSLR_R5FSS0_CORE0_INTR_DDR32SS0_DDRSS_CONTROLLER_0 (151U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_MGASKET_INTR_GLUE_OUT_0 (152U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_SGASKET_INTR_GLUE_OUT_0 (153U) +#define CSLR_R5FSS0_CORE0_INTR_SERDES_10G1_PHY_PWR_TIMEOUT_LVL_0 (154U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF3_CSI_ERR_IRQ_0 (155U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF3_CSI_IRQ_0 (156U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF3_CSI_LEVEL_0 (157U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_14 (158U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_15 (159U) +#define CSLR_R5FSS0_CORE0_INTR_DMASS1_INTAGGR_0_INTAGGR_VINTR_PEND_22 (160U) +#define CSLR_R5FSS0_CORE0_INTR_MMCSD0_EMMCSS_INTR_0 (161U) +#define CSLR_R5FSS0_CORE0_INTR_MMCSD1_EMMCSDSS_INTR_0 (162U) +#define CSLR_R5FSS0_CORE0_INTR_MMCSD2_EMMCSDSS_INTR_0 (163U) +#define CSLR_R5FSS0_CORE0_INTR_ELM0_ELM_POROCPSINTERRUPT_LVL_0 (164U) +#define CSLR_R5FSS0_CORE0_INTR_PCIE0_PCIE_PTM_VALID_PULSE_0 (165U) +#define CSLR_R5FSS0_CORE0_INTR_SERDES_10G0_PHY_PWR_TIMEOUT_LVL_0 (166U) +#define CSLR_R5FSS0_CORE0_INTR_ESM0_ESM_INT_CFG_LVL_0 (167U) +#define CSLR_R5FSS0_CORE0_INTR_ESM0_ESM_INT_HI_LVL_0 (168U) +#define CSLR_R5FSS0_CORE0_INTR_ESM0_ESM_INT_LOW_LVL_0 (169U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF0_CSI_ERR_IRQ_0 (170U) +#define CSLR_R5FSS0_CORE0_INTR_FSS0_OSPI_0_OSPI_LVL_INTR_0 (171U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF1_CSI_ERR_IRQ_0 (172U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF0_CSI_IRQ_0 (173U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF0_CSI_LEVEL_0 (174U) +#define CSLR_R5FSS0_CORE0_INTR_R5FSS0_CORE0_CTI_0 (175U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF1_CSI_IRQ_0 (176U) +#define CSLR_R5FSS0_CORE0_INTR_DDPA0_DDPA_INTR_0 (177U) +#define CSLR_R5FSS0_CORE0_INTR_VPAC0_VPAC_LEVEL_0 (178U) +#define CSLR_R5FSS0_CORE0_INTR_VPAC0_VPAC_LEVEL_1 (179U) +#define CSLR_R5FSS0_CORE0_INTR_VPAC0_VPAC_LEVEL_2 (180U) +#define CSLR_R5FSS0_CORE0_INTR_DDR32SS0_DDRSS_PLL_FREQ_CHANGE_REQ_0 (181U) +#define CSLR_R5FSS0_CORE0_INTR_VPAC0_VPAC_LEVEL_3 (182U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_VTM0_THERM_LVL_GT_TH1_INTR_0 (183U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_VTM0_THERM_LVL_GT_TH2_INTR_0 (184U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_VTM0_THERM_LVL_LT_TH0_INTR_0 (185U) +#define CSLR_R5FSS0_CORE0_INTR_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 (186U) +#define CSLR_R5FSS0_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_0 (187U) +#define CSLR_R5FSS0_CORE0_INTR_MCAN0_MCANSS_MCAN_LVL_INT_1 (188U) +#define CSLR_R5FSS0_CORE0_INTR_VPAC0_VPAC_LEVEL_4 (189U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_I2C0_POINTRPEND_0 (190U) +#define CSLR_R5FSS0_CORE0_INTR_VPAC0_VPAC_LEVEL_5 (191U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_MCRC64_0_INT_MCRC_0 (192U) +#define CSLR_R5FSS0_CORE0_INTR_I2C0_POINTRPEND_0 (193U) +#define CSLR_R5FSS0_CORE0_INTR_I2C1_POINTRPEND_0 (194U) +#define CSLR_R5FSS0_CORE0_INTR_I2C2_POINTRPEND_0 (195U) +#define CSLR_R5FSS0_CORE0_INTR_I2C3_POINTRPEND_0 (196U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_I2C0_POINTRPEND_0 (197U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF2_CSI_ERR_IRQ_0 (198U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF2_CSI_IRQ_0 (199U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF2_CSI_LEVEL_0 (200U) +#define CSLR_R5FSS0_CORE0_INTR_DEBUGSS0_AQCMPINTR_LEVEL_0 (201U) +#define CSLR_R5FSS0_CORE0_INTR_DEBUGSS0_CTM_LEVEL_0 (202U) +#define CSLR_R5FSS0_CORE0_INTR_GLUELOGIC_GLUE_EXT_INTN_OUT_0 (203U) +#define CSLR_R5FSS0_CORE0_INTR_MCSPI0_INTR_SPI_0 (204U) +#define CSLR_R5FSS0_CORE0_INTR_MCSPI1_INTR_SPI_0 (205U) +#define CSLR_R5FSS0_CORE0_INTR_MCSPI2_INTR_SPI_0 (206U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_MCSPI0_INTR_SPI_0 (207U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_MCSPI1_INTR_SPI_0 (208U) +#define CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF1_CSI_LEVEL_0 (209U) +#define CSLR_R5FSS0_CORE0_INTR_UART0_USART_IRQ_0 (210U) +#define CSLR_R5FSS0_CORE0_INTR_UART1_USART_IRQ_0 (211U) +#define CSLR_R5FSS0_CORE0_INTR_UART2_USART_IRQ_0 (212U) +#define CSLR_R5FSS0_CORE0_INTR_UART3_USART_IRQ_0 (213U) +#define CSLR_R5FSS0_CORE0_INTR_UART4_USART_IRQ_0 (214U) +#define CSLR_R5FSS0_CORE0_INTR_UART5_USART_IRQ_0 (215U) +#define CSLR_R5FSS0_CORE0_INTR_UART6_USART_IRQ_0 (216U) +#define CSLR_R5FSS0_CORE0_INTR_MCU_UART0_USART_IRQ_0 (217U) +#define CSLR_R5FSS0_CORE0_INTR_DSS_DSI0_DSI_0_FUNC_INTR_0 (218U) +#define CSLR_R5FSS0_CORE0_INTR_WKUP_UART0_USART_IRQ_0 (219U) +#define CSLR_R5FSS0_CORE0_INTR_USB0_IRQ_0 (220U) +#define CSLR_R5FSS0_CORE0_INTR_USB0_IRQ_1 (221U) +#define CSLR_R5FSS0_CORE0_INTR_USB0_IRQ_2 (222U) +#define CSLR_R5FSS0_CORE0_INTR_USB0_IRQ_3 (223U) +#define CSLR_R5FSS0_CORE0_INTR_USB0_IRQ_4 (224U) +#define CSLR_R5FSS0_CORE0_INTR_USB0_IRQ_5 (225U) +#define CSLR_R5FSS0_CORE0_INTR_USB0_IRQ_6 (226U) +#define CSLR_R5FSS0_CORE0_INTR_USB0_IRQ_7 (227U) +#define CSLR_R5FSS0_CORE0_INTR_USB0_MISC_LEVEL_0 (228U) +#define CSLR_R5FSS0_CORE0_INTR_MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 (229U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_IRQ_0 (230U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_IRQ_1 (231U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_IRQ_2 (232U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_IRQ_3 (233U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_IRQ_4 (234U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_IRQ_5 (235U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_IRQ_6 (236U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_IRQ_7 (237U) +#define CSLR_R5FSS0_CORE0_INTR_USB1_HOST_SYSTEM_ERROR_0 (238U) +#define CSLR_R5FSS0_CORE0_INTR_I2C4_POINTRPEND_0 (239U) +#define CSLR_R5FSS0_CORE0_INTR_MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_3 (240U) +#define CSLR_R5FSS0_CORE0_INTR_MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_3 (241U) +#define CSLR_R5FSS0_CORE0_INTR_MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_3 (242U) +#define CSLR_R5FSS0_CORE0_INTR_MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_3 (243U) +#define CSLR_R5FSS0_CORE0_INTR_C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_24 (244U) +#define CSLR_R5FSS0_CORE0_INTR_C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_25 (245U) +#define CSLR_R5FSS0_CORE0_INTR_C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_26 (246U) +#define CSLR_R5FSS0_CORE0_INTR_C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_27 (247U) +#define CSLR_R5FSS0_CORE0_INTR_GPU0_GPU_PWRCTRL_REQ_0 (248U) +#define CSLR_R5FSS0_CORE0_INTR_C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_24 (249U) +#define CSLR_R5FSS0_CORE0_INTR_C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_25 (250U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP4_XMIT_INTR_PEND_0 (251U) +#define CSLR_R5FSS0_CORE0_INTR_MCASP4_REC_INTR_PEND_0 (252U) +#define CSLR_R5FSS0_CORE0_INTR_C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_26 (254U) +#define CSLR_R5FSS0_CORE0_INTR_C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_27 (255U) + +#define NR_IRQS 256 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_AM67_IRQ_H */ diff --git a/arch/arm/src/am67/CMakeLists.txt b/arch/arm/src/am67/CMakeLists.txt new file mode 100644 index 00000000000..563fd01fefa --- /dev/null +++ b/arch/arm/src/am67/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/am67/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS am67_boot.c am67_irq.c am67_mpuinit.c am67_pinmux.c am67_serial.c + am67_timer.c) + +target_link_options(nuttx PRIVATE -Wl,--entry=_vector_start) + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/am67/Kconfig b/arch/arm/src/am67/Kconfig new file mode 100644 index 00000000000..d461a787ab4 --- /dev/null +++ b/arch/arm/src/am67/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "AM67 Configuration Options" diff --git a/arch/arm/src/am67/Make.defs b/arch/arm/src/am67/Make.defs new file mode 100644 index 00000000000..89a92240ab4 --- /dev/null +++ b/arch/arm/src/am67/Make.defs @@ -0,0 +1,32 @@ +############################################################################ +# arch/arm/src/am67/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-r/Make.defs + +LDFLAGS += --entry=_vector_start + +CHIP_CSRCS += am67_boot.c +CHIP_CSRCS += am67_irq.c +CHIP_CSRCS += am67_mpuinit.c +CHIP_CSRCS += am67_pinmux.c +CHIP_CSRCS += am67_serial.c +CHIP_CSRCS += am67_timer.c diff --git a/arch/arm/src/am67/am67_boot.c b/arch/arm/src/am67/am67_boot.c new file mode 100644 index 00000000000..76e3db760c2 --- /dev/null +++ b/arch/arm/src/am67/am67_boot.c @@ -0,0 +1,178 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "am67_mpuinit.h" +#include "am67_pinmux.h" +#include "arm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUM_VRINGS (0x02) +#define RL_BUFFER_COUNT (0x200) +#define VRING_ALIGN (0x1000) +#define VRING_SIZE (0x8000) +#define VDEV0_VRING_BASE (0xa2200000) +#define RESOURCE_TABLE_BASE (0xa2100000) + +#define NO_RESOURCE_ENTRIES (1) +#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */ +#define RSC_TABLE_VERSION (1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Place resource table in special ELF section */ + +__attribute__ ((section(".resource_table"))) +const struct rptun_rsc_s g_am67_rsc_table = +{ + .rsc_tbl_hdr = + { + RSC_TABLE_VERSION, + NO_RESOURCE_ENTRIES, + { + 0, 0 + } + }, + + .offset = + { + offsetof(struct rptun_rsc_s, rpmsg_vdev) + }, + + .log_trace = + { + RSC_TRACE, 0, 0 + }, + + .rpmsg_vdev = /* SRTM virtio device entry */ + { + RSC_VDEV, + 7, + 2, + RSC_VDEV_FEATURE_NS, + 0, + 0, + 0, + NUM_VRINGS, + { + 0, 0 + } + }, + + .rpmsg_vring0 = + { + VDEV0_VRING_BASE, + VRING_ALIGN, + RL_BUFFER_COUNT, + 0, + 0 + }, + + .rpmsg_vring1 = + { + VDEV0_VRING_BASE + VRING_SIZE, + VRING_ALIGN, + RL_BUFFER_COUNT, + 1, + 0 + }, + + .config = + { + 0 + } +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_boot + * + * Description: + * Complete boot operations started in arm_head.S + * + * Boot Sequence + * + * 1. The __start entry point in armv7-r/arm_head.S is invoked upon power- + * on reset. + * 2. __start prepares CPU for code execution. + * 3a. If CONFIG_ARMV7R_MEMINIT is not defined, then __start will prepare + * memory resources by calling arm_data_initialize() and will then + * branch this function. + * 3b. Otherwise, this function will be called without having initialized + * memory resources! We need to be very careful in this case. Here, + * this function will call tms570_boardinitialize() which, among other + * things, must initialize SDRAM memory. After initializatino of the + * memories, this function will call arm_data_initialize() to + * initialize the memory resources + * 4. This function will then branch to nx_start() to start the operating + * system. + * + ****************************************************************************/ + +void arm_boot(void) +{ + /* Configure the MPU to permit user-space access to its + * ATCM, BTCM and DDR sections + */ + + am67_mpu_init(); + + /* Do pinmux to get UART early */ + + am67_pinmux_init(); + + /* Then start NuttX */ + + nx_start(); +} diff --git a/arch/arm/src/am67/am67_irq.c b/arch/arm/src/am67/am67_irq.c new file mode 100644 index 00000000000..3d3ff7f2a1d --- /dev/null +++ b/arch/arm/src/am67/am67_irq.c @@ -0,0 +1,352 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_irq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "irq/irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define INTR_MAX_INTERRUPTS (512u) +#define INTR_MAX_PRIORITY (16u) +#define INTRC_BASE_ADDR (0x2fff0000u) + +#define VIM_BIT_POS(j) ((j) & 0x1fu) +#define VIM_IRQVEC (0x18u) +#define VIM_ACTIRQ (0x20u) +#define VIM_RAW(j) (0x400u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_STS(j) (0x404u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_EN(j) (0x408u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_DIS(j) (0x40cu + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_MAP(j) (0x418u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_TYPE(j) (0x41cu + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_PRI(j) (0x1000u + ((j) * 0x4u)) +#define VIM_INT_VEC(j) (0x2000u + ((j) * 0x4u)) + +#define INTR_SUCCESS ((int32_t)0) +#define INTR_FAILURE ((int32_t)-1) +#define INTR_TIMEOUT ((int32_t)-2) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int32_t intr_get_irq(uint32_t *int_num); +static void intr_ack_irq(uint32_t int_num); +static void intr_clear_irq(uint32_t int_num); +static void intr_set_irq_pri(uint32_t int_num, uint32_t priority); +static uint32_t intr_get_irq_vec_addr(void); +static void intr_set_irq_vec_addr(uint32_t int_num, uintptr_t vec_addr); + +static void utils_data_and_instruction_barrier(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: intr_get_irq + * + * Description: + * Return the interrupt status corresponding to the given int_num. + * + ****************************************************************************/ + +static int32_t intr_get_irq(uint32_t *int_num) +{ + int32_t status = INTR_FAILURE; + uint32_t value; + + *int_num = 0; + + value = getreg32(INTRC_BASE_ADDR + VIM_ACTIRQ); + + if ((value & 0x80000000u) != 0U) + { + *int_num = (value & (INTR_MAX_INTERRUPTS - 1U)); + status = INTR_SUCCESS; + } + + return status; +} + +/**************************************************************************** + * Name: intr_ack_irq + * + * Description: + * Acknowledge a specific interrupt number by writing to the interrupt + * controller's IRQVEC register. + * + ****************************************************************************/ + +static void intr_ack_irq(uint32_t int_num) +{ + putreg32(int_num, INTRC_BASE_ADDR + VIM_IRQVEC); +} + +/**************************************************************************** + * Name: intr_clear_irq + * + * Description: + * Clear a specific interrupt by setting the corresponding bit in the + * interrupt status register. + * + ****************************************************************************/ + +static void intr_clear_irq(uint32_t int_num) +{ + uint32_t bit_pos; + + bit_pos = VIM_BIT_POS(int_num); + + putreg32((0x1u << bit_pos), INTRC_BASE_ADDR + VIM_STS(int_num)); +} + +/**************************************************************************** + * Name: intr_set_irq_pri + * + * Description: + * Set the priority level (0–15) for a specified interrupt. + * + ****************************************************************************/ + +static void intr_set_irq_pri(uint32_t int_num, uint32_t priority) +{ + putreg32((priority & 0xfu), INTRC_BASE_ADDR + VIM_INT_PRI(int_num)); +} + +/**************************************************************************** + * Name: intr_get_irq_vec_addr + * + * Description: + * Get the interrupt vector address for a specific interrupt number from + * the corresponding interrupt controller register. + * + ****************************************************************************/ + +static uint32_t intr_get_irq_vec_addr(void) +{ + return getreg32(INTRC_BASE_ADDR + VIM_IRQVEC); +} + +/**************************************************************************** + * Name: intr_set_irq_vec_addr + * + * Description: + * Set the interrupt vector address for a specific interrupt number into + * the corresponding interrupt controller register. + * + ****************************************************************************/ + +static void intr_set_irq_vec_addr(uint32_t int_num, uintptr_t vec_addr) +{ + putreg32(((uint32_t)vec_addr & 0xfffffffcu), + INTRC_BASE_ADDR + VIM_INT_VEC(int_num)); +} + +/**************************************************************************** + * Name: utils_data_and_instruction_barrier + * + * Description: + * Enforces CPU memory ordering by executing an Instruction Synchronization + * Barrier (ISB) followed by a Data Synchronization Barrier (DSB), + * ensuring all previous instructions complete and memory accesses are + * synchronized before continuing execution. + * + ****************************************************************************/ + +static void utils_data_and_instruction_barrier(void) +{ + __asm__ __volatile__( + " isb" + "\n\t" + : + : + : "memory"); + __asm__ __volatile__( + " dsb" + "\n\t" + : + : + : "memory"); +} + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +extern int irq_unexpected_isr(int irq, FAR void *context, FAR void *arg); +extern uint32_t *arm_doirq(int irq, uint32_t *regs); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable a specific interrupt by setting the corresponding bit in the + * interrupt enable register after executing a barrier. + * + ****************************************************************************/ + +void up_enable_irq(int int_num) +{ + uint32_t bit_pos; + + utils_data_and_instruction_barrier(); + + bit_pos = VIM_BIT_POS(int_num); + + putreg32((0x1u << bit_pos), INTRC_BASE_ADDR + VIM_INT_EN(int_num)); +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable a specific interrupt by setting the corresponding bit in the + * interrupt disable register and then executing a barrier. + * + ****************************************************************************/ + +void up_disable_irq(int int_num) +{ + uint32_t bit_pos; + + bit_pos = VIM_BIT_POS(int_num); + + putreg32(((uint32_t)0x1 << bit_pos), + INTRC_BASE_ADDR + VIM_INT_DIS(int_num)); + + utils_data_and_instruction_barrier(); +} + +/**************************************************************************** + * Name: up_irqinitialize + * + * Description: + * This function is called by up_initialize() during the bring-up of the + * system. It is the responsibility of this function to but the interrupt + * subsystem into the working and ready state. + * + ****************************************************************************/ + +void up_irqinitialize(void) +{ + int i; + + for (i = 0; i < INTR_MAX_INTERRUPTS; i++) + { + intr_set_irq_pri(i, 0xf); + intr_set_irq_vec_addr((uint32_t)i, (uintptr_t)arm_vectorirq); + } + + for (i = 0; i < INTR_MAX_INTERRUPTS / 32; i++) + { + /* Disable all interrupts. */ + + putreg32(0xffffffffu, INTRC_BASE_ADDR + VIM_INT_DIS(i * 32)); + + /* Clear all pending interrupts. */ + + putreg32(0xffffffffu, INTRC_BASE_ADDR + VIM_STS(i * 32)); + + /* Make all as level. */ + + putreg32(0x0u, INTRC_BASE_ADDR + VIM_INT_TYPE(i * 32)); + + /* Make all as IRQ. */ + + putreg32(0x0u, INTRC_BASE_ADDR + VIM_INT_MAP(i * 32)); + } + + /* Have to read vec addr, sets other registers. */ + + (void)intr_get_irq_vec_addr(); + intr_ack_irq(0); + + for (i = 0; i < NR_IRQS; i++) + { + irq_attach(i, irq_unexpected_isr, NULL); + } + + arm_color_intstack(); + up_irq_enable(); +} + +/**************************************************************************** + * Name: arm_decodeirq + * + * Description: + * This function is called from the IRQ vector handler in arm_vectors.S. + * At this point, the interrupt has been taken and the registers have + * been saved on the stack. This function simply needs to determine the + * the irq number of the interrupt and then to call arm_doirq to dispatch + * the interrupt. + * + * Input parameters: + * regs - A pointer to the register save area on the stack. + * + ****************************************************************************/ + +uint32_t *arm_decodeirq(uint32_t *regs) +{ + uint32_t intr_num; + + /* Have to read vec addr, sets other registers. */ + + (void)intr_get_irq_vec_addr(); + + if (intr_get_irq(&intr_num) == 0) + { + regs = arm_doirq(intr_num, regs); + } + + intr_clear_irq(intr_num); + intr_ack_irq(intr_num); + + return regs; +} diff --git a/arch/arm/src/am67/am67_mpuinit.c b/arch/arm/src/am67/am67_mpuinit.c new file mode 100644 index 00000000000..94b28046cfc --- /dev/null +++ b/arch/arm/src/am67/am67_mpuinit.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_mpuinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "am67_mpuinit.h" +#include "mpu.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_mpu_reset + * + * Description: + * Reset all MPU regions by disabling each region. + * + ****************************************************************************/ + +void am67_mpu_reset(void) +{ + for (int i = 0; i < AM67_NUM_OF_MPU_REGION; i++) + { + mpu_set_region_zero(i); + } +} + +/**************************************************************************** + * Name: am67_mpu_init + * + * Description: + * Initialize the MPU by disabling it, resetting all regions, configuring + * specific memory regions, and then re-enabling the MPU. + * + ****************************************************************************/ + +void am67_mpu_init(void) +{ + mpu_control(false); + + am67_mpu_disable_br(); + + am67_mpu_reset(); + + am67_register_region(AM67_REGISTER_START_ADDR, AM67_REGISTER_SIZE); + am67_tcma_region(AM67_TCMA_START_ADDR, AM67_TCMA_SIZE); + am67_tcmb_region(AM67_TCMB_START_ADDR, AM67_TCMB_SIZE); + am67_mcu_msram_region(AM67_MCU_MSRAM_START_ADDR, AM67_MCU_MSRAM_SIZE); + am67_ddr_region(AM67_DDR_START_ADDR, AM67_DDR_SIZE); + + mpu_control(true); +} diff --git a/arch/arm/src/am67/am67_mpuinit.h b/arch/arm/src/am67/am67_mpuinit.h new file mode 100644 index 00000000000..488c63629be --- /dev/null +++ b/arch/arm/src/am67/am67_mpuinit.h @@ -0,0 +1,194 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_mpuinit.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_AM67_AM67_MPUINIT_H +#define __ARCH_ARM_SRC_AM67_AM67_MPUINIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "mpu.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AM67_NUM_OF_MPU_REGION (5) + +#define AM67_REGISTER_START_ADDR (0x0) +#define AM67_TCMA_START_ADDR (0x0) +#define AM67_TCMB_START_ADDR (0x41010000) +#define AM67_MCU_MSRAM_START_ADDR (0x60000000) +#define AM67_DDR_START_ADDR (0x80000000) + +#define AM67_REGISTER_SIZE (2ul * 1024 * 1024 * 1024) +#define AM67_TCMA_SIZE (32ul * 1024) +#define AM67_TCMB_SIZE (32ul * 1024) +#define AM67_MCU_MSRAM_SIZE (512ul * 1024) + +#define AM67_DDR_SIZE (2ul * 1024 * 1024 * 1024) + +/* REGISTER_REGION + * Not Cacheable + * Not Bufferable + * Shareable + * Execute never + * P:RW U:R + */ +#define am67_register_region(base,size) \ + mpu_configure_region(base, size, MPU_RACR_S | \ + MPU_RACR_AP_RWRW) + +/* TCMA REGION + * Bufferable + * Cacheable + * P:RW U:R0 + * Allow user RW access, executable + */ +#define am67_tcma_region(base, size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_B | \ + MPU_RACR_AP_RWRW) + +/* TCMB REGION + * Bufferable + * Cacheable + * P:RW U:R0 + * Allow user RW access, executable + */ +#define am67_tcmb_region(base, size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_B | \ + MPU_RACR_C | \ + MPU_RACR_AP_RWRW) + +/* TCMB REGION + * Bufferable + * Cacheable + * P:RW U:R0 + * Allow user RW access, executable + */ +#define am67_mcu_msram_region(base,size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_C | \ + MPU_RACR_B | \ + MPU_RACR_AP_RWRW) + +/* DDR REGION + * Shareable + * Cacheable + * Bufferable + * P:RW U:RW + */ +#define am67_ddr_region(base,size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_S | \ + MPU_RACR_C | \ + MPU_RACR_B | \ + MPU_RACR_AP_RWRW) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_mpu_disable_br + * + * Description: + * Disable the MPU background region by clearing bit 17 in the SCTLR + * register. + * + ****************************************************************************/ + +static inline void am67_mpu_disable_br(void) +{ + unsigned int sctlr = cp15_rdsctlr(); + sctlr &= ~(1 << 17); /* Clear bit 17 (disable background region) */ + cp15_wrsctlr(sctlr); +} + +/**************************************************************************** + * Name: mpu_set_region_zero + * + * Description: + * Configure an MPU region with zero base address, size, and attributes + * effectively disabling the specified region. + * + ****************************************************************************/ + +static inline void mpu_set_region_zero(uint32_t region_id) +{ + register uint32_t r0 asm("r0") = region_id; + register uint32_t r1 asm("r1") = 0; + register uint32_t r2 asm("r2") = 0; + register uint32_t r3 asm("r3") = 0; + + asm volatile ( + "mcr p15, 0, %0, c6, c2, 0\n\t" + "mcr p15, 0, %1, c6, c1, 0\n\t" + "mcr p15, 0, %2, c6, c1, 2\n\t" + "mcr p15, 0, %3, c6, c1, 4\n\t" + : + : "r"(r0), "r"(r1), "r"(r2), "r"(r3) + : "memory" + ); +} + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_mpu_reset + * + * Description: + * Reset all MPU regions by disabling each region. + * + ****************************************************************************/ + +void am67_mpu_reset(void); + +/**************************************************************************** + * Name: am67_mpu_init + * + * Description: + * Initialize the MPU by disabling it, resetting all regions, configuring + * specific memory regions, and then re-enabling the MPU. + * + ****************************************************************************/ + +void am67_mpu_init(void); + +#endif /* __ARCH_ARM_SRC_AM67_AM67_MPUINIT_H*/ diff --git a/arch/arm/src/am67/am67_pinmux.c b/arch/arm/src/am67/am67_pinmux.c new file mode 100644 index 00000000000..3b99c13827e --- /dev/null +++ b/arch/arm/src/am67/am67_pinmux.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_pinmux.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "am67_pinmux.h" +#include "arm_internal.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +static struct pinmux_conf_s g_am67_pinmux_conf[] = +{ + /* UART1_RXD -> MCASP0_AFSR (C27) */ + + { + PIN_MCASP0_AFSR, + (PIN_MODE(2) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE) + }, + + /* UART1_TXD -> MCASP0_ACLKR (F24) */ + + { + PIN_MCASP0_ACLKR, + (PIN_MODE(2) | PIN_PULL_DISABLE) + }, + + /* RED LED -> OLDI0_A0N (AF23) */ + + { + PIN_OLDI0_A0N, + (PIN_MODE(7) | PIN_PULL_DISABLE) + }, + + /* GREEN LED -> OLDI0_A0P (AG24) */ + + { + PIN_OLDI0_A0P, + (PIN_MODE(7) | PIN_PULL_DISABLE) + }, + {PINMUX_END, PINMUX_END} +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_pinmux_unlock + * + * Description: + * Unlock the pinmux configuration registers by writing unlock values to + * both lock registers (Lock0 and Lock1) kick registers. + * + ****************************************************************************/ + +static void am67_pinmux_unlock(void) +{ + uint32_t base_addr; + uint32_t kick_addr; + + base_addr = CSL_PADCFG_CTRL0_CFG0_BASE; + + /* Lock 0 */ + + kick_addr = base_addr + CSL_MAIN_PADCONFIG_LOCK0_KICK0_OFFSET; + putreg32(KICK0_UNLOCK_VAL, kick_addr); + kick_addr += 4; + putreg32(KICK1_UNLOCK_VAL, kick_addr); + + /* Lock 1 */ + + kick_addr = base_addr + CSL_MAIN_PADCONFIG_LOCK1_KICK0_OFFSET; + putreg32(KICK0_UNLOCK_VAL, kick_addr); + kick_addr += 4; + putreg32(KICK1_UNLOCK_VAL, kick_addr); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_pinmux_config + * + * Description: + * Configure pin multiplexing settings by writing configuration values to + * pad configuration registers after unlocking the pinmux registers. + * + ****************************************************************************/ + +void am67_pinmux_config(const struct pinmux_conf_s *pinmux_conf) +{ + if (pinmux_conf != NULL) + { + uint32_t base_addr = CSL_PADCFG_CTRL0_CFG0_BASE + PADCFG_PMUX_OFFSET; + + am67_pinmux_unlock(); + + while (pinmux_conf->offset != PINMUX_END) + { + /* Set all the configuration fields */ + + putreg32(pinmux_conf->setting, base_addr + pinmux_conf->offset); + pinmux_conf++; + } + } +} + +/**************************************************************************** + * Name: am67_pinmux_init + * + * Description: + * Initialize pin multiplexing using the global pinmux configuration array. + * + ****************************************************************************/ + +void am67_pinmux_init(void) +{ + am67_pinmux_config(g_am67_pinmux_conf); +} diff --git a/arch/arm/src/am67/am67_pinmux.h b/arch/arm/src/am67/am67_pinmux.h new file mode 100644 index 00000000000..121b31f79d6 --- /dev/null +++ b/arch/arm/src/am67/am67_pinmux.h @@ -0,0 +1,316 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_pinmux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_AM67_AM67_PINMUX_H +#define __ARCH_ARM_SRC_AM67_AM67_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CSL_PADCFG_CTRL0_CFG0_BASE (0xf0000ul) +#define CSL_PADCFG_CTRL0_CFG0_SIZE (0x8000ul) + +#define CSL_MCU_PADCFG_CTRL0_CFG0_BASE (0x4080000ul) +#define CSL_MCU_PADCFG_CTRL0_CFG0_SIZE (0x8000ul) + +#define PADCFG_PMUX_OFFSET (0x4000u) + +#define CSL_MAIN_PADCONFIG_LOCK0_KICK0_OFFSET (0x1008) +#define CSL_MAIN_PADCONFIG_LOCK1_KICK0_OFFSET (0x5008) +#define CSL_MCU_PADCONFIG_LOCK0_KICK0_OFFSET (0x1008) +#define CSL_MCU_PADCONFIG_LOCK1_KICK0_OFFSET (0x5008) + +#define KICK_LOCK_VAL (0x00000000u) +#define KICK0_UNLOCK_VAL (0x68ef3490u) +#define KICK1_UNLOCK_VAL (0xd172bc5au) + +#define PINMUX_END (-1) + +#define PIN_MODE(mode) ((uint32_t) mode) +#define PIN_PULL_DISABLE (((uint32_t) 0x1u) << 16u) +#define PIN_PULL_DIRECTION (((uint32_t) 0x1u) << 17u) +#define PIN_INPUT_ENABLE (((uint32_t) 0x1u) << 18u) +#define PIN_OUTPUT_DISABLE (((uint32_t) 0x1u) << 21u) +#define PIN_WAKEUP_ENABLE (((uint32_t) 0x1u) << 29u) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum pinmux_main_offsets_e +{ + PIN_MMC1_DAT1 = 0x022c, + PIN_MMC1_DAT0 = 0x0230, + PIN_EXT_REFCLK1 = 0x01f0, + PIN_MMC1_DAT3 = 0x0224, + PIN_MMC1_DAT2 = 0x0228, + PIN_VOUT0_VSYNC = 0x0100, + PIN_VOUT0_HSYNC = 0x00f8, + PIN_VOUT0_PCLK = 0x0104, + PIN_VOUT0_DE = 0x00fc, + PIN_VOUT0_DATA0 = 0x00b8, + PIN_VOUT0_DATA1 = 0x00bc, + PIN_VOUT0_DATA2 = 0x00c0, + PIN_VOUT0_DATA3 = 0x00c4, + PIN_VOUT0_DATA4 = 0x00c8, + PIN_VOUT0_DATA5 = 0x00cc, + PIN_VOUT0_DATA6 = 0x00d0, + PIN_VOUT0_DATA7 = 0x00d4, + PIN_VOUT0_DATA8 = 0x00d8, + PIN_VOUT0_DATA9 = 0x00dc, + PIN_VOUT0_DATA10 = 0x00e0, + PIN_VOUT0_DATA11 = 0x00e4, + PIN_VOUT0_DATA12 = 0x00e8, + PIN_VOUT0_DATA13 = 0x00ec, + PIN_VOUT0_DATA14 = 0x00f0, + PIN_VOUT0_DATA15 = 0x00f4, + PIN_GPMC0_AD8 = 0x005c, + PIN_GPMC0_AD9 = 0x0060, + PIN_GPMC0_AD10 = 0x0064, + PIN_GPMC0_AD11 = 0x0068, + PIN_GPMC0_AD12 = 0x006c, + PIN_GPMC0_AD13 = 0x0070, + PIN_GPMC0_AD14 = 0x0074, + PIN_GPMC0_AD15 = 0x0078, + PIN_GPMC0_WAIT1 = 0x009c, + PIN_SPI0_CS1 = 0x01bb, + PIN_UART0_TXD = 0x01cc, + PIN_UART0_RXD = 0x01c8, + PIN_SPI0_CS0 = 0x01b4, + PIN_MMC0_DAT3 = 0x0208, + PIN_I2C1_SCL = 0x01e8, + PIN_I2C1_SDA = 0x01ec, + PIN_MMC0_CLK = 0x0218, + PIN_MMC0_CMD = 0x0220, + PIN_SPI0_CLK = 0x01bc, + PIN_SPI0_D0 = 0x01c0, + PIN_I2C0_SCL = 0x01e0, + PIN_I2C0_SDA = 0x01e4, + PIN_SPI0_D1 = 0x01c4, + PIN_MMC0_DAT0 = 0x0214, + PIN_MMC0_DAT5 = 0x0200, + PIN_MCAN0_TX = 0x01d8, + PIN_MCAN0_RX = 0x01dc, + PIN_MCASP0_ACLKX = 0x01a4, + PIN_MCASP0_AFSX = 0x01a8, + PIN_MCASP0_ACLKR = 0x01b0, + PIN_MCASP0_AFSR = 0x01ac, + PIN_RGMII2_RD2 = 0x018c, + PIN_RGMII2_RD3 = 0x0190, + PIN_RGMII2_TD2 = 0x0174, + PIN_GPMC0_DIR = 0x00a4, + PIN_MCASP0_AXR3 = 0x0194, + PIN_MCASP0_AXR2 = 0x0198, + PIN_MCASP0_AXR0 = 0x01a0, + PIN_MCASP0_AXR1 = 0x019c, + PIN_GPMC0_CSN3 = 0x00b4, + PIN_GPMC0_WPN = 0x00a0, + PIN_GPMC0_AD0 = 0x003c, + PIN_GPMC0_AD1 = 0x0040, + PIN_GPMC0_AD2 = 0x0044, + PIN_GPMC0_AD3 = 0x0048, + PIN_GPMC0_AD4 = 0x004c, + PIN_GPMC0_AD5 = 0x0050, + PIN_GPMC0_AD6 = 0x0054, + PIN_GPMC0_AD7 = 0x0058, + PIN_GPMC0_WAIT0 = 0x0098, + PIN_GPMC0_BE1N = 0x0094, + PIN_GPMC0_CSN0 = 0x00a8, + PIN_GPMC0_CLK = 0x007c, + PIN_GPMC0_ADVN_ALE = 0x0084, + PIN_GPMC0_OEN_REN = 0x0088, + PIN_GPMC0_WEN = 0x008c, + PIN_GPMC0_BE0N_CLE = 0x0090, + PIN_UART0_CTSN = 0x01d0, + PIN_UART0_RTSN = 0x01d4, + PIN_GPMC0_CSN2 = 0x00b0, + PIN_MMC0_DAT6 = 0x01fc, + PIN_MMC0_DAT7 = 0x01f8, + PIN_OSPI0_D6 = 0x0024, + PIN_OSPI0_D7 = 0x0028, + PIN_OSPI0_D5 = 0x0020, + PIN_RGMII2_TD3 = 0x0178, + PIN_RGMII2_TX_CTL = 0x0164, + PIN_MDIO0_MDC = 0x0160, + PIN_MDIO0_MDIO = 0x015c, + PIN_MMC0_DAT1 = 0x0210, + PIN_MMC0_DAT2 = 0x020c, + PIN_MMC0_DAT4 = 0x0204, + PIN_MMC1_CMD = 0x023c, + PIN_MMC1_CLK = 0x0234, + PIN_MMC1_SDCD = 0x0240, + PIN_MMC1_SDWP = 0x0244, + PIN_MMC2_CMD = 0x0120, + PIN_MMC2_CLK = 0x0118, + PIN_MMC2_DAT0 = 0x0114, + PIN_MMC2_DAT1 = 0x0110, + PIN_MMC2_DAT2 = 0x010c, + PIN_MMC2_DAT3 = 0x0108, + PIN_MMC2_SDCD = 0x0124, + PIN_MMC2_SDWP = 0x0128, + PIN_OLDI0_A0N = 0x0260, + PIN_OLDI0_A0P = 0x025c, + PIN_OLDI0_A1N = 0x0268, + PIN_OLDI0_A1P = 0x0264, + PIN_OLDI0_A2N = 0x0270, + PIN_OLDI0_A2P = 0x026c, + PIN_OLDI0_A3N = 0x0278, + PIN_OLDI0_A3P = 0x0274, + PIN_OLDI0_A4N = 0x0280, + PIN_OLDI0_A4P = 0x027c, + PIN_OLDI0_A5N = 0x0288, + PIN_OLDI0_A5P = 0x0284, + PIN_OLDI0_A6N = 0x0290, + PIN_OLDI0_A6P = 0x028c, + PIN_OLDI0_A7N = 0x0298, + PIN_OLDI0_A7P = 0x0294, + PIN_OLDI0_CLK0N = 0x02a0, + PIN_OLDI0_CLK0P = 0x029c, + PIN_OLDI0_CLK1N = 0x02a8, + PIN_OLDI0_CLK1P = 0x02a4, + PIN_OSPI0_CLK = 0x0000, + PIN_OSPI0_CSN0 = 0x002c, + PIN_OSPI0_CSN1 = 0x0030, + PIN_OSPI0_CSN2 = 0x0034, + PIN_OSPI0_CSN3 = 0x0038, + PIN_OSPI0_D0 = 0x000c, + PIN_OSPI0_D1 = 0x0010, + PIN_OSPI0_D2 = 0x0014, + PIN_OSPI0_D3 = 0x0018, + PIN_OSPI0_D4 = 0x001c, + PIN_OSPI0_DQS = 0x0008, + PIN_RGMII1_RD0 = 0x014c, + PIN_RGMII1_RD1 = 0x0150, + PIN_RGMII1_RD2 = 0x0154, + PIN_RGMII1_RD3 = 0x0158, + PIN_RGMII1_RXC = 0x0148, + PIN_RGMII1_RX_CTL = 0x0144, + PIN_RGMII1_TD0 = 0x0134, + PIN_RGMII1_TD1 = 0x0138, + PIN_RGMII1_TD2 = 0x013c, + PIN_RGMII1_TD3 = 0x0140, + PIN_RGMII1_TXC = 0x0130, + PIN_RGMII1_TX_CTL = 0x012c, + PIN_RGMII2_RD0 = 0x0184, + PIN_RGMII2_RD1 = 0x0188, + PIN_RGMII2_RXC = 0x0180, + PIN_RGMII2_RX_CTL = 0x017c, + PIN_RGMII2_TD0 = 0x016c, + PIN_RGMII2_TD1 = 0x0170, + PIN_RGMII2_TXC = 0x0168, + PIN_EXTINTN = 0x01f4, + PIN_PORZ_OUT = 0x0250, + PIN_RESETSTATZ = 0x024c, + PIN_RESET_REQZ = 0x0248, + PIN_GPMC0_CSN1 = 0x00ac, + PIN_OSPI0_LBCLKO = 0x0004, + PIN_USB1_DRVVBUS = 0x0258, + PIN_USB0_DRVVBUS = 0x0254, + PIN_PCIE0_CLKREQN = 0x02ac, +}; + +enum pinmux_mcu_offsets_e +{ + PIN_EMU0 = 0x0078, + PIN_EMU1 = 0x007c, + PIN_TCK = 0x0064, + PIN_TDI = 0x006c, + PIN_TDO = 0x0070, + PIN_TMS = 0x0074, + PIN_TRSTN = 0x0068, + PIN_MCU_I2C0_SCL = 0x0044, + PIN_MCU_I2C0_SDA = 0x0048, + PIN_MCU_MCAN1_RX = 0x0040, + PIN_MCU_MCAN1_TX = 0x003c, + PIN_MCU_MCAN0_RX = 0x0038, + PIN_MCU_MCAN0_TX = 0x0034, + PIN_MCU_SPI0_CLK = 0x0008, + PIN_MCU_SPI0_CS0 = 0x0000, + PIN_MCU_SPI0_D0 = 0x000c, + PIN_MCU_SPI0_D1 = 0x0010, + PIN_WKUP_UART0_RTSN = 0x0030, + PIN_WKUP_UART0_CTSN = 0x002c, + PIN_MCU_UART0_CTSN = 0x001c, + PIN_MCU_UART0_RTSN = 0x0020, + PIN_MCU_ERRORN = 0x0060, + PIN_MCU_SPI0_CS1 = 0x0004, + PIN_MCU_PORZ = 0x0058, + PIN_MCU_RESETSTATZ = 0x005c, + PIN_MCU_RESETZ = 0x0054, + PIN_MCU_UART0_RXD = 0x0014, + PIN_MCU_UART0_TXD = 0x0018, + PIN_WKUP_I2C0_SCL = 0x004c, + PIN_WKUP_I2C0_SDA = 0x0050, + PIN_WKUP_CLKOUT0 = 0x0084, + PIN_PMIC_LPM_EN0 = 0x0080, + PIN_WKUP_UART0_RXD = 0x0024, + PIN_WKUP_UART0_TXD = 0x0028, +}; + +struct pinmux_conf_s +{ + int16_t offset; + uint32_t setting; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_pinmux_config + * + * Description: + * Configure pin multiplexing settings by writing configuration values to + * pad configuration registers after unlocking the pinmux registers. + * + ****************************************************************************/ + +void am67_pinmux_config(const struct pinmux_conf_s *pinmux_conf); + +/**************************************************************************** + * Name: am67_pinmux_init + * + * Description: + * Initialize pin multiplexing using the global pinmux configuration array. + * + ****************************************************************************/ + +void am67_pinmux_init(void); + +#endif /* __ARCH_ARM_SRC_AM67_AM67_PINMUX_H */ diff --git a/arch/arm/src/am67/am67_serial.c b/arch/arm/src/am67/am67_serial.c new file mode 100644 index 00000000000..e0dbb3d3345 --- /dev/null +++ b/arch/arm/src/am67/am67_serial.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_serial.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +#if defined(USE_SERIALDRIVER) /* && defined(HAVE_UART_DEVICE)*/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: open_uart + * + * Description: + * Initialize UART by clearing the register at offset 0x20 from base. + * + ****************************************************************************/ + +static void open_uart(void) +{ + putreg32(0, CONFIG_16550_UART0_BASE + 0x20); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Initialize the serial port by performing early initialization, main + * initialization, and opening the UART. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ + u16550_earlyserialinit(); + u16550_serialinit(); + open_uart(); +} + +/**************************************************************************** + * Name: uart_getreg + * + * Description: + * Read a value from the UART register at the specified offset from the + * base address. + * + ****************************************************************************/ + +uart_datawidth_t uart_getreg(FAR struct u16550_s *priv, unsigned int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: uart_putreg + * + * Description: + * Write a value to the UART register at the specified offset from the + * base address. + * + ****************************************************************************/ + +void uart_putreg(FAR struct u16550_s *priv, unsigned int offset, + uart_datawidth_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/am67/am67_timer.c b/arch/arm/src/am67/am67_timer.c new file mode 100644 index 00000000000..6730dff4b74 --- /dev/null +++ b/arch/arm/src/am67/am67_timer.c @@ -0,0 +1,502 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TIMER0_CLOCK_SRC_MUX_ADDR (0x1081b0u) +#define TIMER0_CLOCK_SRC_HFOSC0_CLKOUT (0x0u) +#define TIMER0_BASE_ADDR (0x2400000u) + +#define AM67_DMTIMER1_1MS_TIMER0_VADDR (0x2400000) +#define AM67_DMTMR1MS_TIDR_OFFSET (0x0000) /* Identification Register Section */ +#define AM67_DMTMR1MS_TIOCP_CFG_OFFSET (0x0010) /* 1ms Timer OCP Configuration Register Section */ +#define AM67_DMTMR1MS_IRQ_EOI_OFFSET (0x0020) /* 1ms Timer IRQ Wakeup Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_RAW_OFFSET (0x0024) /* 1ms Timer IRQ Status Register */ +#define AM67_DMTMR1MS_IRQSTATUS_OFFSET (0x0028) /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_SET_OFFSET (0x002c) /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_CLR_OFFSET (0x0030) /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQWAKEEN_OFFSET (0x0034) /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_TCLR_OFFSET (0x0038) /* 1ms Timer Control Register */ +#define AM67_DMTMR1MS_TCRR_OFFSET (0x003c) /* 1ms Timer Counter Register */ +#define AM67_DMTMR1MS_TLDR_OFFSET (0x0040) /* 1ms Timer Load Register */ +#define AM67_DMTMR1MS_TTGR_OFFSET (0x0044) /* 1ms Timer Trigger Register */ +#define AM67_DMTMR1MS_TWPS_OFFSET (0x0048) /* 1ms Timer Write Posting Bits Register */ +#define AM67_DMTMR1MS_TMAR_OFFSET (0x004c) /* 1ms Timer Match Register */ +#define AM67_DMTMR1MS_TCAR1_OFFSET (0x0050) /* 1ms Timer Capture 1 Register */ +#define AM67_DMTMR1MS_TSICR_OFFSET (0x0054) /* 1ms Timer Synchronous Interface Control Register */ +#define AM67_DMTMR1MS_TCAR2_OFFSET (0x0058) /* 1ms Timer Capture 2 Register */ +#define AM67_DMTMR1MS_TPIR_OFFSET (0x005c) /* 1ms Timer Positive Increment Register */ +#define AM67_DMTMR1MS_TNIR_OFFSET (0x0060) /* 1ms Timer Negative Increment Register */ +#define AM67_DMTMR1MS_TCVR_OFFSET (0x0064) /* 1ms Timer Counter Value Register */ +#define AM67_DMTMR1MS_TOCR_OFFSET (0x0068) /* 1ms Timer Overflow Counter Register */ +#define AM67_DMTMR1MS_TOWR_OFFSET (0x006c) /* 1ms Timer Overflow Interrupts Register */ + +#define TIMER_OVF_INT_SHIFT (0x1) +#define TIMER_IRQ_EOI (0x20u) +#define TIMER_IRQ_STATUS_RAW (0x24u) +#define TIMER_IRQ_STATUS (0x28u) +#define TIMER_IRQ_INT_ENABLE (0x2cu) +#define TIMER_IRQ_INT_DISABLE (0x30u) +#define TIMER_TCLR (0x38u) +#define TIMER_TCRR (0x3cu) +#define TIMER_TLDR (0x40u) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct timer_params_s +{ + /* Input pre-scaler divisor ro apply + * + * Must be power of 2 and between 1 and 256 for GP Timer. + * + * This field is valid only when underlying timer is DM Timer. + * + * This field is not valid when underlying timer is RTI Timer, + * set to 1 in this case. + */ + + uint32_t input_pre_scaler; + + /* Timer input clock in unit of Hz before pre-scaler + * + * System initialization must make any system level muxes, PLLs, + * power required to input this clock are setup properly. + * + * Make sure this value is not 0. + */ + + uint32_t input_clk_hz; + + /* Timer period in units of usecs + * + * Internally timer_params_s.input_clk_hz and + * timer_params_s.input_pre_scaler is used to compute the value to be put + * inside the timer HW register. + * + * When value is 0, period_in_nsec is used instead. + * When both period_in_usec and period_in_nsec are non-zero, + * period_in_nsec is used. + */ + + uint32_t period_in_usec; + + /* Timer period in units of nsecs + * + * Internally timer_params_s.input_clk_hz and + * timer_params_s.input_pre_scaler is used to compute the value to be put + * inside the timer HW register. + * + * When value is 0, period_in_nsec is used instead. + * When both period_in_usec and period_in_nsec are non-zero, + * period_in_nsec is used. + */ + + uint32_t period_in_nsec; + + /* 0: continuous mode of operation + * 1: oneshot mode of operation + * + * Not supported for RTI timer, always set to 0 in this case. + */ + + uint32_t oneshot_mode; + + /* 0: do not enable timer overflow interrupt + * 1: enable timer overflow interrupt + */ + + uint32_t enable_overflow_int; + + /* 0: do not enable DMA trigger from timer + * 1: enable DMA trigger from timer + */ + + uint32_t enable_dma_trigger; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void am67_timer_start(uint32_t base_addr); +static void am67_timer_stop(uint32_t base_addr); +static uint32_t am67_timer_get_count(uint32_t base_addr); +static void am67_timer_clear_overflow_int(uint32_t base_addr); +static void am67_timer_params_init(struct timer_params_s *params); +static void am67_timer_setup(uint32_t base_addr, + struct timer_params_s *params); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_timer_start + * + * Description: + * Start the timer by setting the enable bit in the timer control register. + * + ****************************************************************************/ + +static void am67_timer_start(uint32_t base_addr) +{ + uint32_t value; + uint32_t addr = base_addr + TIMER_TCLR; + + value = getreg32(addr); + putreg32(value | (0x1u << 0), addr); +} + +/**************************************************************************** + * Name: am67_timer_stop + * + * Description: + * Stop the timer by clearing the enable bit in the timer control register. + * + ****************************************************************************/ + +static void am67_timer_stop(uint32_t base_addr) +{ + uint32_t addr = base_addr + TIMER_TCLR; + uint32_t value; + + value = getreg32(addr); + putreg32(value & ~(0x1u << 0), addr); +} + +/**************************************************************************** + * Name: am67_timer_get_count + * + * Description: + * Read and return the current timer count value from the timer counter + * register. + * + ****************************************************************************/ + +static uint32_t am67_timer_get_count(uint32_t base_addr) +{ + return getreg32(base_addr + TIMER_TCRR); +} + +/**************************************************************************** + * Name: am67_timer_clear_overflow_int + * + * Description: + * Clear the timer overflow interrupt by writing to the interrupt status + * register and verify the interrupt is cleared. + * + ****************************************************************************/ + +static void am67_timer_clear_overflow_int(uint32_t base_addr) +{ + uint32_t addr; + uint32_t value = (0x1u << TIMER_OVF_INT_SHIFT); + + /* Clear status for overflow interrupt. */ + + addr = base_addr + TIMER_IRQ_STATUS; + putreg32(value, addr); + + /* Read back and make sure interrupt was indeed cleared, + * if not clear it again. + */ + + if ((bool)(getreg32(addr) & value) == true) + { + putreg32(value, addr); + } +} + +/**************************************************************************** + * Name: am67_timer_params_init + * + * Description: + * Initialize timer parameters with default values including prescaler, + * clock frequency, period, and operational mode settings. + * + ****************************************************************************/ + +static void am67_timer_params_init(struct timer_params_s *params) +{ + params->input_pre_scaler = 1; + params->input_clk_hz = 25 * 1000000; + params->period_in_usec = 10000; + params->period_in_nsec = 0; + params->oneshot_mode = 0; + params->enable_overflow_int = 1; + params->enable_dma_trigger = 0; +} + +/**************************************************************************** + * Name: am67_timer_setup + * + * Description: + * Configure timer parameters including period, mode, prescaler, and + * interrupts based on the provided timer parameters structure. + * + ****************************************************************************/ + +static void am67_timer_setup(uint32_t base_addr, + struct timer_params_s *params) +{ + uint32_t ctrl_val; + uint32_t count_val; + uint32_t reload_val; + uint64_t time_in_nsec; + uint64_t input_clk_hz; + uint64_t timer_cycles; + + /* Stop timer and clear pending interrupts. */ + + am67_timer_stop(base_addr); + am67_timer_clear_overflow_int(base_addr); + + time_in_nsec = (uint64_t)params->period_in_nsec; + if (time_in_nsec == 0U) + { + time_in_nsec = params->period_in_usec * 1000U; + } + + input_clk_hz = params->input_clk_hz / params->input_pre_scaler; + timer_cycles = (input_clk_hz * time_in_nsec) / 1000000000U; + + /* If timerCycles > 32b then we cannot give accurate timing. */ + + /* Calculate count and reload value register value. */ + + count_val = 0xffffffffu - (uint32_t)timer_cycles - 1u; + + /* Keep reload value as 0, later if is auto-reload is enabled, + * it will be set a value > 0. + */ + + reload_val = 0; + + /* Calculate control register value, keep timer disabled. */ + + ctrl_val = 0; + if (params->input_pre_scaler > 1u) + { + uint32_t pre_scale_val; + + for (pre_scale_val = 8; pre_scale_val >= 1u; pre_scale_val--) + { + if ((params->input_pre_scaler & (0x1u << pre_scale_val)) != 0u) + { + break; + } + } + + /* Enable pre-scaler. */ + + ctrl_val |= (0x1u << 5); + + /* Set pre-scaler value. */ + + ctrl_val |= (((pre_scale_val - 1U) & 0x7u) << 2); + } + + if (params->oneshot_mode == 0u) + { + /* Auto-reload timer. */ + + ctrl_val |= (0x1u << 1); + reload_val = count_val; + } + + /* Set timer control value. */ + + putreg32(ctrl_val, base_addr + TIMER_TCLR); + + /* Set timer count value. */ + + putreg32(count_val, base_addr + TIMER_TCRR); + + /* Set reload value. */ + + putreg32(reload_val, base_addr + TIMER_TLDR); + + /* Enable/disable interrupts. */ + + if ((bool)params->enable_overflow_int == true) + { + /* Enable interrupt. */ + + putreg32((0x1u << TIMER_OVF_INT_SHIFT), + base_addr + TIMER_IRQ_INT_ENABLE); + } + else + { + /* Disable interrupt. */ + + putreg32((0x1u << TIMER_OVF_INT_SHIFT), + base_addr + TIMER_IRQ_INT_DISABLE); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: timer_tick_isr + * + * Description: + * Timer tick interrupt service routine that clears the timer overflow + * interrupt and processes system timer events. + * + ****************************************************************************/ + +__attribute__((section(".tick_timer"))) +int timer_tick_isr(int irq, void *context, void *arg) +{ + am67_timer_clear_overflow_int(AM67_DMTIMER1_1MS_TIMER0_VADDR); + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * the architecture-specific timer was initialized). This function is + * functionally equivalent to: + * + * int clock_gettime(clockid_t clockid, FAR struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small errors in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int up_timer_gettime(struct timespec *ts) +{ + uint64_t internal_timer; + + DEBUGASSERT(ts != NULL); + + internal_timer = am67_timer_get_count(AM67_DMTIMER1_1MS_TIMER0_VADDR); + + ts->tv_nsec = internal_timer * 1000000; + ts->tv_sec = internal_timer / 1000; + + return OK; +} + +/**************************************************************************** + * Name: up_timer_start + * + * Description: + * Start the timer by setting the enable bit in the timer control register. + * + ****************************************************************************/ + +int up_timer_start(struct timespec const *ts) +{ + am67_timer_start(AM67_DMTIMER1_1MS_TIMER0_VADDR); + return 0; +} + +/**************************************************************************** + * Name: up_timer_cancel + * + * Description: + * Stop the timer by clearing the enable bit in the timer control register. + * + ****************************************************************************/ + +int up_timer_cancel(struct timespec *ts) +{ + am67_timer_stop(AM67_DMTIMER1_1MS_TIMER0_VADDR); + return 0; +} + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer hardware. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + struct timer_params_s params; + + am67_timer_params_init(¶ms); + + up_disable_irq(CSLR_R5FSS0_CORE0_INTR_TIMER0_INTR_PEND_0); + irq_attach(CSLR_R5FSS0_CORE0_INTR_TIMER0_INTR_PEND_0, + timer_tick_isr, NULL); + + am67_timer_stop(AM67_DMTIMER1_1MS_TIMER0_VADDR); + am67_timer_setup(AM67_DMTIMER1_1MS_TIMER0_VADDR, ¶ms); + am67_timer_start(AM67_DMTIMER1_1MS_TIMER0_VADDR); + + up_enable_irq(CSLR_R5FSS0_CORE0_INTR_TIMER0_INTR_PEND_0); +} diff --git a/arch/arm/src/am67/chip.h b/arch/arm/src/am67/chip.h new file mode 100644 index 00000000000..71e4afe2cbe --- /dev/null +++ b/arch/arm/src/am67/chip.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/am67/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_AM67_CHIP_H +#define __ARCH_ARM_SRC_AM67_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHIP_MPCORE_VBASE (0x0001800000) + +#endif /* __ARCH_ARM_SRC_AM67_CHIP_H */