mirror of
https://github.com/apache/nuttx.git
synced 2026-08-31 14:13:04 +00:00
Added a lower-half timer driver for stm32 which is compatible with the upper-half driver located at /drivers/timers/timer.c
This commit is contained in:
Wail Khemir
parent
88ebcc895b
commit
9451b09d3a
3 changed files with 757 additions and 0 deletions
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@ -111,6 +111,10 @@ CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq
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CHIP_CSRCS += stm32_dma.c stm32_lowputc.c stm32_serial.c stm32_spi.c
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CHIP_CSRCS += stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c
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ifeq ($(CONFIG_TIMER),y)
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CHIP_CSRCS += stm32_tim_lowerhalf.c
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endif
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ifneq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += stm32_timerisr.c
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endif
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@ -185,6 +185,26 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer);
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int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev);
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/****************************************************************************
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* Name: stm32_timer_initialize
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*
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* Description:
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* Bind the configuration timer to a timer lower half instance and
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* register the timer drivers at 'devpath'
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*
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* Input Parameters:
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* devpath - The full path to the timer device. This should be of the form /dev/timer0
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* timer - the timer number.
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*
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* Returned Values:
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* Zero (OK) is returned on success; A negated errno value is returned
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* to indicate the nature of any failure.
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*
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****************************************************************************/
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#ifdef CONFIG_TIMER
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int stm32_timer_initialize(FAR const char *devpath, int timer);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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733
arch/arm/src/stm32/stm32_tim_lowerhalf.c
Normal file
733
arch/arm/src/stm32/stm32_tim_lowerhalf.c
Normal file
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@ -0,0 +1,733 @@
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/****************************************************************************
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* arch/arm/src/stm32/stm32_tim_lowerhalf.c
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*
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* Copyright (C) 2015 Wail Khemir. All rights reserved.
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* Authors: Wail Khemir <khemirwail@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <string.h>
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#include <errno.h>
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#include <nuttx/timers/timer.h>
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#include <arch/board/board.h>
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#include "stm32_tim.h"
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#if defined(CONFIG_TIMER) && \
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( defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM3) || \
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defined(CONFIG_STM32_TIM4) || defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
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defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) )
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure provides the private representation of the "lower-half"
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* driver state structure. This structure must be cast-compatible with the
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* timer_lowerhalf_s structure.
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*/
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struct stm32_lowerhalf_s
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{
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const struct timer_ops_s *ops; /* Lower half operations */
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struct stm32_tim_dev_s *tim; /* stm32 timer driver */
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tccb_t handlerUsr; /* Current user interrupt handler */
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xcpt_t handlerTim; /* Current timer interrupt handler */
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bool started; /* True: Timer has been started */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Helper functions *********************************************************/
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static struct stm32_lowerhalf_s* stm32_get_lowerhalf(int timer);
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static xcpt_t stm32_get_interrupt(int timer);
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/* Interrupt handling *******************************************************/
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#ifdef CONFIG_STM32_TIM1
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static int stm32_tim1_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM2
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static int stm32_tim2_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM3
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static int stm32_tim3_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM4
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static int stm32_tim4_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM5
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static int stm32_tim5_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM6
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static int stm32_tim6_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM7
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static int stm32_tim7_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM8
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static int stm32_tim8_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM9
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static int stm32_tim9_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM10
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static int stm32_tim10_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM11
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static int stm32_tim11_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM12
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static int stm32_tim12_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM13
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static int stm32_tim13_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM14
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static int stm32_tim14_interrupt(int irq, FAR void *context);
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#endif
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static int stm32_timer_handler(struct stm32_lowerhalf_s* attr);
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/* "Lower half" driver methods **********************************************/
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static int stm32_start(struct timer_lowerhalf_s *lower);
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static int stm32_stop(struct timer_lowerhalf_s *lower);
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static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout);
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static tccb_t stm32_sethandler(struct timer_lowerhalf_s *lower, tccb_t handler);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* "Lower half" driver methods */
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static const struct timer_ops_s g_timer_ops =
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{
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.start = stm32_start,
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.stop = stm32_stop,
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.getstatus = 0,
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.settimeout = stm32_settimeout,
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.sethandler = stm32_sethandler,
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.ioctl = 0,
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};
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#ifdef CONFIG_STM32_TIM1
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static struct stm32_lowerhalf_s g_tim1_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM2
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static struct stm32_lowerhalf_s g_tim2_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM3
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static struct stm32_lowerhalf_s g_tim3_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM4
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static struct stm32_lowerhalf_s g_tim4_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM5
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static struct stm32_lowerhalf_s g_tim5_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM6
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static struct stm32_lowerhalf_s g_tim6_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM7
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static struct stm32_lowerhalf_s g_tim7_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM8
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static struct stm32_lowerhalf_s g_tim8_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM9
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static struct stm32_lowerhalf_s g_tim9_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM10
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static struct stm32_lowerhalf_s g_tim10_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM11
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static struct stm32_lowerhalf_s g_tim11_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM12
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static struct stm32_lowerhalf_s g_tim12_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM13
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static struct stm32_lowerhalf_s g_tim13_lowerHalf;
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#endif
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#ifdef CONFIG_STM32_TIM14
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static struct stm32_lowerhalf_s g_tim14_lowerHalf;
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_get_lowerhalf
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*
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* Description:
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* Get the lower half timer structure of the corresponding timer
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*
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* Input Parameters:
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* timer - the timer's number
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*
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* Returned Values:
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* A pointer to the lower half structure on success, NULL on failure
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*
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****************************************************************************/
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static struct stm32_lowerhalf_s* stm32_get_lowerhalf(int timer)
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{
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struct stm32_lowerhalf_s* lower;
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switch(timer)
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{
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#ifdef CONFIG_STM32_TIM1
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case 1:
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lower = &g_tim1_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM2
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case 2:
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lower = &g_tim2_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM3
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case 3:
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lower = &g_tim3_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM4
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case 4:
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lower = &g_tim4_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM5
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case 5:
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lower = &g_tim5_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM6
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case 6:
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lower = &g_tim6_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM7
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case 7:
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lower = &g_tim7_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM8
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case 8:
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lower = &g_tim8_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM9
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case 9:
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lower = &g_tim9_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM10
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case 10:
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lower = &g_tim10_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM11
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case 11:
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lower = &g_tim11_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM12
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case 12:
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lower = &g_tim12_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM13
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case 13:
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lower = &g_tim13_lowerHalf;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM14
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case 14:
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lower = &g_tim14_lowerHalf;
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break;
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#endif
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default:
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lower = 0;
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}
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return lower;
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}
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/****************************************************************************
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* Name: stm32_get_interrupt
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*
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* Description:
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* Get a pointer to the interrupt handler of the corresponding timer
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*
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* Input Parameters:
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* timer - the timer's number
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*
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* Returned Values:
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* A pointer to the interrupt handler on success, NULL on failure
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*
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****************************************************************************/
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static xcpt_t stm32_get_interrupt(int timer)
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{
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xcpt_t intr;
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switch(timer)
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{
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#ifdef CONFIG_STM32_TIM1
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case 1:
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intr = stm32_tim1_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM2
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case 2:
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intr = stm32_tim2_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM3
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case 3:
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intr = stm32_tim3_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM4
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case 4:
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intr = stm32_tim4_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM5
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case 5:
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intr = stm32_tim5_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM6
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case 6:
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intr = stm32_tim6_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM7
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case 7:
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intr = stm32_tim7_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM8
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case 8:
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intr = stm32_tim8_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM9
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case 9:
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intr = stm32_tim9_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM10
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case 10:
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intr = stm32_tim10_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM11
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case 11:
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intr = stm32_tim11_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM12
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case 12:
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intr = stm32_tim12_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM13
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case 13:
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intr = stm32_tim13_interrupt;
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break;
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#endif
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#ifdef CONFIG_STM32_TIM14
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case 14:
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intr = stm32_tim14_interrupt;
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break;
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#endif
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default:
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intr = 0;
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}
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return intr;
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}
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/****************************************************************************
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* Name: stm32_timN_interrupt, N=1..14
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*
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* Description:
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* Individual interrupt handlers for each timer
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*
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****************************************************************************/
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#ifdef CONFIG_STM32_TIM1
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static int stm32_tim1_interrupt(int irq, FAR void *context)
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{
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return stm32_timer_handler(&g_tim1_lowerHalf);
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}
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#endif
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#ifdef CONFIG_STM32_TIM2
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static int stm32_tim2_interrupt(int irq, FAR void *context)
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{
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return stm32_timer_handler(&g_tim2_lowerHalf);
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}
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#endif
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#ifdef CONFIG_STM32_TIM3
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static int stm32_tim3_interrupt(int irq, FAR void *context)
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{
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return stm32_timer_handler(&g_tim3_lowerHalf);
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}
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#endif
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#ifdef CONFIG_STM32_TIM4
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static int stm32_tim4_interrupt(int irq, FAR void *context)
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{
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return stm32_timer_handler(&g_tim4_lowerHalf);
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}
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#endif
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#ifdef CONFIG_STM32_TIM5
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static int stm32_tim5_interrupt(int irq, FAR void *context)
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{
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return stm32_timer_handler(&g_tim5_lowerHalf);
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}
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#endif
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#ifdef CONFIG_STM32_TIM6
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static int stm32_tim6_interrupt(int irq, FAR void *context)
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{
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return stm32_timer_handler(&g_tim6_lowerHalf);
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}
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#endif
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#ifdef CONFIG_STM32_TIM7
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static int stm32_tim7_interrupt(int irq, FAR void *context)
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{
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return stm32_timer_handler(&g_tim7_lowerHalf);
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}
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#endif
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#ifdef CONFIG_STM32_TIM8
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static int stm32_tim8_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_timer_handler(&g_tim8_lowerHalf);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM9
|
||||
static int stm32_tim9_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_timer_handler(&g_tim9_lowerHalf);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM10
|
||||
static int stm32_tim10_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_timer_handler(&g_tim10_lowerHalf);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM11
|
||||
static int stm32_tim11_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_timer_handler(&g_tim11_lowerHalf);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM12
|
||||
static int stm32_tim12_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_timer_handler(&g_tim12_lowerHalf);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM13
|
||||
static int stm32_tim13_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_timer_handler(&g_tim13_lowerHalf);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM14
|
||||
static int stm32_tim14_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_timer_handler(&g_tim14_lowerHalf);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_timer_handler
|
||||
*
|
||||
* Description:
|
||||
* timer interrupt handler
|
||||
*
|
||||
* Input Parameters:
|
||||
*
|
||||
*
|
||||
* Returned Values:
|
||||
*
|
||||
*
|
||||
****************************************************************************/
|
||||
static int stm32_timer_handler(struct stm32_lowerhalf_s* lower)
|
||||
{
|
||||
STM32_TIM_ACKINT(lower->tim, 0);
|
||||
|
||||
uint32_t next_interval_us = 0;
|
||||
int ret = (*lower->handlerUsr)(&next_interval_us);
|
||||
|
||||
if(ret == OK)
|
||||
{
|
||||
if(next_interval_us > 0)
|
||||
STM32_TIM_SETPERIOD(lower->tim, next_interval_us);
|
||||
}
|
||||
else
|
||||
{
|
||||
stm32_stop(lower);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_start
|
||||
*
|
||||
* Description:
|
||||
* Start the timer, resetting the time to the current timeout,
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32_start(struct timer_lowerhalf_s *lower)
|
||||
{
|
||||
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
|
||||
|
||||
if (!priv->started)
|
||||
{
|
||||
STM32_TIM_SETCLOCK(priv->tim, 1000000); // 1000000 Hz = 1 microsecond
|
||||
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP);
|
||||
|
||||
if(priv->handlerUsr)
|
||||
{
|
||||
STM32_TIM_SETISR(priv->tim, priv->handlerTim, 0);
|
||||
STM32_TIM_ENABLEINT(priv->tim, 0);
|
||||
}
|
||||
|
||||
priv->started = true;
|
||||
return OK;
|
||||
}
|
||||
|
||||
/* Return EBUSY to indicate that the timer was already running */
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_stop
|
||||
*
|
||||
* Description:
|
||||
* Stop the timer
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32_stop(struct timer_lowerhalf_s *lower)
|
||||
{
|
||||
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
|
||||
|
||||
if (priv->started)
|
||||
{
|
||||
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED);
|
||||
STM32_TIM_DISABLEINT(priv->tim, 0);
|
||||
STM32_TIM_SETISR(priv->tim, 0, 0);
|
||||
priv->started = false;
|
||||
return OK;
|
||||
}
|
||||
|
||||
/* Return ENODEV to indicate that the timer was not running */
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_settimeout
|
||||
*
|
||||
* Description:
|
||||
* Set a new timeout value (and reset the timer)
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
* timeout - The new timeout value in microseconds.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout)
|
||||
{
|
||||
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
|
||||
|
||||
if (priv->started)
|
||||
{
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
STM32_TIM_SETPERIOD(priv->tim, timeout);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_sethandler
|
||||
*
|
||||
* Description:
|
||||
* Call this user provided timeout handler.
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
* newhandler - The new timer expiration function pointer. If this
|
||||
* function pointer is NULL, then the reset-on-expiration
|
||||
* behavior is restored,
|
||||
*
|
||||
* Returned Values:
|
||||
* The previous timer expiration function pointer or NULL is there was
|
||||
* no previous function pointer.
|
||||
*
|
||||
****************************************************************************/
|
||||
static tccb_t stm32_sethandler(struct timer_lowerhalf_s *lower, tccb_t newhandler)
|
||||
{
|
||||
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
|
||||
|
||||
irqstate_t flags = irqsave();
|
||||
|
||||
/* Get the old handler return value */
|
||||
tccb_t oldhandler = priv->handlerUsr;
|
||||
|
||||
/* Save the new handler */
|
||||
priv->handlerUsr = newhandler;
|
||||
|
||||
if(newhandler)
|
||||
{
|
||||
STM32_TIM_SETISR(priv->tim, priv->handlerTim, 0);
|
||||
STM32_TIM_ENABLEINT(priv->tim, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
STM32_TIM_DISABLEINT(priv->tim, 0);
|
||||
STM32_TIM_SETISR(priv->tim, 0, 0);
|
||||
}
|
||||
|
||||
irqrestore(flags);
|
||||
|
||||
return oldhandler;
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* Bind the configuration timer to a timer lower half instance and
|
||||
* register the timer drivers at 'devpath'
|
||||
*
|
||||
* Input Parameters:
|
||||
* devpath - The full path to the timer device. This should be of the
|
||||
* form /dev/timer0
|
||||
* timer - the timer's number.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero (OK) is returned on success; A negated errno value is returned
|
||||
* to indicate the nature of any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_timer_initialize(FAR const char *devpath, int timer)
|
||||
{
|
||||
struct stm32_lowerhalf_s *lower = stm32_get_lowerhalf(timer);
|
||||
memset(lower, 0, sizeof(struct stm32_lowerhalf_s));
|
||||
|
||||
/* Initialize the non-zero elements of lower half state structure */
|
||||
lower->ops = &g_timer_ops;
|
||||
lower->handlerTim = stm32_get_interrupt(timer);
|
||||
lower->tim = stm32_tim_init(timer);
|
||||
if(!lower->tim)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Register the timer driver as /dev/timerX. The returned value from
|
||||
* timer_register is a handle that could be used with timer_unregister().
|
||||
* REVISIT: The returned handle is discard here.
|
||||
*/
|
||||
void *drvr = timer_register(devpath, (struct timer_lowerhalf_s *)lower);
|
||||
if (!drvr)
|
||||
{
|
||||
/* The actual cause of the failure may have been a failure to allocate
|
||||
* perhaps a failure to register the timer driver (such as if the
|
||||
* 'depath' were not unique). We know here but we return EEXIST to
|
||||
* indicate the failure (implying the non-unique devpath).
|
||||
*/
|
||||
return -EEXIST;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_TIMER */
|
||||
Loading…
Add table
Add a link
Reference in a new issue