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arch/arm/stm32l5: Use common Cortex-M33 USART support
Select STM32_HAVE_IP_USART_M33_V3 and drop the family serial and low-level console sources in favor of the common Cortex-M33 v3 implementation. Provide the USART clock and RCC gate definitions in stm32_rcc_m33.h. Add the LPUART BRR computation (256 * fCK / baud) to the common serial and low-level console code, taken from the STM32L5 driver. Signed-off-by: raiden00pl <raiden00@railab.me> Assisted-by: Claude Code
This commit is contained in:
raiden00pl
Alan C. Assis
parent
6e7ea6019e
commit
93a40354c0
12 changed files with 174 additions and 4466 deletions
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@ -46,16 +46,17 @@
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#ifdef HAVE_CONSOLE
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# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_LPUART1_BASE
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# define STM32_APBCLOCK STM32_LPUART1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_LPUART1_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_LPUART1_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD
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# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS
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# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP
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# define STM32_CONSOLE_TX GPIO_LPUART1_TX
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# define STM32_CONSOLE_RX GPIO_LPUART1_RX
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# define STM32_CONSOLE_IS_LPUART 1
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# define STM32_CONSOLE_BASE STM32_LPUART1_BASE
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# define STM32_APBCLOCK STM32_LPUART1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_LPUART1_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_LPUART1_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD
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# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS
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# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP
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# define STM32_CONSOLE_TX GPIO_LPUART1_TX
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# define STM32_CONSOLE_RX GPIO_LPUART1_RX
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# ifdef CONFIG_LPUART1_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
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# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0)
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@ -65,16 +66,17 @@
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# endif
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# endif
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# elif defined(CONFIG_USART1_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART1_BASE
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# define STM32_APBCLOCK STM32_USART1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_USART1_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_USART1_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
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# define STM32_CONSOLE_TX GPIO_USART1_TX
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# define STM32_CONSOLE_RX GPIO_USART1_RX
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# define STM32_CONSOLE_IS_LPUART 0
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# define STM32_CONSOLE_BASE STM32_USART1_BASE
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# define STM32_APBCLOCK STM32_USART1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_USART1_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_USART1_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
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# define STM32_CONSOLE_TX GPIO_USART1_TX
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# define STM32_CONSOLE_RX GPIO_USART1_RX
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# ifdef CONFIG_USART1_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
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# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
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@ -84,16 +86,17 @@
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# endif
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# endif
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# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART2_BASE
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# define STM32_APBCLOCK STM32_USART2_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_USART2_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_USART2_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
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# define STM32_CONSOLE_TX GPIO_USART2_TX
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# define STM32_CONSOLE_RX GPIO_USART2_RX
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# define STM32_CONSOLE_IS_LPUART 0
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# define STM32_CONSOLE_BASE STM32_USART2_BASE
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# define STM32_APBCLOCK STM32_USART2_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_USART2_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_USART2_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
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# define STM32_CONSOLE_TX GPIO_USART2_TX
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# define STM32_CONSOLE_RX GPIO_USART2_RX
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# ifdef CONFIG_USART2_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
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# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
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@ -103,16 +106,17 @@
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# endif
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# endif
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# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART3_BASE
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# define STM32_APBCLOCK STM32_USART3_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_USART3_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_USART3_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
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# define STM32_CONSOLE_TX GPIO_USART3_TX
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# define STM32_CONSOLE_RX GPIO_USART3_RX
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# define STM32_CONSOLE_IS_LPUART 0
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# define STM32_CONSOLE_BASE STM32_USART3_BASE
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# define STM32_APBCLOCK STM32_USART3_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_USART3_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_USART3_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
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# define STM32_CONSOLE_TX GPIO_USART3_TX
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# define STM32_CONSOLE_RX GPIO_USART3_RX
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# ifdef CONFIG_USART3_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
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# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
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@ -122,16 +126,17 @@
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# endif
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# endif
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# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART4_BASE
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# define STM32_APBCLOCK STM32_UART4_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_UART4_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_UART4_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
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# define STM32_CONSOLE_TX GPIO_UART4_TX
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# define STM32_CONSOLE_RX GPIO_UART4_RX
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# define STM32_CONSOLE_IS_LPUART 0
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# define STM32_CONSOLE_BASE STM32_UART4_BASE
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# define STM32_APBCLOCK STM32_UART4_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_UART4_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_UART4_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
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# define STM32_CONSOLE_TX GPIO_UART4_TX
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# define STM32_CONSOLE_RX GPIO_UART4_RX
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# ifdef CONFIG_UART4_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
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# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
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@ -141,16 +146,17 @@
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# endif
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# endif
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# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART5_BASE
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# define STM32_APBCLOCK STM32_UART5_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_UART5_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_UART5_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
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# define STM32_CONSOLE_TX GPIO_UART5_TX
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# define STM32_CONSOLE_RX GPIO_UART5_RX
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# define STM32_CONSOLE_IS_LPUART 0
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# define STM32_CONSOLE_BASE STM32_UART5_BASE
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# define STM32_APBCLOCK STM32_UART5_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_UART5_RCC_REG
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# define STM32_CONSOLE_APBEN STM32_UART5_RCC_EN
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# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
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# define STM32_CONSOLE_TX GPIO_UART5_TX
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# define STM32_CONSOLE_RX GPIO_UART5_RX
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# ifdef CONFIG_UART5_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
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# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
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@ -218,36 +224,21 @@
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# define USART_CR3_SETBITS 0
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# undef USE_OVER8
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/* Calculate USART BAUD rate divider */
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/* Baud rate for standard USART (SPI mode included):
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*
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* In case of oversampling by 16, the equation is:
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* baud = fCK / UARTDIV
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* UARTDIV = fCK / baud
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*
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* In case of oversampling by 8, the equation is:
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*
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* baud = 2 * fCK / UARTDIV
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* UARTDIV = 2 * fCK / baud
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/* Calculate all baud rate dividers, rounded to the nearest integer.
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* LPUART uses 256 * fCK / baud. USART uses fCK / baud for oversampling
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* by 16, or 2 * fCK / baud for oversampling by 8.
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*/
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# define STM32_LPUART_BRR_VALUE \
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((((uint64_t)STM32_APBCLOCK << 8) + \
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(STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
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# define STM32_USARTDIV8 \
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(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
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# define STM32_USARTDIV16 \
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((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
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/* Use oversamply by 8 only if the divisor is small. But what is small? */
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# if STM32_USARTDIV8 > 2000
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# define STM32_BRR_VALUE STM32_USARTDIV16
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# else
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# define USE_OVER8 1
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# define STM32_BRR_VALUE \
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((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
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# endif
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# define STM32_USART_BRR_VALUE \
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(STM32_USARTDIV8 > 2000 ? STM32_USARTDIV16 : \
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((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)))
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#endif /* HAVE_CONSOLE */
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@ -377,18 +368,29 @@ void stm32_lowsetup(void)
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/* Configure the USART Baud Rate */
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putreg32(STM32_BRR_VALUE,
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STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
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if (STM32_CONSOLE_IS_LPUART)
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{
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putreg32(STM32_LPUART_BRR_VALUE,
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STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
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}
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else
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{
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putreg32(STM32_USART_BRR_VALUE,
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STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
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}
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/* Select oversampling by 8 or by 16 */
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/* Only USART uses oversampling by 8, and only for small divisors. */
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cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
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#ifdef USE_OVER8
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cr |= USART_CR1_OVER8;
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#else
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cr &= ~USART_CR1_OVER8;
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#endif
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if (!STM32_CONSOLE_IS_LPUART && STM32_USARTDIV8 <= 2000)
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{
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cr |= USART_CR1_OVER8;
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}
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else
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{
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cr &= ~USART_CR1_OVER8;
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}
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/* Enable Rx, Tx, and the USART */
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@ -260,6 +260,7 @@ struct stm32_serial_s
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#endif
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const uint8_t irq; /* IRQ associated with this USART */
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const bool islpuart; /* True: This device is an LPUART */
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const uint32_t apbclock; /* PCLK 1 or 2 frequency */
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const uint32_t rccreg; /* RCC enable register */
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const uint32_t rccen; /* RCC enable bit */
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@ -475,6 +476,7 @@ static struct stm32_serial_s g_lpuart1priv =
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},
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.irq = STM32_IRQ_LPUART1,
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.islpuart = true,
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.parity = CONFIG_LPUART1_PARITY,
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.bits = CONFIG_LPUART1_BITS,
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.stopbits2 = CONFIG_LPUART1_2STOP,
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@ -537,6 +539,7 @@ static struct stm32_serial_s g_usart1priv =
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},
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.irq = STM32_IRQ_USART1,
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.islpuart = false,
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.parity = CONFIG_USART1_PARITY,
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.bits = CONFIG_USART1_BITS,
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.stopbits2 = CONFIG_USART1_2STOP,
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@ -601,6 +604,7 @@ static struct stm32_serial_s g_usart2priv =
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},
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.irq = STM32_IRQ_USART2,
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.islpuart = false,
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.parity = CONFIG_USART2_PARITY,
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.bits = CONFIG_USART2_BITS,
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.stopbits2 = CONFIG_USART2_2STOP,
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@ -665,6 +669,7 @@ static struct stm32_serial_s g_usart3priv =
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},
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.irq = STM32_IRQ_USART3,
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.islpuart = false,
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.parity = CONFIG_USART3_PARITY,
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.bits = CONFIG_USART3_BITS,
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.stopbits2 = CONFIG_USART3_2STOP,
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@ -729,6 +734,7 @@ static struct stm32_serial_s g_uart4priv =
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},
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.irq = STM32_IRQ_UART4,
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.islpuart = false,
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.parity = CONFIG_UART4_PARITY,
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.bits = CONFIG_UART4_BITS,
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.stopbits2 = CONFIG_UART4_2STOP,
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@ -793,6 +799,7 @@ static struct stm32_serial_s g_uart5priv =
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},
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.irq = STM32_IRQ_UART5,
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.islpuart = false,
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.parity = CONFIG_UART5_PARITY,
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.bits = CONFIG_UART5_BITS,
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.stopbits2 = CONFIG_UART5_2STOP,
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@ -1036,49 +1043,60 @@ static void stm32serial_setformat(struct uart_dev_s *dev)
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uint32_t cr1;
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uint32_t brr;
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/* In case of oversampling by 8, the equation is:
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*
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* baud = 2 * fCK / usartdiv8
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* usartdiv8 = 2 * fCK / baud
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*/
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usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud;
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/* Baud rate for standard USART (SPI mode included):
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*
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* In case of oversampling by 16, the equation is:
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* baud = fCK / usartdiv16
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* usartdiv16 = fCK / baud
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* = 2 * usartdiv8
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*/
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/* Use oversamply by 8 only if the divisor is small. But what is small? */
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cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET);
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if (usartdiv8 > 2000)
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if (priv->islpuart)
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{
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/* Use usartdiv16 */
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/* LPUART BRR = 256 * fCK / baud */
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brr = (usartdiv8 + 1) >> 1;
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/* Clear oversampling by 8 to enable oversampling by 16 */
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cr1 &= ~USART_CR1_OVER8;
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brr = (((uint64_t)priv->apbclock << 8) +
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(priv->baud >> 1)) / priv->baud;
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}
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else
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{
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DEBUGASSERT(usartdiv8 >= 8);
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/* In case of oversampling by 8, the equation is:
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*
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* baud = 2 * fCK / usartdiv8
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* usartdiv8 = 2 * fCK / baud
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*/
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/* Perform mysterious operations on bits 0-3 */
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usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud;
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||||
|
||||
brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1));
|
||||
/* Baud rate for standard USART (SPI mode included):
|
||||
*
|
||||
* In case of oversampling by 16, the equation is:
|
||||
* baud = fCK / usartdiv16
|
||||
* usartdiv16 = fCK / baud
|
||||
* = usartdiv8 / 2
|
||||
*/
|
||||
|
||||
/* Set oversampling by 8 */
|
||||
/* Use oversampling by 8 only if the divisor is small */
|
||||
|
||||
cr1 |= USART_CR1_OVER8;
|
||||
cr1 = stm32serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
if (usartdiv8 > 2000)
|
||||
{
|
||||
/* Use usartdiv16 */
|
||||
|
||||
brr = (usartdiv8 + 1) >> 1;
|
||||
|
||||
/* Clear oversampling by 8 to enable oversampling by 16 */
|
||||
|
||||
cr1 &= ~USART_CR1_OVER8;
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUGASSERT(usartdiv8 >= 8);
|
||||
|
||||
/* Perform mysterious operations on bits 0-3 */
|
||||
|
||||
brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1));
|
||||
|
||||
/* Set oversampling by 8 */
|
||||
|
||||
cr1 |= USART_CR1_OVER8;
|
||||
}
|
||||
|
||||
stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
}
|
||||
|
||||
stm32serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
stm32serial_putreg(priv, STM32_USART_BRR_OFFSET, brr);
|
||||
|
||||
/* Configure parity mode */
|
||||
|
|
|
|||
|
|
@ -25,9 +25,7 @@
|
|||
list(
|
||||
APPEND
|
||||
SRCS
|
||||
stm32l5_lowputc.c
|
||||
stm32l5_rcc.c
|
||||
stm32l5_serial.c
|
||||
stm32l5_spi.c
|
||||
stm32l5_lse.c
|
||||
stm32l5_lsi.c
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ config STM32_L5_PERIPHERALS
|
|||
default y
|
||||
select STM32_HAVE_IP_EXTI_M33_V1
|
||||
select STM32_HAVE_IP_GPIO_M33_V1
|
||||
select STM32_HAVE_IP_USART_M33_V3
|
||||
select STM32_HAVE_RTC_SUBSECONDS
|
||||
select STM32_HAVE_RTC_MAGIC
|
||||
select STM32_HAVE_RTC
|
||||
|
|
|
|||
|
|
@ -33,8 +33,7 @@ include common/stm32/Make.defs
|
|||
# Required STM32L5 files
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS += stm32l5_lowputc.c stm32l5_rcc.c
|
||||
CHIP_CSRCS += stm32l5_serial.c
|
||||
CHIP_CSRCS += stm32l5_rcc.c
|
||||
CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c
|
||||
CHIP_CSRCS += stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c
|
||||
|
||||
|
|
|
|||
|
|
@ -1,309 +0,0 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/hardware/stm32l5_uart.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
|
||||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
|
||||
#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 2
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET)
|
||||
# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
|
||||
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
|
||||
#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */
|
||||
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
|
||||
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
|
||||
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
|
||||
|
||||
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */
|
||||
#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
|
||||
|
||||
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */
|
||||
#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
|
||||
|
||||
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
|
||||
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */
|
||||
#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length */
|
||||
|
||||
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE| \
|
||||
USART_CR1_TCIE|USART_CR1_TXEIE| \
|
||||
USART_CR1_PEIE|USART_CR1_CMIE| \
|
||||
USART_CR1_RTOIE|USART_CR1_EOBIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-bit/4-bit Address Detection */
|
||||
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
|
||||
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
|
||||
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
|
||||
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
|
||||
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
|
||||
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */
|
||||
|
||||
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/
|
||||
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
|
||||
#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */
|
||||
#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */
|
||||
#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */
|
||||
#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */
|
||||
|
||||
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
|
||||
|
||||
#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */
|
||||
#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */
|
||||
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
|
||||
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */
|
||||
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */
|
||||
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */
|
||||
#define USART_CR3_SCARCNT2_SHIFT (17) /* Bits 17-19: Smart card auto retry count */
|
||||
#define USART_CR3_SCARCNT2_MASK (7 << USART_CR3_SCARCNT2_SHIFT)
|
||||
#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */
|
||||
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
|
||||
#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */
|
||||
#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */
|
||||
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */
|
||||
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
|
||||
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
|
||||
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
|
||||
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
|
||||
/* Receiver timeout register */
|
||||
|
||||
/* Request Register */
|
||||
|
||||
#define USART_CR1_SBRKQ (1 << 1) /* Bit 1: Send Break */
|
||||
|
||||
/* Interrupt and Status register */
|
||||
|
||||
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */
|
||||
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */
|
||||
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */
|
||||
#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */
|
||||
#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
|
||||
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
|
||||
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */
|
||||
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
|
||||
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */
|
||||
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt Flag */
|
||||
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS Flag */
|
||||
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout Flag */
|
||||
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block Flag */
|
||||
#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */
|
||||
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate Error */
|
||||
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate Flag */
|
||||
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy Flag */
|
||||
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match Flag */
|
||||
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break Flag */
|
||||
#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
|
||||
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode Flag */
|
||||
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge Flag */
|
||||
#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge Flag */
|
||||
|
||||
/* ICR */
|
||||
|
||||
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
|
||||
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
|
||||
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */
|
||||
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
|
||||
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
|
||||
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */
|
||||
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
|
||||
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */
|
||||
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
|
||||
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
|
||||
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
|
||||
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
|
||||
|
||||
/* Receive Data register */
|
||||
|
||||
#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_RDR_MASK (0xff << USART_RDR_SHIFT)
|
||||
|
||||
/* Transmit Data register */
|
||||
|
||||
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H */
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
#include "stm32_rcc.h"
|
||||
#include "stm32l5_spi.h"
|
||||
#include "stm32l5_tim.h"
|
||||
#include "stm32l5_uart.h"
|
||||
#include "stm32l5_lowputc.h"
|
||||
#include "stm32_uart.h"
|
||||
#include "stm32_lowputc.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_H */
|
||||
|
|
|
|||
|
|
@ -42,6 +42,32 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* USART clock and RCC definitions */
|
||||
|
||||
#define STM32_LPUART1_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#define STM32_LPUART1_RCC_REG STM32_RCC_APB1ENR2
|
||||
#define STM32_LPUART1_RCC_EN RCC_APB1ENR2_LPUART1EN
|
||||
|
||||
#define STM32_USART1_FREQUENCY STM32_PCLK2_FREQUENCY
|
||||
#define STM32_USART1_RCC_REG STM32_RCC_APB2ENR
|
||||
#define STM32_USART1_RCC_EN RCC_APB2ENR_USART1EN
|
||||
|
||||
#define STM32_USART2_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#define STM32_USART2_RCC_REG STM32_RCC_APB1ENR1
|
||||
#define STM32_USART2_RCC_EN RCC_APB1ENR1_USART2EN
|
||||
|
||||
#define STM32_USART3_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#define STM32_USART3_RCC_REG STM32_RCC_APB1ENR1
|
||||
#define STM32_USART3_RCC_EN RCC_APB1ENR1_USART3EN
|
||||
|
||||
#define STM32_UART4_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#define STM32_UART4_RCC_REG STM32_RCC_APB1ENR1
|
||||
#define STM32_UART4_RCC_EN RCC_APB1ENR1_UART4EN
|
||||
|
||||
#define STM32_UART5_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#define STM32_UART5_RCC_REG STM32_RCC_APB1ENR1
|
||||
#define STM32_UART5_RCC_EN RCC_APB1ENR1_UART5EN
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
|
|
|
|||
|
|
@ -1,415 +0,0 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_lowputc.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "chip.h"
|
||||
|
||||
#include "stm32.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32l5_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Select USART parameters for the selected console */
|
||||
|
||||
#ifdef HAVE_CONSOLE
|
||||
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_LPUART1_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_LPUART1_TX
|
||||
# define STM32_CONSOLE_RX GPIO_LPUART1_RX
|
||||
# ifdef CONFIG_LPUART1_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
|
||||
# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART1_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART1_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
|
||||
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART1_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART1_RX
|
||||
# ifdef CONFIG_USART1_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
|
||||
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART2_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART2_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART2_RX
|
||||
# ifdef CONFIG_USART2_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
|
||||
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_USART3_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART3_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART3_RX
|
||||
# ifdef CONFIG_USART3_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
|
||||
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_UART4_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_UART4_TX
|
||||
# define STM32_CONSOLE_RX GPIO_UART4_RX
|
||||
# ifdef CONFIG_UART4_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
|
||||
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
|
||||
# define STM32_CONSOLE_BASE STM32_UART5_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_UART5_TX
|
||||
# define STM32_CONSOLE_RX GPIO_UART5_RX
|
||||
# ifdef CONFIG_UART5_RS485
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
|
||||
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/* CR1 settings */
|
||||
|
||||
# if STM32_CONSOLE_BITS == 9
|
||||
# define USART_CR1_M0_VALUE USART_CR1_M0
|
||||
# define USART_CR1_M1_VALUE 0
|
||||
# elif STM32_CONSOLE_BITS == 7
|
||||
# define USART_CR1_M0_VALUE 0
|
||||
# define USART_CR1_M1_VALUE USART_CR1_M1
|
||||
# else /* 8 bits */
|
||||
# define USART_CR1_M0_VALUE 0
|
||||
# define USART_CR1_M1_VALUE 0
|
||||
# endif
|
||||
|
||||
# if STM32_CONSOLE_PARITY == 1 /* odd parity */
|
||||
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
|
||||
# elif STM32_CONSOLE_PARITY == 2 /* even parity */
|
||||
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
|
||||
# else /* no parity */
|
||||
# define USART_CR1_PARITY_VALUE 0
|
||||
# endif
|
||||
|
||||
# define USART_CR1_CLRBITS \
|
||||
(USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
|
||||
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \
|
||||
USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \
|
||||
USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
|
||||
|
||||
# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE)
|
||||
|
||||
/* CR2 settings */
|
||||
|
||||
# if STM32_CONSOLE_2STOP != 0
|
||||
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
|
||||
# else
|
||||
# define USART_CR2_STOP2_VALUE 0
|
||||
# endif
|
||||
|
||||
# define USART_CR2_CLRBITS \
|
||||
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
|
||||
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
|
||||
USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \
|
||||
USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \
|
||||
USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK)
|
||||
|
||||
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
|
||||
|
||||
/* CR3 settings */
|
||||
|
||||
# define USART_CR3_CLRBITS \
|
||||
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
|
||||
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
|
||||
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
|
||||
USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
|
||||
USART_CR3_SCARCNT2_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE)
|
||||
|
||||
# define USART_CR3_SETBITS 0
|
||||
|
||||
# undef USE_OVER8
|
||||
|
||||
/* Calculate USART BAUD rate divider */
|
||||
|
||||
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
|
||||
|
||||
/* Baud rate for LPUART:
|
||||
*
|
||||
* baud = 256 * fCK / LPUARTDIV
|
||||
* LPUARTDIV = 256 * fCK / baud
|
||||
*
|
||||
* LPUARTDIV must be in range [0x300, 0xFFFFF].
|
||||
*/
|
||||
|
||||
# define STM32_BRR_VALUE \
|
||||
((((uint64_t)STM32_APBCLOCK << 8) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
|
||||
# else
|
||||
|
||||
/* Baud rate for standard USART (SPI mode included):
|
||||
*
|
||||
* In case of oversampling by 16, the equation is:
|
||||
* baud = fCK / UARTDIV
|
||||
* UARTDIV = fCK / baud
|
||||
*
|
||||
* In case of oversampling by 8, the equation is:
|
||||
*
|
||||
* baud = 2 * fCK / UARTDIV
|
||||
* UARTDIV = 2 * fCK / baud
|
||||
*/
|
||||
|
||||
# define STM32_USARTDIV8 \
|
||||
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV16 \
|
||||
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
|
||||
/* Use oversamply by 8 only if the divisor is small. But what is small? */
|
||||
|
||||
# if STM32_USARTDIV8 > 2000
|
||||
# define STM32_BRR_VALUE STM32_USARTDIV16
|
||||
# else
|
||||
# define USE_OVER8 1
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
|
||||
# endif
|
||||
|
||||
# endif /* CONFIG_LPUART1_SERIAL_CONSOLE */
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Variables
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm_lowputc(char ch)
|
||||
{
|
||||
#ifdef HAVE_CONSOLE
|
||||
/* Wait until the TX data register is empty */
|
||||
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
|
||||
USART_ISR_TXE) == 0);
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
|
||||
STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
|
||||
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
|
||||
USART_ISR_TC) == 0);
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
|
||||
!STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the USART used for the serial
|
||||
* console. Its purpose is to get the console output available as soon
|
||||
* as possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_UART)
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
uint32_t cr;
|
||||
#endif
|
||||
|
||||
#if defined(HAVE_CONSOLE)
|
||||
/* Enable USART APB1/2 clock */
|
||||
|
||||
modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
|
||||
#endif
|
||||
|
||||
/* Enable the console USART and configure GPIO pins needed for rx/tx.
|
||||
*
|
||||
* NOTE: Clocking for selected U[S]ARTs was already provided in
|
||||
* stm32_rcc.c
|
||||
*/
|
||||
|
||||
#ifdef STM32_CONSOLE_TX
|
||||
stm32_configgpio(STM32_CONSOLE_TX);
|
||||
#endif
|
||||
#ifdef STM32_CONSOLE_RX
|
||||
stm32_configgpio(STM32_CONSOLE_RX);
|
||||
#endif
|
||||
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
|
||||
!STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
/* Enable and configure the selected console device */
|
||||
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
/* Configure CR2 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
cr &= ~USART_CR2_CLRBITS;
|
||||
cr |= USART_CR2_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
|
||||
/* Configure CR1 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
cr &= ~USART_CR1_CLRBITS;
|
||||
cr |= USART_CR1_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
/* Configure CR3 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
cr &= ~USART_CR3_CLRBITS;
|
||||
cr |= USART_CR3_SETBITS;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
|
||||
/* Configure the USART Baud Rate */
|
||||
|
||||
putreg32(STM32_BRR_VALUE,
|
||||
STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
|
||||
|
||||
/* Select oversampling by 8 */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#ifdef USE_OVER8
|
||||
cr |= USART_CR1_OVER8;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_UART */
|
||||
}
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_lowputc.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level
|
||||
* initialization of serial console.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_lowsetup(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,300 +0,0 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_uart.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32L5_STM32L5_UART_H
|
||||
#define __ARCH_ARM_STC_STM32L5_STM32L5_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/serial/serial.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L562XX)
|
||||
# include "hardware/stm32l5_uart.h"
|
||||
#else
|
||||
# error "Unsupported STM32L5 chip"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Make sure that we have not enabled more U[S]ARTs than are supported by the
|
||||
* device.
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_STM32_HAVE_UART5)
|
||||
# undef CONFIG_STM32_UART5
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_HAVE_UART4)
|
||||
# undef CONFIG_STM32_UART4
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_HAVE_USART3)
|
||||
# undef CONFIG_STM32_USART3
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_HAVE_USART2)
|
||||
# undef CONFIG_STM32_USART2
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_HAVE_USART1)
|
||||
# undef CONFIG_STM32_USART1
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_HAVE_LPUART1)
|
||||
# undef CONFIG_STM32_LPUART1
|
||||
#endif
|
||||
|
||||
/* Sanity checks */
|
||||
|
||||
#if !defined(CONFIG_STM32_LPUART1)
|
||||
# undef CONFIG_STM32_LPUART1_SERIALDRIVER
|
||||
# undef CONFIG_STM32_LPUART1_1WIREDRIVER
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_USART1)
|
||||
# undef CONFIG_STM32_USART1_SERIALDRIVER
|
||||
# undef CONFIG_STM32_USART1_1WIREDRIVER
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_USART2)
|
||||
# undef CONFIG_STM32_USART2_SERIALDRIVER
|
||||
# undef CONFIG_STM32_USART2_1WIREDRIVER
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_USART3)
|
||||
# undef CONFIG_STM32_USART3_SERIALDRIVER
|
||||
# undef CONFIG_STM32_USART3_1WIREDRIVER
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_UART4)
|
||||
# undef CONFIG_STM32_UART4_SERIALDRIVER
|
||||
# undef CONFIG_STM32_UART4_1WIREDRIVER
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_UART5)
|
||||
# undef CONFIG_STM32_UART5_SERIALDRIVER
|
||||
# undef CONFIG_STM32_UART5_1WIREDRIVER
|
||||
#endif
|
||||
|
||||
/* Is there a USART enabled? */
|
||||
|
||||
#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \
|
||||
defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \
|
||||
defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5)
|
||||
# define HAVE_UART 1
|
||||
#endif
|
||||
|
||||
/* Is there a serial console? */
|
||||
|
||||
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER)
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define CONSOLE_UART 1
|
||||
# define HAVE_CONSOLE 1
|
||||
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER)
|
||||
# undef CONFIG_LPUART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define CONSOLE_UART 2
|
||||
# define HAVE_CONSOLE 1
|
||||
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER)
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define CONSOLE_UART 3
|
||||
# define HAVE_CONSOLE 1
|
||||
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER)
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define CONSOLE_UART 4
|
||||
# define HAVE_CONSOLE 1
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER)
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define CONSOLE_UART 5
|
||||
# define HAVE_CONSOLE 1
|
||||
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER)
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# define CONSOLE_UART 6
|
||||
# define HAVE_CONSOLE 1
|
||||
#else
|
||||
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||
# define CONSOLE_UART 0
|
||||
# undef HAVE_CONSOLE
|
||||
#endif
|
||||
|
||||
/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX
|
||||
* configuration
|
||||
*/
|
||||
|
||||
#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA)
|
||||
# undef CONFIG_USART1_RXDMA
|
||||
# undef CONFIG_USART2_RXDMA
|
||||
# undef CONFIG_USART3_RXDMA
|
||||
# undef CONFIG_UART4_RXDMA
|
||||
# undef CONFIG_UART5_RXDMA
|
||||
#endif
|
||||
|
||||
/* Disable the DMA configuration on all unused USARTs */
|
||||
|
||||
#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER
|
||||
# undef CONFIG_LPUART1_RXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STM32_USART1_SERIALDRIVER
|
||||
# undef CONFIG_USART1_RXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STM32_USART2_SERIALDRIVER
|
||||
# undef CONFIG_USART2_RXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STM32_USART3_SERIALDRIVER
|
||||
# undef CONFIG_USART3_RXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STM32_UART4_SERIALDRIVER
|
||||
# undef CONFIG_UART4_RXDMA
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STM32_UART5_SERIALDRIVER
|
||||
# undef CONFIG_UART5_RXDMA
|
||||
#endif
|
||||
|
||||
/* Is DMA available on any (enabled) USART? */
|
||||
|
||||
#undef SERIAL_HAVE_DMA
|
||||
#if defined(CONFIG_LPUART1_RXDMA) || defined(CONFIG_USART1_RXDMA) || \
|
||||
defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \
|
||||
defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA)
|
||||
# define SERIAL_HAVE_DMA 1
|
||||
#endif
|
||||
|
||||
/* Is DMA used on the console UART? */
|
||||
|
||||
#undef SERIAL_HAVE_CONSOLE_DMA
|
||||
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_LPUART1_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
#endif
|
||||
|
||||
/* Is DMA used on all (enabled) USARTs */
|
||||
|
||||
#define SERIAL_HAVE_ONLY_DMA 1
|
||||
#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_DMA
|
||||
#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_DMA
|
||||
#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_DMA
|
||||
#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_DMA
|
||||
#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_DMA
|
||||
#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
|
||||
# undef SERIAL_HAVE_ONLY_DMA
|
||||
#endif
|
||||
|
||||
/* Is RS-485 used? */
|
||||
|
||||
#if defined(CONFIG_LPUART1_RS485) || defined(CONFIG_USART1_RS485) || \
|
||||
defined(CONFIG_USART2_RS485) || defined(CONFIG_USART3_RS485) || \
|
||||
defined(CONFIG_UART4_RS485) || defined(CONFIG_UART5_RS485)
|
||||
# define HAVE_RS485 1
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_RS485
|
||||
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE)
|
||||
#else
|
||||
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_serial_dma_poll
|
||||
*
|
||||
* Description:
|
||||
* Must be called periodically if any STM32 UART is configured for DMA.
|
||||
* The DMA callback is triggered for each fifo size/2 bytes, but this can
|
||||
* result in some bytes being transferred but not collected if the incoming
|
||||
* data is not a whole multiple of half the FIFO size.
|
||||
*
|
||||
* May be safely called from either interrupt or thread context.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
void stm32_serial_dma_poll(void);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_STC_STM32L5_STM32L5_UART_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue