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Many changes to reduce complaints from CppCheck. Several latent bugs fixes, but probably some new typos introduced

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This commit is contained in:
Gregory Nutt 2014-02-10 18:08:49 -06:00
parent 8b1d3f6698
commit 91b002a043
82 changed files with 1932 additions and 1594 deletions
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3
ChangeLog
View file

@ -6570,3 +6570,6 @@
for the MIO283QT9A LCD. From Toby Duckworth (2014-2-10).
* configs/mikroe-stm32f4/src/up_mio283qt9a.c: The Mikroe STM32F4 can
now support the newer MIO283QT9A LCD. From Toby Duckworth (2014-2-10).
* MANY files changes based on complaints from the tool CppCheck. Several
latent bugs were fixed (and most likely some new typos were introducted)
(2014-2-10).

2
arch/arm/src/c5471/c5471_irq.c
View file

@ -228,7 +228,7 @@ void up_enable_irq(int irq)
void up_maskack_irq(int irq)
{
uint32_t reg = getreg32(INT_CTRL_REG);
uint32_t reg;
/* Mask the interrupt */

2
arch/arm/src/c5471/c5471_watchdog.c
View file

@ -261,7 +261,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
dbg("buflen=%d\n", buflen);
if (buflen >= 18)
{
sprintf(buffer, "#08x %08x\n", c5471_wdt_cntl, c5471_wdt_count);
sprintf(buffer, "%08x %08x\n", c5471_wdt_cntl, c5471_wdt_count);
return 18;
}
return 0;

4
arch/arm/src/common/up_allocateheap.c
View file

@ -112,7 +112,6 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = CONFIG_RAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
@ -151,9 +150,6 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = CONFIG_RAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
/* Return the kernel heap settings (i.e., the part of the heap region

6
arch/arm/src/dm320/dm320_framebuffer.c
View file

@ -1254,7 +1254,7 @@ static int dm320_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursora
attrib->size.w = getreg16(DM320_OSD_CURXL);
attrib->size.h = getreg16(DM320_OSD_CURYL);
#endif
irqrestore();
irqrestore(flags);
attrib->mxsize.w = MAX_XRES;
attrib->mxsize.h = MAX_YRES;
@ -1325,10 +1325,8 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
settings->size.h = MAX_YRES;
}
flags = irqsave();
putreg16(settings->size.w, DM320_OSD_CURXL);
putreg16(settings->size.h, DM320_OSD_CURYL);
restore_flags(flags);
}
#endif
@ -1342,7 +1340,7 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
regval &= ~1;
}
putreg16(regval, DM320_OSD_RECTCUR);
restore_flags(flags);
irqrestore(flags);
gvdbg("DM320_OSD_CURXP: %04x\n", getreg16(DM320_OSD_CURXP));
gvdbg("DM320_OSD_CURYP: %04x\n", getreg16(DM320_OSD_CURYP));

2
arch/arm/src/dm320/dm320_usbdev.c
View file

@ -1761,7 +1761,7 @@ static inline void dm320_epinitialize(struct dm320_usbdev_s *priv)
/* FIFO address, max packet size, dual/single buffered */
dm320_putreg8(addrhi, DM320_USB_TXFIFO1);
dm320_putreg8(addrlo, DM320_USB_TXFIFO1);
dm320_putreg8(addrhi|g_epinfo[i].fifo, DM320_USB_TXFIFO2);
/* TX endpoint max packet size */

2
arch/arm/src/imx/imx_serial.c
View file

@ -879,8 +879,10 @@ static int up_interrupt(int irq, void *context)
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
struct inode *inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
#endif
int ret = OK;
switch (cmd)

4
arch/arm/src/imx/imx_spi.c
View file

@ -500,10 +500,10 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
{
#ifndef CONFIG_SPI_POLLWAIT
irqstate_t flags;
#endif
uint32_t regval;
int ntxd;
int ret;
#endif
int ntxd;
/* Set up to perform the transfer */

2
arch/arm/src/kl/kl_serial.c
View file

@ -709,7 +709,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
}
else
{
priv->ie |= UART_C2_RIE;
priv->ie &= ~UART_C2_RIE;
up_setuartint(priv);
}

2
arch/arm/src/lm/lm_start.c
View file

@ -100,7 +100,9 @@ extern void _vectors(void);
void __start(void)
{
#ifdef CONFIG_BOOT_RUNFROMFLASH
const uint32_t *src;
#endif
uint32_t *dest;
/* Configure the uart so that we can get debug output as soon as possible */

568
arch/arm/src/lpc31xx/lpc31_i2c.c
View file

@ -72,49 +72,50 @@
* Pre-processor Definitions
****************************************************************************/
#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */
#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */
/****************************************************************************
* Private Data
****************************************************************************/
struct lpc31_i2cdev_s
{
struct i2c_dev_s dev; /* Generic I2C device */
struct i2c_msg_s msg; /* a single message for legacy read/write */
unsigned int base; /* Base address of registers */
uint16_t clkid; /* Clock for this device */
uint16_t rstid; /* Reset for this device */
uint16_t irqid; /* IRQ for this device */
struct i2c_dev_s dev; /* Generic I2C device */
struct i2c_msg_s msg; /* a single message for legacy read/write */
unsigned int base; /* Base address of registers */
uint16_t clkid; /* Clock for this device */
uint16_t rstid; /* Reset for this device */
uint16_t irqid; /* IRQ for this device */
sem_t mutex; /* Only one thread can access at a time */
sem_t mutex; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
WDOG_ID timeout; /* watchdog to timeout when bus hung */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
WDOG_ID timeout; /* watchdog to timeout when bus hung */
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
unsigned int nmsg; /* number of transfer remaining */
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
unsigned int nmsg; /* number of transfer remaining */
uint16_t header[3]; /* I2C address header */
uint16_t hdrcnt; /* number of bytes of header */
uint16_t wrcnt; /* number of bytes sent to tx fifo */
uint16_t rdcnt; /* number of bytes read from rx fifo */
uint16_t header[3]; /* I2C address header */
uint16_t hdrcnt; /* number of bytes of header */
uint16_t wrcnt; /* number of bytes sent to tx fifo */
uint16_t rdcnt; /* number of bytes read from rx fifo */
};
#define I2C_STATE_DONE 0
#define I2C_STATE_START 1
#define I2C_STATE_HEADER 2
#define I2C_STATE_TRANSFER 3
#define I2C_STATE_DONE 0
#define I2C_STATE_START 1
#define I2C_STATE_HEADER 2
#define I2C_STATE_TRANSFER 3
static struct lpc31_i2cdev_s i2cdevices[2];
/****************************************************************************
* Private Functions
****************************************************************************/
static int i2c_interrupt (int irq, FAR void *context);
static void i2c_progress (struct lpc31_i2cdev_s *priv);
static void i2c_timeout (int argc, uint32_t arg, ...);
static void i2c_reset (struct lpc31_i2cdev_s *priv);
static int i2c_interrupt(int irq, FAR void *context);
static void i2c_progress(struct lpc31_i2cdev_s *priv);
static void i2c_timeout(int argc, uint32_t arg, ...);
static void i2c_reset(struct lpc31_i2cdev_s *priv);
/****************************************************************************
* Public Functions
@ -130,13 +131,14 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int
static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen);
static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count);
struct i2c_ops_s lpc31_i2c_ops = {
.setfrequency = i2c_setfrequency,
.setaddress = i2c_setaddress,
.write = i2c_write,
.read = i2c_read,
struct i2c_ops_s lpc31_i2c_ops =
{
.setfrequency = i2c_setfrequency,
.setaddress = i2c_setaddress,
.write = i2c_write,
.read = i2c_read,
#ifdef CONFIG_I2C_TRANSFER
.transfer = i2c_transfer
.transfer = i2c_transfer
#endif
};
@ -151,41 +153,41 @@ struct i2c_ops_s lpc31_i2c_ops = {
struct i2c_dev_s *up_i2cinitialize(int port)
{
struct lpc31_i2cdev_s *priv = &i2cdevices[port];
priv->base = (port == 0) ? LPC31_I2C0_VBASE : LPC31_I2C1_VBASE;
priv->clkid = (port == 0) ? CLKID_I2C0PCLK : CLKID_I2C1PCLK;
priv->rstid = (port == 0) ? RESETID_I2C0RST : RESETID_I2C1RST;
priv->irqid = (port == 0) ? LPC31_IRQ_I2C0 : LPC31_IRQ_I2C1;
sem_init (&priv->mutex, 0, 1);
sem_init (&priv->wait, 0, 0);
sem_init(&priv->mutex, 0, 1);
sem_init(&priv->wait, 0, 0);
/* Enable I2C system clocks */
lpc31_enableclock (priv->clkid);
lpc31_enableclock(priv->clkid);
/* Reset I2C blocks */
lpc31_softreset (priv->rstid);
lpc31_softreset(priv->rstid);
/* Soft reset the device */
i2c_reset (priv);
i2c_reset(priv);
/* Allocate a watchdog timer */
priv->timeout = wd_create();
DEBUGASSERT(priv->timeout != 0);
/* Attach Interrupt Handler */
irq_attach (priv->irqid, i2c_interrupt);
irq_attach(priv->irqid, i2c_interrupt);
/* Enable Interrupt Handler */
up_enable_irq(priv->irqid);
/* Install our operations */
priv->dev.ops = &lpc31_i2c_ops;
return &priv->dev;
}
@ -197,23 +199,23 @@ struct i2c_dev_s *up_i2cinitialize(int port)
*
*******************************************************************************/
void up_i2cuninitalize (struct lpc31_i2cdev_s *priv)
void up_i2cuninitalize(struct lpc31_i2cdev_s *priv)
{
/* Disable All Interrupts, soft reset the device */
i2c_reset (priv);
i2c_reset(priv);
/* Detach Interrupt Handler */
irq_detach (priv->irqid);
irq_detach(priv->irqid);
/* Reset I2C blocks */
lpc31_softreset (priv->rstid);
lpc31_softreset(priv->rstid);
/* Disable I2C system clocks */
lpc31_disableclock (priv->clkid);
lpc31_disableclock(priv->clkid);
}
/*******************************************************************************
@ -228,22 +230,25 @@ static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
uint32_t freq = lpc31_clkfreq (priv->clkid, DOMAINID_AHB0APB1);
uint32_t freq = lpc31_clkfreq(priv->clkid, DOMAINID_AHB0APB1);
if (freq > 100000)
{
{
/* asymetric per 400Khz I2C spec */
putreg32 (((47 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET);
putreg32 (((83 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET);
}
putreg32(((47 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET);
putreg32(((83 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET);
}
else
{
{
/* 50/50 mark space ratio */
putreg32 (((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET);
putreg32 (((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET);
}
putreg32(((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET);
putreg32(((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET);
}
/* FIXME: This function should return the actual selected frequency */
return frequency;
}
@ -254,6 +259,7 @@ static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
* Set the I2C slave address for a subsequent read/write
*
*******************************************************************************/
static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
@ -275,20 +281,21 @@ static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
* frequency and slave address.
*
*******************************************************************************/
static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
int ret;
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
int ret;
DEBUGASSERT (dev != NULL);
priv->msg.flags &= ~I2C_M_READ;
priv->msg.buffer = (uint8_t*)buffer;
priv->msg.length = buflen;
DEBUGASSERT(dev != NULL);
ret = i2c_transfer (dev, &priv->msg, 1);
priv->msg.flags &= ~I2C_M_READ;
priv->msg.buffer = (uint8_t*)buffer;
priv->msg.length = buflen;
return ret == 1 ? OK : -ETIMEDOUT;
ret = i2c_transfer(dev, &priv->msg, 1);
return ret == 1 ? OK : -ETIMEDOUT;
}
/*******************************************************************************
@ -299,20 +306,21 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle
* frequency and slave address.
*
*******************************************************************************/
static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
int ret;
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
int ret;
DEBUGASSERT (dev != NULL);
priv->msg.flags |= I2C_M_READ;
priv->msg.buffer = buffer;
priv->msg.length = buflen;
DEBUGASSERT(dev != NULL);
ret = i2c_transfer (dev, &priv->msg, 1);
priv->msg.flags |= I2C_M_READ;
priv->msg.buffer = buffer;
priv->msg.length = buflen;
return ret == 1 ? OK : -ETIMEDOUT;
ret = i2c_transfer(dev, &priv->msg, 1);
return ret == 1 ? OK : -ETIMEDOUT;
}
/*******************************************************************************
@ -323,37 +331,39 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
*
*******************************************************************************/
static int i2c_transfer (FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count)
static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
irqstate_t flags;
int ret;
sem_wait (&priv->mutex);
sem_wait(&priv->mutex);
flags = irqsave();
priv->state = I2C_STATE_START;
priv->msgs = msgs;
priv->nmsg = count;
i2c_progress (priv);
i2c_progress(priv);
/* start a watchdog to timeout the transfer if
* the bus is locked up... */
wd_start (priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
* the bus is locked up...
*/
wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
while (priv->state != I2C_STATE_DONE)
{
sem_wait (&priv->wait);
sem_wait(&priv->wait);
}
wd_cancel (priv->timeout);
wd_cancel(priv->timeout);
ret = count - priv->nmsg;
irqrestore (flags);
sem_post (&priv->mutex);
irqrestore(flags);
sem_post(&priv->mutex);
return ret;
}
@ -365,16 +375,16 @@ static int i2c_transfer (FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs,
*
*******************************************************************************/
static int i2c_interrupt (int irq, FAR void *context)
static int i2c_interrupt(int irq, FAR void *context)
{
if (irq == LPC31_IRQ_I2C0)
{
i2c_progress (&i2cdevices[0]);
i2c_progress(&i2cdevices[0]);
}
if (irq == LPC31_IRQ_I2C1)
{
i2c_progress (&i2cdevices[1]);
i2c_progress(&i2cdevices[1]);
}
return OK;
@ -388,170 +398,194 @@ static int i2c_interrupt (int irq, FAR void *context)
*
*******************************************************************************/
static void i2c_progress (struct lpc31_i2cdev_s *priv)
static void i2c_progress(struct lpc31_i2cdev_s *priv)
{
struct i2c_msg_s *msg;
uint32_t stat, ctrl;
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET);
/* Were there arbitration problems? */
if ((stat & I2C_STAT_AFI) != 0)
{
/* Perform a soft reset */
i2c_reset (priv);
i2c_reset(priv);
/* FIXME: automatic retry? */
priv->state = I2C_STATE_DONE;
sem_post (&priv->wait);
sem_post(&priv->wait);
return;
}
while (priv->nmsg > 0)
{
ctrl = I2C_CTRL_NAIE | I2C_CTRL_AFIE | I2C_CTRL_TDIE;
msg = priv->msgs;
switch (priv->state)
{
case I2C_STATE_START:
if ((msg->flags & I2C_M_TEN) != 0)
{
priv->header[0] = I2C_TX_START | 0xF0 | ((msg->addr & 0x300) >> 7);
priv->header[1] = msg->addr & 0xFF;
priv->hdrcnt = 2;
if (msg->flags & I2C_M_READ)
{
priv->header[2] = priv->header[0] | 1;
priv->hdrcnt++;
}
}
else
{
priv->header[0] = I2C_TX_START | (msg->addr << 1) | (msg->flags & I2C_M_READ);
priv->hdrcnt = 1;
}
case I2C_STATE_START:
if ((msg->flags & I2C_M_TEN) != 0)
{
priv->header[0] = I2C_TX_START | 0xF0 | ((msg->addr & 0x300) >> 7);
priv->header[1] = msg->addr & 0xFF;
priv->hdrcnt = 2;
if (msg->flags & I2C_M_READ)
{
priv->header[2] = priv->header[0] | 1;
priv->hdrcnt++;
}
}
else
{
priv->header[0] = I2C_TX_START | (msg->addr << 1) | (msg->flags & I2C_M_READ);
priv->hdrcnt = 1;
}
putreg32 (ctrl, priv->base + LPC31_I2C_CTRL_OFFSET);
putreg32(ctrl, priv->base + LPC31_I2C_CTRL_OFFSET);
priv->state = I2C_STATE_HEADER;
priv->wrcnt = 0;
/* DROP THROUGH */
case I2C_STATE_HEADER:
while ((priv->wrcnt != priv->hdrcnt) && (stat & I2C_STAT_TFF) == 0)
{
putreg32(priv->header[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
priv->wrcnt++;
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
}
if (priv->wrcnt < priv->hdrcnt)
{
/* Enable Tx FIFO Not Full Interrupt */
putreg32 (ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET);
goto out;
}
priv->state = I2C_STATE_TRANSFER;
priv->wrcnt = 0;
priv->rdcnt = 0;
/* DROP THROUGH */
case I2C_STATE_TRANSFER:
if (msg->flags & I2C_M_READ)
{
while ((priv->rdcnt != msg->length) && (stat & I2C_STAT_RFE) == 0)
{
msg->buffer[priv->rdcnt] = getreg32 (priv->base + LPC31_I2C_RX_OFFSET);
priv->rdcnt++;
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
}
if (priv->rdcnt < msg->length)
{
/* Not all data received, fill the Tx FIFO with more dummies */
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
{
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
putreg32 (I2C_TX_STOP, priv->base + LPC31_I2C_TX_OFFSET);
else
putreg32 (0, priv->base + LPC31_I2C_TX_OFFSET);
priv->wrcnt++;
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
}
if (priv->wrcnt < msg->length)
{
/* Enable Tx FIFO not full and Rx Fifo Avail Interrupts */
putreg32 (ctrl | I2C_CTRL_TFFIE | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET);
}
else
{
/* Enable Rx Fifo Avail Interrupts */
putreg32 (ctrl | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET);
}
goto out;
}
}
else /* WRITE */
{
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
{
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
putreg32 (I2C_TX_STOP | msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
else
putreg32 (msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
priv->wrcnt++;
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
}
if (priv->wrcnt < msg->length)
{
/* Enable Tx Fifo not full Interrupt */
putreg32 (ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET);
goto out;
}
}
/* Transfer completed, move onto the next one */
priv->state = I2C_STATE_START;
if (--priv->nmsg == 0)
{
/* Final transfer, wait for Transmit Done Interrupt */
putreg32 (ctrl, priv->base + LPC31_I2C_CTRL_OFFSET);
goto out;
}
priv->msgs++;
break;
}
}
priv->state = I2C_STATE_HEADER;
priv->wrcnt = 0;
/* DROP THROUGH */
out:
case I2C_STATE_HEADER:
while ((priv->wrcnt != priv->hdrcnt) && (stat & I2C_STAT_TFF) == 0)
{
putreg32(priv->header[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
priv->wrcnt++;
stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET);
}
if (priv->wrcnt < priv->hdrcnt)
{
/* Enable Tx FIFO Not Full Interrupt */
putreg32(ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET);
goto out;
}
priv->state = I2C_STATE_TRANSFER;
priv->wrcnt = 0;
priv->rdcnt = 0;
/* DROP THROUGH */
case I2C_STATE_TRANSFER:
if (msg->flags & I2C_M_READ)
{
while ((priv->rdcnt != msg->length) && (stat & I2C_STAT_RFE) == 0)
{
msg->buffer[priv->rdcnt] = getreg32 (priv->base + LPC31_I2C_RX_OFFSET);
priv->rdcnt++;
stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET);
}
if (priv->rdcnt < msg->length)
{
/* Not all data received, fill the Tx FIFO with more dummies */
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
{
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
{
putreg32(I2C_TX_STOP, priv->base + LPC31_I2C_TX_OFFSET);
}
else
{
putreg32(0, priv->base + LPC31_I2C_TX_OFFSET);
}
priv->wrcnt++;
stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET);
}
if (priv->wrcnt < msg->length)
{
/* Enable Tx FIFO not full and Rx Fifo Avail Interrupts */
putreg32(ctrl | I2C_CTRL_TFFIE | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET);
}
else
{
/* Enable Rx Fifo Avail Interrupts */
putreg32(ctrl | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET);
}
goto out;
}
}
else /* WRITE */
{
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
{
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
{
putreg32(I2C_TX_STOP | msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
}
else
{
putreg32(msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
}
priv->wrcnt++;
stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET);
}
if (priv->wrcnt < msg->length)
{
/* Enable Tx Fifo not full Interrupt */
putreg32(ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET);
goto out;
}
}
/* Transfer completed, move onto the next one */
priv->state = I2C_STATE_START;
if (--priv->nmsg == 0)
{
/* Final transfer, wait for Transmit Done Interrupt */
putreg32(ctrl, priv->base + LPC31_I2C_CTRL_OFFSET);
goto out;
}
priv->msgs++;
break;
}
}
out:
if (stat & I2C_STAT_TDI)
{
putreg32 (I2C_STAT_TDI, priv->base + LPC31_I2C_STAT_OFFSET);
putreg32(I2C_STAT_TDI, priv->base + LPC31_I2C_STAT_OFFSET);
/* You'd expect the NAI bit to be set when no acknowledge was
* received - but it gets cleared whenever a write it done to
* received - but it gets cleared whenever a write it done to
* the TXFIFO - so we've gone and cleared it while priming the
* rest of the transfer! */
if ((stat = getreg32 (priv->base + LPC31_I2C_TXFL_OFFSET)) != 0)
{
if (priv->nmsg == 0)
priv->nmsg++;
i2c_reset (priv);
}
* rest of the transfer!
*/
if ((stat = getreg32(priv->base + LPC31_I2C_TXFL_OFFSET)) != 0)
{
if (priv->nmsg == 0)
{
priv->nmsg++;
}
i2c_reset(priv);
}
priv->state = I2C_STATE_DONE;
sem_post (&priv->wait);
sem_post(&priv->wait);
}
}
@ -563,32 +597,37 @@ out:
*
*******************************************************************************/
static void i2c_timeout (int argc, uint32_t arg, ...)
static void i2c_timeout(int argc, uint32_t arg, ...)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) arg;
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) arg;
irqstate_t flags = irqsave();
if (priv->state != I2C_STATE_DONE)
irqstate_t flags = irqsave();
if (priv->state != I2C_STATE_DONE)
{
/* If there's data remaining in the TXFIFO, then ensure at least
* one transfer has failed to complete.. */
/* If there's data remaining in the TXFIFO, then ensure at least
* one transfer has failed to complete.
*/
if (getreg32 (priv->base + LPC31_I2C_TXFL_OFFSET) != 0)
{
if (priv->nmsg == 0)
priv->nmsg++;
}
if (getreg32(priv->base + LPC31_I2C_TXFL_OFFSET) != 0)
{
if (priv->nmsg == 0)
{
priv->nmsg++;
}
}
/* Soft reset the USB controller */
i2c_reset (priv);
/* Soft reset the USB controller */
/* Mark the transfer as finished */
priv->state = I2C_STATE_DONE;
sem_post (&priv->wait);
i2c_reset(priv);
/* Mark the transfer as finished */
priv->state = I2C_STATE_DONE;
sem_post(&priv->wait);
}
irqrestore (flags);
irqrestore(flags);
}
/*******************************************************************************
@ -598,11 +637,12 @@ static void i2c_timeout (int argc, uint32_t arg, ...)
* Perform a soft reset of the I2C controller
*
*******************************************************************************/
static void i2c_reset (struct lpc31_i2cdev_s *priv)
static void i2c_reset(struct lpc31_i2cdev_s *priv)
{
putreg32 (I2C_CTRL_RESET, priv->base + LPC31_I2C_CTRL_OFFSET);
putreg32(I2C_CTRL_RESET, priv->base + LPC31_I2C_CTRL_OFFSET);
/* Wait for Reset to complete */
while ((getreg32 (priv->base + LPC31_I2C_CTRL_OFFSET) & I2C_CTRL_RESET) != 0)
while ((getreg32(priv->base + LPC31_I2C_CTRL_OFFSET) & I2C_CTRL_RESET) != 0)
;
}

8
arch/arm/src/sam34/sam4l_gpio.c
View file

@ -214,7 +214,7 @@ static inline int sam_configinterrupt(uintptr_t base, uint32_t pin,
* 11 Reserved
*/
gpio_pinset_t edges = cfgset & GPIO_INT_MASK;
gpio_pinset_t edges = (cfgset & GPIO_INT_MASK);
if (edges == GPIO_INT_RISING)
{
@ -398,16 +398,16 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
* 11 Reserved
*/
edges = cfgset & GPIO_INT_MASK;
edges = (cfgset & GPIO_INT_MASK);
if (edges == GPIO_INT_RISING)
{
/* Rising only.. disable interrrupts on the falling edge */
/* Rising only.. disable interrupts on the falling edge */
putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET);
}
else if (edges == GPIO_INT_FALLING)
{
/* Falling only.. disable interrrupts on the rising edge */
/* Falling only.. disable interrupts on the rising edge */
putreg32(pin, base + SAM_GPIO_IMR1S_OFFSET);
}

2
arch/arm/src/stm32/stm32_dumpgpio.c
View file

@ -109,12 +109,10 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
irqstate_t flags;
uint32_t base;
unsigned int port;
unsigned int pin;
/* Get the base address associated with the GPIO port */
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
base = g_gpiobase[port];
/* The following requires exclusive access to the GPIO registers */

2
arch/arm/src/str71x/str71x_serial.c
View file

@ -753,8 +753,10 @@ static int up_interrupt(int irq, void *context)
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
struct inode *inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
#endif
int ret = OK;
switch (cmd)

7
arch/avr/src/avr/up_checkstack.c
View file

@ -82,7 +82,10 @@ size_t up_check_tcbstack(FAR struct tcb_s *tcb)
{
FAR uint8_t *ptr;
size_t mark;
int i, j;
#if 0
int i;
int j;
#endif
/* The AVR uses a push-down stack: the stack grows toward lower addresses
* in memory. We need to start at the lowest address in the stack memory
@ -121,8 +124,10 @@ size_t up_check_tcbstack(FAR struct tcb_s *tcb)
{
ch = 'X';
}
up_putc(ch);
}
up_putc('\n');
}
}

2
arch/hc/src/m9s12/m9s12_ethernet.c
View file

@ -291,7 +291,7 @@ static void emac_receive(FAR struct emac_driver_s *priv)
}
}
}
while (); /* While there are more packets to be processed */
while (true); /* While there are more packets to be processed */
}
/****************************************************************************

2
arch/sim/src/up_touchscreen.c
View file

@ -534,7 +534,7 @@ static int up_poll(FAR struct file *filep, FAR struct pollfd *fds,
{
FAR struct inode *inode;
FAR struct up_dev_s *priv;
int ret = OK;
int ret;
int i;
ivdbg("setup: %d\n", (int)setup);

4
arch/z16/src/z16f/z16f_serial.c
View file

@ -302,8 +302,7 @@ static uint8_t z16f_disableuartirq(struct uart_dev_s *dev)
static void z16f_restoreuartirq(struct uart_dev_s *dev, uint8_t state)
{
struct z16f_uart_s *priv = (struct z16f_uart_s*)dev->priv;
irqstate_t flags = irqsave();
irqstate_t flags = irqsave();
z16f_txint(dev, (state & STATE_TXENABLED) ? true : false);
z16f_rxint(dev, (state & STATE_RXENABLED) ? true : false);
@ -400,7 +399,6 @@ static int z16f_setup(struct uart_dev_s *dev)
static void z16f_shutdown(struct uart_dev_s *dev)
{
struct z16f_uart_s *priv = (struct z16f_uart_s*)dev->priv;
(void)z16f_disableuartirq(dev);
}

1
arch/z80/src/ez80/ez80_i2c.c
View file

@ -393,7 +393,6 @@ static void i2c_stop(void)
static int i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit)
{
uint8_t sr;
int ret = OK;
/* Wait for the IFLG bit to transition to 1. At this point, we should
* have status == 8 meaning that the start bit was sent successfully.

5
arch/z80/src/ez80/ez80_spi.c
View file

@ -284,7 +284,7 @@ static uint8_t spi_waitspif(void)
* Name: spi_transfer
*
* Description:
* Send one byte on SPI, return th response
* Send one byte on SPI, return the response
*
* Input Parameters:
* ch - the byte to send
@ -361,7 +361,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
FAR const uint8_t *ptr = (FAR const uint8_t*)buffer;
uint8_t response;
/* Loop while thre are bytes remaining to be sent */
/* Loop while there are bytes remaining to be sent */
while (buflen-- > 0)
{
@ -392,7 +392,6 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t buflen)
{
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
uint8_t response;
/* Loop while thre are bytes remaining to be sent */

1
arch/z80/src/z180/z180_mmu.c
View file

@ -438,7 +438,6 @@ int up_addrenv_destroy(task_addrenv_t addrenv)
int up_addrenv_assign(task_addrenv_t addrenv, FAR struct tcb_s *tcb)
{
FAR struct z180_cbr_s *cbr = (FAR struct z180_cbr_s *)addrenv;
int ret;
/* Make sure that there is no address environment in place on this TCB */

7
arch/z80/src/z8/z8_serial.c
View file

@ -284,8 +284,7 @@ static uint8_t z8_disableuartirq(FAR struct uart_dev_s *dev)
static void z8_restoreuartirq(FAR struct uart_dev_s *dev, uint8_t state)
{
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
irqstate_t flags = irqsave();
irqstate_t flags = irqsave();
z8_txint(dev, (state & STATE_TXENABLED) ? true : false);
z8_rxint(dev, (state & STATE_RXENABLED) ? true : false);
@ -322,8 +321,7 @@ static void z8_consoleput(uint8_t ch)
void z8_uartconfigure(void)
{
uint16_t brg;
uint8_t val;
uint8_t val;
/* Configure GPIO Port A pins 4 & 5 for alternate function */
@ -421,7 +419,6 @@ static int z8_setup(FAR struct uart_dev_s *dev)
static void z8_shutdown(FAR struct uart_dev_s *dev)
{
struct z8_uart_s *priv = (struct z8_uart_s*)dev->priv;
(void)z8_disableuartirq(dev);
}

5
binfmt/libelf/libelf_sections.c
View file

@ -124,12 +124,13 @@ static inline int elf_sectname(FAR struct elf_loadinfo_s *loadinfo,
readlen = loadinfo->buflen - bytesread;
if (offset + readlen > loadinfo->filelen)
{
readlen = loadinfo->filelen - offset;
if (readlen <= 0)
if (loadinfo->filelen <= offset)
{
bdbg("At end of file\n");
return -EINVAL;
}
readlen = loadinfo->filelen - offset;
}
/* Read that number of bytes into the array */

5
binfmt/libelf/libelf_symbols.c
View file

@ -110,12 +110,13 @@ static int elf_symname(FAR struct elf_loadinfo_s *loadinfo,
readlen = loadinfo->buflen - bytesread;
if (offset + readlen > loadinfo->filelen)
{
readlen = loadinfo->filelen - offset;
if (readlen <= 0)
if (loadinfo->filelen <= offset)
{
bdbg("At end of file\n");
return -EINVAL;
}
readlen = loadinfo->filelen - offset;
}
/* Read that number of bytes into the array */

2
binfmt/libnxflat/libnxflat_init.c
View file

@ -97,7 +97,6 @@ int nxflat_init(const char *filename, struct nxflat_loadinfo_s *loadinfo)
{
uint32_t datastart;
uint32_t dataend;
uint32_t bssstart;
uint32_t bssend;
int ret;
@ -152,7 +151,6 @@ int nxflat_init(const char *filename, struct nxflat_loadinfo_s *loadinfo)
datastart = ntohl(loadinfo->header.h_datastart);
dataend = ntohl(loadinfo->header.h_dataend);
bssstart = dataend;
bssend = ntohl(loadinfo->header.h_bssend);
/* And put this information into the loadinfo structure as well.

2
configs/lpc4330-xplorer/src/up_nsh.c
View file

@ -103,7 +103,7 @@ static int nsh_spifi_initialize(void)
return ret;
}
#else
/* Initialize to provide NXFFS on the MTD interface */1G
/* Initialize to provide NXFFS on the MTD interface */
ret = nxffs_initialize(mtd);
if (ret < 0)

2
configs/mikroe-stm32f4/src/up_clockconfig.c
View file

@ -109,7 +109,7 @@ void stm32_board_clockconfig(void)
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PLL dividers and multiplers to configure the main PLL */
/* Set the PLL dividers and multipliers to configure the main PLL */
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);

3
configs/mikroe-stm32f4/src/up_nsh.c
View file

@ -181,9 +181,6 @@
int nsh_archinitialize(void)
{
#if defined(HAVE_USBHOST) || defined(HAVE_USBMONITOR)
int ret;
#endif
#ifdef CONFIG_STM32_SPI3
FAR struct spi_dev_s *spi;
FAR struct mtd_dev_s *mtd;

2
configs/mx1ads/src/up_boot.c
View file

@ -81,7 +81,7 @@ void imx_boardinitialize(void)
(IMX_CSCR_USBDIV << PLL_CSCR_USBDIV_SHIFT) | /* USB divider */
CSCR_SDCNT_4thEDGE | /* Shutdown on 4th edge */
(IMX_CSCR_BCLKDIV << PLL_CSCR_BCLKDIV_SHIFT) | /* Bclock divider */
PLL_CSCR_SPEN | PLL_CSCR_MPEN); /* Enable MUC and System PLL */
PLL_CSCR_SPEN | PLL_CSCR_MPEN); /* Enable MUC and System PLL */
putreg32(regval, IMX_PLL_CSCR);
/* Use these new frequencies now */

3
configs/olimex-strp711/src/up_nsh.c
View file

@ -125,11 +125,10 @@
int nsh_archinitialize(void)
{
#ifdef NSH_HAVEMMCSD
FAR struct spi_dev_s *spi;
int ret;
#ifdef NSH_HAVEMMCSD
/* Get the SPI port */
message("nsh_archinitialize: Initializing SPI port %d\n",

3
configs/pic32mx7mmb/src/up_touchscreen.c
View file

@ -1365,9 +1365,6 @@ int arch_tcinitialize(int minor)
{
FAR struct tc_dev_s *priv;
char devname[DEV_NAMELEN];
#ifdef CONFIG_TOUCHSCREEN_MULTIPLE
irqstate_t flags;
#endif
int ret;
ivdbg("minor: %d\n", minor);

2
configs/px4fmu-v2_upstream/src/px4fmu2_init.c
View file

@ -195,7 +195,9 @@ void stm32_boardinitialize(void)
int nsh_archinitialize(void)
{
#ifdef CONFIG_MMCSD
int ret;
#endif
/* Configure ADC pins */

1
configs/sam4l-xplained/src/sam_buttons.c
View file

@ -147,6 +147,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler)
sam_gpioirq(IRQ_SW0);
(void)irq_attach(IRQ_SW0, irqhandler);
sam_gpioirqenable(IRQ_SW0);
irqrestore(flags);
}
/* Return the old button handler (so that it can be restored) */

1
configs/sam4s-xplained/src/sam_buttons.c
View file

@ -145,6 +145,7 @@ xcpt_t board_button_irq(int id, xcpt_t irqhandler)
sam_gpioirq(IRQ_BP2);
(void)irq_attach(IRQ_BP2, irqhandler);
sam_gpioirqenable(IRQ_BP2);
irqrestore(flags);
}
/* Return the old button handler (so that it can be restored) */

3
configs/skp16c26/src/up_lcd.c
View file

@ -116,6 +116,7 @@ static inline void up_setrs(bool data)
{
regval &= ~(1 << 0); /* Low = control */
}
putreg8(regval, M16C_P6);
}
@ -128,7 +129,7 @@ static inline void up_seten(void)
/* Set bit 1 of port 6 */
register uint8_t regval = getreg8(M16C_P6);
regval = (1 << 1);
regval |= (1 << 1);
putreg8(regval, M16C_P6);
}

10
configs/stm32ldiscovery/src/stm32_nsh.c
View file

@ -82,13 +82,11 @@
int nsh_archinitialize(void)
{
int ret = OK;
#ifdef CONFIG_STM32_LCD
/* Initialize the SLCD and register the SLCD device as /dev/slcd */
#ifdef CONFIG_STM32_LCD
ret = stm32_slcd_initialize();
return stm32_slcd_initialize();
#else
return OK;
#endif
return ret;
}

2
configs/twr-k60n512/src/up_buttons.c
View file

@ -135,7 +135,7 @@ uint8_t board_buttons(void)
#ifdef CONFIG_ARCH_IRQBUTTONS
xcpt_t board_button_irq(int id, xcpt_t irqhandler)
{
xcpt_t oldhandler = NULL;
xcpt_t oldhandler;
uint32_t pinset;
/* Map the button id to the GPIO bit set. */

6
configs/us7032evb1/shterm/shterm.c
View file

@ -110,6 +110,7 @@ static void putconsole(char ch)
{
(void)putc(ch, g_logstream);
}
(void)putchar(ch);
}
@ -139,6 +140,7 @@ static void printconsole(const char *fmt, ...)
{
(void)vfprintf(g_logstream, fmt, ap);
}
(void)vprintf(fmt, ap);
va_end(ap);
}
@ -435,7 +437,7 @@ static void close_tty(void)
(void)close(g_fd);
}
if (g_logstream >= 0)
if (g_logstream)
{
(void)fclose(g_logstream);
}
@ -717,7 +719,7 @@ int main(int argc, char **argv, char **envp)
{
sendfile(g_fd, filename, 0);
}
else if (ch1 == 'v' || ch1 == 'v')
else if (ch1 == 'v' || ch1 == 'V')
{
sendfile(g_fd, filename, 1);
}

6
drivers/analog/adc.c
View file

@ -362,9 +362,9 @@ static ssize_t adc_write(FAR struct file *filep, FAR const char *buffer, size_t
static int adc_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
FAR struct inode *inode = filep->f_inode;
FAR struct adc_dev_s *dev = inode->i_private;
int ret = OK;
FAR struct inode *inode = filep->f_inode;
FAR struct adc_dev_s *dev = inode->i_private;
int ret;
ret = dev->ad_ops->ao_ioctl(dev, cmd, arg);
return ret;

242
drivers/analog/ads1255.c
View file

@ -107,14 +107,14 @@
struct up_dev_s
{
uint8_t channel;
uint32_t sps;
uint8_t pga;
uint8_t buf;
const uint8_t *mux;
int irq;
int devno;
FAR struct spi_dev_s *spi; /* Cached SPI device reference */
uint8_t channel;
uint32_t sps;
uint8_t pga;
uint8_t buf;
const uint8_t *mux;
int irq;
int devno;
FAR struct spi_dev_s *spi; /* Cached SPI device reference */
};
/****************************************************************************
@ -136,28 +136,28 @@ static int adc_interrupt(int irq, void *context);
static const struct adc_ops_s g_adcops =
{
.ao_reset = adc_reset, /* ao_reset */
.ao_setup = adc_setup, /* ao_setup */
.ao_shutdown = adc_shutdown, /* ao_shutdown */
.ao_rxint = adc_rxint, /* ao_rxint */
.ao_ioctl = adc_ioctl /* ao_read */
.ao_reset = adc_reset, /* ao_reset */
.ao_setup = adc_setup, /* ao_setup */
.ao_shutdown = adc_shutdown, /* ao_shutdown */
.ao_rxint = adc_rxint, /* ao_rxint */
.ao_ioctl = adc_ioctl /* ao_read */
};
static struct up_dev_s g_adcpriv =
{
.mux = (const uint8_t [])
{
CONFIG_ADS1255_MUX,0
},
.sps = CONFIG_ADS1255_SPS,
.channel = 0,
.irq = CONFIG_ADS1255_IRQ,
.mux = (const uint8_t [])
{
CONFIG_ADS1255_MUX,0
},
.sps = CONFIG_ADS1255_SPS,
.channel = 0,
.irq = CONFIG_ADS1255_IRQ,
};
static struct adc_dev_s g_adcdev =
{
.ad_ops = &g_adcops,
.ad_priv= &g_adcpriv,
.ad_ops = &g_adcops,
.ad_priv= &g_adcpriv,
};
/****************************************************************************
@ -166,141 +166,155 @@ static struct adc_dev_s g_adcdev =
static uint8_t getspsreg(uint16_t sps)
{
static const unsigned short sps_tab[]=
static const unsigned short sps_tab[]=
{
3,7,12,20,27,40,55,80,300,750,1500,3000,5000,10000,20000,65535,
};
static const unsigned char sps_reg[]=
{
0x03,0x13,0x23,0x33,0x43,0x53,0x63,0x72,0x82,0x92,0xa1,0xb0,0xc0,0xd0,0xe0,0xf0,
};
int i;
for (i=0; i<16; i++)
{
3,7,12,20,27,40,55,80,300,750,1500,3000,5000,10000,20000,65535,
};
static const unsigned char sps_reg[]=
{
0x03,0x13,0x23,0x33,0x43,0x53,0x63,0x72,0x82,0x92,0xa1,0xb0,0xc0,0xd0,0xe0,0xf0,
};
int i;
for (i=0; i<16; i++)
{
if (sps<sps_tab[i])
break;
if (sps<sps_tab[i])
{
break;
}
}
return sps_reg[i];
return sps_reg[i];
}
/****************************************************************************
* ad_private Functions
****************************************************************************/
/* Reset the ADC device. Called early to initialize the hardware. This
* is called, before ao_setup() and on error conditions.
*/
* is called, before ao_setup() and on error conditions.
*/
static void adc_reset(FAR struct adc_dev_s *dev)
{
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
FAR struct spi_dev_s *spi = priv->spi;
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
FAR struct spi_dev_s *spi = priv->spi;
SPI_SETMODE(spi, SPIDEV_MODE1);
SPI_SETBITS(spi, 8);
SPI_SETFREQUENCY(spi, CONFIG_ADS1255_FREQUENCY);
usleep(1000);
SPI_SELECT(spi, priv->devno, true);
SPI_SEND(spi,ADS125X_WREG+0x03); //WRITE SPS REG
SPI_SEND(spi,0x00); //count=1
SPI_SEND(spi,0x63);
SPI_SELECT(spi, priv->devno, false);
SPI_SETMODE(spi, SPIDEV_MODE1);
SPI_SETBITS(spi, 8);
SPI_SETFREQUENCY(spi, CONFIG_ADS1255_FREQUENCY);
usleep(1000);
SPI_SELECT(spi, priv->devno, true);
SPI_SEND(spi,ADS125X_WREG+0x03); /* WRITE SPS REG */
SPI_SEND(spi,0x00); /* count=1 */
SPI_SEND(spi,0x63);
SPI_SELECT(spi, priv->devno, false);
}
/* Configure the ADC. This method is called the first time that the ADC
* device is opened. This will occur when the port is first opened.
* This setup includes configuring and attaching ADC interrupts. Interrupts
* are all disabled upon return.
*/
* device is opened. This will occur when the port is first opened.
* This setup includes configuring and attaching ADC interrupts. Interrupts
* are all disabled upon return.
*/
static int adc_setup(FAR struct adc_dev_s *dev)
{
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
FAR struct spi_dev_s *spi = priv->spi;
int ret = irq_attach(priv->irq, adc_interrupt);
if (ret == OK)
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
FAR struct spi_dev_s *spi = priv->spi;
int ret = irq_attach(priv->irq, adc_interrupt);
if (ret == OK)
{
SPI_SELECT(spi, priv->devno, true);
SPI_SEND(spi,ADS125X_WREG); //WRITE REG from 0
SPI_SEND(spi,0x03); //count=4+1
if (priv->buf)
SPI_SEND(spi,ADS125X_BUFON); //REG0 STATUS BUFFER ON
else
SPI_SEND(spi,ADS125X_BUFOFF);
SPI_SEND(spi,priv->mux[0]);
SPI_SEND(spi,priv->pga); //REG2 ADCON PGA=2
SPI_SEND(spi,getspsreg(priv->sps));
usleep(1000);
SPI_SEND(spi,ADS125X_SELFCAL);
SPI_SELECT(spi, priv->devno, false);
up_enable_irq(priv->irq);
SPI_SELECT(spi, priv->devno, true);
SPI_SEND(spi,ADS125X_WREG); /* WRITE REG from 0 */
SPI_SEND(spi,0x03); /* count=4+1 */
if (priv->buf)
{
SPI_SEND(spi,ADS125X_BUFON); /* REG0 STATUS BUFFER ON */
}
else
{
SPI_SEND(spi,ADS125X_BUFOFF);
}
SPI_SEND(spi,priv->mux[0]);
SPI_SEND(spi,priv->pga); /* REG2 ADCON PGA=2 */
SPI_SEND(spi,getspsreg(priv->sps));
usleep(1000);
SPI_SEND(spi,ADS125X_SELFCAL);
SPI_SELECT(spi, priv->devno, false);
up_enable_irq(priv->irq);
}
return ret;
return ret;
}
/* Disable the ADC. This method is called when the ADC device is closed.
* This method reverses the operation the setup method.
*/
* This method reverses the operation the setup method.
*/
static void adc_shutdown(FAR struct adc_dev_s *dev)
{
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
up_disable_irq(priv->irq);
irq_detach(priv->irq);
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
up_disable_irq(priv->irq);
irq_detach(priv->irq);
}
/* Call to enable or disable RX interrupts */
static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
{
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
if (enable)
up_enable_irq(priv->irq);
else
up_disable_irq(priv->irq);
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
if (enable)
{
up_enable_irq(priv->irq);
}
else
{
up_disable_irq(priv->irq);
}
}
/* All ioctl calls will be routed through this method */
static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
{
dbg("Fix me:Not Implemented\n");
return 0;
dbg("Fix me:Not Implemented\n");
return 0;
}
static int adc_interrupt(int irq, void *context)
{
uint32_t regval;
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
FAR struct spi_dev_s *spi = priv->spi;
unsigned char buf[4];
unsigned char ch;
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
FAR struct spi_dev_s *spi = priv->spi;
unsigned char buf[4];
unsigned char ch;
SPI_SELECT(spi, priv->devno, true);
SPI_SEND(spi,ADS125X_RDATA);
up_udelay(10);
buf[3]=SPI_SEND(spi,0xff);
buf[2]=SPI_SEND(spi,0xff);
buf[1]=SPI_SEND(spi,0xff);
buf[0]=0;
SPI_SELECT(spi, priv->devno, true);
SPI_SEND(spi,ADS125X_RDATA);
up_udelay(10);
buf[3]=SPI_SEND(spi,0xff);
buf[2]=SPI_SEND(spi,0xff);
buf[1]=SPI_SEND(spi,0xff);
buf[0]=0;
priv->channel++;
ch = priv->mux[priv->channel];
if ( ch == 0 )
priv->channel++;
ch = priv->mux[priv->channel];
if ( ch == 0 )
{
priv->channel=0;
ch = priv->mux[0];
priv->channel=0;
ch = priv->mux[0];
}
SPI_SEND(spi,ADS125X_WREG+0x01);
SPI_SEND(spi,0x00);
SPI_SEND(spi,ch);
SPI_SEND(spi,ADS125X_SYNC);
up_udelay(2);
SPI_SEND(spi,ADS125X_WAKEUP);
SPI_SELECT(spi, priv->devno, false);
SPI_SEND(spi,ADS125X_WREG+0x01);
SPI_SEND(spi,0x00);
SPI_SEND(spi,ch);
SPI_SEND(spi,ADS125X_SYNC);
up_udelay(2);
SPI_SEND(spi,ADS125X_WAKEUP);
SPI_SELECT(spi, priv->devno, false);
adc_receive(&g_adcdev,priv->channel,*(int32_t *)buf);
return OK;
adc_receive(&g_adcdev,priv->channel,*(int32_t *)buf);
return OK;
}
/****************************************************************************
@ -323,13 +337,13 @@ static int adc_interrupt(int irq, void *context)
FAR struct adc_dev_s *up_ads1255initialize(FAR struct spi_dev_s *spi, unsigned int devno)
{
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
/* Driver state data */
/* Driver state data */
priv->spi = spi;
priv->devno = devno;
return &g_adcdev;
priv->spi = spi;
priv->devno = devno;
return &g_adcdev;
}
#endif

108
drivers/analog/dac.c
View file

@ -68,7 +68,6 @@
#define HALF_SECOND_MSEC 500
#define HALF_SECOND_USEC 500000L
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
@ -155,11 +154,14 @@ static int dac_open(FAR struct file *filep)
dev->ad_ocount = tmp;
}
irqrestore(flags);
}
}
sem_post(&dev->ad_closesem);
}
return ret;
}
@ -220,6 +222,7 @@ static int dac_close(FAR struct file *filep)
sem_post(&dev->ad_closesem);
}
}
return ret;
}
@ -260,6 +263,7 @@ static int dac_xmit(FAR struct dac_dev_s *dev)
enable = (ret == OK ? true : false);
}
dev->ad_ops->ao_txint(dev, enable);
return ret;
}
@ -274,7 +278,7 @@ static ssize_t dac_write(FAR struct file *filep, FAR const char *buffer, size_t
FAR struct dac_dev_s *dev = inode->i_private;
FAR struct dac_fifo_s *fifo = &dev->ad_xmit;
FAR struct dac_msg_s *msg;
bool empty = false;
bool empty;
ssize_t nsent = 0;
irqstate_t flags;
int nexttail;
@ -295,18 +299,30 @@ static ssize_t dac_write(FAR struct file *filep, FAR const char *buffer, size_t
* shorter than the minimum.
*/
if (buflen % 5 ==0 )
msglen=5;
else if (buflen % 4 ==0 )
msglen=4;
else if (buflen % 3 ==0 )
msglen=3;
else if (buflen % 2 ==0 )
msglen=2;
if (buflen % 5 == 0 )
{
msglen = 5;
}
else if (buflen % 4 == 0)
{
msglen = 4;
}
else if (buflen % 3 == 0)
{
msglen = 3;
}
else if (buflen % 2 == 0)
{
msglen = 2;
}
else if (buflen == 1)
msglen=1;
{
msglen = 1;
}
else
msglen=5;
{
msglen = 5;
}
while ((buflen - nsent) >= msglen )
{
@ -336,6 +352,7 @@ static ssize_t dac_write(FAR struct file *filep, FAR const char *buffer, size_t
{
ret = nsent;
}
goto return_with_irqdisabled;
}
@ -370,35 +387,36 @@ static ssize_t dac_write(FAR struct file *filep, FAR const char *buffer, size_t
* CAN message at the tail of the FIFO.
*/
if (msglen==5)
{
msg = (FAR struct dac_msg_s *)&buffer[nsent];
memcpy(&fifo->af_buffer[fifo->af_tail], msg, msglen);
}
else if(msglen == 4)
{
fifo->af_buffer[fifo->af_tail].am_channel=buffer[nsent];
fifo->af_buffer[fifo->af_tail].am_data=*(uint32_t *)&buffer[nsent];
fifo->af_buffer[fifo->af_tail].am_data&=0xffffff00;
}
else if(msglen == 3)
{
fifo->af_buffer[fifo->af_tail].am_channel=buffer[nsent];
fifo->af_buffer[fifo->af_tail].am_data=(*(uint16_t *)&buffer[nsent+1]);
fifo->af_buffer[fifo->af_tail].am_data<<=16;
}
else if(msglen == 2)
{
fifo->af_buffer[fifo->af_tail].am_channel=0;
fifo->af_buffer[fifo->af_tail].am_data=(*(uint16_t *)&buffer[nsent]);
fifo->af_buffer[fifo->af_tail].am_data<<=16;
}
else if(msglen == 1)
{
fifo->af_buffer[fifo->af_tail].am_channel=0;
fifo->af_buffer[fifo->af_tail].am_data=buffer[nsent];
fifo->af_buffer[fifo->af_tail].am_data<<=24;
}
if (msglen == 5)
{
msg = (FAR struct dac_msg_s *)&buffer[nsent];
memcpy(&fifo->af_buffer[fifo->af_tail], msg, msglen);
}
else if (msglen == 4)
{
fifo->af_buffer[fifo->af_tail].am_channel=buffer[nsent];
fifo->af_buffer[fifo->af_tail].am_data=*(uint32_t *)&buffer[nsent];
fifo->af_buffer[fifo->af_tail].am_data&=0xffffff00;
}
else if(msglen == 3)
{
fifo->af_buffer[fifo->af_tail].am_channel=buffer[nsent];
fifo->af_buffer[fifo->af_tail].am_data=(*(uint16_t *)&buffer[nsent+1]);
fifo->af_buffer[fifo->af_tail].am_data<<=16;
}
else if(msglen == 2)
{
fifo->af_buffer[fifo->af_tail].am_channel=0;
fifo->af_buffer[fifo->af_tail].am_data=(*(uint16_t *)&buffer[nsent]);
fifo->af_buffer[fifo->af_tail].am_data<<=16;
}
else if(msglen == 1)
{
fifo->af_buffer[fifo->af_tail].am_channel=0;
fifo->af_buffer[fifo->af_tail].am_data=buffer[nsent];
fifo->af_buffer[fifo->af_tail].am_data<<=24;
}
/* Increment the tail of the circular buffer */
fifo->af_tail = nexttail;
@ -432,9 +450,9 @@ return_with_irqdisabled:
static int dac_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
FAR struct inode *inode = filep->f_inode;
FAR struct dac_dev_s *dev = inode->i_private;
int ret = OK;
FAR struct inode *inode = filep->f_inode;
FAR struct dac_dev_s *dev = inode->i_private;
int ret;
ret = dev->ad_ops->ao_ioctl(dev, cmd, arg);
return ret;
@ -480,6 +498,7 @@ int dac_txdone(FAR struct dac_dev_s *dev)
ret = sem_post(&dev->ad_xmit.af_sem);
}
}
return ret;
}
@ -496,4 +515,3 @@ int dac_register(FAR const char *path, FAR struct dac_dev_s *dev)
return register_driver(path, &dac_fops, 0555, dev);
}

9
drivers/audio/vs1053.c
View file

@ -1255,9 +1255,12 @@ static void *vs1053_workerthread(pthread_addr_t pvarg)
{
FAR struct vs1053_struct_s *dev = (struct vs1053_struct_s *) pvarg;
struct audio_msg_s msg;
FAR struct ap_buffer_s *pBuf;
int size, prio;
FAR struct ap_buffer_s *pBuf;
int size;
int prio;
#ifndef CONFIG_AUDIO_EXCLUDE_STOP
uint16_t reg;
#endif
uint8_t timeout;
auddbg("Entry\n");
@ -1454,7 +1457,7 @@ static int vs1053_start(FAR struct audio_lowerhalf_s *lower)
/* Pop the first enqueued buffer */
if ((ret = (sem_wait(&dev->apbq_sem)) == OK))
if ((ret = sem_wait(&dev->apbq_sem)) == OK)
{
dev->pBuf = (FAR struct ap_buffer_s *) dq_remfirst(&dev->apbq);
apb_reference(dev->pBuf); /* Add our buffer reference */

6
drivers/input/ads7843e.c
View file

@ -1080,10 +1080,10 @@ static int ads7843e_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
static int ads7843e_poll(FAR struct file *filep, FAR struct pollfd *fds,
bool setup)
{
FAR struct inode *inode;
FAR struct inode *inode;
FAR struct ads7843e_dev_s *priv;
int ret = OK;
int i;
int ret;
int i;
ivdbg("setup: %d\n", (int)setup);
DEBUGASSERT(filep && fds);

8
drivers/input/max11802.c
View file

@ -1061,12 +1061,10 @@ static int max11802_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
static int max11802_poll(FAR struct file *filep, FAR struct pollfd *fds,
bool setup)
{
FAR struct inode *inode;
FAR struct inode *inode;
FAR struct max11802_dev_s *priv;
pollevent_t eventset;
int ndx;
int ret = OK;
int i;
int ret;
int i;
ivdbg("setup: %d\n", (int)setup);
DEBUGASSERT(filep && fds);

3
drivers/input/stmpe811_gpio.c
View file

@ -381,7 +381,7 @@ int stmpe811_gpioattach(STMPE811_HANDLE handle, uint8_t pinconfig,
{
/* Enable interrupts for this GPIO */
regval &= ~GPIO_PIN(pin);
regval |= GPIO_PIN(pin);
}
else
{
@ -389,6 +389,7 @@ int stmpe811_gpioattach(STMPE811_HANDLE handle, uint8_t pinconfig,
regval &= ~GPIO_PIN(pin);
}
stmpe811_putreg8(priv, STMPE811_GPIO_EN, regval);
sem_post(&priv->exclsem);

4
drivers/input/stmpe811_tsc.c
View file

@ -769,7 +769,7 @@ static void stmpe811_timeout(int argc, uint32_t arg1, ...)
/* Are we still stuck in the pen down state? */
if (priv->sample.contact == CONTACT_MOVE ||
if (priv->sample.contact == CONTACT_DOWN ||
priv->sample.contact == CONTACT_MOVE)
{
/* Yes... is the worker thread available? If not, then apparently
@ -1127,7 +1127,7 @@ void stmpe811_tscworker(FAR struct stmpe811_dev_s *priv, uint8_t intsta)
*/
ignored:
if (priv->sample.contact == CONTACT_MOVE ||
if (priv->sample.contact == CONTACT_DOWN ||
priv->sample.contact == CONTACT_MOVE)
{
(void)wd_start(priv->wdog, STMPE811_PENUP_TICKS, stmpe811_timeout,

3
drivers/lcd/st7567.c
View file

@ -455,12 +455,11 @@ static int st7567_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buff
FAR struct st7567_dev_s *priv = &g_st7567dev;
FAR uint8_t *fbptr;
FAR uint8_t *ptr;
uint8_t devcol;
uint8_t fbmask;
uint8_t page;
uint8_t usrmask;
uint8_t i;
int pixlen;
int pixlen;
gvdbg("row: %d col: %d npixels: %d\n", row, col, npixels);
DEBUGASSERT(buffer);

2
drivers/mtd/mtd_config.c
View file

@ -905,7 +905,7 @@ static int mtdconfig_open(FAR struct file *filep)
{
FAR struct inode *inode = filep->f_inode;
FAR struct mtdconfig_struct_s *dev = inode->i_private;
int ret = OK;
int ret;
/* Get exclusive access to the device */

2
drivers/net/dm90x0.c
View file

@ -908,7 +908,7 @@ static void dm9x_receive(struct dm9x_driver_s *dm9x)
mdrah = getreg(DM9X_MDRAH);
mdral = getreg(DM9X_MDRAL);
getreg(DM9X_MRCMDX); /* Dummy read */
getreg(DM9X_MRCMDX); /* Dummy read */
rxbyte = (uint8_t)DM9X_DATA; /* Get the most up-to-date data */
/* Packet ready for receive check */

1161
drivers/net/e1000.c
View file

File diff suppressed because it is too large Load diff

2
drivers/power/battery.c
View file

@ -152,7 +152,7 @@ static int bat_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
FAR struct inode *inode = filep->f_inode;
FAR struct battery_dev_s *dev = inode->i_private;
int ret = -EINVAL;
int ret;
/* Inforce mutually exclusive access to the battery driver */

131
drivers/sercomm/console.c
View file

@ -50,10 +50,12 @@
#include <nuttx/sercomm/sercomm.h>
/* stubs to make serial driver happy */
void sercomm_recvchars(void *a) { }
void sercomm_xmitchars(void *a) { }
/* Stubs to make memory allocator happy */
void cons_puts(void *foo){}
void delay_ms(int ms){}
@ -61,7 +63,7 @@ void delay_ms(int ms){}
* Fileops Prototypes and Structures
************************************************************************************/
typedef FAR struct file file_t;
typedef FAR struct file file_t;
static ssize_t sc_console_read(file_t *filep, FAR char *buffer, size_t buflen);
static ssize_t sc_console_write(file_t *filep, FAR const char *buffer, size_t buflen);
@ -72,26 +74,28 @@ static int sc_console_poll(file_t *filep, FAR struct pollfd *fds, bool setup
static const struct file_operations g_sercom_console_ops =
{
0, /* open, always opened */
0, /* close, stays open */
sc_console_read, /* read */
sc_console_write, /* write */
0, /* seek, not supported */
sc_console_ioctl, /* ioctl */
0, /* open, always opened */
0, /* close, stays open */
sc_console_read, /* read */
sc_console_write, /* write */
0, /* seek, not supported */
sc_console_ioctl, /* ioctl */
#ifndef CONFIG_DISABLE_POLL
sc_console_poll /* poll */
sc_console_poll /* poll */
#endif
};
static FAR uart_dev_t *readdev = NULL;
static struct msgb *recvmsg = NULL;
/****************************************************************************
* Helper functions
****************************************************************************/
static FAR uart_dev_t *readdev = NULL;
static struct msgb *recvmsg = NULL;
static void recv_cb(uint8_t dlci, struct msgb *msg)
{
sem_post(&readdev->recvsem);
recvmsg = msg;
sem_post(&readdev->recvsem);
recvmsg = msg;
}
/****************************************************************************
@ -101,58 +105,71 @@ static void recv_cb(uint8_t dlci, struct msgb *msg)
/* XXX: recvmsg is overwritten when multiple msg arrive! */
static ssize_t sc_console_read(file_t *filep, FAR char *buffer, size_t buflen)
{
size_t len;
struct msgb *tmp;
size_t len;
struct msgb *tmp;
/* Wait until data is received */
while(recvmsg == NULL) {
sem_wait(&readdev->recvsem);
}
/* Wait until data is received */
len = recvmsg->len > buflen ? buflen : recvmsg->len;
memcpy(buffer, msgb_get(recvmsg, len), len);
while (recvmsg == NULL)
{
sem_wait(&readdev->recvsem);
}
if(recvmsg->len == 0) {
/* prevent inconsistent msg by first invalidating it, then free it */
tmp = recvmsg;
recvmsg = NULL;
msgb_free(tmp);
}
len = recvmsg->len > buflen ? buflen : recvmsg->len;
memcpy(buffer, msgb_get(recvmsg, len), len);
return len;
if (recvmsg->len == 0)
{
/* prevent inconsistent msg by first invalidating it, then free it */
tmp = recvmsg;
recvmsg = NULL;
msgb_free(tmp);
}
return len;
}
/* XXX: redirect to old Osmocom-BB comm/sercomm_cons.c -> 2 buffers */
extern int sercomm_puts(const char *s);
static ssize_t sc_console_write(file_t *filep, FAR const char *buffer, size_t buflen)
{
int i, cnt;
char dstbuf[32];
char dstbuf[32];
int cnt;
if (buflen >= 31)
cnt = 31;
else
cnt = buflen;
if (buflen >= 31)
{
cnt = 31;
}
else
{
cnt = buflen;
}
memcpy(dstbuf, buffer, cnt);
dstbuf[cnt] = '\0';
memcpy(dstbuf, buffer, cnt);
dstbuf[cnt] = '\0';
/* print part of our buffer */
sercomm_puts(dstbuf);
/* print part of our buffer */
/* wait a little bit to get data transfered */
up_mdelay(1);
sercomm_puts(dstbuf);
return cnt;
/* wait a little bit to get data transfered */
up_mdelay(1);
return cnt;
}
/* Forward ioctl to uart driver */
static int sc_console_ioctl(struct file *filep, int cmd, unsigned long arg)
{
FAR struct inode *inode = filep->f_inode;
FAR uart_dev_t *dev = inode->i_private;
FAR struct inode *inode = filep->f_inode;
FAR uart_dev_t *dev = inode->i_private;
return dev->ops->ioctl(filep, cmd, arg);
return dev->ops->ioctl(filep, cmd, arg);
}
/************************************************************************************
@ -160,23 +177,25 @@ static int sc_console_ioctl(struct file *filep, int cmd, unsigned long arg)
************************************************************************************/
/* Use sercomm on uart driver, register console driver */
int sercomm_register(FAR const char *path, FAR uart_dev_t *dev)
{
/* XXX: initialize MODEMUART to be used for sercomm*/
uart_init(SERCOMM_UART_NR, 1);
uart_baudrate(SERCOMM_UART_NR, UART_115200);
readdev = dev;
sercomm_register_rx_cb(SC_DLCI_LOADER, &recv_cb);
/* XXX: initialize MODEMUART to be used for sercomm*/
sem_init(&dev->xmit.sem, 0, 1);
sem_init(&dev->recv.sem, 0, 1);
sem_init(&dev->closesem, 0, 1);
sem_init(&dev->xmitsem, 0, 0);
sem_init(&dev->recvsem, 0, 0);
uart_init(SERCOMM_UART_NR, 1);
uart_baudrate(SERCOMM_UART_NR, UART_115200);
readdev = dev;
sercomm_register_rx_cb(SC_DLCI_LOADER, &recv_cb);
sem_init(&dev->xmit.sem, 0, 1);
sem_init(&dev->recv.sem, 0, 1);
sem_init(&dev->closesem, 0, 1);
sem_init(&dev->xmitsem, 0, 0);
sem_init(&dev->recvsem, 0, 0);
#ifndef CONFIG_DISABLE_POLL
sem_init(&dev->pollsem, 0, 1);
sem_init(&dev->pollsem, 0, 1);
#endif
dbg("Registering %s\n", path);
return register_driver(path, &g_sercom_console_ops, 0666, NULL);
dbg("Registering %s\n", path);
return register_driver(path, &g_sercom_console_ops, 0666, NULL);
}

758
drivers/sercomm/uart.c
View file

@ -51,419 +51,563 @@
#include "uart.h"
#define BASE_ADDR_UART_MODEM 0xffff5000
#define OFFSET_IRDA 0x800
#define BASE_ADDR_UART_MODEM 0xffff5000
#define OFFSET_IRDA 0x800
#define UART_REG(n,m) (BASE_ADDR_UART_MODEM + ((n)*OFFSET_IRDA)+(m))
#define UART_REG(n,m) (BASE_ADDR_UART_MODEM + ((n)*OFFSET_IRDA)+(m))
#define LCR7BIT 0x80
#define LCRBFBIT 0x40
#define MCR6BIT 0x20
#define REG_OFFS(m) ((m) & ~(LCR7BIT|LCRBFBIT|MCR6BIT))
#define LCR7BIT 0x80
#define LCRBFBIT 0x40
#define MCR6BIT 0x20
#define REG_OFFS(m) ((m) & ~(LCR7BIT|LCRBFBIT|MCR6BIT))
/* read access LCR[7] = 0 */
enum uart_reg {
RHR = 0,
IER = 1,
IIR = 2,
LCR = 3,
MCR = 4,
LSR = 5,
MSR = 6,
SPR = 7,
MDR1 = 8,
DMR2 = 9,
SFLSR = 0x0a,
RESUME = 0x0b,
SFREGL = 0x0c,
SFREGH = 0x0d,
BLR = 0x0e,
ACREG = 0x0f,
SCR = 0x10,
SSR = 0x11,
EBLR = 0x12,
/* read access LCR[7] = 1 */
DLL = RHR | LCR7BIT,
DLH = IER | LCR7BIT,
DIV1_6 = ACREG | LCR7BIT,
/* read/write access LCR[7:0] = 0xbf */
EFR = IIR | LCRBFBIT,
XON1 = MCR | LCRBFBIT,
XON2 = LSR | LCRBFBIT,
XOFF1 = MSR | LCRBFBIT,
XOFF2 = SPR | LCRBFBIT,
/* read/write access if EFR[4] = 1 and MCR[6] = 1 */
TCR = MSR | MCR6BIT,
TLR = SPR | MCR6BIT,
enum uart_reg
{
RHR = 0,
IER = 1,
IIR = 2,
LCR = 3,
MCR = 4,
LSR = 5,
MSR = 6,
SPR = 7,
MDR1 = 8,
DMR2 = 9,
SFLSR = 0x0a,
RESUME = 0x0b,
SFREGL = 0x0c,
SFREGH = 0x0d,
BLR = 0x0e,
ACREG = 0x0f,
SCR = 0x10,
SSR = 0x11,
EBLR = 0x12,
/* read access LCR[7] = 1 */
DLL = RHR | LCR7BIT,
DLH = IER | LCR7BIT,
DIV1_6 = ACREG | LCR7BIT,
/* read/write access LCR[7:0] = 0xbf */
EFR = IIR | LCRBFBIT,
XON1 = MCR | LCRBFBIT,
XON2 = LSR | LCRBFBIT,
XOFF1 = MSR | LCRBFBIT,
XOFF2 = SPR | LCRBFBIT,
/* read/write access if EFR[4] = 1 and MCR[6] = 1 */
TCR = MSR | MCR6BIT,
TLR = SPR | MCR6BIT,
};
/* write access LCR[7] = 0 */
#define THR RHR
#define FCR IIR /* only if EFR[4] = 1 */
#define TXFLL SFLSR
#define TXFLH RESUME
#define RXFLL SFREGL
#define RXFLH SFREGH
enum fcr_bits {
FIFO_EN = (1 << 0),
RX_FIFO_CLEAR = (1 << 1),
TX_FIFO_CLEAR = (1 << 2),
DMA_MODE = (1 << 3),
};
#define TX_FIFO_TRIG_SHIFT 4
#define RX_FIFO_TRIG_SHIFT 6
#define THR RHR
#define FCR IIR /* only if EFR[4] = 1 */
#define TXFLL SFLSR
#define TXFLH RESUME
#define RXFLL SFREGL
#define RXFLH SFREGH
enum iir_bits {
IIR_INT_PENDING = 0x01,
IIR_INT_TYPE = 0x3E,
IIR_INT_TYPE_RX_STATUS_ERROR = 0x06,
IIR_INT_TYPE_RX_TIMEOUT = 0x0C,
IIR_INT_TYPE_RHR = 0x04,
IIR_INT_TYPE_THR = 0x02,
IIR_INT_TYPE_MSR = 0x00,
IIR_INT_TYPE_XOFF = 0x10,
IIR_INT_TYPE_FLOW = 0x20,
IIR_FCR0_MIRROR = 0xC0,
enum fcr_bits
{
FIFO_EN = (1 << 0),
RX_FIFO_CLEAR = (1 << 1),
TX_FIFO_CLEAR = (1 << 2),
DMA_MODE = (1 << 3),
};
#define UART_REG_UIR 0xffff6000
#define TX_FIFO_TRIG_SHIFT 4
#define RX_FIFO_TRIG_SHIFT 6
enum iir_bits
{
IIR_INT_PENDING = 0x01,
IIR_INT_TYPE = 0x3E,
IIR_INT_TYPE_RX_STATUS_ERROR = 0x06,
IIR_INT_TYPE_RX_TIMEOUT = 0x0C,
IIR_INT_TYPE_RHR = 0x04,
IIR_INT_TYPE_THR = 0x02,
IIR_INT_TYPE_MSR = 0x00,
IIR_INT_TYPE_XOFF = 0x10,
IIR_INT_TYPE_FLOW = 0x20,
IIR_FCR0_MIRROR = 0xC0,
};
#define UART_REG_UIR 0xffff6000
/* enable or disable the divisor latch for access to DLL, DLH */
static void uart_set_lcr7bit(int uart, int on)
{
uint8_t reg;
uint8_t reg;
reg = readb(UART_REG(uart, LCR));
if (on)
reg |= (1 << 7);
else
reg &= ~(1 << 7);
writeb(reg, UART_REG(uart, LCR));
reg = readb(UART_REG(uart, LCR));
if (on)
{
reg |= (1 << 7);
}
else
{
reg &= ~(1 << 7);
}
writeb(reg, UART_REG(uart, LCR));
}
static uint8_t old_lcr;
static void uart_set_lcr_bf(int uart, int on)
{
if (on) {
old_lcr = readb(UART_REG(uart, LCR));
writeb(0xBF, UART_REG(uart, LCR));
} else {
writeb(old_lcr, UART_REG(uart, LCR));
}
if (on)
{
old_lcr = readb(UART_REG(uart, LCR));
writeb(0xBF, UART_REG(uart, LCR));
}
else
{
writeb(old_lcr, UART_REG(uart, LCR));
}
}
/* Enable or disable the TCR_TLR latch bit in MCR[6] */
static void uart_set_mcr6bit(int uart, int on)
{
uint8_t mcr;
/* we assume EFR[4] is always set to 1 */
mcr = readb(UART_REG(uart, MCR));
if (on)
mcr |= (1 << 6);
else
mcr &= ~(1 << 6);
writeb(mcr, UART_REG(uart, MCR));
uint8_t mcr;
/* we assume EFR[4] is always set to 1 */
mcr = readb(UART_REG(uart, MCR));
if (on)
{
mcr |= (1 << 6);
}
else
{
mcr &= ~(1 << 6);
}
writeb(mcr, UART_REG(uart, MCR));
}
static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val)
{
if (reg & LCRBFBIT)
uart_set_lcr_bf(uart, 1);
else if (reg & LCR7BIT)
uart_set_lcr7bit(uart, 1);
else if (reg & MCR6BIT)
uart_set_mcr6bit(uart, 1);
if (reg & LCRBFBIT)
{
uart_set_lcr_bf(uart, 1);
}
else if (reg & LCR7BIT)
{
uart_set_lcr7bit(uart, 1);
}
else if (reg & MCR6BIT)
{
uart_set_mcr6bit(uart, 1);
}
writeb(val, UART_REG(uart, REG_OFFS(reg)));
writeb(val, UART_REG(uart, REG_OFFS(reg)));
if (reg & LCRBFBIT)
uart_set_lcr_bf(uart, 0);
else if (reg & LCR7BIT)
uart_set_lcr7bit(uart, 0);
else if (reg & MCR6BIT)
uart_set_mcr6bit(uart, 0);
if (reg & LCRBFBIT)
{
uart_set_lcr_bf(uart, 0);
}
else if (reg & LCR7BIT)
{
uart_set_lcr7bit(uart, 0);
}
else if (reg & MCR6BIT)
{
uart_set_mcr6bit(uart, 0);
}
}
/* read from a UART register, applying any required latch bits */
static uint8_t uart_reg_read(int uart, enum uart_reg reg)
{
uint8_t ret;
uint8_t ret;
if (reg & LCRBFBIT)
uart_set_lcr_bf(uart, 1);
else if (reg & LCR7BIT)
uart_set_lcr7bit(uart, 1);
else if (reg & MCR6BIT)
uart_set_mcr6bit(uart, 1);
if (reg & LCRBFBIT)
{
uart_set_lcr_bf(uart, 1);
}
else if (reg & LCR7BIT)
{
uart_set_lcr7bit(uart, 1);
}
else if (reg & MCR6BIT)
{
uart_set_mcr6bit(uart, 1);
}
ret = readb(UART_REG(uart, REG_OFFS(reg)));
ret = readb(UART_REG(uart, REG_OFFS(reg)));
if (reg & LCRBFBIT)
uart_set_lcr_bf(uart, 0);
else if (reg & LCR7BIT)
uart_set_lcr7bit(uart, 0);
else if (reg & MCR6BIT)
uart_set_mcr6bit(uart, 0);
if (reg & LCRBFBIT)
{
uart_set_lcr_bf(uart, 0);
}
else if (reg & LCR7BIT)
{
uart_set_lcr7bit(uart, 0);
}
else if (reg & MCR6BIT)
{
uart_set_mcr6bit(uart, 0);
}
return ret;
return ret;
}
#if 0
static void uart_irq_handler_cons(__unused enum irq_nr irqnr)
{
const uint8_t uart = CONS_UART_NR;
uint8_t iir;
const uint8_t uart = CONS_UART_NR;
uint8_t iir;
//uart_putchar_nb(uart, 'U');
//uart_putchar_nb(uart, 'U');
iir = uart_reg_read(uart, IIR);
if (iir & IIR_INT_PENDING)
return;
iir = uart_reg_read(uart, IIR);
if (iir & IIR_INT_PENDING)
{
return;
}
switch (iir & IIR_INT_TYPE) {
case IIR_INT_TYPE_RHR:
break;
case IIR_INT_TYPE_THR:
if (cons_rb_flush() == 1) {
/* everything was flushed, disable THR IRQ */
uint8_t ier = uart_reg_read(uart, IER);
ier &= ~(1 << 1);
uart_reg_write(uart, IER, ier);
}
break;
case IIR_INT_TYPE_MSR:
break;
case IIR_INT_TYPE_RX_STATUS_ERROR:
break;
case IIR_INT_TYPE_RX_TIMEOUT:
break;
case IIR_INT_TYPE_XOFF:
break;
}
switch (iir & IIR_INT_TYPE)
{
case IIR_INT_TYPE_RHR:
break;
case IIR_INT_TYPE_THR:
if (cons_rb_flush() == 1)
{
/* everything was flushed, disable THR IRQ */
uint8_t ier = uart_reg_read(uart, IER);
ier &= ~(1 << 1);
uart_reg_write(uart, IER, ier);
}
break;
case IIR_INT_TYPE_MSR:
break;
case IIR_INT_TYPE_RX_STATUS_ERROR:
break;
case IIR_INT_TYPE_RX_TIMEOUT:
break;
case IIR_INT_TYPE_XOFF:
break;
}
}
#endif
static void uart_irq_handler_sercomm(__unused enum irq_nr irqnr, __unused void *context)
{
const uint8_t uart = SERCOMM_UART_NR;
uint8_t iir, ch;
const uint8_t uart = SERCOMM_UART_NR;
uint8_t iir, ch;
//uart_putchar_nb(uart, 'U');
//uart_putchar_nb(uart, 'U');
iir = uart_reg_read(uart, IIR);
if (iir & IIR_INT_PENDING)
return;
iir = uart_reg_read(uart, IIR);
if (iir & IIR_INT_PENDING)
{
return;
}
switch (iir & IIR_INT_TYPE) {
case IIR_INT_TYPE_RX_TIMEOUT:
case IIR_INT_TYPE_RHR:
/* as long as we have rx data available */
while (uart_getchar_nb(uart, &ch)) {
if (sercomm_drv_rx_char(ch) < 0) {
/* sercomm cannot receive more data right now */
uart_irq_enable(uart, UART_IRQ_RX_CHAR, 0);
}
}
break;
case IIR_INT_TYPE_THR:
/* as long as we have space in the FIFO */
while (!uart_tx_busy(uart)) {
/* get a byte from sercomm */
if (!sercomm_drv_pull(&ch)) {
/* no more bytes in sercomm, stop TX interrupts */
uart_irq_enable(uart, UART_IRQ_TX_EMPTY, 0);
break;
}
/* write the byte into the TX FIFO */
uart_putchar_nb(uart, ch);
}
break;
case IIR_INT_TYPE_MSR:
printf("UART IRQ MSR\n");
break;
case IIR_INT_TYPE_RX_STATUS_ERROR:
printf("UART IRQ RX_SE\n");
break;
case IIR_INT_TYPE_XOFF:
printf("UART IRQXOFF\n");
break;
}
switch (iir & IIR_INT_TYPE)
{
case IIR_INT_TYPE_RX_TIMEOUT:
case IIR_INT_TYPE_RHR:
/* as long as we have rx data available */
while (uart_getchar_nb(uart, &ch))
{
if (sercomm_drv_rx_char(ch) < 0)
{
/* sercomm cannot receive more data right now */
uart_irq_enable(uart, UART_IRQ_RX_CHAR, 0);
}
}
break;
case IIR_INT_TYPE_THR:
/* as long as we have space in the FIFO */
while (!uart_tx_busy(uart))
{
/* get a byte from sercomm */
if (!sercomm_drv_pull(&ch))
{
/* no more bytes in sercomm, stop TX interrupts */
uart_irq_enable(uart, UART_IRQ_TX_EMPTY, 0);
break;
}
/* write the byte into the TX FIFO */
uart_putchar_nb(uart, ch);
}
break;
case IIR_INT_TYPE_MSR:
printf("UART IRQ MSR\n");
break;
case IIR_INT_TYPE_RX_STATUS_ERROR:
printf("UART IRQ RX_SE\n");
break;
case IIR_INT_TYPE_XOFF:
printf("UART IRQXOFF\n");
break;
}
}
static const uint8_t uart2irq[] = {
[0] = IRQ_UART_IRDA,
[1] = IRQ_UART_MODEM,
static const uint8_t uart2irq[] =
{
[0] = IRQ_UART_IRDA,
[1] = IRQ_UART_MODEM,
};
void uart_init(uint8_t uart, uint8_t interrupts)
{
uint8_t irq = uart2irq[uart];
uart_reg_write(uart, IER, 0x00);
if (uart == SERCOMM_UART_NR) {
sercomm_init();
irq_attach(IRQ_UART_MODEM, (xcpt_t)uart_irq_handler_sercomm);
up_enable_irq(IRQ_UART_MODEM);
uart_irq_enable(uart, UART_IRQ_RX_CHAR, 1);
}
#if 0
if (uart == CONS_UART_NR) {
cons_init();
if(interrupts) {
irq_register_handler(irq, &uart_irq_handler_cons);
irq_config(irq, 0, 0, 0xff);
irq_enable(irq);
}
} else {
sercomm_init();
if(interrupts) {
irq_register_handler(irq, &uart_irq_handler_sercomm);
irq_config(irq, 0, 0, 0xff);
irq_enable(irq);
}
uart_irq_enable(uart, UART_IRQ_RX_CHAR, 1);
}
#endif
#if 0
if (uart == 1) {
/* assign UART to MCU and unmask interrupts*/
writeb(UART_REG_UIR, 0x00);
}
uint8_t irq = uart2irq[uart];
#endif
/* if we don't initialize these, we get strange corruptions in the
received data... :-( */
uart_reg_write(uart, MDR1, 0x07); /* turn off UART */
uart_reg_write(uart, XON1, 0x00); /* Xon1/Addr Register */
uart_reg_write(uart, XON2, 0x00); /* Xon2/Addr Register */
uart_reg_write(uart, XOFF1, 0x00); /* Xoff1 Register */
uart_reg_write(uart, XOFF2, 0x00); /* Xoff2 Register */
uart_reg_write(uart, EFR, 0x00); /* Enhanced Features Register */
uart_reg_write(uart, IER, 0x00);
/* select UART mode */
uart_reg_write(uart, MDR1, 0);
/* no XON/XOFF flow control, ENHANCED_EN, no auto-RTS/CTS */
uart_reg_write(uart, EFR, (1 << 4));
/* enable Tx/Rx FIFO, Tx trigger at 56 spaces, Rx trigger at 60 chars */
uart_reg_write(uart, FCR, FIFO_EN | RX_FIFO_CLEAR | TX_FIFO_CLEAR |
(3 << TX_FIFO_TRIG_SHIFT) | (3 << RX_FIFO_TRIG_SHIFT));
if (uart == SERCOMM_UART_NR)
{
sercomm_init();
irq_attach(IRQ_UART_MODEM, (xcpt_t)uart_irq_handler_sercomm);
up_enable_irq(IRQ_UART_MODEM);
uart_irq_enable(uart, UART_IRQ_RX_CHAR, 1);
}
/* THR interrupt only when TX FIFO and TX shift register are empty */
uart_reg_write(uart, SCR, (1 << 0));// | (1 << 3));
#if 0
if (uart == CONS_UART_NR)
{
cons_init();
if(interrupts)
{
irq_register_handler(irq, &uart_irq_handler_cons);
irq_config(irq, 0, 0, 0xff);
irq_enable(irq);
}
}
else
{
sercomm_init();
if(interrupts)
{
irq_register_handler(irq, &uart_irq_handler_sercomm);
irq_config(irq, 0, 0, 0xff);
irq_enable(irq);
}
/* 8 bit, 1 stop bit, no parity, no break */
uart_reg_write(uart, LCR, 0x03);
uart_irq_enable(uart, UART_IRQ_RX_CHAR, 1);
}
#endif
#if 0
if (uart == 1)
{
/* assign UART to MCU and unmask interrupts*/
uart_set_lcr7bit(uart, 0);
writeb(UART_REG_UIR, 0x00);
}
#endif
/* if we don't initialize these, we get strange corruptions in the
* received data... :-(
*/
uart_reg_write(uart, MDR1, 0x07); /* turn off UART */
uart_reg_write(uart, XON1, 0x00); /* Xon1/Addr Register */
uart_reg_write(uart, XON2, 0x00); /* Xon2/Addr Register */
uart_reg_write(uart, XOFF1, 0x00); /* Xoff1 Register */
uart_reg_write(uart, XOFF2, 0x00); /* Xoff2 Register */
uart_reg_write(uart, EFR, 0x00); /* Enhanced Features Register */
/* select UART mode */
uart_reg_write(uart, MDR1, 0);
/* no XON/XOFF flow control, ENHANCED_EN, no auto-RTS/CTS */
uart_reg_write(uart, EFR, (1 << 4));
/* enable Tx/Rx FIFO, Tx trigger at 56 spaces, Rx trigger at 60 chars */
uart_reg_write(uart, FCR, FIFO_EN | RX_FIFO_CLEAR | TX_FIFO_CLEAR |
(3 << TX_FIFO_TRIG_SHIFT) | (3 << RX_FIFO_TRIG_SHIFT));
/* THR interrupt only when TX FIFO and TX shift register are empty */
uart_reg_write(uart, SCR, (1 << 0));// | (1 << 3));
/* 8 bit, 1 stop bit, no parity, no break */
uart_reg_write(uart, LCR, 0x03);
uart_set_lcr7bit(uart, 0);
}
void uart_poll(uint8_t uart) {
/* if(uart == CONS_UART_NR) {
uart_irq_handler_cons(0);
} else
*/ {
uart_irq_handler_sercomm(0, NULL);
}
void uart_poll(uint8_t uart)
{
#if 0
if (uart == CONS_UART_NR)
{
uart_irq_handler_cons(0);
}
else
#endif
{
uart_irq_handler_sercomm(0, NULL);
}
}
void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on)
{
uint8_t ier = uart_reg_read(uart, IER);
uint8_t mask = 0;
uint8_t ier = uart_reg_read(uart, IER);
uint8_t mask = 0;
switch (irq) {
case UART_IRQ_TX_EMPTY:
mask = (1 << 1);
break;
case UART_IRQ_RX_CHAR:
mask = (1 << 0);
break;
}
switch (irq)
{
case UART_IRQ_TX_EMPTY:
mask = (1 << 1);
break;
if (on)
ier |= mask;
else
ier &= ~mask;
case UART_IRQ_RX_CHAR:
mask = (1 << 0);
break;
}
uart_reg_write(uart, IER, ier);
if (on)
{
ier |= mask;
}
else
{
ier &= ~mask;
}
uart_reg_write(uart, IER, ier);
}
void uart_putchar_wait(uint8_t uart, int c)
{
/* wait while TX FIFO indicates full */
while (readb(UART_REG(uart, SSR)) & 0x01) { }
/* wait while TX FIFO indicates full */
/* put character in TX FIFO */
writeb(c, UART_REG(uart, THR));
while (readb(UART_REG(uart, SSR)) & 0x01) { }
/* put character in TX FIFO */
writeb(c, UART_REG(uart, THR));
}
int uart_putchar_nb(uint8_t uart, int c)
{
/* if TX FIFO indicates full, abort */
if (readb(UART_REG(uart, SSR)) & 0x01)
return 0;
/* if TX FIFO indicates full, abort */
writeb(c, UART_REG(uart, THR));
return 1;
if (readb(UART_REG(uart, SSR)) & 0x01)
{
return 0;
}
writeb(c, UART_REG(uart, THR));
return 1;
}
int uart_getchar_nb(uint8_t uart, uint8_t *ch)
{
uint8_t lsr;
uint8_t lsr;
lsr = readb(UART_REG(uart, LSR));
lsr = readb(UART_REG(uart, LSR));
/* something strange happened */
if (lsr & 0x02)
printf("LSR RX_OE\n");
if (lsr & 0x04)
printf("LSR RX_PE\n");
if (lsr & 0x08)
printf("LSR RX_FE\n");
if (lsr & 0x10)
printf("LSR RX_BI\n");
if (lsr & 0x80)
printf("LSR RX_FIFO_STS\n");
/* something strange happened */
/* is the Rx FIFO empty? */
if (!(lsr & 0x01))
return 0;
if (lsr & 0x02)
{
printf("LSR RX_OE\n");
}
*ch = readb(UART_REG(uart, RHR));
//printf("getchar_nb(%u) = %02x\n", uart, *ch);
return 1;
if (lsr & 0x04)
{
printf("LSR RX_PE\n");
}
if (lsr & 0x08)
{
printf("LSR RX_FE\n");
}
if (lsr & 0x10)
{
printf("LSR RX_BI\n");
}
if (lsr & 0x80)
{
printf("LSR RX_FIFO_STS\n");
}
/* is the Rx FIFO empty? */
if (!(lsr & 0x01))
{
return 0;
}
*ch = readb(UART_REG(uart, RHR));
//printf("getchar_nb(%u) = %02x\n", uart, *ch);
return 1;
}
int uart_tx_busy(uint8_t uart)
{
if (readb(UART_REG(uart, SSR)) & 0x01)
return 1;
return 0;
if (readb(UART_REG(uart, SSR)) & 0x01)
{
return 1;
}
return 0;
}
static const uint16_t divider[] = {
[UART_38400] = 21, /* 38,690 */
[UART_57600] = 14, /* 58,035 */
[UART_115200] = 7, /* 116,071 */
[UART_230400] = 4, /* 203,125! (-3% would be 223,488) */
[UART_460800] = 2, /* 406,250! (-3% would be 446,976) */
[UART_921600] = 1, /* 812,500! (-3% would be 893,952) */
static const uint16_t divider[] =
{
[UART_38400] = 21, /* 38,690 */
[UART_57600] = 14, /* 58,035 */
[UART_115200] = 7, /* 116,071 */
[UART_230400] = 4, /* 203,125! (-3% would be 223,488) */
[UART_460800] = 2, /* 406,250! (-3% would be 446,976) */
[UART_921600] = 1, /* 812,500! (-3% would be 893,952) */
};
int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt)
{
uint16_t div;
uint16_t div;
if (bdrt > ARRAY_SIZE(divider))
return -1;
if (bdrt > ARRAY_SIZE(divider))
{
return -1;
}
div = divider[bdrt];
uart_set_lcr7bit(uart, 1);
writeb(div & 0xff, UART_REG(uart, DLL));
writeb(div >> 8, UART_REG(uart, DLH));
uart_set_lcr7bit(uart, 0);
div = divider[bdrt];
uart_set_lcr7bit(uart, 1);
writeb(div & 0xff, UART_REG(uart, DLL));
writeb(div >> 8, UART_REG(uart, DLH));
uart_set_lcr7bit(uart, 0);
return 0;
return 0;
}

5
drivers/syslog/ramlog.c
View file

@ -692,11 +692,10 @@ int ramlog_register(FAR const char *devpath, FAR char *buffer, size_t buflen)
int ramlog_consoleinit(void)
{
FAR struct ramlog_dev_s *priv = &g_sysdev;
int ret;
/* Register the console character driver */
ret = register_driver("/dev/console", &g_ramlogfops, 0666, priv);
return register_driver("/dev/console", &g_ramlogfops, 0666, priv);
}
#endif
@ -738,11 +737,11 @@ int ramlog_sysloginit(void)
int syslog_putc(int ch)
{
FAR struct ramlog_dev_s *priv = &g_sysdev;
#ifdef CONFIG_RAMLOG_CRLF
int ret;
/* Ignore carriage returns */
#ifdef CONFIG_RAMLOG_CRLF
if (ch == '\r')
{
return ch;

8
drivers/usbdev/usbmsc.c
View file

@ -1384,7 +1384,7 @@ int usbmsc_bindlun(FAR void *handle, FAR const char *drvrpath,
int ret;
#ifdef CONFIG_DEBUG
if (!alloc || !drvrpath || startsector < 0 || nsectors < 0)
if (!alloc || !drvrpath || startsector < 0)
{
usbtrace(TRACE_CLSERROR(USBMSC_TRACEERR_BINLUNINVALIDARGS1), 0);
return -EINVAL;
@ -1722,11 +1722,9 @@ void usbmsc_uninitialize(FAR void *handle)
FAR struct usbmsc_alloc_s *alloc = (FAR struct usbmsc_alloc_s *)handle;
FAR struct usbmsc_dev_s *priv;
irqstate_t flags;
#ifdef SDCC
pthread_addr_t result1, result2;
pthread_attr_t attr;
#endif
#if 0
void *value;
#endif
int i;
#ifdef CONFIG_DEBUG

2
drivers/usbdev/usbmsc_desc.c
View file

@ -360,7 +360,7 @@ int16_t usbmsc_mkcfgdesc(uint8_t *buf)
{
#ifdef CONFIG_USBDEV_DUALSPEED
FAR const struct usb_epdesc_s *epdesc;
bool hispeed = (speed == USB_SPEED_HIGH);
bool hispeed;
#endif
/* Configuration descriptor. If the USB mass storage device is

2
drivers/wireless/cc3000/cc3000.c
View file

@ -1292,7 +1292,7 @@ static int cc3000_poll(FAR struct file *filep, FAR struct pollfd *fds,
{
FAR struct inode *inode;
FAR struct cc3000_dev_s *priv;
int ret = OK;
int ret;
int i;
nllvdbg("setup: %d\n", (int)setup);

28
drivers/wireless/cc3000/socket.c
View file

@ -186,6 +186,7 @@ int cc3000_socket(int domain, int type, int protocol)
int cc3000_closesocket(int sockfd)
{
int ret;
cc3000_lib_lock();
ret = cc3000_closesocket_impl(sockfd);
#ifdef CONFIG_CC3000_MT
@ -243,6 +244,7 @@ int cc3000_closesocket(int sockfd)
int cc3000_do_accept(int sockfd, struct sockaddr *addr, socklen_t *addrlen)
{
int ret;
cc3000_lib_lock();
ret = cc3000_accept_impl(sockfd, addr, addrlen);
cc3000_lib_unlock();
@ -265,8 +267,6 @@ int cc3000_accept(int sockfd, struct sockaddr *addr, socklen_t *addrlen)
}
#else
{
int ret = OK;
cc3000_accept_socket(sockfd,0);
short nonBlocking=CC3000_SOCK_OFF;
@ -306,7 +306,7 @@ int cc3000_accept(int sockfd, struct sockaddr *addr, socklen_t *addrlen)
int cc3000_bind(int sockfd, FAR const struct sockaddr *addr, socklen_t addrlen)
{
int ret = OK;
int ret;
cc3000_lib_lock();
ret = cc3000_bind_impl(sockfd, addr, addrlen);
@ -340,7 +340,7 @@ int cc3000_bind(int sockfd, FAR const struct sockaddr *addr, socklen_t addrlen)
int cc3000_listen(int sockfd, int backlog)
{
int ret = OK;
int ret;
cc3000_lib_lock();
ret = cc3000_listen_impl(sockfd,backlog);
@ -380,7 +380,7 @@ int cc3000_listen(int sockfd, int backlog)
int cc3000_connect(int sockfd, FAR const struct sockaddr *addr, socklen_t addrlen)
{
int ret = OK;
int ret;
cc3000_lib_lock();
ret = cc3000_connect_impl(sockfd, addr, addrlen);
@ -430,7 +430,7 @@ int cc3000_connect(int sockfd, FAR const struct sockaddr *addr, socklen_t addrle
int cc3000_select(int nfds, fd_set *readfds, fd_set *writefds,fd_set *exceptfds,
struct timeval *timeout)
{
int ret = OK;
int ret;
cc3000_lib_lock();
ret = cc3000_select_impl(nfds, (TICC3000fd_set *)readfds,
@ -492,7 +492,7 @@ int cc3000_select(int nfds, fd_set *readfds, fd_set *writefds,fd_set *exceptfds,
int cc3000_setsockopt(int sockfd, int level, int option,
FAR const void *value, socklen_t value_len)
{
int ret = OK;
int ret;
cc3000_lib_lock();
ret = cc3000_setsockopt_impl(sockfd, level, option, value, value_len);
@ -552,7 +552,7 @@ int cc3000_setsockopt(int sockfd, int level, int option,
int cc3000_getsockopt(int sockfd, int level, int option, FAR void *value,
FAR socklen_t *value_len)
{
int ret = OK;
int ret;
cc3000_lib_lock();
ret = cc3000_getsockopt_impl(sockfd, level, option, value, value_len);
@ -584,7 +584,7 @@ int cc3000_getsockopt(int sockfd, int level, int option, FAR void *value,
ssize_t cc3000_recv(int sockfd, FAR void *buf, size_t len, int flags)
{
ssize_t ret = OK;
ssize_t ret;
#ifdef CONFIG_CC3000_MT
ret = cc3000_wait_data(sockfd);
@ -632,7 +632,7 @@ ssize_t cc3000_recv(int sockfd, FAR void *buf, size_t len, int flags)
ssize_t cc3000_recvfrom(int sockfd, FAR void *buf, size_t len, int flags,
FAR struct sockaddr *from, FAR socklen_t *fromlen)
{
ssize_t ret = OK;
ssize_t ret;
#ifdef CONFIG_CC3000_MT
ret = cc3000_wait_data(sockfd);
@ -672,7 +672,7 @@ ssize_t cc3000_recvfrom(int sockfd, FAR void *buf, size_t len, int flags,
ssize_t cc3000_send(int sockfd, FAR const void *buf, size_t len, int flags)
{
ssize_t ret = OK;
ssize_t ret;
cc3000_lib_lock();
ret = cc3000_send_impl(sockfd, buf, len, flags);
@ -709,7 +709,7 @@ ssize_t cc3000_send(int sockfd, FAR const void *buf, size_t len, int flags)
ssize_t cc3000_sendto(int sockfd, FAR const void *buf, size_t len, int flags,
FAR const struct sockaddr *to, socklen_t tolen)
{
ssize_t ret = OK;
ssize_t ret;
cc3000_lib_lock();
ret = cc3000_sendto_impl(sockfd, buf, len, flags, to, tolen);
@ -744,7 +744,7 @@ ssize_t cc3000_sendto(int sockfd, FAR const void *buf, size_t len, int flags,
// TODO: Standard is struct hostent *gethostbyname(const char *name);
int cc3000_gethostbyname(char * hostname, uint16_t usNameLen, unsigned long* out_ip_addr)
{
int ret = OK;
int ret;
cc3000_lib_lock();
ret = cc3000_gethostbyname_impl(hostname, usNameLen, out_ip_addr);
@ -775,7 +775,7 @@ int cc3000_mdnsadvertiser(uint16_t mdnsEnabled, char *deviceServiceName,
uint16_t deviceServiceNameLength)
{
int ret = OK;
int ret;
cc3000_lib_lock();
ret = cc3000_mdnsadvertiser_impl(mdnsEnabled, deviceServiceName, deviceServiceNameLength);

46
drivers/wireless/cc3000/socket_imp.c
View file

@ -135,9 +135,9 @@ int HostFlowControlConsumeBuff(int sd)
if (tSLInformation.slTransmitDataError != 0)
{
errno = tSLInformation.slTransmitDataError;
set_errno(tSLInformation.slTransmitDataError);
tSLInformation.slTransmitDataError = 0;
return errno;
return tSLInformation.slTransmitDataError;
}
if (SOCKET_STATUS_ACTIVE != get_socket_active_status(sd))
@ -165,9 +165,9 @@ int HostFlowControlConsumeBuff(int sd)
if (tSLInformation.slTransmitDataError != 0)
{
errno = tSLInformation.slTransmitDataError;
set_errno(tSLInformation.slTransmitDataError);
tSLInformation.slTransmitDataError = 0;
return errno;
return tSLInformation.slTransmitDataError;
}
if (SOCKET_STATUS_ACTIVE != get_socket_active_status(sd))
@ -240,10 +240,8 @@ int cc3000_socket_impl(long domain, long type, long protocol)
/* Process the event */
errno = ret;
set_errno(ret);
set_socket_active_status(ret, SOCKET_STATUS_ACTIVE);
return ret;
}
@ -282,7 +280,7 @@ long cc3000_closesocket_impl(long sd)
/* Since we are in blocking state - wait for event complete */
SimpleLinkWaitEvent(HCI_CMND_CLOSE_SOCKET, &ret);
errno = ret;
set_errno(ret);
/* Since 'close' call may result in either OK (and then it closed) or error
* mark this socket as invalid
@ -344,7 +342,6 @@ long cc3000_accept_impl(long sd, struct sockaddr *addr, socklen_t *addrlen)
uint8_t *ptr, *args;
tBsdReturnParams tAcceptReturnArguments;
ret = EFAIL;
ptr = tSLInformation.pucTxCommandBuffer;
args = (ptr + HEADERS_SIZE_CMD);
@ -366,8 +363,8 @@ long cc3000_accept_impl(long sd, struct sockaddr *addr, socklen_t *addrlen)
memcpy(addr, &tAcceptReturnArguments.tSocketAddress, CC3000_ASIC_ADDR_LEN);
*addrlen = CC3000_ASIC_ADDR_LEN;
errno = tAcceptReturnArguments.iStatus;
ret = errno;
set_errno(tAcceptReturnArguments.iStatus);
ret = tAcceptReturnArguments.iStatus;
/* if succeeded, iStatus = new socket descriptor. otherwise - error number */
@ -433,8 +430,7 @@ long cc3000_bind_impl(long sd, const struct sockaddr *addr, socklen_t addrlen)
SimpleLinkWaitEvent(HCI_CMND_BIND, &ret);
errno = ret;
set_errno(ret);
return ret;
}
@ -484,8 +480,8 @@ long cc3000_listen_impl(long sd, long backlog)
/* Since we are in blocking state - wait for event complete */
SimpleLinkWaitEvent(HCI_CMND_LISTEN, &ret);
errno = ret;
set_errno(ret);
return ret;
}
@ -518,11 +514,11 @@ int cc3000_gethostbyname_impl(char * hostname, uint16_t usNameLen, unsigned long
tBsdGethostbynameParams ret;
uint8_t *ptr, *args;
errno = EFAIL;
set_errno(EFAIL);
if (usNameLen > CC3000_HOSTNAME_MAX_LENGTH)
{
return errno;
return get_errno();
}
ptr = tSLInformation.pucTxCommandBuffer;
@ -543,11 +539,11 @@ int cc3000_gethostbyname_impl(char * hostname, uint16_t usNameLen, unsigned long
SimpleLinkWaitEvent(HCI_EVNT_BSD_GETHOSTBYNAME, &ret);
errno = ret.retVal;
set_errno(ret.retVal);
(*((long*)out_ip_addr)) = ret.outputAddress;
return errno;
return ret.retVal;
}
#endif
@ -607,8 +603,7 @@ long cc3000_connect_impl(long sd, const struct sockaddr *addr, socklen_t addrlen
SimpleLinkWaitEvent(HCI_CMND_CONNECT, &ret);
errno = ret;
set_errno(ret);
return (long)ret;
}
@ -727,7 +722,7 @@ int cc3000_select_impl(long nfds, TICC3000fd_set *readsds, TICC3000fd_set *write
}
else
{
errno = tParams.iStatus;
set_errno(tParams.iStatus);
return -1;
}
}
@ -813,7 +808,7 @@ int cc3000_setsockopt_impl(long sd, long level, long optname, const void *optval
}
else
{
errno = ret;
set_errno(ret);
return ret;
}
}
@ -898,8 +893,8 @@ int cc3000_getsockopt_impl(long sd, long level, long optname, void *optval, sock
}
else
{
errno = tRetParams.iStatus;
return errno;
set_errno(tRetParams.iStatus);
return tRetParams.iStatus;
}
}
@ -961,8 +956,7 @@ int simple_link_recv(long sd, void *buf, long len, long flags, struct sockaddr *
SimpleLinkWaitData((uint8_t *)buf, (uint8_t *)from, (uint8_t *)fromlen);
}
errno = tSocketReadEvent.iNumberOfBytes;
set_errno(tSocketReadEvent.iNumberOfBytes);
return tSocketReadEvent.iNumberOfBytes;
}

7
drivers/wireless/cc3000/wlan.c
View file

@ -396,7 +396,7 @@ long wlan_connect(unsigned long ulSecType, char *ssid, long ssid_len,
/* Wait for command complete event */
SimpleLinkWaitEvent(HCI_CMND_WLAN_CONNECT, &ret);
errno = ret;
set_errno(ret);
cc3000_lib_unlock();
return ret;
}
@ -436,7 +436,7 @@ long wlan_connect(char *ssid, long ssid_len)
/* Wait for command complete event */
SimpleLinkWaitEvent(HCI_CMND_WLAN_CONNECT, &ret);
errno = ret;
set_errno(ret);
cc3000_lib_unlock();
@ -473,7 +473,7 @@ long wlan_disconnect(void)
/* Wait for command complete event */
SimpleLinkWaitEvent(HCI_CMND_WLAN_DISCONNECT, &ret);
errno = ret;
set_errno(ret);
cc3000_lib_unlock();
@ -1055,7 +1055,6 @@ long wlan_smart_config_start(unsigned long algoEncryptedFlag)
/* Fill in HCI packet structure */
args = UINT32_TO_STREAM(args, algoEncryptedFlag);
ret = EFAIL;
hci_command_send(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_START, ptr,
WLAN_SMART_CONFIG_START_PARAMS_LEN);

6
fs/fat/fs_fat32.c
View file

@ -391,7 +391,7 @@ static int fat_close(FAR struct file *filep)
struct inode *inode;
struct fat_file_s *ff;
struct fat_mountpt_s *fs;
int ret = OK;
int ret;
/* Sanity checks */
@ -1505,7 +1505,7 @@ static int fat_opendir(struct inode *mountpt, const char *relpath, struct fs_dir
errout_with_semaphore:
fat_semgive(fs);
return ERROR;
return ret;
}
/****************************************************************************
@ -1523,7 +1523,7 @@ static int fat_readdir(struct inode *mountpt, struct fs_dirent_s *dir)
uint8_t ch;
uint8_t attribute;
bool found;
int ret = OK;
int ret;
/* Sanity checks */

2
fs/nxffs/nxffs_open.c
View file

@ -1132,7 +1132,7 @@ int nxffs_close(FAR struct file *filep)
{
FAR struct nxffs_volume_s *volume;
FAR struct nxffs_ofile_s *ofile;
int ret = -ENOSYS;
int ret;
fvdbg("Closing\n");

2
fs/romfs/fs_romfs.c
View file

@ -745,7 +745,7 @@ static int romfs_opendir(FAR struct inode *mountpt, FAR const char *relpath,
errout_with_semaphore:
romfs_semgive(rm);
return ERROR;
return ret;
}
/****************************************************************************

5
fs/smartfs/smartfs_procfs.c
View file

@ -435,14 +435,11 @@ static int smartfs_rewinddir(struct fs_dirent_s *dir)
static int smartfs_stat(const char *relpath, struct stat *buf)
{
int ret = -ENOENT;
/* TODO: Decide if the relpath is valid and if it is a file
* or a directory and set it's permissions.
*/
buf->st_mode = S_IFDIR|S_IROTH|S_IRGRP|S_IRUSR;
ret = OK;
/* File/directory size, access block size */
@ -450,7 +447,7 @@ static int smartfs_stat(const char *relpath, struct stat *buf)
buf->st_blksize = 0;
buf->st_blocks = 0;
return ret;
return OK;
}
/****************************************************************************

4
fs/smartfs/smartfs_smart.c
View file

@ -192,7 +192,7 @@ static int smartfs_open(FAR struct file *filep, const char *relpath,
sf = (struct smartfs_ofile_s *) kmalloc(sizeof *sf);
if (sf == NULL)
{
ret = ENOMEM;
ret = -ENOMEM;
goto errout_with_semaphore;
}
@ -213,7 +213,7 @@ static int smartfs_open(FAR struct file *filep, const char *relpath,
{
/* Can't open a dir as a file! */
ret = EISDIR;
ret = -EISDIR;
goto errout_with_buffer;
}

3
fs/smartfs/smartfs_utils.c
View file

@ -854,11 +854,10 @@ int smartfs_createentry(struct smartfs_mountpt_s *fs,
goto errout;
}
nextsector = ret;
nextsector = (uint16_t) ret;
/* Set the newly allocated sector's type (file or dir) */
nextsector = (uint16_t) ret;
if ((type & SMARTFS_DIRENT_TYPE) == SMARTFS_DIRENT_TYPE_DIR)
{
chainheader->type = SMARTFS_SECTOR_TYPE_DIR;

2
graphics/nxbe/nxbe_getrectangle.c
View file

@ -104,7 +104,7 @@ void nxbe_getrectangle(FAR struct nxbe_window_s *wnd,
struct nxgl_rect_s remaining;
#ifdef CONFIG_DEBUG
if (!wnd || !rect || ! rect || plane >= wnd->be->vinfo.nplanes)
if (!wnd || !rect || !dest || plane >= wnd->be->vinfo.nplanes)
{
gvdbg("Invalid parameters\n");
return;

1
graphics/nxconsole/nxcon_kbdin.c
View file

@ -272,7 +272,6 @@ int nxcon_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
FAR struct inode *inode = filep->f_inode;
FAR struct nxcon_state_s *priv;
pollevent_t eventset;
int ndx;
int ret;
int i;

3
graphics/nxconsole/nxcon_redraw.c
View file

@ -148,5 +148,6 @@ void nxcon_redraw(NXCONSOLE handle, FAR const struct nxgl_rect_s *rect, bool mor
{
nxcon_fillchar(priv, rect, &priv->bm[i]);
}
ret = nxcon_sempost(priv);
(void)nxcon_sempost(priv);
}

2
graphics/nxmu/nx_start.c
View file

@ -148,7 +148,7 @@ int nx_server(int argc, char *argv[])
/* Then start the server (nx_run does not normally return) */
ret = nx_run(dev);
gvdbg("nx_run returned: %d\n", errno);
gvdbg("nx_run returned: %d\n", ret);
return EXIT_FAILURE;
}

7
include/nuttx/input/touchscreen.h
View file

@ -128,7 +128,8 @@ struct touch_sample_s
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
extern "C"
{
#else
#define EXTERN extern
#endif
@ -151,7 +152,7 @@ extern "C" {
*
****************************************************************************/
EXTERN int arch_tcinitialize(int minor);
int arch_tcinitialize(int minor);
/****************************************************************************
* Name: arch_tcuninitialize
@ -169,7 +170,7 @@ EXTERN int arch_tcinitialize(int minor);
*
****************************************************************************/
EXTERN void arch_tcuninitialize(void);
void arch_tcuninitialize(void);
#undef EXTERN
#ifdef __cplusplus

2
libc/audio/lib_buffer.c
View file

@ -138,7 +138,7 @@ int apb_alloc(FAR struct audio_buf_desc_s *bufdesc)
{
/* Populate the buffer contents */
memset(pBuf, bufsize, 0);
memset(pBuf, 0, bufsize);
pBuf->i.channels = 1;
pBuf->crefs = 1;
pBuf->nmaxbytes = bufdesc->numbytes;

2
libc/time/lib_isleapyear.c
View file

@ -83,6 +83,6 @@
int clock_isleapyear(int year)
{
return year % 400 ? (year % 100 ? (year % 4 ? 0 : 1) : 0) : 1;
return (year % 400) ? ((year % 100) ? ((year % 4) ? 0 : 1) : 0) : 1;
}

2
net/bind.c
View file

@ -92,7 +92,7 @@ int psock_bind(FAR struct socket *psock, const struct sockaddr *addr,
#endif
int err;
int ret;
int ret = OK;
/* Verify that the psock corresponds to valid, allocated socket */

9
net/uip/uip_igmpgroup.c
View file

@ -133,7 +133,7 @@ static FAR sq_queue_t g_freelist;
****************************************************************************/
/****************************************************************************
* Name: uip_grpalloc
* Name: uip_grpheapalloc
*
* Description:
* Allocate a new group from heap memory.
@ -169,6 +169,7 @@ static inline FAR struct igmp_group_s *uip_grpprealloc(void)
memset(group, 0, sizeof(struct igmp_group_s));
group->flags = IGMP_PREALLOCATED;
}
return group;
}
#endif
@ -237,9 +238,10 @@ FAR struct igmp_group_s *uip_grpalloc(FAR struct uip_driver_s *dev,
grplldbg("Allocate from the heap\n");
group = uip_grpheapalloc();
}
grplldbg("group: %p\n", group);
/* Check if we succesfully allocated a group structure */
/* Check if we successfully allocated a group structure */
if (group)
{
@ -262,6 +264,7 @@ FAR struct igmp_group_s *uip_grpalloc(FAR struct uip_driver_s *dev,
sq_addfirst((FAR sq_entry_t*)group, &dev->grplist);
uip_unlock(flags);
}
return group;
}
@ -300,6 +303,7 @@ FAR struct igmp_group_s *uip_grpfind(FAR struct uip_driver_s *dev,
break;
}
}
uip_unlock(flags);
return group;
}
@ -326,6 +330,7 @@ FAR struct igmp_group_s *uip_grpallocfind(FAR struct uip_driver_s *dev,
{
group = uip_grpalloc(dev, addr);
}
grplldbg("group: %p\n", group);
return group;
}

4
net/uip/uip_igmpinit.c
View file

@ -104,14 +104,12 @@ void uip_igmpinit(void)
void uip_igmpdevinit(struct uip_driver_s *dev)
{
struct igmp_group_s *group;
nvdbg("IGMP initializing dev %p\n", dev);
DEBUGASSERT(dev->grplist.head == NULL);
/* Add the all systems address to the group */
group = uip_grpalloc(dev, &g_allsystems);
(void)uip_grpalloc(dev, &g_allsystems);
/* Allow the IGMP messages at the MAC level */

221
tools/bdf-converter.c
View file

@ -33,12 +33,12 @@
*
****************************************************************************/
/*
/*
* Based one the "Glyph Bitmap Distribution Format (BDF) Specification",
* Version 2.2, by Adobe Systems Incorporated.
*
*/
/****************************************************************************
* Included Files
****************************************************************************/
@ -58,7 +58,7 @@
#define VERBOSE
#define DBG
*/
// BDF Specification Version 2.2:
// This version lifts the restriction on line length. In this version, the new
// maximum length of a value of the type string is 65535 characters, and hence
@ -126,6 +126,7 @@ typedef struct nx_fontmetric_s
* line - The line to trim
*
****************************************************************************/
static void trimLine(char *line)
{
char *str;
@ -157,15 +158,16 @@ static void trimLine(char *line)
* info[3] = -2
*
****************************************************************************/
static void bdf_parseintline(char *line, unsigned int count, int *info)
{
char *str, *token, *saveptr1;
str = line;
/* Ignore the key */
token = (char *)strtok_r(str, " ", &saveptr1);
while ((token = (char *)strtok_r(NULL, " ", &saveptr1)) && count--)
{
*(info++) = atoi(token);
@ -182,6 +184,7 @@ static void bdf_parseintline(char *line, unsigned int count, int *info)
* ginfo - A glyphinfo_t struct with the glyph's information.
*
****************************************************************************/
#ifdef DBG
static void bdf_printglyphinfo(const glyphinfo_t *ginfo)
{
@ -212,6 +215,7 @@ static void bdf_printglyphinfo(const glyphinfo_t *ginfo)
* info - A nx_fontmetric_t struct with the glyph's information.
*
****************************************************************************/
#ifdef DBG
static void bdf_printnxmetricinfo(const nx_fontmetric_t *info)
{
@ -240,49 +244,50 @@ static void bdf_printnxmetricinfo(const nx_fontmetric_t *info)
*
* Input Parameters:
* file - The input file stream pointing to the first line of the
* glyph's information (right after STARTCHAR).
* glyph's information (right after STARTCHAR).
* ginfo - A glyphinfo_t struct to fill with the glyph's information.
*
****************************************************************************/
static void bdf_getglyphinfo(FILE *file, glyphinfo_t *ginfo)
{
char line[BDF_MAX_LINE_LENGTH];
char lineCopy[BDF_MAX_LINE_LENGTH];
char *str, *token, *saveptr1;
bool done;
done = false;
while(fgets(line, BDF_MAX_LINE_LENGTH, file) != NULL && !done)
while (fgets(line, BDF_MAX_LINE_LENGTH, file) != NULL && !done)
{
trimLine(line);
strcpy(lineCopy, line);
str = line;
while ((token = (char *)strtok_r(str, " ", &saveptr1)))
{
/* ENCODING information */
if(strcmp(token, "ENCODING") == 0)
if (strcmp(token, "ENCODING") == 0)
{
token = (char *)strtok_r(NULL, " ", &saveptr1);
ginfo->encoding = atoi(token);
}
/* DWIDTH information */
if(strcmp(token, "DWIDTH") == 0)
if (strcmp(token, "DWIDTH") == 0)
{
token = (char *)strtok_r(NULL, " ", &saveptr1);
ginfo->dw_x0 = atoi(token);
token = (char *)strtok_r(NULL, " ", &saveptr1);
ginfo->dw_y0 = atoi(token);
}
/* BBX information */
else if(strcmp(token, "BBX") == 0)
else if (strcmp(token, "BBX") == 0)
{
int bbxinfo[4];
bdf_parseintline(lineCopy, 4, bbxinfo);
@ -290,15 +295,14 @@ static void bdf_getglyphinfo(FILE *file, glyphinfo_t *ginfo)
ginfo->bb_h = bbxinfo[1];
ginfo->bb_x_off = bbxinfo[2];
ginfo->bb_y_off = bbxinfo[3];
/* This is the last BDF property of interest*/
done = true;
}
str = NULL;
}
}
}
@ -310,44 +314,43 @@ static void bdf_getglyphinfo(FILE *file, glyphinfo_t *ginfo)
*
* Input Parameters:
* file - The input file stream pointing to the first line of the
* glyph's bitmap (right after BITMAP).
* glyph's bitmap (right after BITMAP).
* ginfo - A glyphinfo_t struct to fill with the glyph's bitmap.
*
****************************************************************************/
static void bdf_getglyphbitmap(FILE *file, glyphinfo_t *ginfo)
{
char line[BDF_MAX_LINE_LENGTH];
uint64_t *bitmap;
bool readingbitmap;
bitmap = ginfo->bitmap;
readingbitmap = true;
while (readingbitmap)
{
if (fgets(line, BDF_MAX_LINE_LENGTH, file) != NULL)
{
trimLine(line);
if(strcmp(line, "ENDCHAR") == 0)
{
readingbitmap = false;
}
else
{
char *endptr;
*bitmap = strtoul(line, &endptr, 16);
bitmap++;
}
}
{
trimLine(line);
if (strcmp(line, "ENDCHAR") == 0)
{
readingbitmap = false;
}
else
{
char *endptr;
*bitmap = strtoul(line, &endptr, 16);
bitmap++;
}
}
else
{
/* error condition */
readingbitmap = false;
}
{
/* error condition */
readingbitmap = false;
}
}
}
@ -382,21 +385,20 @@ static void bdf_getstride(glyphinfo_t *ginfo, uint32_t *stride)
* nxmetric - A nx_fontmetric_t struct with the glyph's information.
*
****************************************************************************/
static void bdf_printoutput(FILE *out,
static void bdf_printoutput(FILE *out,
glyphinfo_t *ginfo,
nx_fontmetric_t *nxmetric)
{
/* Only interested in the 7 and 8 bit ranges */
if ((ginfo->encoding >= NXFONT_MIN7BIT &&
ginfo->encoding <= NXFONT_MAX7BIT) ||
(ginfo->encoding >= NXFONT_MIN8BIT &&
ginfo->encoding <= NXFONT_MAX8BIT))
{
/* Glyph general info */
if (ginfo->bb_x_off < 0)
{
fprintf(out,
@ -409,9 +411,9 @@ static void bdf_printoutput(FILE *out,
{
fprintf(out, "/* %s (%d) */\n", ginfo->name, ginfo->encoding);
}
/* Glyph metrics */
fprintf(out,
"#define NXFONT_METRICS_%d {%d, %d, %d, %d, %d, 0}\n",
ginfo->encoding,
@ -420,9 +422,9 @@ static void bdf_printoutput(FILE *out,
nxmetric->height,
nxmetric->xoffset,
nxmetric->yoffset);
/* Glyph bitmap */
fprintf(out, "#define NXFONT_BITMAP_%d {", ginfo->encoding);
int i, j;
for (i = 0; i < ginfo->bb_h - 1; i++)
@ -432,28 +434,28 @@ static void bdf_printoutput(FILE *out,
int nxbyteoffset;
uint8_t nxbyte = 0;
uint64_t tempbitmap = ginfo->bitmap[i];
/* Get the next byte */
nxbyteoffset = (nxmetric->stride - j) * 8;
nxbyte = (uint8_t)(tempbitmap >> nxbyteoffset);
fprintf(out, "0x%x, ", nxbyte);
}
}
/* Different behavior for the last bitmap */
for (j = 1; j <= nxmetric->stride; j++)
{
int nxbyteoffset;
uint8_t nxbyte = 0;
uint64_t tempbitmap = ginfo->bitmap[i];
/* Get the next byte */
nxbyteoffset = (nxmetric->stride - j) * 8;
nxbyte = (uint8_t)(tempbitmap >> nxbyteoffset);
if (j == nxmetric->stride)
{
fprintf(out, "0x%x}\n", nxbyte);
@ -462,11 +464,10 @@ static void bdf_printoutput(FILE *out,
{
fprintf(out, "0x%x, ", nxbyte);
}
}
}
fprintf(out, "\n");
}
}
/****************************************************************************
@ -480,26 +481,26 @@ int main(int argc, char **argv)
char lineCopy[BDF_MAX_LINE_LENGTH];
char *str, *token, *saveptr1;
char *input, *output;
/* FONTBOUNDINGBOX properties*/
int fbb_x = 0;
int fbb_y = 0;
int fbb_x_off = 0;
//int fbb_x_off = 0;
int fbb_y_off = 0;
/* Input BDF file */
input = argv[1];
if (input == NULL)
{
printf("%s: no input file\n", argv[0]);
exit(0);
}
file = fopen(input, "r");
if (file == NULL)
{
printf("%s: error opening file %s\n", argv[0], input);
@ -511,8 +512,9 @@ int main(int argc, char **argv)
printf("Opening \"%s\"\n", input);
#endif /* VERBOSE */
}
/* Output file */
if (argv[2])
{
output = argv[2];
@ -521,9 +523,9 @@ int main(int argc, char **argv)
{
output = "nxfonts_myfont.h";
}
out = fopen(output, "w");
if (out == NULL)
{
printf("%s: error opening file %s\n", argv[0], output);
@ -534,61 +536,62 @@ int main(int argc, char **argv)
{
while (fgets(line, BDF_MAX_LINE_LENGTH, file) != NULL)
{
#ifdef DBG
printf("--\n");
#endif /* DBG */
// Save a copy of the line
strcpy(lineCopy,line);
// Clean it
trimLine(line);
str = line;
while ((token = (char *)strtok_r(str, " ", &saveptr1)))
{
/* FONTBOUNDINGBOX - Global font information */
if (strcmp(token, "FONTBOUNDINGBOX") == 0)
{
int fbbinfo[4];
bdf_parseintline(lineCopy, 4, fbbinfo);
fbb_x = fbbinfo[0];
fbb_y = fbbinfo[1];
fbb_x_off = fbbinfo[2];
//fbb_x_off = fbbinfo[2];
fbb_y_off = fbbinfo[3];
/* Print FONTBOUNDINGBOX information */
fprintf(out, "/* Maximum height and width of any");
fprintf(out, " glyph in the set */\n\n");
fprintf(out, "#define NXFONT_MAXHEIGHT %d\n", fbb_y);
fprintf(out, "#define NXFONT_MAXWIDTH %d\n\n", fbb_x);
}
/* STARTCHAR - Individual glyph information */
if (strcmp(token, "STARTCHAR") == 0)
{
glyphinfo_t ginfo;
/* Glyph name */
ginfo.name = (char *)strtok_r(NULL, " ", &saveptr1);
#ifdef VERBOSE
printf("Processing glyph: %s\n", ginfo.name);
#endif /* VERBOSE */
/* Glyph information:
* ENCODING
* DWIDTH
* BBX
*/
ginfo.encoding = 0;
ginfo.dw_x0 = 0;
ginfo.dw_y0 = 0;
@ -597,18 +600,18 @@ int main(int argc, char **argv)
ginfo.bb_x_off = 0;
ginfo.bb_y_off = 0;
bdf_getglyphinfo(file, &ginfo);
/* Glyph bitmap */
ginfo.bitmap = malloc(sizeof(uint64_t) * ginfo.bb_h);
bdf_getglyphbitmap(file, &ginfo);
#ifdef DBG
bdf_printglyphinfo(&ginfo);
#endif /* DBG */
/* Convert to nxfonts */
nx_fontmetric_t nxmetric;
uint32_t stride;
bdf_getstride(&ginfo, &stride);
@ -618,7 +621,7 @@ int main(int argc, char **argv)
/* The NuttX font format does not support
* negative X offsets. */
if (ginfo.bb_x_off < 0)
{
nxmetric.xoffset = 0;
@ -632,12 +635,11 @@ int main(int argc, char **argv)
{
nxmetric.xoffset = ginfo.bb_x_off;
}
nxmetric.yoffset = fbb_y + fbb_y_off -
ginfo.bb_y_off - ginfo.bb_h;
#ifdef DBG
#ifdef DBG
bdf_printnxmetricinfo(&nxmetric);
#endif /* DBG */
@ -652,25 +654,26 @@ int main(int argc, char **argv)
{
bdf_printoutput(out, &ginfo, &nxmetric);
}
/* Free memory */
free(ginfo.bitmap);
}
str = NULL;
}
}
fclose(file);
fclose(out);
/* The End */
printf("Generated \"%s\"\n", output);
}
return EXIT_SUCCESS;
}

2
tools/configure.c
View file

@ -200,7 +200,7 @@ static void parse_args(int argc, char **argv)
fprintf(stderr, "ERROR: Missing option argument, option: %c\n", optopt);
show_usage(argv[0], EXIT_FAILURE);
break;
default:
fprintf(stderr, "ERROR: Unexpected option: %c\n", ch);
show_usage(argv[0], EXIT_FAILURE);
}

8
tools/kconfig2html.c
View file

@ -2101,7 +2101,6 @@ static inline char *process_menu(FILE *stream, const char *kconfigdir)
const char *paranum;
char *menuname;
char *token = NULL;
char *ptr;
/* Get the menu information */
@ -2114,7 +2113,7 @@ static inline char *process_menu(FILE *stream, const char *kconfigdir)
/* Process each line in the choice */
while ((ptr = kconfig_line(stream)) != NULL)
while (kconfig_line(stream) != NULL)
{
/* Process the first token on the Kconfig file line */
@ -2228,11 +2227,10 @@ static char *parse_kconfigfile(FILE *stream, const char *kconfigdir)
{
enum token_type_e tokid;
char *token = NULL;
char *ptr;
/* Process each line in the Kconfig file */
while ((ptr = kconfig_line(stream)) != NULL)
while (kconfig_line(stream) != NULL)
{
/* Process the first token on the Kconfig file line */
@ -2475,7 +2473,7 @@ int main(int argc, char **argv, char **envp)
error("Missing option argument, option: %c\n", optopt);
show_usage(argv[0], ERROR_MISSING_OPTION_ARGUMENT);
break;
default:
error("Unexpected option: %c\n", ch);
show_usage(argv[0], ERROR_UNEXPECTED_OPTION);
}

2
tools/mkdeps.c
View file

@ -635,8 +635,6 @@ static char *cywin2windows(const char *str, const char *append, enum slashmode_e
if (append)
{
char *tmp;
alloclen = sizeof(str) + sizeof(append) + 1;
allocpath = (char *)malloc(alloclen);
if (!allocpath)

2
tools/mksymtab.c
View file

@ -148,7 +148,7 @@ int main(int argc, char **argv, char **envp)
fprintf(stderr, "Missing option argument, option: %c\n", optopt);
show_usage(argv[0]);
break;
default:
fprintf(stderr, "Unexpected option: %c\n", ch);
show_usage(argv[0]);
}

2
tools/mksyscall.c
View file

@ -606,7 +606,7 @@ int main(int argc, char **argv, char **envp)
fprintf(stderr, "Missing option argument, option: %c\n", optopt);
show_usage(argv[0]);
break;
default:
fprintf(stderr, "Unexpected option: %c\n", ch);
show_usage(argv[0]);
}