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https://github.com/apache/nuttx.git
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imxrt:Add LPI2C DMA
This commit is contained in:
David Sidrane
Xiang Xiao
parent
f34acdb936
commit
85ec2e1446
2 changed files with 549 additions and 35 deletions
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@ -804,6 +804,11 @@ config LPI2C1_BUSYIDLE
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int "Bus idle timeout period in clock cycles"
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default 0
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config LPI2C1_DMA
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bool "Enable DMA for I2C1"
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default n
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depends on IMXRT_LPI2C_DMA
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config LPI2C1_FILTSCL
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int "I2C master digital glitch filters for SCL input in clock cycles"
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default 0
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@ -825,6 +830,11 @@ config LPI2C2_BUSYIDLE
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int "Bus idle timeout period in clock cycles"
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default 0
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config LPI2C2_DMA
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bool "Enable DMA for I2C2"
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default n
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depends on IMXRT_LPI2C_DMA
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config LPI2C2_FILTSCL
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int "I2C master digital glitch filters for SCL input in clock cycles"
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default 0
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@ -846,6 +856,11 @@ config LPI2C3_BUSYIDLE
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int "Bus idle timeout period in clock cycles"
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default 0
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config LPI2C3_DMA
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bool "Enable DMA for I2C3"
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default n
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depends on IMXRT_LPI2C_DMA
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config LPI2C3_FILTSCL
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int "I2C master digital glitch filters for SCL input in clock cycles"
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default 0
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@ -867,6 +882,11 @@ config LPI2C4_BUSYIDLE
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int "Bus idle timeout period in clock cycles"
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default 0
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config LPI2C4_DMA
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bool "Enable DMA for I2C4"
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default n
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depends on IMXRT_LPI2C_DMA
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config LPI2C4_FILTSCL
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int "I2C master digital glitch filters for SCL input in clock cycles"
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default 0
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@ -1591,6 +1611,25 @@ endmenu # Memory Configuration
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menu "LPI2C Configuration"
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depends on IMXRT_LPI2C
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config IMXRT_LPI2C_DMA
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bool "I2C DMA Support"
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default n
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depends on IMXRT_LPI2C && IMXRT_EDMA && !I2C_POLLED
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---help---
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This option enables the DMA for I2C transfers.
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Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value
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for the I2C dma streams, else the default priority level is set to
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medium.
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config IMXRT_LPI2C_DMA_MAXMSG
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int "Maximum number messages that will be DMAed"
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default 8
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depends on IMXRT_LPI2C_DMA
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---help---
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This option set the mumber of mesg that can be in a transfer.
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It is used to allocate space for the 16 bit LPI2C commands
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that will be DMA-ed to the LPI2C device.
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config IMXRT_LPI2C_DYNTIMEO
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bool "Use dynamic timeouts"
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default n
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@ -44,8 +44,11 @@
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#include "arm_internal.h"
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#include "imxrt_lpi2c.h"
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#include "imxrt_edma.h"
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#include "imxrt_gpio.h"
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#include "imxrt_lpi2c.h"
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#include "hardware/imxrt_dmamux.h"
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#include "hardware/imxrt_pinmux.h"
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#include "hardware/imxrt_ccm.h"
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#include "imxrt_periphclks.h"
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@ -171,6 +174,9 @@ struct imxrt_lpi2c_config_s
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#ifndef CONFIG_I2C_POLLED
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uint32_t irq; /* Event IRQ */
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#endif
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#ifdef CONFIG_IMXRT_LPI2C_DMA
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uint32_t dma_reqsrc; /* DMA mux source */
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#endif
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};
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/* I2C Device Private Data */
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@ -211,6 +217,11 @@ struct imxrt_lpi2c_priv_s
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#endif
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uint32_t status; /* End of transfer SR2|SR1 status */
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#ifdef CONFIG_IMXRT_LPI2C_DMA
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DMACH_HANDLE dma; /* DMA handle */
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uint16_t cmnds[CONFIG_IMXRT_LPI2C_DMA_MAXMSG]; /* Commands */
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#endif
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};
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/****************************************************************************
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@ -278,6 +289,11 @@ static int imxrt_lpi2c_transfer(struct i2c_master_s *dev,
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static int imxrt_lpi2c_reset(struct i2c_master_s *dev);
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#endif
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#ifdef CONFIG_IMXRT_LPI2C_DMA
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static void imxrt_dma_callback(DMACH_HANDLE handle, void *arg, bool done,
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int result);
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@ -302,12 +318,18 @@ static const char *g_trace_names[] =
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static const struct i2c_ops_s imxrt_lpi2c_ops =
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{
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.transfer = imxrt_lpi2c_transfer
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.transfer = imxrt_lpi2c_transfer,
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#ifdef CONFIG_I2C_RESET
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, .reset = imxrt_lpi2c_reset
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.reset = imxrt_lpi2c_reset,
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#endif
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};
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#ifdef CONFIG_IMXRT_LPI2C_DMA
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/* Receive Data DMA Enable */
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static uint32_t g_lpi2c_mder_rdde = LPI2C_MDER_RDDE;
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#endif
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/* I2C device structures */
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#ifdef CONFIG_IMXRT_LPI2C1
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@ -331,6 +353,9 @@ static const struct imxrt_lpi2c_config_s imxrt_lpi2c1_config =
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#ifndef CONFIG_I2C_POLLED
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.irq = IMXRT_IRQ_LPI2C1,
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#endif
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#ifdef CONFIG_LPI2C1_DMA
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.dma_reqsrc = IMXRT_DMACHAN_LPI2C1,
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#endif
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};
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static struct imxrt_lpi2c_priv_s imxrt_lpi2c1_priv =
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@ -369,6 +394,9 @@ static const struct imxrt_lpi2c_config_s imxrt_lpi2c2_config =
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#ifndef CONFIG_I2C_POLLED
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.irq = IMXRT_IRQ_LPI2C2,
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#endif
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#ifdef CONFIG_LPI2C2_DMA
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.dma_reqsrc = IMXRT_DMACHAN_LPI2C2,
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#endif
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};
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static struct imxrt_lpi2c_priv_s imxrt_lpi2c2_priv =
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@ -407,6 +435,9 @@ static const struct imxrt_lpi2c_config_s imxrt_lpi2c3_config =
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#ifndef CONFIG_I2C_POLLED
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.irq = IMXRT_IRQ_LPI2C3,
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#endif
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#ifdef CONFIG_LPI2C3_DMA
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.dma_reqsrc = IMXRT_DMACHAN_LPI2C3,
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#endif
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};
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static struct imxrt_lpi2c_priv_s imxrt_lpi2c3_priv =
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@ -445,6 +476,9 @@ static const struct imxrt_lpi2c_config_s imxrt_lpi2c4_config =
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#ifndef CONFIG_I2C_POLLED
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.irq = IMXRT_IRQ_LPI2C4,
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#endif
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#ifdef CONFIG_LPI2C4_DMA
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.dma_reqsrc = IMXRT_DMACHAN_LPI2C4,
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#endif
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};
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static struct imxrt_lpi2c_priv_s imxrt_lpi2c4_priv =
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@ -587,30 +621,43 @@ imxrt_lpi2c_sem_waitdone(struct imxrt_lpi2c_priv_s *priv)
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flags = enter_critical_section();
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/* Enable Interrupts when master mode */
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if (priv->config->mode == LPI2C_MASTER)
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#ifdef CONFIG_IMXRT_LPI2C_DMA
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if (priv->dma == NULL)
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{
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if ((priv->flags & I2C_M_READ) != 0)
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#endif
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/* Enable Interrupts when master mode */
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if (priv->config->mode == LPI2C_MASTER)
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{
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regval = LPI2C_MIER_TDIE | LPI2C_MIER_RDIE | LPI2C_MIER_NDIE | \
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LPI2C_MIER_ALIE | LPI2C_MIER_SDIE;
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imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MIER_OFFSET, regval);
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if ((priv->flags & I2C_M_READ) != 0)
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{
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regval = LPI2C_MIER_TDIE | LPI2C_MIER_RDIE |
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LPI2C_MIER_NDIE | LPI2C_MIER_ALIE |
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LPI2C_MIER_SDIE;
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imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MIER_OFFSET, regval);
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}
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else
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{
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regval = LPI2C_MIER_TDIE | LPI2C_MIER_NDIE | \
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LPI2C_MIER_ALIE | LPI2C_MIER_SDIE;
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imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MIER_OFFSET, regval);
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}
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}
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/* Enable Interrupts when slave mode */
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else
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{
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regval = LPI2C_MIER_TDIE | LPI2C_MIER_NDIE | \
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LPI2C_MIER_ALIE | LPI2C_MIER_SDIE;
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imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MIER_OFFSET, regval);
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#warning Missing logic for I2C Slave mode
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}
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}
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/* Enable Interrupts when slave mode */
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else
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{
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#warning Missing logic for I2C Slave mode
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/* Signal the interrupt handler that we are waiting. NOTE: Interrupts
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* are currently disabled but will be temporarily re-enabled below when
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* nxsem_timedwait() sleeps.
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*/
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#ifdef CONFIG_IMXRT_LPI2C_DMA
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}
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#endif
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/* Signal the interrupt handler that we are waiting. NOTE: Interrupts
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* are currently disabled but will be temporarily re-enabled below when
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@ -861,6 +908,59 @@ imxrt_lpi2c_sem_destroy(struct imxrt_lpi2c_priv_s *priv)
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#endif
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}
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/****************************************************************************
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* Name: imxrt_dma_callback
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*
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* Description:
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* This function performs the next I2C operation
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*
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****************************************************************************/
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#ifdef CONFIG_IMXRT_LPI2C_DMA
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static void imxrt_dma_callback(DMACH_HANDLE handle, void *arg, bool done,
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int result)
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{
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struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)arg;
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imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MIER_OFFSET, 0,
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LPI2C_MIER_SDIE);
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if (result != OK)
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{
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priv->status = imxrt_lpi2c_getstatus(priv);
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if ((priv->status & LPI2C_MSR_ERROR_MASK) != 0)
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{
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i2cerr("ERROR: MSR: status: 0x0%" PRIx32 "\n", priv->status);
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imxrt_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0);
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/* Clear the TX and RX FIFOs */
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imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCR_OFFSET, 0,
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LPI2C_MCR_RTF | LPI2C_MCR_RRF);
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/* Clear the error */
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imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MSR_OFFSET,
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(priv->status & (LPI2C_MSR_NDF |
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LPI2C_MSR_ALF |
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LPI2C_MSR_FEF |
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LPI2C_MSR_PLTF)));
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if (priv->intstate == INTSTATE_WAITING)
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{
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/* inform the thread that transfer is complete
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* and wake it up
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*/
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priv->intstate = INTSTATE_DONE;
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nxsem_post(&priv->sem_isr);
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}
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}
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}
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}
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#endif
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/****************************************************************************
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* Name: imxrt_lpi2c_trace*
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*
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@ -1217,6 +1317,20 @@ imxrt_lpi2c_getstatus(struct imxrt_lpi2c_priv_s *priv)
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return imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MSR_OFFSET);
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}
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/****************************************************************************
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* Name: imxrt_lpi2c_getenabledints
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*
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* Description:
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* Get 32-bit status
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*
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****************************************************************************/
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static inline uint32_t
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imxrt_lpi2c_getenabledints(FAR struct imxrt_lpi2c_priv_s *priv)
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{
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return imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MIER_OFFSET);
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}
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/****************************************************************************
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* Name: imxrt_lpi2c_isr_process
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*
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@ -1229,6 +1343,79 @@ static int imxrt_lpi2c_isr_process(struct imxrt_lpi2c_priv_s *priv)
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{
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uint32_t status = imxrt_lpi2c_getstatus(priv);
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#ifdef CONFIG_IMXRT_LPI2C_DMA
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uint32_t current_status = status;
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/* Condition the status with only the enabled interrupts */
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status &= imxrt_lpi2c_getenabledints(priv);
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if (priv->dma != NULL)
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{
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/* End of packet or Stop */
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if ((status & (LPI2C_MSR_SDF | LPI2C_MSR_EPF)) != 0)
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{
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imxrt_lpi2c_traceevent(priv, I2CEVENT_STOP, 0);
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/* Acknowledge End of packet or Stop */
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imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MSR_OFFSET, status &
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(LPI2C_MSR_SDF |
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LPI2C_MSR_EPF));
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}
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/* Is there an Error condition */
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if (current_status & LPI2C_MSR_ERROR_MASK)
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{
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imxrt_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0);
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/* Shutdown DMA */
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imxrt_dmach_stop(priv->dma);
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/* Clear the TX and RX FIFOs */
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imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCR_OFFSET, 0,
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LPI2C_MCR_RTF | LPI2C_MCR_RRF);
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/* Clear the error */
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imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MSR_OFFSET,
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(current_status & (LPI2C_MSR_NDF |
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LPI2C_MSR_ALF |
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LPI2C_MSR_FEF)));
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/* Return the full error status */
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status = current_status;
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}
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/* Mark that this transaction stopped */
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priv->msgv = NULL;
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priv->msgc = 0;
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priv->dcnt = -1;
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if (priv->intstate == INTSTATE_WAITING)
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{
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/* Update Status once at the end */
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priv->status = status;
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/* inform the thread that transfer is complete
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* and wake it up
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*/
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priv->intstate = INTSTATE_DONE;
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nxsem_post(&priv->sem_isr);
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}
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return OK;
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}
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#endif
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/* Check for new trace setup */
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imxrt_lpi2c_tracenew(priv, status);
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@ -1369,8 +1556,8 @@ static int imxrt_lpi2c_isr_process(struct imxrt_lpi2c_priv_s *priv)
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* and wake it up
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*/
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nxsem_post(&priv->sem_isr);
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priv->intstate = INTSTATE_DONE;
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nxsem_post(&priv->sem_isr);
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}
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#else
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priv->status = status;
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@ -1412,22 +1599,22 @@ static int imxrt_lpi2c_isr_process(struct imxrt_lpi2c_priv_s *priv)
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LPI2C_MSR_FEF)));
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#ifndef CONFIG_I2C_POLLED
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if (priv->intstate == INTSTATE_WAITING)
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{
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/* Update Status once at the end */
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if (priv->intstate == INTSTATE_WAITING)
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{
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/* Update Status once at the end */
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priv->status = status;
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/* inform the thread that transfer is complete
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* and wake it up
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*/
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nxsem_post(&priv->sem_isr);
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priv->intstate = INTSTATE_DONE;
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}
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#else
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priv->status = status;
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/* inform the thread that transfer is complete
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* and wake it up
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*/
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priv->intstate = INTSTATE_DONE;
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nxsem_post(&priv->sem_isr);
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}
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#else
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priv->status = status;
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priv->intstate = INTSTATE_DONE;
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#endif
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}
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@ -1448,7 +1635,8 @@ static int imxrt_lpi2c_isr(int irq, void *context, void *arg)
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struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)arg;
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DEBUGASSERT(priv != NULL);
|
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return imxrt_lpi2c_isr_process(priv);
|
||||
int rv = imxrt_lpi2c_isr_process(priv);
|
||||
return rv;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1547,7 +1735,7 @@ static int imxrt_lpi2c_init(struct imxrt_lpi2c_priv_s *priv)
|
|||
/* Pin config and ignore NACK disable */
|
||||
|
||||
imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCFGR1_OFFSET,
|
||||
LPI2C_MCFGR1_IGNACK | LPI2C_MCFGR1_PINCFG_MASK, 0);
|
||||
LPI2C_MCFGR1_IGNACK, LPI2C_MCFGR1_AUTOSTOP);
|
||||
|
||||
/* Set tx and rx watermarks */
|
||||
|
||||
|
|
@ -1621,6 +1809,260 @@ static int imxrt_lpi2c_deinit(struct imxrt_lpi2c_priv_s *priv)
|
|||
* Device Driver Operations
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lpi2c_dma_configure
|
||||
*
|
||||
* Description:
|
||||
* Create a TCD to change from TX to RX
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPI2C_DMA
|
||||
static int imxrt_lpi2c_dma_configure_mder(FAR struct imxrt_lpi2c_priv_s *
|
||||
priv)
|
||||
{
|
||||
struct imxrt_edma_xfrconfig_s config;
|
||||
memset(&config, 0, sizeof(config));
|
||||
|
||||
config.saddr = (uint32_t) &g_lpi2c_mder_rdde;
|
||||
config.daddr = priv->config->base + IMXRT_LPI2C_MDER_OFFSET;
|
||||
config.soff = 0;
|
||||
config.doff = sizeof(uint8_t);
|
||||
config.iter = 1;
|
||||
config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE;
|
||||
config.ssize = EDMA_8BIT;
|
||||
config.dsize = EDMA_8BIT;
|
||||
config.nbytes = sizeof(uint8_t);
|
||||
|
||||
up_clean_dcache((uintptr_t)config.saddr ,
|
||||
(uintptr_t)config.saddr + config.nbytes);
|
||||
|
||||
return imxrt_dmach_xfrsetup(priv->dma, &config);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lpi2c_dma_command_configure
|
||||
*
|
||||
* Description:
|
||||
* Create a command TCD
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPI2C_DMA
|
||||
static int imxrt_lpi2c_dma_command_configure(FAR struct imxrt_lpi2c_priv_s
|
||||
*priv, uint16_t *ccmd,
|
||||
uint32_t ncmd)
|
||||
{
|
||||
struct imxrt_edma_xfrconfig_s config;
|
||||
memset(&config, 0, sizeof(config));
|
||||
|
||||
config.saddr = (uint32_t) ccmd;
|
||||
config.daddr = priv->config->base + IMXRT_LPI2C_MTDR_OFFSET;
|
||||
config.soff = sizeof(uint16_t);
|
||||
config.doff = 0;
|
||||
config.iter = 1;
|
||||
config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE;
|
||||
config.ssize = EDMA_16BIT;
|
||||
config.dsize = EDMA_16BIT;
|
||||
config.nbytes = sizeof(uint16_t) * ncmd;
|
||||
|
||||
up_clean_dcache((uintptr_t)config.saddr ,
|
||||
(uintptr_t)config.saddr + config.nbytes);
|
||||
|
||||
return imxrt_dmach_xfrsetup(priv->dma, &config);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lpi2c_dma_data_configure
|
||||
*
|
||||
* Description:
|
||||
* Create a data TCD
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPI2C_DMA
|
||||
static int imxrt_lpi2c_dma_data_configure(FAR struct imxrt_lpi2c_priv_s
|
||||
*priv,
|
||||
struct i2c_msg_s *msg)
|
||||
{
|
||||
struct imxrt_edma_xfrconfig_s config;
|
||||
memset(&config, 0, sizeof(config));
|
||||
|
||||
config.iter = msg->length;
|
||||
config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE;
|
||||
config.ssize = EDMA_8BIT;
|
||||
config.dsize = EDMA_8BIT;
|
||||
config.nbytes = sizeof(msg->buffer[0]);
|
||||
|
||||
if (msg->flags & I2C_M_READ)
|
||||
{
|
||||
config.saddr = priv->config->base + IMXRT_LPI2C_MRDR_OFFSET;
|
||||
config.daddr = (uint32_t) msg->buffer;
|
||||
config.soff = 0;
|
||||
config.doff = sizeof(msg->buffer[0]);
|
||||
up_invalidate_dcache((uintptr_t)msg->buffer,
|
||||
(uintptr_t)msg->buffer + msg->length);
|
||||
}
|
||||
else
|
||||
{
|
||||
config.saddr = (uint32_t) msg->buffer;
|
||||
config.daddr = priv->config->base + IMXRT_LPI2C_MTDR_OFFSET;
|
||||
config.soff = sizeof(msg->buffer[0]);
|
||||
config.doff = 0;
|
||||
up_clean_dcache((uintptr_t)msg->buffer,
|
||||
(uintptr_t)msg->buffer + msg->length);
|
||||
}
|
||||
|
||||
return imxrt_dmach_xfrsetup(priv->dma, &config) ? 0 : msg->length;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lpi2c_configure_dma_transfer
|
||||
*
|
||||
* Description:
|
||||
* DMA based I2C transfer function
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPI2C_DMA
|
||||
static int imxrt_lpi2c_form_command_list(FAR struct imxrt_lpi2c_priv_s
|
||||
*priv, struct i2c_msg_s *msg,
|
||||
int ncmds)
|
||||
{
|
||||
ssize_t length = 0;
|
||||
|
||||
if (priv->flags & I2C_M_NOSTART)
|
||||
{
|
||||
if (priv->flags & I2C_M_READ)
|
||||
{
|
||||
/* No start read operation */
|
||||
|
||||
priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_RXD |
|
||||
LPI2C_MTDR_DATA(msg->length - 1);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* A start based read or write operation */
|
||||
|
||||
/* Create bus address with R/W */
|
||||
|
||||
uint16_t badd = (priv->flags & I2C_M_READ) ? I2C_READADDR8(msg->addr) :
|
||||
I2C_WRITEADDR8(msg->addr);
|
||||
|
||||
priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_START | LPI2C_MTDR_DATA(badd);
|
||||
|
||||
if (badd & I2C_READBIT)
|
||||
{
|
||||
length = msg->length;
|
||||
while (length)
|
||||
{
|
||||
if (length > 256u)
|
||||
{
|
||||
priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_RXD |
|
||||
LPI2C_MTDR_DATA(256u - 1);
|
||||
length -= 256u;
|
||||
}
|
||||
else
|
||||
{
|
||||
priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_RXD |
|
||||
LPI2C_MTDR_DATA(length - 1);
|
||||
length = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ncmds;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lpi2c_dma_transfer
|
||||
*
|
||||
* Description:
|
||||
* DMA based I2C transfer function
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPI2C_DMA
|
||||
static int imxrt_lpi2c_dma_transfer(FAR struct imxrt_lpi2c_priv_s *priv)
|
||||
{
|
||||
int m;
|
||||
int ntotcmds = 0;
|
||||
int ncmds = 0;
|
||||
uint16_t *ccmnd = NULL;
|
||||
|
||||
/* Disable Interrupts */
|
||||
|
||||
imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MIER_OFFSET,
|
||||
LPI2C_MIER_RDIE | LPI2C_MIER_TDIE, 0);
|
||||
|
||||
/* Disable DMA */
|
||||
|
||||
imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MDER_OFFSET, LPI2C_MDER_TDDE |
|
||||
LPI2C_MDER_RDDE, 0);
|
||||
|
||||
/* Turn off auto_stop option */
|
||||
|
||||
imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCFGR1_OFFSET, 0,
|
||||
LPI2C_MCFGR1_IGNACK | LPI2C_MCFGR1_AUTOSTOP);
|
||||
|
||||
/* Form chains of tcd to process the messages */
|
||||
|
||||
for (m = 0; m < priv->msgc; m++)
|
||||
{
|
||||
ncmds = 0;
|
||||
priv->flags = priv->msgv[m].flags;
|
||||
|
||||
/* Form a command list */
|
||||
|
||||
ccmnd = &priv->cmnds[ntotcmds];
|
||||
|
||||
ncmds = imxrt_lpi2c_form_command_list(priv, &priv->msgv[m], ntotcmds);
|
||||
|
||||
/* Have commands for this message ? */
|
||||
|
||||
if (ncmds != 0)
|
||||
{
|
||||
/* Build up a TCD with the command from this message */
|
||||
|
||||
imxrt_lpi2c_dma_command_configure(priv, ccmnd, ncmds - ntotcmds);
|
||||
|
||||
ntotcmds += ncmds;
|
||||
|
||||
DEBUGASSERT(ntotcmds < CONFIG_IMXRT_LPI2C_DMA_MAXMSG);
|
||||
|
||||
if (priv->flags & I2C_M_READ)
|
||||
{
|
||||
/* We have commands and this message is a read.
|
||||
* Since there is only one DMA request line for both TX/RX
|
||||
* we must insert a DMA operation to switch to the LSI2C from
|
||||
* TX to RX DMA
|
||||
*/
|
||||
|
||||
imxrt_lpi2c_dma_configure_mder(priv);
|
||||
}
|
||||
|
||||
imxrt_lpi2c_dma_data_configure(priv, &priv->msgv[m]);
|
||||
}
|
||||
}
|
||||
|
||||
imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MIER_OFFSET,
|
||||
LPI2C_MIER_NDIE | LPI2C_MIER_ALIE |
|
||||
LPI2C_MIER_PLTIE | LPI2C_MIER_FEIE);
|
||||
|
||||
imxrt_dmach_start(priv->dma, imxrt_dma_callback, (void *)priv);
|
||||
|
||||
imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MDER_OFFSET, 0,
|
||||
LPI2C_MDER_TDDE | LPI2C_MDER_RDDE);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lpi2c_transfer
|
||||
*
|
||||
|
|
@ -1678,11 +2120,26 @@ static int imxrt_lpi2c_transfer(struct i2c_master_s *dev,
|
|||
* the BUSY flag.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPI2C_DMA
|
||||
if (priv->dma)
|
||||
{
|
||||
imxrt_lpi2c_dma_transfer(priv);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (imxrt_lpi2c_sem_waitdone(priv) < 0)
|
||||
{
|
||||
#ifdef CONFIG_IMXRT_LPI2C_DMA
|
||||
if (priv->dma)
|
||||
{
|
||||
imxrt_dmach_stop(priv->dma);
|
||||
}
|
||||
|
||||
#endif
|
||||
ret = -ETIMEDOUT;
|
||||
|
||||
i2cerr("ERROR: Timed out: MCR: status: 0x%" PRIx32 "\n", priv->status);
|
||||
i2cerr("ERROR: Timed out: MSR: status: 0x0%" PRIx32 "\n",
|
||||
priv->status);
|
||||
}
|
||||
|
||||
/* Check for error status conditions */
|
||||
|
|
@ -1920,6 +2377,15 @@ struct i2c_master_s *imxrt_i2cbus_initialize(int port)
|
|||
{
|
||||
imxrt_lpi2c_sem_init(priv);
|
||||
imxrt_lpi2c_init(priv);
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPI2C_DMA
|
||||
if (priv->config->dma_reqsrc != 0)
|
||||
{
|
||||
priv->dma = imxrt_dmach_alloc(priv->config->dma_reqsrc |
|
||||
DMAMUX_CHCFG_ENBL, 0);
|
||||
DEBUGASSERT(priv->dma != NULL);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
|
@ -1961,6 +2427,15 @@ int imxrt_i2cbus_uninitialize(struct i2c_master_s *dev)
|
|||
|
||||
/* Disable power and other HW resource (GPIO's) */
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPI2C_DMA
|
||||
if (priv->dma != NULL)
|
||||
{
|
||||
imxrt_dmach_stop(priv->dma);
|
||||
imxrt_dmach_free(priv->dma);
|
||||
priv->dma = NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
imxrt_lpi2c_deinit(priv);
|
||||
|
||||
/* Release unused resources */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue