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stm32h7: added stm32-dac driver
+ added dac driver * modified Kconfig for DAC, DAC_DMA, TMX_DAC * checked DMA+DAC/DAC only * checked DCASH/wo DCASH * checked TIM 1,2,4,5,6,7,8,15 Signed-off-by: Andrey Sobol <andrey.sobol.nn@gmail.com>
This commit is contained in:
Andrey Sobol
Alan C. Assis
parent
3b1aea4bb0
commit
85041e1699
7 changed files with 1334 additions and 12 deletions
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@ -116,6 +116,7 @@ endif # STM32_HRTIM_DAC
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config STM32_DAC1CH1_TIMER
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int "DAC1CH1 timer"
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depends on !STM32_DAC1CH1_DMA_EXTERNAL
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range 1 15 if ARCH_CHIP_STM32H7
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range 2 8
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config STM32_DAC1CH1_TIMER_FREQUENCY
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@ -177,6 +178,7 @@ endif # STM32_HRTIM_DAC
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config STM32_DAC1CH2_TIMER
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int "DAC1CH2 timer"
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depends on !STM32_DAC1CH2_DMA_EXTERNAL
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range 1 15 if ARCH_CHIP_STM32H7
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range 2 8
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config STM32_DAC1CH2_TIMER_FREQUENCY
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@ -946,6 +946,7 @@ config STM32_HAVE_TIM_DAC_TRIGGER
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default y if STM32_COMMON_LEGACY
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default y if ARCH_CHIP_STM32F7
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default y if STM32_COMMON_L4_L5_U5
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default y if ARCH_CHIP_STM32H7
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config STM32_HAVE_TIM1
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bool
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@ -51,6 +51,7 @@ config STM32_H7_PERIPHERALS
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select STM32_HAVE_USART_RXFIFO_THRESHOLD
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select STM32_HAVE_FDCAN_H7
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select STM32_HAVE_IP_WDG_M3M4_V1
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select STM32_HAVE_DAC1
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choice
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prompt "STM32 H7 Chip Selection"
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@ -75,6 +75,10 @@ ifeq ($(CONFIG_STM32_ADC),y)
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CHIP_CSRCS += stm32_adc.c
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endif
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ifeq ($(CONFIG_STM32_DAC),y)
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CHIP_CSRCS += stm32_dac.c
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endif
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ifeq ($(CONFIG_STM32_FDCAN),y)
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CHIP_CSRCS += stm32_fdcan_sock.c
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endif
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@ -87,22 +87,22 @@
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#define DAC_CR_EN1 (1 << 0) /* Bit 0: ch1 enable */
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#define DAC_CR_TEN1 (1 << 1) /* Bit 1: ch1 trigger enable */
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#define DAC_CR_TSEL1_SHIFT (1 << 2) /* Bits 5-2: ch1 trigger sel */
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#define DAC_CR_TSEL1_SHIFT (2) /* Bits 5-2: ch1 trigger sel */
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#define DAC_CR_TSEL1_MASK (15 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_WAVE1_SHIFT (1 << 6) /* Bits 7-6: ch1 wave enable */
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#define DAC_CR_WAVE1_SHIFT (6) /* Bits 7-6: ch1 wave enable */
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#define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT)
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#define DAC_CR_MAMP1_SHIFT (1 << 8) /* Bits 11-8: ch1 mask/amplitude */
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#define DAC_CR_MAMP1_SHIFT (8) /* Bits 11-8: ch1 mask/amplitude */
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#define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: ch1 dma enable */
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#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: ch1 dma underrun interrupt enable */
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#define DAC_CR_CEN1 (1 << 14) /* Bit 14: ch1 calibration enable */
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#define DAC_CR_EN2 (1 << 16) /* Bit 16: ch2 enable */
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#define DAC_CR_TEN2 (1 << 17) /* Bit 17: ch2 trigger enable */
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#define DAC_CR_TSEL2_SHIFT (1 << 18) /* Bits 28-21: ch2 trigger sel */
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#define DAC_CR_TSEL2_SHIFT (8) /* Bits 28-21: ch2 trigger sel */
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#define DAC_CR_TSEL2_MASK (15 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_WAVE2_SHIFT (1 << 22) /* Bits 23-22: ch2 wave enable */
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#define DAC_CR_WAVE2_SHIFT (22) /* Bits 23-22: ch2 wave enable */
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#define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT)
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#define DAC_CR_MAMP2_SHIFT (1 << 24) /* Bits 27-24: ch2 mask/amplitude */
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#define DAC_CR_MAMP2_SHIFT (24) /* Bits 27-24: ch2 mask/amplitude */
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#define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: ch2 dma enable */
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#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: ch2 dma underrun interrupt enable */
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@ -123,19 +123,19 @@
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#define DAC_SR_BWST2 (1 << 31) /* Bit 31: ch2 busy writing */
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/* DAC mode control register */
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#define DAC_MCR_MODE1_SHIFT (1 << 0) /* Bits 2-0: ch1 mode */
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#define DAC_MCR_MODE1_SHIFT (0) /* Bits 2-0: ch1 mode */
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#define DAC_MCR_MODE1_MASK (7 << DAC_MCR_MODE1_SHIFT)
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#define DAC_MCR_MODE1_NORM (4 << DAC_MCR_MODE1_SHIFT) /* ch1 normal mode */
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#define DAC_MCR_MODE1_SAMPLE_HOLD (0 << DAC_MCR_MODE1_SHIFT) /* ch1 sample and hold mode */
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#define DAC_MCR_MODE1_DIS_BUFFER (2 << DAC_MCR_MODE1_SHIFT) /* ch1 buffer disabled */
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#define DAC_MCR_MODE1_EXT (0 << DAC_MCR_MODE1_SHIFT) /* ch1 to external pin */
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#define DAC_MCR_MODE1_ON_CHIP (1 << DAC_MCR_MODE1_SHIFT) /* ch1 to on chip and external */
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#define DAC_MCR_MODE2_SHIFT (1 << 16) /* Bits 18-16: ch2 mode */
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#define DAC_MCR_MODE1_EXT (1 << DAC_MCR_MODE1_SHIFT) /* ch1 to external pin */
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#define DAC_MCR_MODE1_ON_CHIP (5 << DAC_MCR_MODE1_SHIFT) /* ch1 to on chip and external */
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#define DAC_MCR_MODE2_SHIFT (16) /* Bits 18-16: ch2 mode */
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#define DAC_MCR_MODE2_MASK (7 << DAC_MCR_MODE2_SHIFT)
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#define DAC_MCR_MODE2_NORM (4 << DAC_MCR_MODE2_SHIFT) /* ch2 normal mode */
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#define DAC_MCR_MODE2_SAMPLE_HOLD (0 << DAC_MCR_MODE2_SHIFT) /* ch2 sample and hold mode */
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#define DAC_MCR_MODE2_DIS_BUFFER (2 << DAC_MCR_MODE2_SHIFT) /* ch2 buffer disabled */
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#define DAC_MCR_MODE2_EXT (0 << DAC_MCR_MODE2_SHIFT) /* ch2 to external pin */
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#define DAC_MCR_MODE2_ON_CHIP (1 << DAC_MCR_MODE2_SHIFT) /* ch2 to on chip and external */
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#define DAC_MCR_MODE2_EXT (1 << DAC_MCR_MODE2_SHIFT) /* ch2 to external pin */
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#define DAC_MCR_MODE2_ON_CHIP (5 << DAC_MCR_MODE2_SHIFT) /* ch2 to on chip and external */
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#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_DAC_H */
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1132
arch/arm/src/stm32h7/stm32_dac.c
Normal file
1132
arch/arm/src/stm32h7/stm32_dac.c
Normal file
File diff suppressed because it is too large
Load diff
182
arch/arm/src/stm32h7/stm32_dac.h
Normal file
182
arch/arm/src/stm32h7/stm32_dac.h
Normal file
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@ -0,0 +1,182 @@
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/****************************************************************************
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* arch/arm/src/stm32h7/stm32_dac.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32H7_DAC_H
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#define __ARCH_ARM_SRC_STM32_STM32H7_DAC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "hardware/stm32_dac.h"
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#include <nuttx/analog/dac.h>
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/****************************************************************************
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* Pre-processor definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is
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* to control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then
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* CONFIG_STM32_TIMn_DAC must also be defined to indicate that timer "n"
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* is intended to be used for that purpose.
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*/
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#ifndef CONFIG_STM32_TIM1
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# undef CONFIG_STM32_TIM1_DAC
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#endif
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#ifndef CONFIG_STM32_TIM2
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# undef CONFIG_STM32_TIM2_DAC
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#endif
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#ifndef CONFIG_STM32_TIM3
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# undef CONFIG_STM32_TIM3_DAC
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#endif
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#ifndef CONFIG_STM32_TIM4
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# undef CONFIG_STM32_TIM4_DAC
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#endif
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#ifndef CONFIG_STM32_TIM5
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# undef CONFIG_STM32_TIM5_DAC
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#endif
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#ifndef CONFIG_STM32_TIM6
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# undef CONFIG_STM32_TIM6_DAC
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#endif
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#ifndef CONFIG_STM32_TIM7
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# undef CONFIG_STM32_TIM7_DAC
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#endif
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#ifndef CONFIG_STM32_TIM8
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# undef CONFIG_STM32_TIM8_DAC
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#endif
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#ifndef CONFIG_STM32_TIM15
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# undef CONFIG_STM32_TIM15_DAC
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#endif
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#ifndef CONFIG_STM32_TIM16
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# undef CONFIG_STM32_TIM16_DAC
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#endif
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#ifndef CONFIG_STM32_TIM17
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# undef CONFIG_STM32_TIM17_DAC
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#endif
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/* Low-level ops helpers ****************************************************/
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#define DAC_ENABLE(dac,d) \
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(dac)->llops->enable(dac,d)
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#define DAC_WRITE_DRO(dac,d) \
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(dac)->llops->write_dro(dac,d)
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#define DAC_START_DMA(dac) \
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(dac)->llops->start_dma(dac)
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#define DAC_STOP_DMA(dac) \
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(dac)->llops->stop_dma(dac)
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#define DAC_DUMP_REGS(dac) \
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(dac)->llops->dump_regs(dac)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifdef CONFIG_STM32_DAC_LL_OPS
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/* This structure provides the publicly visible representation of the
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* "lower-half" DAC driver structure.
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*/
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struct stm32_dac_dev_s
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{
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/* Publicly visible portion of the "lower-half" ADC driver structure */
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const struct stm32_dac_ops_s *llops;
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/* Require cast-compatibility with private "lower-half" ADC structure */
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};
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/* Low-level operations for DAC */
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struct stm32_dac_ops_s
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{
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/* Enable / Disable DAC */
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void (*enable)(struct stm32_dac_dev_s *dev, bool enabled);
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/* Write DRO */
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void (*write_dro)(struct stm32_dac_dev_s *dev, uint16_t data);
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/* Start DMA */
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void (*start_dma)(struct stm32_dac_dev_s *dev);
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/* Stop DMA */
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void (*stop_dma)(struct stm32_dac_dev_s *dev);
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/* Dump DAC regs */
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void (*dump_regs)(struct stm32_dac_dev_s *dev);
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};
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#endif /* CONFIG_STM32_DAC_LL_OPS */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: stm32_dacinitialize
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*
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* Description:
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* Initialize the DAC
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*
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* Input Parameters:
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* intf - The DAC interface number.
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*
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* Returned Value:
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* Valid dac device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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struct dac_dev_s;
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struct dac_dev_s *stm32_dacinitialize(int intf);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_STM32_STM32H7_DAC_H */
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