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arch/mips/pic32mz: add PHY ioctls and link interrupts to the Ethernet driver.
The driver had no d_ioctl, so CONFIG_NETDEV_PHY_IOCTL had no effect. Implement SIOCGMIIPHY, SIOCGMIIREG and SIOCSMIIREG and, with CONFIG_ARCH_PHY_INTERRUPT, SIOCMIINOTIFY. SIOCMIINOTIFY subscribes through phy_notify_subscribe() (the board provides arch_phy_irq()) and enables the PHY link down and auto-negotiation complete interrupts. This is what CONFIG_NETINIT_MONITOR needs. The PHY interrupt is implemented for the LAN8720 and LAN8740; add their interrupt source/mask register bits to mii.h. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
This commit is contained in:
Daniel P. Carvalho
Alan C. Assis
parent
ea65363d57
commit
81f3d7443d
2 changed files with 152 additions and 0 deletions
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@ -46,6 +46,10 @@
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#include <nuttx/net/ip.h>
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#include <nuttx/net/netdev.h>
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#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
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# include <nuttx/net/phy.h>
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#endif
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#ifdef CONFIG_NET_PKT
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# include <nuttx/net/pkt.h>
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#endif
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@ -284,6 +288,16 @@
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# undef PIC32MZ_HAVE_PHY
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#endif
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/* PHY interrupt source/mask registers and the link up/down events */
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#if defined(CONFIG_ETH0_PHY_LAN8720) || defined(CONFIG_ETH0_PHY_LAN8740) || \
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defined(CONFIG_ETH0_PHY_LAN8740A)
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# define PIC32MZ_PHY_ISR MII_LAN8720_ISR
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# define PIC32MZ_PHY_IMR MII_LAN8720_IMR
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# define PIC32MZ_PHY_INTEN (MII_LAN8720_INT_LINKDOWN | \
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MII_LAN8720_INT_ANCOMPLETE)
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#endif
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/* These definitions are used to remember the speed/duplex settings */
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#define PIC32MZ_SPEED_MASK 0x01
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@ -471,6 +485,10 @@ static int pic32mz_txavail(struct net_driver_s *dev);
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static int pic32mz_addmac(struct net_driver_s *dev, const uint8_t *mac);
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static int pic32mz_rmmac(struct net_driver_s *dev, const uint8_t *mac);
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#endif
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#if defined(CONFIG_NETDEV_IOCTL) && defined(PIC32MZ_HAVE_PHY)
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static int pic32mz_ioctl(struct net_driver_s *dev, int cmd,
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unsigned long arg);
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#endif
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/* PHY initialization functions */
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@ -492,6 +510,9 @@ static inline int pic32mz_phyautoneg(uint8_t phyaddr);
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static int pic32mz_phymode(uint8_t phyaddr, uint8_t mode);
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# endif
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static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv);
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# if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
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static int pic32mz_phyintenable(struct pic32mz_driver_s *priv);
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# endif
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#else
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# define pic32mz_phyinit(priv)
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#endif
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@ -2556,6 +2577,94 @@ static int pic32mz_rmmac(struct net_driver_s *dev, const uint8_t *mac)
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}
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#endif
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/****************************************************************************
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* Function: pic32mz_ioctl
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*
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* Description:
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* Handle network IOCTL commands directed to this device.
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*
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* Input Parameters:
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* dev - Reference to the NuttX driver state structure
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* cmd - The IOCTL command
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* arg - The argument for the IOCTL command
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*
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* Returned Value:
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* OK on success; Negated errno on failure.
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*
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* Assumptions:
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* The network device is locked.
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*
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****************************************************************************/
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#if defined(CONFIG_NETDEV_IOCTL) && defined(PIC32MZ_HAVE_PHY)
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static int pic32mz_ioctl(struct net_driver_s *dev, int cmd,
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unsigned long arg)
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{
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#ifdef CONFIG_NETDEV_PHY_IOCTL
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struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)dev->d_private;
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#endif
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int ret;
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switch (cmd)
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{
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#ifdef CONFIG_NETDEV_PHY_IOCTL
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#ifdef CONFIG_ARCH_PHY_INTERRUPT
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case SIOCMIINOTIFY: /* Set up for PHY event notifications */
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{
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struct mii_ioctl_notify_s *req =
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(struct mii_ioctl_notify_s *)((uintptr_t)arg);
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ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
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if (ret == OK)
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{
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/* Enable PHY link up/down interrupts */
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ret = pic32mz_phyintenable(priv);
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}
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}
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break;
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#endif
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case SIOCGMIIPHY: /* Get MII PHY address */
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{
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struct mii_ioctl_data_s *req =
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(struct mii_ioctl_data_s *)((uintptr_t)arg);
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req->phy_id = priv->pd_phyaddr;
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ret = OK;
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}
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break;
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case SIOCGMIIREG: /* Get register from MII PHY */
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{
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struct mii_ioctl_data_s *req =
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(struct mii_ioctl_data_s *)((uintptr_t)arg);
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req->val_out = pic32mz_phyread(req->phy_id, req->reg_num);
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ret = OK;
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}
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break;
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case SIOCSMIIREG: /* Set register in MII PHY */
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{
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struct mii_ioctl_data_s *req =
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(struct mii_ioctl_data_s *)((uintptr_t)arg);
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pic32mz_phywrite(req->phy_id, req->reg_num, req->val_in);
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ret = OK;
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}
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break;
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#endif /* CONFIG_NETDEV_PHY_IOCTL */
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default:
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ret = -ENOTTY;
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break;
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}
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return ret;
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}
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#endif
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/****************************************************************************
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* Name: pic32mz_showmii
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*
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@ -2587,6 +2696,36 @@ static void pic32mz_showmii(uint8_t phyaddr, const char *msg)
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}
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#endif
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/****************************************************************************
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* Function: pic32mz_phyintenable
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*
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* Description:
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* Enable the PHY link up/down interrupts. Reading the interrupt source
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* register clears any pending event, so the PHY interrupt output is
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* released before the new events are enabled.
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*
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* Input Parameters:
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* priv - A reference to the private driver state structure
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*
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* Returned Value:
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* OK on success; -ENOSYS if the PHY interrupts are not supported.
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*
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****************************************************************************/
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#if defined(PIC32MZ_HAVE_PHY) && defined(CONFIG_NETDEV_PHY_IOCTL) && \
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defined(CONFIG_ARCH_PHY_INTERRUPT)
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static int pic32mz_phyintenable(struct pic32mz_driver_s *priv)
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{
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#ifdef PIC32MZ_PHY_INTEN
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pic32mz_phyread(priv->pd_phyaddr, PIC32MZ_PHY_ISR);
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pic32mz_phywrite(priv->pd_phyaddr, PIC32MZ_PHY_IMR, PIC32MZ_PHY_INTEN);
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return OK;
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#else
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return -ENOSYS;
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#endif
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}
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#endif
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/****************************************************************************
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* Function: pic32mz_phybusywait
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*
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@ -3395,6 +3534,9 @@ static inline int pic32mz_ethinitialize(int intf)
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#ifdef CONFIG_NET_MCASTGROUP
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priv->pd_dev.d_addmac = pic32mz_addmac; /* Add multicast MAC address */
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priv->pd_dev.d_rmmac = pic32mz_rmmac; /* Remove multicast MAC address */
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#endif
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#if defined(CONFIG_NETDEV_IOCTL) && defined(PIC32MZ_HAVE_PHY)
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priv->pd_dev.d_ioctl = pic32mz_ioctl; /* Support PHY ioctl() calls */
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#endif
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priv->pd_dev.d_private = priv; /* Used to recover private state from dev */
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@ -468,6 +468,16 @@
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#define MII_LAN8720_SPSCR_GPIO1 (1 << 8) /* Bit 8: GPIO1 */
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#define MII_LAN8720_SPSCR_GPIO2 (1 << 9) /* Bit 9: GPIO2 */
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/* Bit 10-11: Reserved */
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/* SMSC LAN8720 ISR and IMR register bits (same layout on the LAN8740) */
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#define MII_LAN8720_INT_ANPAGE (1 << 1) /* Bit 1: Auto-negotiation page received */
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#define MII_LAN8720_INT_PDFAULT (1 << 2) /* Bit 2: Parallel detection fault */
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#define MII_LAN8720_INT_ANLPACK (1 << 3) /* Bit 3: Auto-negotiation LP acknowledge */
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#define MII_LAN8720_INT_LINKDOWN (1 << 4) /* Bit 4: Link down */
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#define MII_LAN8720_INT_REMFAULT (1 << 5) /* Bit 5: Remote fault detected */
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#define MII_LAN8720_INT_ANCOMPLETE (1 << 6) /* Bit 6: Auto-negotiation complete */
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#define MII_LAN8720_INT_ENERGYON (1 << 7) /* Bit 7: ENERGYON generated */
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#define MII_LAN8720_SPSCR_ANEGDONE (1 << 12) /* Bit 12: Autonegotiation complete */
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/* Bits 13-15: Reserved */
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