diff --git a/arch/arm/include/imxrt/chip.h b/arch/arm/include/imxrt/chip.h index 40cdc557049..82e2218bbe0 100644 --- a/arch/arm/include/imxrt/chip.h +++ b/arch/arm/include/imxrt/chip.h @@ -84,6 +84,11 @@ /* MIMXRT1170DVMA TODO */ # define IMXRT_GPIO_NPORTS 13 /* Thirteen total ports */ +#elif defined(CONFIG_ARCH_CHIP_MIMXRT1189CVM8C) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33) +/* MIMXRT1189CVM8C - Dual-core Cortex-M33 + Cortex-M7 */ + +# define IMXRT_GPIO_NPORTS 6 /* Six general purpose GPIO ports */ #else # error "Unknown i.MX RT chip type" #endif diff --git a/arch/arm/src/imxrt/CMakeLists.txt b/arch/arm/src/imxrt/CMakeLists.txt index b17af15dd10..aeb4e487941 100644 --- a/arch/arm/src/imxrt/CMakeLists.txt +++ b/arch/arm/src/imxrt/CMakeLists.txt @@ -24,7 +24,11 @@ # Required i.MX RT files -set(SRCS imxrt_allocateheap.c imxrt_start.c imxrt_periphclks.c) +set(SRCS imxrt_allocateheap.c imxrt_start.c) + +if(NOT CONFIG_IMXRT_RGPIO) + list(APPEND SRCS imxrt_periphclks.c) +endif() if(CONFIG_IMXRT_PROGMEM) list(APPEND SRCS imxrt_flash.c) @@ -35,14 +39,18 @@ list( SRCS imxrt_irq.c imxrt_clrpend.c - imxrt_gpio.c - imxrt_daisy.c imxrt_wdog.c imxrt_serial.c imxrt_xbar.c imxrt_ocotp.c imxrt_lowputc.c) +if(CONFIG_IMXRT_RGPIO) + list(APPEND SRCS imxrt_rgpio.c) +else() + list(APPEND SRCS imxrt_gpio.c imxrt_daisy.c) +endif() + # Configuration-dependent i.MX RT files if(CONFIG_IMXRT_CLOCKCONFIG_VER3) @@ -53,7 +61,9 @@ else() list(APPEND SRCS imxrt_clockconfig_ver1.c) endif() -if(CONFIG_IMXRT_IOMUX_VER2) +if(CONFIG_IMXRT_IOMUX_VER3) + list(APPEND SRCS imxrt_iomuxc_ver3.c) +elseif(CONFIG_IMXRT_IOMUX_VER2) list(APPEND SRCS imxrt_iomuxc_ver2.c) else() list(APPEND SRCS imxrt_iomuxc_ver1.c) @@ -70,7 +80,11 @@ else() endif() if(CONFIG_IMXRT_GPIO_IRQ) - list(APPEND SRCS imxrt_gpioirq.c) + if(CONFIG_IMXRT_RGPIO) + list(APPEND SRCS imxrt_rgpioirq.c) + else() + list(APPEND SRCS imxrt_gpioirq.c) + endif() endif() if(CONFIG_ARM_MPU) diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index fd46a6dc4a7..072575db570 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -235,6 +235,8 @@ config ARCH_FAMILY_IMXRT118x select IMXRT_HAVE_LPUART11 select IMXRT_HAVE_LPUART12 select IMXRT_CLOCKCONFIG_VER3 + select IMXRT_IOMUX_VER3 + select IMXRT_RGPIO ---help--- i.MX RT1180 dual-core Crossover Processors (Cortex-M33 + Cortex-M7). @@ -417,6 +419,19 @@ config IMXRT_IOMUX_VER2 bool default n +config IMXRT_IOMUX_VER3 + bool + default n + ---help--- + Selects the "generation 3" IOMUXC driver used by RT118x. + +config IMXRT_RGPIO + bool + default n + ---help--- + Selects the RGPIO driver (arch/arm/src/imxrt/imxrt_rgpio.c) that + targets the RGPIO IP block used on RT118x. + config IMXRT_TRDC bool default n @@ -2451,42 +2466,52 @@ if IMXRT_GPIO_IRQ config IMXRT_GPIO1_0_15_IRQ bool "GPIO1 Pins 0-15 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO1_16_31_IRQ bool "GPIO1 Pins 16-31 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO2_0_15_IRQ bool "GPIO2 Pins 0-15 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO2_16_31_IRQ bool "GPIO2 Pins 16-31 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO3_0_15_IRQ bool "GPIO3 Pins 0-15 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO3_16_31_IRQ bool "GPIO3 Pins 16-31 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO4_0_15_IRQ bool "GPIO4 Pins 0-15 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO4_16_31_IRQ bool "GPIO4 Pins 16-31 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO5_0_15_IRQ bool "GPIO5 Pins 0-15 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO5_16_31_IRQ bool "GPIO5 Pins 16-31 interrupts" default n + depends on !IMXRT_RGPIO config IMXRT_GPIO6_0_15_IRQ bool "GPIO6 Pins 0-15 interrupts" diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs index ab93227b025..84d74cd4b23 100644 --- a/arch/arm/src/imxrt/Make.defs +++ b/arch/arm/src/imxrt/Make.defs @@ -30,13 +30,22 @@ endif # Required i.MX RT files -CHIP_CSRCS = imxrt_allocateheap.c imxrt_start.c imxrt_periphclks.c +CHIP_CSRCS = imxrt_allocateheap.c imxrt_start.c +ifneq ($(CONFIG_IMXRT_RGPIO),y) +CHIP_CSRCS += imxrt_periphclks.c +endif ifeq ($(CONFIG_IMXRT_PROGMEM),y) CHIP_CSRCS += imxrt_flash.c endif -CHIP_CSRCS += imxrt_irq.c imxrt_clrpend.c imxrt_gpio.c -CHIP_CSRCS += imxrt_daisy.c imxrt_wdog.c imxrt_serial.c -CHIP_CSRCS += imxrt_xbar.c imxrt_ocotp.c imxrt_lowputc.c +CHIP_CSRCS += imxrt_irq.c imxrt_clrpend.c +ifeq ($(CONFIG_IMXRT_RGPIO),y) +CHIP_CSRCS += imxrt_rgpio.c +else +CHIP_CSRCS += imxrt_gpio.c +CHIP_CSRCS += imxrt_daisy.c +endif +CHIP_CSRCS += imxrt_wdog.c imxrt_serial.c imxrt_xbar.c imxrt_ocotp.c +CHIP_CSRCS += imxrt_lowputc.c # Configuration-dependent i.MX RT files @@ -48,7 +57,9 @@ else CHIP_CSRCS += imxrt_clockconfig_ver1.c endif -ifeq ($(CONFIG_IMXRT_IOMUX_VER2),y) +ifeq ($(CONFIG_IMXRT_IOMUX_VER3),y) +CHIP_CSRCS += imxrt_iomuxc_ver3.c +else ifeq ($(CONFIG_IMXRT_IOMUX_VER2),y) CHIP_CSRCS += imxrt_iomuxc_ver2.c else CHIP_CSRCS += imxrt_iomuxc_ver1.c @@ -65,8 +76,12 @@ CHIP_CSRCS += imxrt_tickless.c endif ifeq ($(CONFIG_IMXRT_GPIO_IRQ),y) +ifeq ($(CONFIG_IMXRT_RGPIO),y) +CHIP_CSRCS += imxrt_rgpioirq.c +else CHIP_CSRCS += imxrt_gpioirq.c endif +endif ifeq ($(CONFIG_ARM_MPU),y) CHIP_CSRCS += imxrt_mpuinit.c diff --git a/arch/arm/src/imxrt/hardware/imxrt_gpio.h b/arch/arm/src/imxrt/hardware/imxrt_gpio.h index 41b439f19f8..a522be745e0 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_gpio.h +++ b/arch/arm/src/imxrt/hardware/imxrt_gpio.h @@ -37,6 +37,8 @@ # include "hardware/rt106x/imxrt106x_gpio.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x) # include "hardware/rt117x/imxrt117x_gpio.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# include "hardware/imxrt_memorymap.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h index 8d307b47e00..09100656450 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h @@ -30,10 +30,13 @@ #include /* IMXRT117X IOMUX Differs too much from IMXRT10XX - * hence we use a VER2 driver + * hence we use a VER2 driver. IMXRT118x uses another (generation 3) + * IOMUXC IP; that is IMXRT_IOMUX_VER3. */ -#ifdef CONFIG_IMXRT_IOMUX_VER2 +#ifdef CONFIG_IMXRT_IOMUX_VER3 +#include "imxrt_iomuxc_ver3.h" +#elif defined(CONFIG_IMXRT_IOMUX_VER2) #include "imxrt_iomuxc_ver2.h" #else #include "imxrt_iomuxc_ver1.h" diff --git a/arch/arm/src/imxrt/hardware/imxrt_pinmux.h b/arch/arm/src/imxrt/hardware/imxrt_pinmux.h index 2518ea4f4fa..1c66fb1edc7 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_pinmux.h +++ b/arch/arm/src/imxrt/hardware/imxrt_pinmux.h @@ -37,6 +37,8 @@ # include "hardware/rt106x/imxrt106x_pinmux.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x) # include "hardware/rt117x/imxrt117x_pinmux.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# include "hardware/rt118x/imxrt118x_pinmux.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpio.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpio.h new file mode 100644 index 00000000000..688b675ded8 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpio.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPIO_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/imxrt_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RGPIO register offsets (IMXRT1180RM chapter 16) **************************/ + +#define IMXRT_GPIO_VERID_OFFSET (0x0000) /* Version ID */ +#define IMXRT_GPIO_PARAM_OFFSET (0x0004) /* Parameter */ +#define IMXRT_GPIO_LOCK_OFFSET (0x000c) /* Lock */ +#define IMXRT_GPIO_PCNS_OFFSET (0x0010) /* Pin Control Nonsecure */ +#define IMXRT_GPIO_ICNS_OFFSET (0x0014) /* Interrupt Control Nonsecure */ +#define IMXRT_GPIO_PCNP_OFFSET (0x0018) /* Pin Control Nonprivilege */ +#define IMXRT_GPIO_ICNP_OFFSET (0x001c) /* Interrupt Control Nonprivilege */ +#define IMXRT_GPIO_PDOR_OFFSET (0x0040) /* Port Data Output */ +#define IMXRT_GPIO_PSOR_OFFSET (0x0044) /* Port Set Output */ +#define IMXRT_GPIO_PCOR_OFFSET (0x0048) /* Port Clear Output */ +#define IMXRT_GPIO_PTOR_OFFSET (0x004c) /* Port Toggle Output */ +#define IMXRT_GPIO_PDIR_OFFSET (0x0050) /* Port Data Input */ +#define IMXRT_GPIO_PDDR_OFFSET (0x0054) /* Port Data Direction */ +#define IMXRT_GPIO_PIDR_OFFSET (0x0058) /* Port Input Disable */ +#define IMXRT_GPIO_P0DR_OFFSET (0x0060) /* Pin Data (0-31 at n * 4h) */ +#define IMXRT_GPIO_ICR0_OFFSET (0x0080) /* Interrupt Control (0-31 at n * 4h) */ +#define IMXRT_GPIO_GICLR_OFFSET (0x0100) /* Global Interrupt Control Low */ +#define IMXRT_GPIO_GICHR_OFFSET (0x0104) /* Global Interrupt Control High */ +#define IMXRT_GPIO_ISFR0_OFFSET (0x0120) /* Interrupt Status Flag 0 (0..15) */ +#define IMXRT_GPIO_ISFR1_OFFSET (0x0124) /* Interrupt Status Flag 1 (16..31) */ + +/* GPIO port enumeration ****************************************************/ + +#define GPIO1 0 +#define GPIO2 1 +#define GPIO3 2 +#define GPIO4 3 +#define GPIO5 4 +#define GPIO6 5 + +#define IMXRT_GPIO_NPORTS 6 +#define IMXRT_GPIO_NPINS 32 + +/* Register bit definitions *************************************************/ + +/* Most registers are laid out simply with one bit per pin */ + +#define GPIO_PIN(n) (1u << (n)) /* Bit n: Pin n, n=0-31 */ + +/* ICRN register (per-pin interrupt configuration) */ + +#define IMXRT_GPIO_ICRN_ISF (1u << 24) /* Bit 24: Interrupt Status Flag */ +#define IMXRT_GPIO_ICRN_LK (1u << 23) /* Bit 23: Lock */ +#define IMXRT_GPIO_ICRN_IRQS (1u << 20) /* Bit 20: Selects the interrupt/DMA channel */ +#define IMXRT_GPIO_ICRN_SHIFT (16) /* Bits 16-19: Interrupt Configuration */ +#define IMXRT_GPIO_ICRN_MASK (0xfu << IMXRT_GPIO_ICRN_SHIFT) +# define IMXRT_GPIO_ICRN_DISABLED (0u << IMXRT_GPIO_ICRN_SHIFT) /* ISF disabled */ +# define IMXRT_GPIO_ICRN_DMARISING (1u << IMXRT_GPIO_ICRN_SHIFT) /* DMA rising */ +# define IMXRT_GPIO_ICRN_DMAFALLING (2u << IMXRT_GPIO_ICRN_SHIFT) /* DMA falling */ +# define IMXRT_GPIO_ICRN_DMABOTH (3u << IMXRT_GPIO_ICRN_SHIFT) /* DMA both */ +# define IMXRT_GPIO_ICRN_ISFRISING (5u << IMXRT_GPIO_ICRN_SHIFT) /* ISF-only rising */ +# define IMXRT_GPIO_ICRN_ISFFALLING (6u << IMXRT_GPIO_ICRN_SHIFT) /* ISF-only falling */ +# define IMXRT_GPIO_ICRN_ISFBOTH (7u << IMXRT_GPIO_ICRN_SHIFT) /* ISF-only both */ +# define IMXRT_GPIO_ICRN_ZERO (8u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ when 0 */ +# define IMXRT_GPIO_ICRN_RISING (9u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ rising */ +# define IMXRT_GPIO_ICRN_FALLING (10u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ falling */ +# define IMXRT_GPIO_ICRN_BOTH (11u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ both */ +# define IMXRT_GPIO_ICRN_ONE (12u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ when 1 */ + +/* Global Interrupt Control Low (pins 0..15) */ + +#define IMXRT_GPIO_GICLR_GIWD_SHIFT (0) +#define IMXRT_GPIO_GICLR_GIWD_MASK (0xffffu << IMXRT_GPIO_GICLR_GIWD_SHIFT) +# define IMXRT_GPIO_GICLR_GIWD_PIN(n) ((uint32_t)(n) << IMXRT_GPIO_GICLR_GIWD_SHIFT) +#define IMXRT_GPIO_GICLR_GIWE_SHIFT (16) +#define IMXRT_GPIO_GICLR_GIWE_MASK (0xffffu << IMXRT_GPIO_GICLR_GIWE_SHIFT) +# define IMXRT_GPIO_GICLR_GIWE_PIN(n) ((uint32_t)(n) << IMXRT_GPIO_GICLR_GIWE_SHIFT) + +/* Global Interrupt Control High (pins 16..31) */ + +#define IMXRT_GPIO_GICHR_GIWD_SHIFT (0) +#define IMXRT_GPIO_GICHR_GIWD_MASK (0xffffu << IMXRT_GPIO_GICHR_GIWD_SHIFT) +# define IMXRT_GPIO_GICHR_GIWD_PIN(n) ((uint32_t)((n) - 16) << IMXRT_GPIO_GICHR_GIWD_SHIFT) +#define IMXRT_GPIO_GICHR_GIWE_SHIFT (16) +#define IMXRT_GPIO_GICHR_GIWE_MASK (0xffffu << IMXRT_GPIO_GICHR_GIWE_SHIFT) +# define IMXRT_GPIO_GICHR_GIWE_PIN(n) ((uint32_t)((n) - 16) << IMXRT_GPIO_GICHR_GIWE_SHIFT) + +/* Interrupt Status Flag Register */ + +#define IMXRT_GPIO_ISFR(n) (1u << (n)) /* Interrupt Status Flag, n=0-31 */ + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPIO_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_iomuxc.h new file mode 100644 index 00000000000..b21a534f338 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_iomuxc.h @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_iomuxc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_IOMUXC_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IOMUXC register bit-fields (IMXRT1180RM chapter 17) + * + * SW_MUX_CTL_PAD register: + * [3:0] MUX_MODE (alternate function 0..12) + * [4] SION (force input path) + * + * SW_PAD_CTL_PAD register: + * [1] PDRV (0 = high driver, 1 = normal driver) + * [3:2] PULL (00 = keep, 01 = pull-up, 10 = pull-down, 11 = disabled) + * [4] ODE (open drain enable) + * [5] HYS (Schmitt trigger / hysteresis enable) + * [6] FSEL_APC (fast/slow slew select) + * [7] DDR_MODE (DDR input mode; only implemented on selected pads) + */ + +/* MUX_CTL fields */ + +#define IOMUXC_MUX_MODE_SHIFT (0) +#define IOMUXC_MUX_MODE_MASK (0x0fu << IOMUXC_MUX_MODE_SHIFT) +# define IOMUXC_MUX_MODE_ALT(n) (((n) & 0x0fu) << IOMUXC_MUX_MODE_SHIFT) +# define IOMUXC_MUX_MODE_ALT0 IOMUXC_MUX_MODE_ALT(0) +# define IOMUXC_MUX_MODE_ALT1 IOMUXC_MUX_MODE_ALT(1) +# define IOMUXC_MUX_MODE_ALT2 IOMUXC_MUX_MODE_ALT(2) +# define IOMUXC_MUX_MODE_ALT3 IOMUXC_MUX_MODE_ALT(3) +# define IOMUXC_MUX_MODE_ALT4 IOMUXC_MUX_MODE_ALT(4) +# define IOMUXC_MUX_MODE_ALT5 IOMUXC_MUX_MODE_ALT(5) +# define IOMUXC_MUX_MODE_ALT6 IOMUXC_MUX_MODE_ALT(6) +# define IOMUXC_MUX_MODE_ALT7 IOMUXC_MUX_MODE_ALT(7) +# define IOMUXC_MUX_MODE_ALT8 IOMUXC_MUX_MODE_ALT(8) +# define IOMUXC_MUX_MODE_ALT9 IOMUXC_MUX_MODE_ALT(9) +# define IOMUXC_MUX_MODE_ALT10 IOMUXC_MUX_MODE_ALT(10) +# define IOMUXC_MUX_MODE_ALT11 IOMUXC_MUX_MODE_ALT(11) +# define IOMUXC_MUX_MODE_ALT12 IOMUXC_MUX_MODE_ALT(12) + +#define IOMUXC_MUX_SION_SHIFT (4) +#define IOMUXC_MUX_SION_MASK (0x01u << IOMUXC_MUX_SION_SHIFT) +# define IOMUXC_MUX_SION_OFF (0u << IOMUXC_MUX_SION_SHIFT) +# define IOMUXC_MUX_SION_ON (1u << IOMUXC_MUX_SION_SHIFT) + +/* PAD_CTL fields */ + +#define IOMUXC_PAD_PDRV_SHIFT (1) +#define IOMUXC_PAD_PDRV_MASK (0x01u << IOMUXC_PAD_PDRV_SHIFT) +# define IOMUXC_PAD_PDRV_HIGH (0u << IOMUXC_PAD_PDRV_SHIFT) +# define IOMUXC_PAD_PDRV_NORMAL (1u << IOMUXC_PAD_PDRV_SHIFT) + +#define IOMUXC_PAD_PULL_SHIFT (2) +#define IOMUXC_PAD_PULL_MASK (0x03u << IOMUXC_PAD_PULL_SHIFT) +# define IOMUXC_PAD_PULL_KEEP (0u << IOMUXC_PAD_PULL_SHIFT) +# define IOMUXC_PAD_PULL_UP (1u << IOMUXC_PAD_PULL_SHIFT) +# define IOMUXC_PAD_PULL_DOWN (2u << IOMUXC_PAD_PULL_SHIFT) +# define IOMUXC_PAD_PULL_NONE (3u << IOMUXC_PAD_PULL_SHIFT) + +#define IOMUXC_PAD_ODE_SHIFT (4) +#define IOMUXC_PAD_ODE_MASK (0x01u << IOMUXC_PAD_ODE_SHIFT) +# define IOMUXC_PAD_ODE_OFF (0u << IOMUXC_PAD_ODE_SHIFT) +# define IOMUXC_PAD_ODE_ON (1u << IOMUXC_PAD_ODE_SHIFT) + +#define IOMUXC_PAD_HYS_SHIFT (5) +#define IOMUXC_PAD_HYS_MASK (0x01u << IOMUXC_PAD_HYS_SHIFT) +# define IOMUXC_PAD_HYS_OFF (0u << IOMUXC_PAD_HYS_SHIFT) +# define IOMUXC_PAD_HYS_ON (1u << IOMUXC_PAD_HYS_SHIFT) + +#define IOMUXC_PAD_FSEL_SHIFT (6) +#define IOMUXC_PAD_FSEL_MASK (0x01u << IOMUXC_PAD_FSEL_SHIFT) +# define IOMUXC_PAD_FSEL_SLOW (0u << IOMUXC_PAD_FSEL_SHIFT) +# define IOMUXC_PAD_FSEL_FAST (1u << IOMUXC_PAD_FSEL_SHIFT) + +#define IOMUXC_PAD_DDR_SHIFT (7) +#define IOMUXC_PAD_DDR_MASK (0x01u << IOMUXC_PAD_DDR_SHIFT) +# define IOMUXC_PAD_DDR_OFF (0u << IOMUXC_PAD_DDR_SHIFT) +# define IOMUXC_PAD_DDR_ON (1u << IOMUXC_PAD_DDR_SHIFT) + +/**************************************************************************** + * IMXRT_PADCFG packed encoding + **************************************************************************** + * + * The (mux/pad/daisy) register addresses for every RT1180 pin/alt combo can + * be derived from a single uint32_t using pure arithmetic, without any run- + * time look-up tables. The two IOMUXC instances on RT1180 (main IOMUXC at + * 0x42a1_0000 and AON IOMUXC at 0x443c_0000) each expose: + * + * MUX_CTL[i] = base + ctl_first + i * 4 (contiguous, verified) + * PAD_CTL[i] = MUX_CTL[i] + pad_delta (constant offset per bank) + * DAISY[j] = base + dsy_first + j * 4 (base offset differs; j + * may be sparse but is + * still expressible as an + * index into the daisy + * region) + * + * Constants per bank (from IMXRT1180RM Ch. 17): + * + * +---------------+---------+-----------+-----------+-----------+ + * | bank | ctl_bit | ctl_first | pad_delta | dsy_first | + * +---------------+---------+-----------+-----------+-----------+ + * | main IOMUXC | 0 | 0x010 | 0x248 | 0x4A0 | + * | AON IOMUXC | 1 | 0x000 | 0x074 | 0x0E8 | + * +---------------+---------+-----------+-----------+-----------+ + * + * PADCFG bit layout (LSB..MSB): + * + * bits 0- 2 dsy_val (3 b) value written to DAISY register + * bits 3- 8 reserved (6 b) must be zero + * bits 9-17 dsy_idx (9 b) DAISY[j]; IMXRT_PADCFG_NO_DSYIDX = none + * bits 18-21 mux_mode (4 b) ALT 0..12 + * bits 22-29 pad_idx (8 b) MUX_CTL[i] where i = pad_idx + * bit 30 dsy_bank (1 b) 0 = main IOMUXC, 1 = AON IOMUXC + * bit 31 pad_bank (1 b) 0 = main IOMUXC, 1 = AON IOMUXC + * + * Together with a two-entry bank descriptor (see imxrt_iomuxc.c) this + * encoding suffices to compute all three register addresses at run time + * with only shifts, masks, and a single indexed load of the descriptor + * struct. There is no per-pin ROM table. + */ + +#define IMXRT_PADCFG_PADBANK_SHIFT (31) +#define IMXRT_PADCFG_PADBANK_MASK (0x1u << IMXRT_PADCFG_PADBANK_SHIFT) + +#define IMXRT_PADCFG_DSYBANK_SHIFT (30) +#define IMXRT_PADCFG_DSYBANK_MASK (0x1u << IMXRT_PADCFG_DSYBANK_SHIFT) + +#define IMXRT_PADCFG_PADIDX_SHIFT (22) +#define IMXRT_PADCFG_PADIDX_MASK (0xffu << IMXRT_PADCFG_PADIDX_SHIFT) + +#define IMXRT_PADCFG_MUX_SHIFT (18) +#define IMXRT_PADCFG_MUX_MASK (0xfu << IMXRT_PADCFG_MUX_SHIFT) + +#define IMXRT_PADCFG_DSYIDX_SHIFT (9) +#define IMXRT_PADCFG_DSYIDX_MASK (0x1ffu << IMXRT_PADCFG_DSYIDX_SHIFT) + +/* Sentinel dsy_idx meaning "this pin/alt has no input daisy". */ + +#define IMXRT_PADCFG_NO_DSYIDX (0x1ffu) + +#define IMXRT_PADCFG_DSY_SHIFT (0) +#define IMXRT_PADCFG_DSY_MASK (0x7u << IMXRT_PADCFG_DSY_SHIFT) + +/* Compile-time packer used by the auto-generated imxrt118x_pinmux.h. */ + +#define IMXRT_PADCFG(_padbank, _padidx, _mux, _dsybank, _dsyidx, _dsy) \ + ((((uint32_t)(_padbank) & 0x1u) << IMXRT_PADCFG_PADBANK_SHIFT) | \ + (((uint32_t)(_dsybank) & 0x1u) << IMXRT_PADCFG_DSYBANK_SHIFT) | \ + (((uint32_t)(_padidx) & 0xffu) << IMXRT_PADCFG_PADIDX_SHIFT) | \ + (((uint32_t)(_mux) & 0xfu) << IMXRT_PADCFG_MUX_SHIFT) | \ + (((uint32_t)(_dsyidx) & 0x1ffu) << IMXRT_PADCFG_DSYIDX_SHIFT) | \ + (((uint32_t)(_dsy) & 0x7u) << IMXRT_PADCFG_DSY_SHIFT)) + +/* Field extraction helpers (used by the runtime driver). */ + +#define IMXRT_PADCFG_PADBANK(_v) \ + (((_v) & IMXRT_PADCFG_PADBANK_MASK) >> IMXRT_PADCFG_PADBANK_SHIFT) +#define IMXRT_PADCFG_DSYBANK(_v) \ + (((_v) & IMXRT_PADCFG_DSYBANK_MASK) >> IMXRT_PADCFG_DSYBANK_SHIFT) +#define IMXRT_PADCFG_PADIDX(_v) \ + (((_v) & IMXRT_PADCFG_PADIDX_MASK) >> IMXRT_PADCFG_PADIDX_SHIFT) +#define IMXRT_PADCFG_MUX(_v) \ + (((_v) & IMXRT_PADCFG_MUX_MASK) >> IMXRT_PADCFG_MUX_SHIFT) +#define IMXRT_PADCFG_DSYIDX(_v) \ + (((_v) & IMXRT_PADCFG_DSYIDX_MASK) >> IMXRT_PADCFG_DSYIDX_SHIFT) +#define IMXRT_PADCFG_DSY(_v) \ + (((_v) & IMXRT_PADCFG_DSY_MASK) >> IMXRT_PADCFG_DSY_SHIFT) + +/**************************************************************************** + * Bank descriptor type + ****************************************************************************/ + +#define IMXRT_PADCFG_NBANKS (2) +#define IMXRT_PADCFG_BANK_MAIN (0) +#define IMXRT_PADCFG_BANK_AON (1) + +#ifndef __ASSEMBLY__ + +struct imxrt_iomux_bank_s +{ + uint32_t base; /* IOMUXC instance base address */ + uint16_t ctl_first; /* Offset of MUX_CTL[0] within the bank */ + uint16_t pad_delta; /* pad_reg = mux_reg + pad_delta */ + uint16_t dsy_first; /* Offset of DAISY[0] within the bank */ +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_pinmux.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_pinmux.h new file mode 100644 index 00000000000..ff9e826f052 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_pinmux.h @@ -0,0 +1,1842 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_pinmux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_PINMUX_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/rt118x/imxrt118x_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Each IOMUXC_PAD__ constant is a packed uint32_t suitable for + * use as the padcfg argument of IOMUX_PIN(padcfg, pad_ctl, sion) or + * IOMUX_GPIO(padcfg, pad_ctl, gpio). The layout and packing is defined + * in imxrt118x_iomuxc.h. + */ + +#define IOMUXC_PAD_GPIO_EMC_B1_00_SEMC_DATA00 IMXRT_PADCFG(0, 0, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_XBAR1_XBAR_INOUT04 IMXRT_PADCFG(0, 0, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_SINC3_MOD_CLK0 IMXRT_PADCFG(0, 0, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_LPUART3_CTS_B IMXRT_PADCFG(0, 0, 0x3, 0, 119, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_NETC_PINMUX_ETH3_TXD03 IMXRT_PADCFG(0, 0, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_GPIO2_IO00 IMXRT_PADCFG(0, 0, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_KPP_ROW03 IMXRT_PADCFG(0, 0, 0x6, 0, 77, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00 IMXRT_PADCFG(0, 0, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_NETC_PINMUX_ETH4_TXD03 IMXRT_PADCFG(0, 0, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_ECAT_TX_DATA3_0 IMXRT_PADCFG(0, 0, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_AHB_SRAMC_DATA00 IMXRT_PADCFG(0, 0, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_01_SEMC_DATA01 IMXRT_PADCFG(0, 1, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_XBAR1_XBAR_INOUT05 IMXRT_PADCFG(0, 1, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_SINC3_MOD_CLK1 IMXRT_PADCFG(0, 1, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_LPUART3_RTS_B IMXRT_PADCFG(0, 1, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_NETC_PINMUX_ETH3_TXD02 IMXRT_PADCFG(0, 1, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_GPIO2_IO01 IMXRT_PADCFG(0, 1, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_KPP_COL03 IMXRT_PADCFG(0, 1, 0x6, 0, 69, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01 IMXRT_PADCFG(0, 1, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_NETC_PINMUX_ETH4_TXD02 IMXRT_PADCFG(0, 1, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_ECAT_TX_DATA2_0 IMXRT_PADCFG(0, 1, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_AHB_SRAMC_DATA01 IMXRT_PADCFG(0, 1, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_02_SEMC_DATA02 IMXRT_PADCFG(0, 2, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_XBAR1_XBAR_INOUT06 IMXRT_PADCFG(0, 2, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_SINC3_MOD_CLK2 IMXRT_PADCFG(0, 2, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_LPUART3_RX IMXRT_PADCFG(0, 2, 0x3, 0, 120, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_NETC_PINMUX_ETH3_RX_CLK IMXRT_PADCFG(0, 2, 0x4, 0, 222, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_GPIO2_IO02 IMXRT_PADCFG(0, 2, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_KPP_ROW02 IMXRT_PADCFG(0, 2, 0x6, 0, 76, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02 IMXRT_PADCFG(0, 2, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_NETC_PINMUX_ETH4_RX_CLK IMXRT_PADCFG(0, 2, 0x9, 0, 230, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_ECAT_RX_CLK_0 IMXRT_PADCFG(0, 2, 0xa, 0, 3, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_AHB_SRAMC_DATA02 IMXRT_PADCFG(0, 2, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_03_SEMC_DATA03 IMXRT_PADCFG(0, 3, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_XBAR1_XBAR_INOUT07 IMXRT_PADCFG(0, 3, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_SINC3_EMCLK00 IMXRT_PADCFG(0, 3, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_LPUART3_TX IMXRT_PADCFG(0, 3, 0x3, 0, 121, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_NETC_PINMUX_ETH3_RXD03 IMXRT_PADCFG(0, 3, 0x4, 0, 228, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_GPIO2_IO03 IMXRT_PADCFG(0, 3, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_KPP_COL02 IMXRT_PADCFG(0, 3, 0x6, 0, 68, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03 IMXRT_PADCFG(0, 3, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_NETC_PINMUX_ETH4_RXD03 IMXRT_PADCFG(0, 3, 0x9, 0, 236, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_ECAT_RX_DATA3_0 IMXRT_PADCFG(0, 3, 0xa, 0, 11, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_AHB_SRAMC_DATA03 IMXRT_PADCFG(0, 3, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_04_SEMC_DATA04 IMXRT_PADCFG(0, 4, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_XBAR1_XBAR_INOUT08 IMXRT_PADCFG(0, 4, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_SINC3_EMBIT00 IMXRT_PADCFG(0, 4, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_LPUART3_DSR_B IMXRT_PADCFG(0, 4, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_NETC_PINMUX_ETH3_RXD02 IMXRT_PADCFG(0, 4, 0x4, 0, 227, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_GPIO2_IO04 IMXRT_PADCFG(0, 4, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_KPP_ROW01 IMXRT_PADCFG(0, 4, 0x6, 0, 75, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04 IMXRT_PADCFG(0, 4, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_NETC_PINMUX_ETH4_RXD02 IMXRT_PADCFG(0, 4, 0x9, 0, 235, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_ECAT_RX_DATA2_0 IMXRT_PADCFG(0, 4, 0xa, 0, 9, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_AHB_SRAMC_DATA04 IMXRT_PADCFG(0, 4, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_05_SEMC_DATA05 IMXRT_PADCFG(0, 5, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_XBAR1_XBAR_INOUT09 IMXRT_PADCFG(0, 5, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_SINC3_EMCLK01 IMXRT_PADCFG(0, 5, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_LPUART3_DCD_B IMXRT_PADCFG(0, 5, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_NETC_PINMUX_ETH3_TXD00 IMXRT_PADCFG(0, 5, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_GPIO2_IO05 IMXRT_PADCFG(0, 5, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_KPP_ROW07 IMXRT_PADCFG(0, 5, 0x6, 0, 81, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05 IMXRT_PADCFG(0, 5, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_NETC_PINMUX_ETH4_TXD00 IMXRT_PADCFG(0, 5, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_ECAT_TX_DATA0_0 IMXRT_PADCFG(0, 5, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_AHB_SRAMC_DATA05 IMXRT_PADCFG(0, 5, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_06_SEMC_DATA06 IMXRT_PADCFG(0, 6, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_FLEXPWM4_PWMB03 IMXRT_PADCFG(0, 6, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_SINC3_EMBIT01 IMXRT_PADCFG(0, 6, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_LPUART3_RI_B IMXRT_PADCFG(0, 6, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_NETC_PINMUX_ETH3_TXD01 IMXRT_PADCFG(0, 6, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_GPIO2_IO06 IMXRT_PADCFG(0, 6, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_KPP_COL07 IMXRT_PADCFG(0, 6, 0x6, 0, 73, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06 IMXRT_PADCFG(0, 6, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_NETC_PINMUX_ETH4_TXD01 IMXRT_PADCFG(0, 6, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_ECAT_TX_DATA1_0 IMXRT_PADCFG(0, 6, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_AHB_SRAMC_DATA06 IMXRT_PADCFG(0, 6, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_07_SEMC_DATA07 IMXRT_PADCFG(0, 7, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_FLEXPWM4_PWMA03 IMXRT_PADCFG(0, 7, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_SINC3_EMCLK02 IMXRT_PADCFG(0, 7, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_LPUART3_DTR_B IMXRT_PADCFG(0, 7, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_NETC_PINMUX_ETH3_TX_EN IMXRT_PADCFG(0, 7, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_GPIO2_IO07 IMXRT_PADCFG(0, 7, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_KPP_ROW06 IMXRT_PADCFG(0, 7, 0x6, 0, 80, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07 IMXRT_PADCFG(0, 7, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_NETC_PINMUX_ETH4_TX_EN IMXRT_PADCFG(0, 7, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_ECAT_TX_EN_0 IMXRT_PADCFG(0, 7, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_AHB_SRAMC_DATA07 IMXRT_PADCFG(0, 7, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_08_SEMC_DM00 IMXRT_PADCFG(0, 8, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_FLEXPWM2_PWMB03 IMXRT_PADCFG(0, 8, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_SINC3_EMBIT02 IMXRT_PADCFG(0, 8, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_LPUART4_DSR_B IMXRT_PADCFG(0, 8, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_NETC_PINMUX_ETH3_TX_CLK IMXRT_PADCFG(0, 8, 0x4, 0, 229, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_GPIO2_IO08 IMXRT_PADCFG(0, 8, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_KPP_COL06 IMXRT_PADCFG(0, 8, 0x6, 0, 72, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08 IMXRT_PADCFG(0, 8, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_NETC_PINMUX_ETH4_TX_CLK IMXRT_PADCFG(0, 8, 0x9, 0, 237, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_ECAT_TX_CLK_0 IMXRT_PADCFG(0, 8, 0xa, 0, 17, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_AHB_SRAMC_LBB IMXRT_PADCFG(0, 8, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_09_SEMC_ADDR00 IMXRT_PADCFG(0, 9, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_FLEXPWM2_PWMA03 IMXRT_PADCFG(0, 9, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_SINC3_EMCLK03 IMXRT_PADCFG(0, 9, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_LPUART4_DCD_B IMXRT_PADCFG(0, 9, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_NETC_PINMUX_ETH3_RXD00 IMXRT_PADCFG(0, 9, 0x4, 0, 225, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_GPIO2_IO09 IMXRT_PADCFG(0, 9, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_KPP_ROW05 IMXRT_PADCFG(0, 9, 0x6, 0, 79, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09 IMXRT_PADCFG(0, 9, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_NETC_PINMUX_ETH4_RXD00 IMXRT_PADCFG(0, 9, 0x9, 0, 233, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_ECAT_RX_DATA0_0 IMXRT_PADCFG(0, 9, 0xa, 0, 5, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_AHB_SRAMC_ADDR00 IMXRT_PADCFG(0, 9, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_10_SEMC_ADDR01 IMXRT_PADCFG(0, 10, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_FLEXPWM3_PWMB03 IMXRT_PADCFG(0, 10, 0x1, 0, 40, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_SINC3_EMBIT03 IMXRT_PADCFG(0, 10, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_LPUART4_RI_B IMXRT_PADCFG(0, 10, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_NETC_PINMUX_ETH3_RXD01 IMXRT_PADCFG(0, 10, 0x4, 0, 226, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_GPIO2_IO10 IMXRT_PADCFG(0, 10, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_KPP_COL05 IMXRT_PADCFG(0, 10, 0x6, 0, 71, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10 IMXRT_PADCFG(0, 10, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_NETC_PINMUX_ETH4_RXD01 IMXRT_PADCFG(0, 10, 0x9, 0, 234, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_ECAT_RX_DATA1_0 IMXRT_PADCFG(0, 10, 0xa, 0, 7, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_AHB_SRAMC_ADDR01 IMXRT_PADCFG(0, 10, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_11_SEMC_ADDR02 IMXRT_PADCFG(0, 11, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_FLEXPWM3_PWMA03 IMXRT_PADCFG(0, 11, 0x1, 0, 36, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_SINC_FILTER_GLUE3_BREAK IMXRT_PADCFG(0, 11, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_LPUART4_DTR_B IMXRT_PADCFG(0, 11, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_NETC_PINMUX_ETH3_RX_DV IMXRT_PADCFG(0, 11, 0x4, 0, 223, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_GPIO2_IO11 IMXRT_PADCFG(0, 11, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_KPP_ROW04 IMXRT_PADCFG(0, 11, 0x6, 0, 78, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11 IMXRT_PADCFG(0, 11, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_NETC_PINMUX_ETH4_RX_DV IMXRT_PADCFG(0, 11, 0x9, 0, 231, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_ECAT_RX_DV_0 IMXRT_PADCFG(0, 11, 0xa, 0, 13, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_AHB_SRAMC_ADDR02 IMXRT_PADCFG(0, 11, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_12_SEMC_ADDR03 IMXRT_PADCFG(0, 12, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_FLEXPWM4_PWMA00 IMXRT_PADCFG(0, 12, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_LPUART4_TX IMXRT_PADCFG(0, 12, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_NETC_PINMUX_ETH3_RX_ER IMXRT_PADCFG(0, 12, 0x4, 0, 224, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_GPIO2_IO12 IMXRT_PADCFG(0, 12, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_KPP_COL04 IMXRT_PADCFG(0, 12, 0x6, 0, 70, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12 IMXRT_PADCFG(0, 12, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_NETC_PINMUX_ETH4_RX_ER IMXRT_PADCFG(0, 12, 0x9, 0, 232, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_ECAT_PT0_RX_ER IMXRT_PADCFG(0, 12, 0xa, 0, 15, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_AHB_SRAMC_ADDR03 IMXRT_PADCFG(0, 12, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_13_SEMC_ADDR04 IMXRT_PADCFG(0, 13, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_FLEXPWM4_PWMB00 IMXRT_PADCFG(0, 13, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_LPUART4_RX IMXRT_PADCFG(0, 13, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_NETC_PINMUX_ETH2_RX_DV IMXRT_PADCFG(0, 13, 0x3, 0, 215, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_NETC_PINMUX_ETH3_TX_ER IMXRT_PADCFG(0, 13, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_GPIO2_IO13 IMXRT_PADCFG(0, 13, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_KPP_COL01 IMXRT_PADCFG(0, 13, 0x6, 0, 67, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13 IMXRT_PADCFG(0, 13, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_NETC_PINMUX_ETH4_TX_ER IMXRT_PADCFG(0, 13, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_QTIMER1_TIMER1 IMXRT_PADCFG(0, 13, 0xa, 0, 239, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_AHB_SRAMC_ADDR04 IMXRT_PADCFG(0, 13, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_14_SEMC_ADDR05 IMXRT_PADCFG(0, 14, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_FLEXPWM4_PWMA01 IMXRT_PADCFG(0, 14, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_LPUART5_TX IMXRT_PADCFG(0, 14, 0x2, 0, 128, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_NETC_PINMUX_ETH2_TX_EN IMXRT_PADCFG(0, 14, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_NETC_ETH3_CRS IMXRT_PADCFG(0, 14, 0x4, 0, 196, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_GPIO2_IO14 IMXRT_PADCFG(0, 14, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_KPP_ROW00 IMXRT_PADCFG(0, 14, 0x6, 0, 74, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14 IMXRT_PADCFG(0, 14, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_NETC_ETH4_CRS IMXRT_PADCFG(0, 14, 0x9, 0, 200, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_LPUART4_CTS_B IMXRT_PADCFG(0, 14, 0xa, 0, 122, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_AHB_SRAMC_ADDR05 IMXRT_PADCFG(0, 14, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_15_SEMC_ADDR06 IMXRT_PADCFG(0, 15, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_FLEXPWM4_PWMB01 IMXRT_PADCFG(0, 15, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_LPUART5_RX IMXRT_PADCFG(0, 15, 0x2, 0, 127, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_NETC_PINMUX_ETH2_TX_CLK IMXRT_PADCFG(0, 15, 0x3, 0, 221, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_NETC_ETH3_COL IMXRT_PADCFG(0, 15, 0x4, 0, 195, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_GPIO2_IO15 IMXRT_PADCFG(0, 15, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_KPP_COL00 IMXRT_PADCFG(0, 15, 0x6, 0, 66, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15 IMXRT_PADCFG(0, 15, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_NETC_ETH4_COL IMXRT_PADCFG(0, 15, 0x9, 0, 199, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_LPUART4_RTS_B IMXRT_PADCFG(0, 15, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_AHB_SRAMC_ADDR06 IMXRT_PADCFG(0, 15, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_16_SEMC_ADDR07 IMXRT_PADCFG(0, 16, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_FLEXPWM4_PWMB02 IMXRT_PADCFG(0, 16, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_LPUART9_TX IMXRT_PADCFG(0, 16, 0x2, 0, 139, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_NETC_PINMUX_ETH2_RXD00 IMXRT_PADCFG(0, 16, 0x3, 0, 217, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_NETC_ETH3_SLV_MDC IMXRT_PADCFG(0, 16, 0x4, 0, 197, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_GPIO2_IO16 IMXRT_PADCFG(0, 16, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_NETC_ETH4_SLV_MDC IMXRT_PADCFG(0, 16, 0x6, 0, 201, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16 IMXRT_PADCFG(0, 16, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_NETC_ETH2_SLV_MDC IMXRT_PADCFG(0, 16, 0x9, 0, 193, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_LPSPI6_PCS2 IMXRT_PADCFG(0, 16, 0xa, 0, 110, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_AHB_SRAMC_ADDR07 IMXRT_PADCFG(0, 16, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_17_SEMC_ADDR08 IMXRT_PADCFG(0, 17, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_FLEXPWM4_PWMA02 IMXRT_PADCFG(0, 17, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_LPUART9_RX IMXRT_PADCFG(0, 17, 0x2, 0, 138, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_NETC_PINMUX_ETH2_RXD01 IMXRT_PADCFG(0, 17, 0x3, 0, 218, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_NETC_ETH3_SLV_MDIO IMXRT_PADCFG(0, 17, 0x4, 0, 198, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_GPIO2_IO17 IMXRT_PADCFG(0, 17, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_NETC_ETH4_SLV_MDIO IMXRT_PADCFG(0, 17, 0x6, 0, 202, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17 IMXRT_PADCFG(0, 17, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_NETC_ETH2_SLV_MDIO IMXRT_PADCFG(0, 17, 0x9, 0, 194, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_LPSPI6_PCS1 IMXRT_PADCFG(0, 17, 0xa, 0, 109, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_AHB_SRAMC_ADDR08 IMXRT_PADCFG(0, 17, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_18_SEMC_ADDR09 IMXRT_PADCFG(0, 18, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_FLEXPWM2_PWMA00 IMXRT_PADCFG(0, 18, 0x1, 0, 27, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_QTIMER1_TIMER0 IMXRT_PADCFG(0, 18, 0x2, 0, 238, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_LPSPI6_SCK IMXRT_PADCFG(0, 18, 0x3, 0, 112, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_NETC_ETH2_CRS IMXRT_PADCFG(0, 18, 0x4, 0, 192, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_GPIO2_IO18 IMXRT_PADCFG(0, 18, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18 IMXRT_PADCFG(0, 18, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_NETC_EMDC IMXRT_PADCFG(0, 18, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_AHB_SRAMC_ADDR09 IMXRT_PADCFG(0, 18, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_19_SEMC_ADDR11 IMXRT_PADCFG(0, 19, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_FLEXPWM2_PWMB00 IMXRT_PADCFG(0, 19, 0x1, 0, 30, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_QTIMER2_TIMER0 IMXRT_PADCFG(0, 19, 0x2, 0, 241, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_LPSPI6_SDI IMXRT_PADCFG(0, 19, 0x3, 0, 113, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_NETC_ETH2_COL IMXRT_PADCFG(0, 19, 0x4, 0, 191, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_GPIO2_IO19 IMXRT_PADCFG(0, 19, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19 IMXRT_PADCFG(0, 19, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_NETC_EMDIO IMXRT_PADCFG(0, 19, 0xa, 0, 190, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_AHB_SRAMC_ADDR11 IMXRT_PADCFG(0, 19, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_20_SEMC_ADDR12 IMXRT_PADCFG(0, 20, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_FLEXPWM2_PWMA01 IMXRT_PADCFG(0, 20, 0x1, 0, 28, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_QTIMER3_TIMER0 IMXRT_PADCFG(0, 20, 0x2, 0, 244, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_LPSPI6_SDO IMXRT_PADCFG(0, 20, 0x3, 0, 114, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_NETC_PINMUX_ETH2_TX_ER IMXRT_PADCFG(0, 20, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_GPIO2_IO20 IMXRT_PADCFG(0, 20, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20 IMXRT_PADCFG(0, 20, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_AHB_SRAMC_ADDR12 IMXRT_PADCFG(0, 20, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_21_SEMC_BA0 IMXRT_PADCFG(0, 21, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_FLEXPWM2_PWMB01 IMXRT_PADCFG(0, 21, 0x1, 0, 31, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_QTIMER4_TIMER0 IMXRT_PADCFG(0, 21, 0x2, 0, 247, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_LPSPI6_PCS0 IMXRT_PADCFG(0, 21, 0x3, 0, 108, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_NETC_PINMUX_ETH2_RX_CLK IMXRT_PADCFG(0, 21, 0x4, 0, 214, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_GPIO2_IO21 IMXRT_PADCFG(0, 21, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21 IMXRT_PADCFG(0, 21, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_LPUART4_CTS_B IMXRT_PADCFG(0, 21, 0x9, 0, 122, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_21_FLEXSPI2_BUS2BIT_B_DQS IMXRT_PADCFG(0, 21, 0xa, 0, 53, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_AHB_SRAMC_ADDR13 IMXRT_PADCFG(0, 21, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_22_SEMC_BA1 IMXRT_PADCFG(0, 22, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_FLEXPWM2_PWMB02 IMXRT_PADCFG(0, 22, 0x1, 0, 32, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_QTIMER5_TIMER0 IMXRT_PADCFG(0, 22, 0x2, 0, 250, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_LPSPI4_SCK IMXRT_PADCFG(0, 22, 0x3, 0, 98, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_NETC_PINMUX_ETH2_RXD02 IMXRT_PADCFG(0, 22, 0x4, 0, 219, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_GPIO2_IO22 IMXRT_PADCFG(0, 22, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22 IMXRT_PADCFG(0, 22, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_LPUART4_RTS_B IMXRT_PADCFG(0, 22, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_FLEXSPI2_BUS2BIT_B_DATA03 IMXRT_PADCFG(0, 22, 0xa, 0, 61, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_AHB_SRAMC_ADDR14 IMXRT_PADCFG(0, 22, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_23_SEMC_ADDR10 IMXRT_PADCFG(0, 23, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_FLEXPWM2_PWMA02 IMXRT_PADCFG(0, 23, 0x1, 0, 29, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_QTIMER6_TIMER0 IMXRT_PADCFG(0, 23, 0x2, 0, 253, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_LPSPI4_SDI IMXRT_PADCFG(0, 23, 0x3, 0, 99, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_NETC_PINMUX_ETH2_RXD03 IMXRT_PADCFG(0, 23, 0x4, 0, 220, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_GPIO2_IO23 IMXRT_PADCFG(0, 23, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23 IMXRT_PADCFG(0, 23, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_FLEXSPI2_BUS2BIT_B_DATA02 IMXRT_PADCFG(0, 23, 0xa, 0, 60, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_AHB_SRAMC_ADDR10 IMXRT_PADCFG(0, 23, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_24_SEMC_CAS IMXRT_PADCFG(0, 24, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_FLEXPWM1_PWMA00 IMXRT_PADCFG(0, 24, 0x1, 0, 21, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_QTIMER7_TIMER0 IMXRT_PADCFG(0, 24, 0x2, 0, 256, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_LPSPI4_SDO IMXRT_PADCFG(0, 24, 0x3, 0, 100, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_NETC_PINMUX_ETH2_TXD03 IMXRT_PADCFG(0, 24, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_GPIO2_IO24 IMXRT_PADCFG(0, 24, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24 IMXRT_PADCFG(0, 24, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_NETC_ETH3_SLV_MDC IMXRT_PADCFG(0, 24, 0x9, 0, 197, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_24_FLEXSPI2_BUS2BIT_B_DATA01 IMXRT_PADCFG(0, 24, 0xa, 0, 59, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_AHB_SRAMC_ADDR15 IMXRT_PADCFG(0, 24, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_25_SEMC_RAS IMXRT_PADCFG(0, 25, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_FLEXPWM1_PWMB00 IMXRT_PADCFG(0, 25, 0x1, 0, 24, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_QTIMER8_TIMER0 IMXRT_PADCFG(0, 25, 0x2, 0, 258, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_LPSPI4_PCS0 IMXRT_PADCFG(0, 25, 0x3, 0, 97, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_NETC_PINMUX_ETH2_TXD02 IMXRT_PADCFG(0, 25, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_GPIO2_IO25 IMXRT_PADCFG(0, 25, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25 IMXRT_PADCFG(0, 25, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_NETC_ETH3_SLV_MDIO IMXRT_PADCFG(0, 25, 0x9, 0, 198, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_25_FLEXSPI2_BUS2BIT_B_DATA00 IMXRT_PADCFG(0, 25, 0xa, 0, 58, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_AHB_SRAMC_ADDR16 IMXRT_PADCFG(0, 25, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_26_SEMC_CLK IMXRT_PADCFG(0, 26, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_FLEXPWM1_PWMA01 IMXRT_PADCFG(0, 26, 0x1, 0, 22, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_XBAR1_XBAR_INOUT10 IMXRT_PADCFG(0, 26, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_FLEXSPI2_BUS2BIT_A_SS1_B IMXRT_PADCFG(0, 26, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_NETC_PINMUX_ETH2_TXD01 IMXRT_PADCFG(0, 26, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_GPIO2_IO26 IMXRT_PADCFG(0, 26, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_ECAT_TX_DATA1_1 IMXRT_PADCFG(0, 26, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_LPSPI6_SCK IMXRT_PADCFG(0, 26, 0xa, 0, 112, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_26_AHB_SRAMC_WE IMXRT_PADCFG(0, 26, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_27_SEMC_CKE IMXRT_PADCFG(0, 27, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_FLEXPWM1_PWMB01 IMXRT_PADCFG(0, 27, 0x1, 0, 25, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_XBAR1_XBAR_INOUT11 IMXRT_PADCFG(0, 27, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_FLEXSPI2_BUS2BIT_B_SS1_B IMXRT_PADCFG(0, 27, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_NETC_PINMUX_ETH2_TXD00 IMXRT_PADCFG(0, 27, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_GPIO2_IO27 IMXRT_PADCFG(0, 27, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_ECAT_TX_DATA0_1 IMXRT_PADCFG(0, 27, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_LPUART6_RI_B IMXRT_PADCFG(0, 27, 0x9, 0, 132, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_LPSPI6_SDI IMXRT_PADCFG(0, 27, 0xa, 0, 113, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_27_AHB_SRAMC_OEB IMXRT_PADCFG(0, 27, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_28_SEMC_WE IMXRT_PADCFG(0, 28, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_FLEXPWM1_PWMB02 IMXRT_PADCFG(0, 28, 0x1, 0, 26, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_XBAR1_XBAR_INOUT12 IMXRT_PADCFG(0, 28, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_FLEXSPI2_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 28, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_NETC_PINMUX_ETH2_TX_EN IMXRT_PADCFG(0, 28, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_GPIO2_IO28 IMXRT_PADCFG(0, 28, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_ECAT_TX_EN_1 IMXRT_PADCFG(0, 28, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_LPUART6_DTR_B IMXRT_PADCFG(0, 28, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_LPSPI6_SDO IMXRT_PADCFG(0, 28, 0xa, 0, 114, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_28_AHB_SRAMC_ADV IMXRT_PADCFG(0, 28, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_29_SEMC_CS0 IMXRT_PADCFG(0, 29, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_FLEXPWM1_PWMA02 IMXRT_PADCFG(0, 29, 0x1, 0, 23, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_XBAR1_XBAR_INOUT13 IMXRT_PADCFG(0, 29, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_FLEXSPI2_BUS2BIT_B_DQS IMXRT_PADCFG(0, 29, 0x3, 0, 53, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_29_NETC_PINMUX_ETH2_TX_CLK IMXRT_PADCFG(0, 29, 0x4, 0, 221, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_29_GPIO2_IO29 IMXRT_PADCFG(0, 29, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_ECAT_TX_CLK_1 IMXRT_PADCFG(0, 29, 0x6, 0, 18, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_LPUART6_DCD_B IMXRT_PADCFG(0, 29, 0x9, 0, 130, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_LPSPI6_PCS0 IMXRT_PADCFG(0, 29, 0xa, 0, 108, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_29_AHB_SRAMC_CS0 IMXRT_PADCFG(0, 29, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_30_SEMC_DATA08 IMXRT_PADCFG(0, 30, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_FLEXPWM3_PWMA00 IMXRT_PADCFG(0, 30, 0x1, 0, 33, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_XBAR1_XBAR_INOUT14 IMXRT_PADCFG(0, 30, 0x2, 0, 293, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_FLEXSPI2_BUS2BIT_B_DATA03 IMXRT_PADCFG(0, 30, 0x3, 0, 61, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_30_NETC_PINMUX_ETH2_RXD00 IMXRT_PADCFG(0, 30, 0x4, 0, 217, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_30_GPIO2_IO30 IMXRT_PADCFG(0, 30, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_ECAT_RX_DATA0_1 IMXRT_PADCFG(0, 30, 0x6, 0, 6, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_LPUART6_DSR_B IMXRT_PADCFG(0, 30, 0x9, 0, 131, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_LPSPI6_PCS1 IMXRT_PADCFG(0, 30, 0xa, 0, 109, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_30_AHB_SRAMC_DATA08 IMXRT_PADCFG(0, 30, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_31_SEMC_DATA09 IMXRT_PADCFG(0, 31, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_FLEXPWM3_PWMB00 IMXRT_PADCFG(0, 31, 0x1, 0, 37, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_LPUART6_TX IMXRT_PADCFG(0, 31, 0x2, 0, 134, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_FLEXSPI2_BUS2BIT_B_DATA02 IMXRT_PADCFG(0, 31, 0x3, 0, 60, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_31_NETC_PINMUX_ETH2_RXD01 IMXRT_PADCFG(0, 31, 0x4, 0, 218, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_31_GPIO2_IO31 IMXRT_PADCFG(0, 31, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_ECAT_RX_DATA1_1 IMXRT_PADCFG(0, 31, 0x6, 0, 8, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_LPSPI5_SCK IMXRT_PADCFG(0, 31, 0x9, 0, 105, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_LPSPI6_PCS2 IMXRT_PADCFG(0, 31, 0xa, 0, 110, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_31_AHB_SRAMC_DATA09 IMXRT_PADCFG(0, 31, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_32_SEMC_DATA10 IMXRT_PADCFG(0, 32, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_FLEXPWM3_PWMA01 IMXRT_PADCFG(0, 32, 0x1, 0, 34, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_LPUART6_RX IMXRT_PADCFG(0, 32, 0x2, 0, 133, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_FLEXSPI2_BUS2BIT_B_DATA01 IMXRT_PADCFG(0, 32, 0x3, 0, 59, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_32_NETC_PINMUX_ETH2_RX_DV IMXRT_PADCFG(0, 32, 0x4, 0, 215, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_32_GPIO3_IO00 IMXRT_PADCFG(0, 32, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_ECAT_RX_DV_1 IMXRT_PADCFG(0, 32, 0x6, 0, 14, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_LPSPI5_SDO IMXRT_PADCFG(0, 32, 0x9, 0, 107, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_LPSPI6_PCS3 IMXRT_PADCFG(0, 32, 0xa, 0, 111, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_AHB_SRAMC_DATA10 IMXRT_PADCFG(0, 32, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_33_SEMC_DATA11 IMXRT_PADCFG(0, 33, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_FLEXPWM3_PWMB01 IMXRT_PADCFG(0, 33, 0x1, 0, 38, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_LPUART6_CTS_B IMXRT_PADCFG(0, 33, 0x2, 0, 129, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_FLEXSPI2_BUS2BIT_B_DATA00 IMXRT_PADCFG(0, 33, 0x3, 0, 58, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_33_NETC_PINMUX_ETH2_RX_ER IMXRT_PADCFG(0, 33, 0x4, 0, 216, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_GPIO3_IO01 IMXRT_PADCFG(0, 33, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_ECAT_RX_ER_1 IMXRT_PADCFG(0, 33, 0x6, 0, 16, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_LPSPI5_SDI IMXRT_PADCFG(0, 33, 0x9, 0, 106, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_NETC_PINMUX_ETH2_RX_CLK IMXRT_PADCFG(0, 33, 0xa, 0, 214, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_33_AHB_SRAMC_DATA11 IMXRT_PADCFG(0, 33, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_34_SEMC_DATA12 IMXRT_PADCFG(0, 34, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_FLEXPWM3_PWMB02 IMXRT_PADCFG(0, 34, 0x1, 0, 39, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_LPUART6_RTS_B IMXRT_PADCFG(0, 34, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_FLEXSPI2_BUS2BIT_B_SCLK IMXRT_PADCFG(0, 34, 0x3, 0, 63, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_NETC_PINMUX_ETH2_RXD02 IMXRT_PADCFG(0, 34, 0x4, 0, 219, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_34_GPIO3_IO02 IMXRT_PADCFG(0, 34, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_ECAT_RX_DATA2_1 IMXRT_PADCFG(0, 34, 0x6, 0, 10, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_NETC_PINMUX_ETH0_TXD00 IMXRT_PADCFG(0, 34, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_LPSPI5_PCS0 IMXRT_PADCFG(0, 34, 0xa, 0, 101, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_AHB_SRAMC_DATA12 IMXRT_PADCFG(0, 34, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_35_SEMC_DATA13 IMXRT_PADCFG(0, 35, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_FLEXPWM3_PWMA02 IMXRT_PADCFG(0, 35, 0x1, 0, 35, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_LPUART5_TX IMXRT_PADCFG(0, 35, 0x2, 0, 128, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_35_FLEXSPI2_BUS2BIT_A_DATA00 IMXRT_PADCFG(0, 35, 0x3, 0, 54, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_NETC_PINMUX_ETH2_RXD03 IMXRT_PADCFG(0, 35, 0x4, 0, 220, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_35_GPIO3_IO03 IMXRT_PADCFG(0, 35, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_ECAT_RX_DATA3_1 IMXRT_PADCFG(0, 35, 0x6, 0, 12, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_NETC_PINMUX_ETH0_TXD01 IMXRT_PADCFG(0, 35, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_LPSPI5_PCS1 IMXRT_PADCFG(0, 35, 0xa, 0, 102, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_AHB_SRAMC_DATA13 IMXRT_PADCFG(0, 35, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_36_SEMC_DATA14 IMXRT_PADCFG(0, 36, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_FLEXPWM1_PWMA00 IMXRT_PADCFG(0, 36, 0x1, 0, 21, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_36_LPUART5_RX IMXRT_PADCFG(0, 36, 0x2, 0, 127, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_36_FLEXSPI2_BUS2BIT_A_DATA01 IMXRT_PADCFG(0, 36, 0x3, 0, 55, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_NETC_PINMUX_ETH2_TXD03 IMXRT_PADCFG(0, 36, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_GPIO3_IO04 IMXRT_PADCFG(0, 36, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_ECAT_TX_DATA3_1 IMXRT_PADCFG(0, 36, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_NETC_PINMUX_ETH0_TX_EN IMXRT_PADCFG(0, 36, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_AHB_SRAMC_DATA14 IMXRT_PADCFG(0, 36, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_37_SEMC_DATA15 IMXRT_PADCFG(0, 37, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_FLEXPWM1_PWMB00 IMXRT_PADCFG(0, 37, 0x1, 0, 24, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_37_LPUART5_CTS_B IMXRT_PADCFG(0, 37, 0x2, 0, 123, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_FLEXSPI2_BUS2BIT_A_DATA02 IMXRT_PADCFG(0, 37, 0x3, 0, 56, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_NETC_PINMUX_ETH2_TXD02 IMXRT_PADCFG(0, 37, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_GPIO3_IO05 IMXRT_PADCFG(0, 37, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_ECAT_TX_DATA2_1 IMXRT_PADCFG(0, 37, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_NETC_PINMUX_ETH0_TX_CLK IMXRT_PADCFG(0, 37, 0x9, 0, 213, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_AHB_SRAMC_DATA15 IMXRT_PADCFG(0, 37, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_38_SEMC_DM01 IMXRT_PADCFG(0, 38, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_FLEXPWM1_PWMB03 IMXRT_PADCFG(0, 38, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_LPUART5_RTS_B IMXRT_PADCFG(0, 38, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_FLEXSPI2_BUS2BIT_A_DATA03 IMXRT_PADCFG(0, 38, 0x3, 0, 57, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_NETC_PINMUX_ETH2_RX_CLK IMXRT_PADCFG(0, 38, 0x4, 0, 214, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B1_38_GPIO3_IO06 IMXRT_PADCFG(0, 38, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_ECAT_RX_CLK_1 IMXRT_PADCFG(0, 38, 0x6, 0, 4, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_NETC_PINMUX_ETH0_RXD00 IMXRT_PADCFG(0, 38, 0x9, 0, 209, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_AHB_SRAMC_UBB IMXRT_PADCFG(0, 38, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_39_SEMC_DQS IMXRT_PADCFG(0, 39, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_FLEXPWM1_PWMA03 IMXRT_PADCFG(0, 39, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_XBAR1_XBAR_INOUT15 IMXRT_PADCFG(0, 39, 0x2, 0, 294, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_FLEXSPI2_BUS2BIT_A_SS0_B IMXRT_PADCFG(0, 39, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_NETC_PINMUX_ETH2_TX_ER IMXRT_PADCFG(0, 39, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_GPIO3_IO07 IMXRT_PADCFG(0, 39, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_QTIMER2_TIMER1 IMXRT_PADCFG(0, 39, 0x6, 0, 242, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_NETC_PINMUX_ETH0_RXD01 IMXRT_PADCFG(0, 39, 0x9, 0, 210, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_AHB_SRAMC_CS1 IMXRT_PADCFG(0, 39, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_40_SEMC_RDY IMXRT_PADCFG(0, 40, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_NETC_EMDC IMXRT_PADCFG(0, 40, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_NETC_ETH2_SLV_MDC IMXRT_PADCFG(0, 40, 0x2, 0, 193, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_40_FLEXSPI2_BUS2BIT_A_DQS IMXRT_PADCFG(0, 40, 0x3, 0, 52, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_NETC_ETH2_CRS IMXRT_PADCFG(0, 40, 0x4, 0, 192, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_40_GPIO3_IO08 IMXRT_PADCFG(0, 40, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_QTIMER3_TIMER1 IMXRT_PADCFG(0, 40, 0x6, 0, 245, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_NETC_PINMUX_ETH0_RX_DV IMXRT_PADCFG(0, 40, 0x9, 0, 207, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_AHB_SRAMC_CS2 IMXRT_PADCFG(0, 40, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_41_SEMC_CSX00 IMXRT_PADCFG(0, 41, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_NETC_EMDIO IMXRT_PADCFG(0, 41, 0x1, 0, 190, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_41_NETC_ETH2_SLV_MDIO IMXRT_PADCFG(0, 41, 0x2, 0, 194, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_41_FLEXSPI2_BUS2BIT_A_SCLK IMXRT_PADCFG(0, 41, 0x3, 0, 62, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_NETC_ETH2_COL IMXRT_PADCFG(0, 41, 0x4, 0, 191, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_41_GPIO3_IO09 IMXRT_PADCFG(0, 41, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_QTIMER4_TIMER1 IMXRT_PADCFG(0, 41, 0x6, 0, 248, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_NETC_PINMUX_ETH0_RX_ER IMXRT_PADCFG(0, 41, 0x9, 0, 208, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_AHB_SRAMC_CS3 IMXRT_PADCFG(0, 41, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_00_SEMC_DATA16 IMXRT_PADCFG(0, 42, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M IMXRT_PADCFG(0, 42, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_QTIMER5_TIMER1 IMXRT_PADCFG(0, 42, 0x2, 0, 251, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_NETC_EMDC IMXRT_PADCFG(0, 42, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_NETC_PINMUX_ETH0_RX_CLK IMXRT_PADCFG(0, 42, 0x4, 0, 206, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_GPIO3_IO10 IMXRT_PADCFG(0, 42, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20 IMXRT_PADCFG(0, 42, 0x6, 0, 298, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_LPSPI5_SCK IMXRT_PADCFG(0, 42, 0x8, 0, 105, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_00_LPI2C3_SCL IMXRT_PADCFG(0, 42, 0x9, 0, 82, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_FLEXPWM3_PWMA00 IMXRT_PADCFG(0, 42, 0xa, 0, 33, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_00_ECAT_RX_CLK_0 IMXRT_PADCFG(0, 42, 0xc, 0, 3, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_01_SEMC_DATA17 IMXRT_PADCFG(0, 43, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_USDHC2_CD_B IMXRT_PADCFG(0, 43, 0x1, 0, 291, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_QTIMER6_TIMER1 IMXRT_PADCFG(0, 43, 0x2, 0, 254, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_NETC_EMDIO IMXRT_PADCFG(0, 43, 0x3, 0, 190, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_01_NETC_PINMUX_ETH0_RXD02 IMXRT_PADCFG(0, 43, 0x4, 0, 211, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_GPIO3_IO11 IMXRT_PADCFG(0, 43, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21 IMXRT_PADCFG(0, 43, 0x6, 0, 299, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_LPSPI5_PCS0 IMXRT_PADCFG(0, 43, 0x8, 0, 101, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_01_LPI2C3_SDA IMXRT_PADCFG(0, 43, 0x9, 0, 83, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_FLEXPWM3_PWMB00 IMXRT_PADCFG(0, 43, 0xa, 0, 37, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_01_ECAT_RX_DATA2_0 IMXRT_PADCFG(0, 43, 0xc, 0, 9, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_02_SEMC_DATA18 IMXRT_PADCFG(0, 44, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_USDHC2_WP IMXRT_PADCFG(0, 44, 0x1, 0, 292, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_QTIMER7_TIMER1 IMXRT_PADCFG(0, 44, 0x2, 0, 257, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_NETC_PINMUX_ETH0_RXD03 IMXRT_PADCFG(0, 44, 0x4, 0, 212, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_GPIO3_IO12 IMXRT_PADCFG(0, 44, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22 IMXRT_PADCFG(0, 44, 0x6, 0, 300, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_LPSPI5_SDO IMXRT_PADCFG(0, 44, 0x8, 0, 107, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_02_CCM_CLKO1 IMXRT_PADCFG(0, 44, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_FLEXPWM3_PWMA01 IMXRT_PADCFG(0, 44, 0xa, 0, 34, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_02_ECAT_RX_DATA3_0 IMXRT_PADCFG(0, 44, 0xc, 0, 11, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_03_SEMC_DATA19 IMXRT_PADCFG(0, 45, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_USDHC2_VSELECT IMXRT_PADCFG(0, 45, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_QTIMER8_TIMER1 IMXRT_PADCFG(0, 45, 0x2, 0, 259, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_NETC_PINMUX_ETH0_TXD02 IMXRT_PADCFG(0, 45, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_GPIO3_IO13 IMXRT_PADCFG(0, 45, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23 IMXRT_PADCFG(0, 45, 0x6, 0, 301, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_LPSPI5_SDI IMXRT_PADCFG(0, 45, 0x8, 0, 106, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_03_NETC_ETH3_CRS IMXRT_PADCFG(0, 45, 0x9, 0, 196, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_03_FLEXPWM3_PWMB01 IMXRT_PADCFG(0, 45, 0xa, 0, 38, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_03_ECAT_TX_DATA2_0 IMXRT_PADCFG(0, 45, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_04_SEMC_DATA20 IMXRT_PADCFG(0, 46, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_USDHC2_RESET_B IMXRT_PADCFG(0, 46, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_SAI2_MCLK IMXRT_PADCFG(0, 46, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_NETC_PINMUX_ETH0_TXD03 IMXRT_PADCFG(0, 46, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_GPIO3_IO14 IMXRT_PADCFG(0, 46, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24 IMXRT_PADCFG(0, 46, 0x6, 0, 302, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_LPSPI3_SCK IMXRT_PADCFG(0, 46, 0x8, 0, 94, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_NETC_ETH3_COL IMXRT_PADCFG(0, 46, 0x9, 0, 195, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_04_FLEXPWM3_PWMB02 IMXRT_PADCFG(0, 46, 0xa, 0, 39, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_04_ECAT_TX_DATA3_0 IMXRT_PADCFG(0, 46, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_05_SEMC_DATA21 IMXRT_PADCFG(0, 47, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_NETC_ETH4_SLV_MDC IMXRT_PADCFG(0, 47, 0x1, 0, 201, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_05_SAI2_RX_SYNC IMXRT_PADCFG(0, 47, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_NETC_PINMUX_ETH0_TXD00 IMXRT_PADCFG(0, 47, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_NETC_ETH4_CRS IMXRT_PADCFG(0, 47, 0x4, 0, 200, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_05_GPIO3_IO15 IMXRT_PADCFG(0, 47, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25 IMXRT_PADCFG(0, 47, 0x6, 0, 303, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_LPSPI3_PCS0 IMXRT_PADCFG(0, 47, 0x8, 0, 90, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_NETC_PINMUX_ETH3_TXD00 IMXRT_PADCFG(0, 47, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_FLEXPWM3_PWMA02 IMXRT_PADCFG(0, 47, 0xa, 0, 35, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_05_ECAT_TX_DATA0_0 IMXRT_PADCFG(0, 47, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_06_SEMC_DATA22 IMXRT_PADCFG(0, 48, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_NETC_ETH4_SLV_MDIO IMXRT_PADCFG(0, 48, 0x1, 0, 202, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_06_SAI2_RX_BCLK IMXRT_PADCFG(0, 48, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_NETC_PINMUX_ETH0_TXD01 IMXRT_PADCFG(0, 48, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_NETC_ETH4_COL IMXRT_PADCFG(0, 48, 0x4, 0, 199, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_06_GPIO3_IO16 IMXRT_PADCFG(0, 48, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26 IMXRT_PADCFG(0, 48, 0x6, 0, 304, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_LPSPI3_SDO IMXRT_PADCFG(0, 48, 0x8, 0, 96, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_NETC_PINMUX_ETH3_TXD01 IMXRT_PADCFG(0, 48, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_FLEXPWM3_PWMB03 IMXRT_PADCFG(0, 48, 0xa, 0, 40, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_06_ECAT_TX_DATA1_0 IMXRT_PADCFG(0, 48, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_07_SEMC_DATA23 IMXRT_PADCFG(0, 49, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_NETC_PINMUX_ETH4_TX_ER IMXRT_PADCFG(0, 49, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_SAI2_RX_DATA IMXRT_PADCFG(0, 49, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_NETC_PINMUX_ETH0_TX_EN IMXRT_PADCFG(0, 49, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_GPIO3_IO17 IMXRT_PADCFG(0, 49, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27 IMXRT_PADCFG(0, 49, 0x6, 0, 305, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_LPSPI3_SDI IMXRT_PADCFG(0, 49, 0x8, 0, 95, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_NETC_PINMUX_ETH3_TX_EN IMXRT_PADCFG(0, 49, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_FLEXPWM3_PWMA03 IMXRT_PADCFG(0, 49, 0xa, 0, 36, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_07_ECAT_TX_EN_0 IMXRT_PADCFG(0, 49, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_08_SEMC_DM02 IMXRT_PADCFG(0, 50, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_NETC_PINMUX_ETH4_RX_CLK IMXRT_PADCFG(0, 50, 0x1, 0, 230, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_08_SAI2_TX_DATA IMXRT_PADCFG(0, 50, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_NETC_PINMUX_ETH0_TX_CLK IMXRT_PADCFG(0, 50, 0x3, 0, 213, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_08_GPIO3_IO18 IMXRT_PADCFG(0, 50, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28 IMXRT_PADCFG(0, 50, 0x6, 0, 306, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_LPSPI3_PCS3 IMXRT_PADCFG(0, 50, 0x8, 0, 93, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_NETC_PINMUX_ETH3_TX_CLK IMXRT_PADCFG(0, 50, 0x9, 0, 229, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_08_CCM_CLKO2 IMXRT_PADCFG(0, 50, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_ECAT_TX_CLK_0 IMXRT_PADCFG(0, 50, 0xc, 0, 17, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_09_SEMC_DATA24 IMXRT_PADCFG(0, 51, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_NETC_PINMUX_ETH4_RXD03 IMXRT_PADCFG(0, 51, 0x1, 0, 236, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_09_SAI2_TX_BCLK IMXRT_PADCFG(0, 51, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_NETC_PINMUX_ETH0_RXD00 IMXRT_PADCFG(0, 51, 0x3, 0, 209, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_09_GPIO3_IO19 IMXRT_PADCFG(0, 51, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29 IMXRT_PADCFG(0, 51, 0x6, 0, 307, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_LPSPI3_PCS2 IMXRT_PADCFG(0, 51, 0x8, 0, 92, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_NETC_PINMUX_ETH3_RXD00 IMXRT_PADCFG(0, 51, 0x9, 0, 225, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_09_QTIMER1_TIMER0 IMXRT_PADCFG(0, 51, 0xa, 0, 238, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_09_ECAT_RX_DATA0_0 IMXRT_PADCFG(0, 51, 0xc, 0, 5, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_10_SEMC_DATA25 IMXRT_PADCFG(0, 52, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_NETC_PINMUX_ETH4_RXD02 IMXRT_PADCFG(0, 52, 0x1, 0, 235, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_10_SAI2_TX_SYNC IMXRT_PADCFG(0, 52, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_NETC_PINMUX_ETH0_RXD01 IMXRT_PADCFG(0, 52, 0x3, 0, 210, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_10_GPIO3_IO20 IMXRT_PADCFG(0, 52, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30 IMXRT_PADCFG(0, 52, 0x6, 0, 308, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_LPSPI3_PCS1 IMXRT_PADCFG(0, 52, 0x8, 0, 91, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_NETC_PINMUX_ETH3_RXD01 IMXRT_PADCFG(0, 52, 0x9, 0, 226, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_10_QTIMER1_TIMER1 IMXRT_PADCFG(0, 52, 0xa, 0, 239, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_10_ECAT_RX_DATA1_0 IMXRT_PADCFG(0, 52, 0xc, 0, 7, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_11_SEMC_DATA26 IMXRT_PADCFG(0, 53, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_NETC_PINMUX_ETH4_TXD03 IMXRT_PADCFG(0, 53, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_SPDIF_OUT IMXRT_PADCFG(0, 53, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_NETC_PINMUX_ETH0_RX_DV IMXRT_PADCFG(0, 53, 0x3, 0, 207, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_11_LPSPI5_PCS3 IMXRT_PADCFG(0, 53, 0x4, 0, 104, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_GPIO3_IO21 IMXRT_PADCFG(0, 53, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31 IMXRT_PADCFG(0, 53, 0x6, 0, 309, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_SAI3_RX_SYNC IMXRT_PADCFG(0, 53, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_NETC_PINMUX_ETH3_RX_DV IMXRT_PADCFG(0, 53, 0x9, 0, 223, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_11_QTIMER1_TIMER2 IMXRT_PADCFG(0, 53, 0xa, 0, 240, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_ECAT_RX_DV_0 IMXRT_PADCFG(0, 53, 0xc, 0, 13, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_12_SEMC_DATA27 IMXRT_PADCFG(0, 54, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_NETC_PINMUX_ETH4_TXD02 IMXRT_PADCFG(0, 54, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_SPDIF_IN IMXRT_PADCFG(0, 54, 0x2, 0, 282, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_NETC_PINMUX_ETH0_RX_ER IMXRT_PADCFG(0, 54, 0x3, 0, 208, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_12_LPSPI5_PCS2 IMXRT_PADCFG(0, 54, 0x4, 0, 103, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_GPIO3_IO22 IMXRT_PADCFG(0, 54, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32 IMXRT_PADCFG(0, 54, 0x6, 0, 310, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_SAI3_RX_BCLK IMXRT_PADCFG(0, 54, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_NETC_PINMUX_ETH3_RX_ER IMXRT_PADCFG(0, 54, 0x9, 0, 224, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_12_QTIMER1_TIMER3 IMXRT_PADCFG(0, 54, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_ECAT_PT0_RX_ER IMXRT_PADCFG(0, 54, 0xc, 0, 15, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_13_SEMC_DATA28 IMXRT_PADCFG(0, 55, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_NETC_PINMUX_ETH4_TXD00 IMXRT_PADCFG(0, 55, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_LPUART11_TX IMXRT_PADCFG(0, 55, 0x2, 0, 118, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_NETC_PINMUX_ETH0_TXD03 IMXRT_PADCFG(0, 55, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_LPSPI5_PCS1 IMXRT_PADCFG(0, 55, 0x4, 0, 102, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_13_GPIO3_IO23 IMXRT_PADCFG(0, 55, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33 IMXRT_PADCFG(0, 55, 0x6, 0, 311, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_SAI3_RX_DATA IMXRT_PADCFG(0, 55, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_NETC_PINMUX_ETH3_TXD03 IMXRT_PADCFG(0, 55, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_QTIMER2_TIMER0 IMXRT_PADCFG(0, 55, 0xa, 0, 241, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_13_ECAT_TX_DATA0_1 IMXRT_PADCFG(0, 55, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_14_SEMC_DATA29 IMXRT_PADCFG(0, 56, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_NETC_PINMUX_ETH4_TXD01 IMXRT_PADCFG(0, 56, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_LPUART11_RX IMXRT_PADCFG(0, 56, 0x2, 0, 117, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_NETC_PINMUX_ETH0_TXD02 IMXRT_PADCFG(0, 56, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_LPUART5_DSR_B IMXRT_PADCFG(0, 56, 0x4, 0, 125, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_GPIO3_IO24 IMXRT_PADCFG(0, 56, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34 IMXRT_PADCFG(0, 56, 0x6, 0, 312, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_SAI3_TX_DATA IMXRT_PADCFG(0, 56, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_NETC_PINMUX_ETH3_TXD02 IMXRT_PADCFG(0, 56, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_QTIMER2_TIMER1 IMXRT_PADCFG(0, 56, 0xa, 0, 242, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_14_ECAT_TX_DATA1_1 IMXRT_PADCFG(0, 56, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_15_SEMC_DATA30 IMXRT_PADCFG(0, 57, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_NETC_PINMUX_ETH4_TX_EN IMXRT_PADCFG(0, 57, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_LPUART11_CTS_B IMXRT_PADCFG(0, 57, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_NETC_PINMUX_ETH0_RX_CLK IMXRT_PADCFG(0, 57, 0x3, 0, 206, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_15_LPUART5_DCD_B IMXRT_PADCFG(0, 57, 0x4, 0, 124, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_GPIO3_IO25 IMXRT_PADCFG(0, 57, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35 IMXRT_PADCFG(0, 57, 0x6, 0, 313, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_SAI3_TX_BCLK IMXRT_PADCFG(0, 57, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_NETC_PINMUX_ETH3_RX_CLK IMXRT_PADCFG(0, 57, 0x9, 0, 222, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_15_QTIMER2_TIMER2 IMXRT_PADCFG(0, 57, 0xa, 0, 243, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_ECAT_TX_EN_1 IMXRT_PADCFG(0, 57, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_16_SEMC_DATA31 IMXRT_PADCFG(0, 58, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_NETC_PINMUX_ETH4_TX_CLK IMXRT_PADCFG(0, 58, 0x1, 0, 237, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_16_LPUART11_RTS_B IMXRT_PADCFG(0, 58, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_NETC_PINMUX_ETH0_RXD02 IMXRT_PADCFG(0, 58, 0x3, 0, 211, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_16_LPUART5_DTR_B IMXRT_PADCFG(0, 58, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_GPIO3_IO26 IMXRT_PADCFG(0, 58, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14 IMXRT_PADCFG(0, 58, 0x6, 0, 293, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_16_SAI3_TX_SYNC IMXRT_PADCFG(0, 58, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_NETC_PINMUX_ETH3_RXD02 IMXRT_PADCFG(0, 58, 0x9, 0, 227, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_16_QTIMER2_TIMER3 IMXRT_PADCFG(0, 58, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_ECAT_TX_CLK_1 IMXRT_PADCFG(0, 58, 0xc, 0, 18, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_17_SEMC_DM03 IMXRT_PADCFG(0, 59, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_17_NETC_PINMUX_ETH4_RXD00 IMXRT_PADCFG(0, 59, 0x1, 0, 233, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_LPUART5_TX IMXRT_PADCFG(0, 59, 0x2, 0, 128, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_17_NETC_PINMUX_ETH0_RXD03 IMXRT_PADCFG(0, 59, 0x3, 0, 212, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_GPIO3_IO27 IMXRT_PADCFG(0, 59, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15 IMXRT_PADCFG(0, 59, 0x6, 0, 294, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_SAI3_MCLK IMXRT_PADCFG(0, 59, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_17_NETC_PINMUX_ETH3_RXD03 IMXRT_PADCFG(0, 59, 0x9, 0, 228, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_QTIMER3_TIMER0 IMXRT_PADCFG(0, 59, 0xa, 0, 244, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_ECAT_RX_DATA0_1 IMXRT_PADCFG(0, 59, 0xc, 0, 6, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_18_SEMC_DQS4 IMXRT_PADCFG(0, 60, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_NETC_PINMUX_ETH4_RXD01 IMXRT_PADCFG(0, 60, 0x1, 0, 234, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_18_LPUART5_RX IMXRT_PADCFG(0, 60, 0x2, 0, 127, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_18_NETC_PINMUX_ETH0_TX_ER IMXRT_PADCFG(0, 60, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_GPIO3_IO28 IMXRT_PADCFG(0, 60, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16 IMXRT_PADCFG(0, 60, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_EWM_EWM_OUT_B IMXRT_PADCFG(0, 60, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_NETC_PINMUX_ETH3_TX_ER IMXRT_PADCFG(0, 60, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_QTIMER3_TIMER1 IMXRT_PADCFG(0, 60, 0xa, 0, 245, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_18_ECAT_RX_DATA1_1 IMXRT_PADCFG(0, 60, 0xc, 0, 8, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_19_SEMC_CLKX00 IMXRT_PADCFG(0, 61, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_NETC_PINMUX_ETH4_RX_DV IMXRT_PADCFG(0, 61, 0x1, 0, 231, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_19_LPUART5_CTS_B IMXRT_PADCFG(0, 61, 0x2, 0, 123, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_19_NETC_ETH0_CRS IMXRT_PADCFG(0, 61, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_NETC_EMDC IMXRT_PADCFG(0, 61, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_GPIO3_IO29 IMXRT_PADCFG(0, 61, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_XBAR1_XBAR_INOUT36 IMXRT_PADCFG(0, 61, 0x6, 0, 314, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_LPI2C3_SCL IMXRT_PADCFG(0, 61, 0x8, 0, 82, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_19_NETC_ETH3_SLV_MDC IMXRT_PADCFG(0, 61, 0x9, 0, 197, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_19_QTIMER3_TIMER2 IMXRT_PADCFG(0, 61, 0xa, 0, 246, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_ECAT_RX_DV_1 IMXRT_PADCFG(0, 61, 0xc, 0, 14, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_20_SEMC_CLKX01 IMXRT_PADCFG(0, 62, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_NETC_PINMUX_ETH4_RX_ER IMXRT_PADCFG(0, 62, 0x1, 0, 232, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_20_LPUART5_RTS_B IMXRT_PADCFG(0, 62, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_NETC_ETH0_COL IMXRT_PADCFG(0, 62, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_NETC_EMDIO IMXRT_PADCFG(0, 62, 0x4, 0, 190, 0x3) +#define IOMUXC_PAD_GPIO_EMC_B2_20_GPIO3_IO30 IMXRT_PADCFG(0, 62, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_XBAR1_XBAR_INOUT37 IMXRT_PADCFG(0, 62, 0x6, 0, 315, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_LPI2C3_SDA IMXRT_PADCFG(0, 62, 0x8, 0, 83, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_20_NETC_ETH3_SLV_MDIO IMXRT_PADCFG(0, 62, 0x9, 0, 198, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_20_QTIMER3_TIMER3 IMXRT_PADCFG(0, 62, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_ECAT_RX_ER_1 IMXRT_PADCFG(0, 62, 0xc, 0, 16, 0x1) + +#define IOMUXC_PAD_GPIO_AD_00_CAN2_TX IMXRT_PADCFG(0, 63, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_MIC_CLK IMXRT_PADCFG(0, 63, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_GPT2_CAPTURE1 IMXRT_PADCFG(0, 63, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_FLEXPWM1_PWMA00 IMXRT_PADCFG(0, 63, 0x4, 0, 21, 0x2) +#define IOMUXC_PAD_GPIO_AD_00_GPIO4_IO00 IMXRT_PADCFG(0, 63, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_SINC1_MOD_CLK0 IMXRT_PADCFG(0, 63, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_FLEXIO2_FLEXIO00 IMXRT_PADCFG(0, 63, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_QTIMER4_TIMER0 IMXRT_PADCFG(0, 63, 0x9, 0, 247, 0x1) + +#define IOMUXC_PAD_GPIO_AD_01_CAN2_RX IMXRT_PADCFG(0, 64, 0x1, 0, 1, 0x0) +#define IOMUXC_PAD_GPIO_AD_01_MIC_BITSTREAM00 IMXRT_PADCFG(0, 64, 0x2, 0, 140, 0x0) +#define IOMUXC_PAD_GPIO_AD_01_GPT2_CAPTURE2 IMXRT_PADCFG(0, 64, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_01_FLEXPWM1_PWMB00 IMXRT_PADCFG(0, 64, 0x4, 0, 24, 0x2) +#define IOMUXC_PAD_GPIO_AD_01_GPIO4_IO01 IMXRT_PADCFG(0, 64, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_01_SINC1_MOD_CLK1 IMXRT_PADCFG(0, 64, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_01_FLEXIO2_FLEXIO01 IMXRT_PADCFG(0, 64, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_01_QTIMER4_TIMER1 IMXRT_PADCFG(0, 64, 0x9, 0, 248, 0x1) + +#define IOMUXC_PAD_GPIO_AD_02_MIC_BITSTREAM01 IMXRT_PADCFG(0, 65, 0x2, 0, 141, 0x0) +#define IOMUXC_PAD_GPIO_AD_02_GPT2_COMPARE1 IMXRT_PADCFG(0, 65, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_02_FLEXPWM1_PWMA01 IMXRT_PADCFG(0, 65, 0x4, 0, 22, 0x1) +#define IOMUXC_PAD_GPIO_AD_02_GPIO4_IO02 IMXRT_PADCFG(0, 65, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_02_SINC1_MOD_CLK2 IMXRT_PADCFG(0, 65, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_02_FLEXIO2_FLEXIO02 IMXRT_PADCFG(0, 65, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_02_QTIMER4_TIMER2 IMXRT_PADCFG(0, 65, 0x9, 0, 249, 0x0) + +#define IOMUXC_PAD_GPIO_AD_03_MIC_BITSTREAM02 IMXRT_PADCFG(0, 66, 0x2, 0, 142, 0x0) +#define IOMUXC_PAD_GPIO_AD_03_GPT2_COMPARE2 IMXRT_PADCFG(0, 66, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_03_FLEXPWM1_PWMB01 IMXRT_PADCFG(0, 66, 0x4, 0, 25, 0x1) +#define IOMUXC_PAD_GPIO_AD_03_GPIO4_IO03 IMXRT_PADCFG(0, 66, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_03_SINC1_EMCLK00 IMXRT_PADCFG(0, 66, 0x6, 0, 273, 0x0) +#define IOMUXC_PAD_GPIO_AD_03_FLEXIO2_FLEXIO03 IMXRT_PADCFG(0, 66, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_03_QTIMER4_TIMER3 IMXRT_PADCFG(0, 66, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_04_MIC_BITSTREAM03 IMXRT_PADCFG(0, 67, 0x2, 0, 143, 0x0) +#define IOMUXC_PAD_GPIO_AD_04_GPT2_COMPARE3 IMXRT_PADCFG(0, 67, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_04_FLEXPWM1_PWMB02 IMXRT_PADCFG(0, 67, 0x4, 0, 26, 0x1) +#define IOMUXC_PAD_GPIO_AD_04_GPIO4_IO04 IMXRT_PADCFG(0, 67, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_04_SINC1_EMBIT00 IMXRT_PADCFG(0, 67, 0x6, 0, 269, 0x0) +#define IOMUXC_PAD_GPIO_AD_04_FLEXIO2_FLEXIO04 IMXRT_PADCFG(0, 67, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_04_QTIMER5_TIMER0 IMXRT_PADCFG(0, 67, 0x9, 0, 250, 0x1) + +#define IOMUXC_PAD_GPIO_AD_05_GPT2_CLK IMXRT_PADCFG(0, 68, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_05_FLEXPWM1_PWMA02 IMXRT_PADCFG(0, 68, 0x4, 0, 23, 0x1) +#define IOMUXC_PAD_GPIO_AD_05_GPIO4_IO05 IMXRT_PADCFG(0, 68, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_05_SINC1_EMCLK01 IMXRT_PADCFG(0, 68, 0x6, 0, 274, 0x0) +#define IOMUXC_PAD_GPIO_AD_05_CCM_ENET_REF_CLK_25M IMXRT_PADCFG(0, 68, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_05_FLEXIO2_FLEXIO05 IMXRT_PADCFG(0, 68, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_05_QTIMER5_TIMER1 IMXRT_PADCFG(0, 68, 0x9, 0, 251, 0x1) + +#define IOMUXC_PAD_GPIO_AD_06_USB_OTG2_OC IMXRT_PADCFG(0, 69, 0x0, 0, 285, 0x0) +#define IOMUXC_PAD_GPIO_AD_06_CAN3_TX IMXRT_PADCFG(0, 69, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_06_FLEXPWM1_PWMX00 IMXRT_PADCFG(0, 69, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_06_GPIO4_IO06 IMXRT_PADCFG(0, 69, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_06_SINC1_EMBIT01 IMXRT_PADCFG(0, 69, 0x6, 0, 270, 0x0) +#define IOMUXC_PAD_GPIO_AD_06_FLEXIO2_FLEXIO06 IMXRT_PADCFG(0, 69, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_06_QTIMER5_TIMER2 IMXRT_PADCFG(0, 69, 0x9, 0, 252, 0x0) + +#define IOMUXC_PAD_GPIO_AD_07_USB_OTG2_PWR IMXRT_PADCFG(0, 70, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_07_CAN3_RX IMXRT_PADCFG(0, 70, 0x1, 0, 2, 0x0) +#define IOMUXC_PAD_GPIO_AD_07_FLEXPWM1_PWMX01 IMXRT_PADCFG(0, 70, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_07_GPIO4_IO07 IMXRT_PADCFG(0, 70, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_07_SINC1_EMCLK02 IMXRT_PADCFG(0, 70, 0x6, 0, 275, 0x0) +#define IOMUXC_PAD_GPIO_AD_07_FLEXIO2_FLEXIO07 IMXRT_PADCFG(0, 70, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_07_QTIMER5_TIMER3 IMXRT_PADCFG(0, 70, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_08_USBPHY2_OTG_ID IMXRT_PADCFG(0, 71, 0x0, 0, 288, 0x0) +#define IOMUXC_PAD_GPIO_AD_08_LPI2C5_SCL IMXRT_PADCFG(0, 71, 0x1, 0, 86, 0x0) +#define IOMUXC_PAD_GPIO_AD_08_FLEXPWM1_PWMX02 IMXRT_PADCFG(0, 71, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_08_GPIO4_IO08 IMXRT_PADCFG(0, 71, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_08_SINC1_EMBIT02 IMXRT_PADCFG(0, 71, 0x6, 0, 271, 0x0) +#define IOMUXC_PAD_GPIO_AD_08_FLEXIO2_FLEXIO08 IMXRT_PADCFG(0, 71, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_08_QTIMER6_TIMER0 IMXRT_PADCFG(0, 71, 0x9, 0, 253, 0x1) + +#define IOMUXC_PAD_GPIO_AD_09_USBPHY1_OTG_ID IMXRT_PADCFG(0, 72, 0x0, 0, 287, 0x0) +#define IOMUXC_PAD_GPIO_AD_09_LPI2C5_SDA IMXRT_PADCFG(0, 72, 0x1, 0, 87, 0x0) +#define IOMUXC_PAD_GPIO_AD_09_FLEXPWM1_PWMX03 IMXRT_PADCFG(0, 72, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_09_GPIO4_IO09 IMXRT_PADCFG(0, 72, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_09_SINC1_EMCLK03 IMXRT_PADCFG(0, 72, 0x6, 0, 276, 0x0) +#define IOMUXC_PAD_GPIO_AD_09_FLEXIO2_FLEXIO09 IMXRT_PADCFG(0, 72, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_09_QTIMER6_TIMER1 IMXRT_PADCFG(0, 72, 0x9, 0, 254, 0x1) + +#define IOMUXC_PAD_GPIO_AD_10_USB_OTG1_PWR IMXRT_PADCFG(0, 73, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_10_FLEXPWM2_PWMX00 IMXRT_PADCFG(0, 73, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_10_GPIO4_IO10 IMXRT_PADCFG(0, 73, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_10_SINC1_EMBIT03 IMXRT_PADCFG(0, 73, 0x6, 0, 272, 0x0) +#define IOMUXC_PAD_GPIO_AD_10_FLEXIO2_FLEXIO10 IMXRT_PADCFG(0, 73, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_10_QTIMER6_TIMER2 IMXRT_PADCFG(0, 73, 0x9, 0, 255, 0x0) + +#define IOMUXC_PAD_GPIO_AD_11_USB_OTG1_OC IMXRT_PADCFG(0, 74, 0x0, 0, 286, 0x0) +#define IOMUXC_PAD_GPIO_AD_11_FLEXPWM2_PWMX01 IMXRT_PADCFG(0, 74, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_11_GPIO4_IO11 IMXRT_PADCFG(0, 74, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_11_SINC_FILTER_GLUE1_BREAK IMXRT_PADCFG(0, 74, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_11_FLEXIO2_FLEXIO11 IMXRT_PADCFG(0, 74, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_11_QTIMER6_TIMER3 IMXRT_PADCFG(0, 74, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_12_SPDIF_LOCK IMXRT_PADCFG(0, 75, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_LPI2C5_SCLS IMXRT_PADCFG(0, 75, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_GPT1_CAPTURE1 IMXRT_PADCFG(0, 75, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_KPP_ROW07 IMXRT_PADCFG(0, 75, 0x3, 0, 81, 0x1) +#define IOMUXC_PAD_GPIO_AD_12_FLEXPWM2_PWMX02 IMXRT_PADCFG(0, 75, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_GPIO4_IO12 IMXRT_PADCFG(0, 75, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_XBAR1_XBAR_INOUT18 IMXRT_PADCFG(0, 75, 0x6, 0, 296, 0x0) +#define IOMUXC_PAD_GPIO_AD_12_EWM_EWM_OUT_B IMXRT_PADCFG(0, 75, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_FLEXIO2_FLEXIO12 IMXRT_PADCFG(0, 75, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_13_SPDIF_SR_CLK IMXRT_PADCFG(0, 76, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_LPI2C5_SDAS IMXRT_PADCFG(0, 76, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_GPT1_CAPTURE2 IMXRT_PADCFG(0, 76, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_KPP_COL07 IMXRT_PADCFG(0, 76, 0x3, 0, 73, 0x1) +#define IOMUXC_PAD_GPIO_AD_13_FLEXPWM2_PWMX03 IMXRT_PADCFG(0, 76, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_GPIO4_IO13 IMXRT_PADCFG(0, 76, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_LPUART3_TX IMXRT_PADCFG(0, 76, 0x6, 0, 121, 0x1) +#define IOMUXC_PAD_GPIO_AD_13_USDHC2_CD_B IMXRT_PADCFG(0, 76, 0x7, 0, 291, 0x1) +#define IOMUXC_PAD_GPIO_AD_13_FLEXIO2_FLEXIO13 IMXRT_PADCFG(0, 76, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_14_SPDIF_EXT_CLK IMXRT_PADCFG(0, 77, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_LPI2C5_HREQ IMXRT_PADCFG(0, 77, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_GPT1_COMPARE1 IMXRT_PADCFG(0, 77, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_KPP_ROW06 IMXRT_PADCFG(0, 77, 0x3, 0, 80, 0x1) +#define IOMUXC_PAD_GPIO_AD_14_FLEXPWM3_PWMX00 IMXRT_PADCFG(0, 77, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_GPIO4_IO14 IMXRT_PADCFG(0, 77, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_LPUART3_RX IMXRT_PADCFG(0, 77, 0x6, 0, 120, 0x1) +#define IOMUXC_PAD_GPIO_AD_14_USDHC2_WP IMXRT_PADCFG(0, 77, 0x7, 0, 292, 0x1) +#define IOMUXC_PAD_GPIO_AD_14_FLEXIO2_FLEXIO14 IMXRT_PADCFG(0, 77, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_15_SPDIF_IN IMXRT_PADCFG(0, 78, 0x0, 0, 282, 0x1) +#define IOMUXC_PAD_GPIO_AD_15_LPUART10_TX IMXRT_PADCFG(0, 78, 0x1, 0, 116, 0x0) +#define IOMUXC_PAD_GPIO_AD_15_GPT1_COMPARE2 IMXRT_PADCFG(0, 78, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_KPP_COL06 IMXRT_PADCFG(0, 78, 0x3, 0, 72, 0x1) +#define IOMUXC_PAD_GPIO_AD_15_FLEXPWM3_PWMX01 IMXRT_PADCFG(0, 78, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_GPIO4_IO15 IMXRT_PADCFG(0, 78, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_LPUART3_CTS_B IMXRT_PADCFG(0, 78, 0x6, 0, 119, 0x1) +#define IOMUXC_PAD_GPIO_AD_15_LPSPI3_PCS1 IMXRT_PADCFG(0, 78, 0x7, 0, 91, 0x1) +#define IOMUXC_PAD_GPIO_AD_15_FLEXIO2_FLEXIO15 IMXRT_PADCFG(0, 78, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_CAN1_TX IMXRT_PADCFG(0, 78, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_ECAT_CLK_ECAT_CLK25 IMXRT_PADCFG(0, 78, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_16_SPDIF_OUT IMXRT_PADCFG(0, 79, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_LPUART10_RX IMXRT_PADCFG(0, 79, 0x1, 0, 115, 0x0) +#define IOMUXC_PAD_GPIO_AD_16_GPT1_COMPARE3 IMXRT_PADCFG(0, 79, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_KPP_ROW05 IMXRT_PADCFG(0, 79, 0x3, 0, 79, 0x1) +#define IOMUXC_PAD_GPIO_AD_16_FLEXPWM3_PWMX02 IMXRT_PADCFG(0, 79, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_GPIO4_IO16 IMXRT_PADCFG(0, 79, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_LPUART3_RTS_B IMXRT_PADCFG(0, 79, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_LPSPI3_SCK IMXRT_PADCFG(0, 79, 0x7, 0, 94, 0x1) +#define IOMUXC_PAD_GPIO_AD_16_FLEXIO2_FLEXIO16 IMXRT_PADCFG(0, 79, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_CAN1_RX IMXRT_PADCFG(0, 79, 0x9, 0, 0, 0x0) +#define IOMUXC_PAD_GPIO_AD_16_ECAT_LINK_0 IMXRT_PADCFG(0, 79, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_17_SAI4_MCLK IMXRT_PADCFG(0, 80, 0x0, 0, 260, 0x0) +#define IOMUXC_PAD_GPIO_AD_17_ACMP1_CMPO IMXRT_PADCFG(0, 80, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_GPT1_CLK IMXRT_PADCFG(0, 80, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_KPP_COL05 IMXRT_PADCFG(0, 80, 0x3, 0, 71, 0x1) +#define IOMUXC_PAD_GPIO_AD_17_FLEXPWM3_PWMX03 IMXRT_PADCFG(0, 80, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_GPIO4_IO17 IMXRT_PADCFG(0, 80, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_I3C2_PUR IMXRT_PADCFG(0, 80, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_LPSPI3_PCS0 IMXRT_PADCFG(0, 80, 0x7, 0, 90, 0x1) +#define IOMUXC_PAD_GPIO_AD_17_FLEXIO2_FLEXIO17 IMXRT_PADCFG(0, 80, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_LPI2C3_HREQ IMXRT_PADCFG(0, 80, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_ECAT_LINK_1 IMXRT_PADCFG(0, 80, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_18_SAI4_RX_SYNC IMXRT_PADCFG(0, 81, 0x0, 0, 264, 0x0) +#define IOMUXC_PAD_GPIO_AD_18_ACMP2_CMPO IMXRT_PADCFG(0, 81, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_18_LPUART5_RI_B IMXRT_PADCFG(0, 81, 0x2, 0, 126, 0x0) +#define IOMUXC_PAD_GPIO_AD_18_KPP_ROW04 IMXRT_PADCFG(0, 81, 0x3, 0, 78, 0x1) +#define IOMUXC_PAD_GPIO_AD_18_FLEXPWM4_PWMX00 IMXRT_PADCFG(0, 81, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_18_GPIO4_IO18 IMXRT_PADCFG(0, 81, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_18_I3C2_SCL IMXRT_PADCFG(0, 81, 0x6, 0, 64, 0x0) +#define IOMUXC_PAD_GPIO_AD_18_LPSPI3_SDO IMXRT_PADCFG(0, 81, 0x7, 0, 96, 0x1) +#define IOMUXC_PAD_GPIO_AD_18_FLEXIO2_FLEXIO18 IMXRT_PADCFG(0, 81, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_18_LPI2C3_SCL IMXRT_PADCFG(0, 81, 0x9, 0, 82, 0x2) +#define IOMUXC_PAD_GPIO_AD_18_ECAT_PROM_CLK IMXRT_PADCFG(0, 81, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_19_SAI4_RX_BCLK IMXRT_PADCFG(0, 82, 0x0, 0, 261, 0x0) +#define IOMUXC_PAD_GPIO_AD_19_ACMP3_CMPO IMXRT_PADCFG(0, 82, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_19_XBAR1_XBAR_INOUT19 IMXRT_PADCFG(0, 82, 0x2, 0, 297, 0x0) +#define IOMUXC_PAD_GPIO_AD_19_KPP_COL04 IMXRT_PADCFG(0, 82, 0x3, 0, 70, 0x1) +#define IOMUXC_PAD_GPIO_AD_19_FLEXPWM4_PWMX01 IMXRT_PADCFG(0, 82, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_19_GPIO4_IO19 IMXRT_PADCFG(0, 82, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_19_I3C2_SDA IMXRT_PADCFG(0, 82, 0x6, 0, 65, 0x0) +#define IOMUXC_PAD_GPIO_AD_19_LPSPI3_SDI IMXRT_PADCFG(0, 82, 0x7, 0, 95, 0x1) +#define IOMUXC_PAD_GPIO_AD_19_FLEXIO2_FLEXIO19 IMXRT_PADCFG(0, 82, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_19_LPI2C3_SDA IMXRT_PADCFG(0, 82, 0x9, 0, 83, 0x2) +#define IOMUXC_PAD_GPIO_AD_19_ECAT_PROM_DATA IMXRT_PADCFG(0, 82, 0xc, 0, 20, 0x0) + +#define IOMUXC_PAD_GPIO_AD_20_SAI4_RX_DATA00 IMXRT_PADCFG(0, 83, 0x0, 0, 262, 0x0) +#define IOMUXC_PAD_GPIO_AD_20_ACMP4_CMPO IMXRT_PADCFG(0, 83, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_20_LPIT2_TRIGGER00 IMXRT_PADCFG(0, 83, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_20_SINC1_EMCLK00 IMXRT_PADCFG(0, 83, 0x3, 0, 273, 0x1) +#define IOMUXC_PAD_GPIO_AD_20_FLEXPWM4_PWMX02 IMXRT_PADCFG(0, 83, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_20_GPIO4_IO20 IMXRT_PADCFG(0, 83, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_20_NETC_TMR_TRIG1 IMXRT_PADCFG(0, 83, 0x6, 0, 203, 0x0) +#define IOMUXC_PAD_GPIO_AD_20_NETC_1588_CLK IMXRT_PADCFG(0, 83, 0x7, 0, 205, 0x0) +#define IOMUXC_PAD_GPIO_AD_20_FLEXIO2_FLEXIO20 IMXRT_PADCFG(0, 83, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_21_SAI4_TX_DATA00 IMXRT_PADCFG(0, 84, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_LPIT2_TRIGGER01 IMXRT_PADCFG(0, 84, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_SINC1_EMBIT00 IMXRT_PADCFG(0, 84, 0x3, 0, 269, 0x1) +#define IOMUXC_PAD_GPIO_AD_21_FLEXPWM4_PWMX03 IMXRT_PADCFG(0, 84, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_GPIO4_IO21 IMXRT_PADCFG(0, 84, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_NETC_TMR_TRIG2 IMXRT_PADCFG(0, 84, 0x6, 0, 204, 0x0) +#define IOMUXC_PAD_GPIO_AD_21_NETC_TMR_GCLK IMXRT_PADCFG(0, 84, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_FLEXIO2_FLEXIO21 IMXRT_PADCFG(0, 84, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_ECAT_LED_RUN IMXRT_PADCFG(0, 84, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_22_SAI4_TX_BCLK IMXRT_PADCFG(0, 85, 0x0, 0, 265, 0x0) +#define IOMUXC_PAD_GPIO_AD_22_LPIT2_TRIGGER02 IMXRT_PADCFG(0, 85, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_22_SINC1_EMCLK01 IMXRT_PADCFG(0, 85, 0x3, 0, 274, 0x1) +#define IOMUXC_PAD_GPIO_AD_22_GPIO4_IO22 IMXRT_PADCFG(0, 85, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_22_NETC_TMR_ALARM1 IMXRT_PADCFG(0, 85, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_22_FLEXIO2_FLEXIO22 IMXRT_PADCFG(0, 85, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_22_ECAT_LED_ERR IMXRT_PADCFG(0, 85, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_23_SAI4_TX_SYNC IMXRT_PADCFG(0, 86, 0x0, 0, 266, 0x0) +#define IOMUXC_PAD_GPIO_AD_23_LPIT2_TRIGGER03 IMXRT_PADCFG(0, 86, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_23_SINC1_EMBIT01 IMXRT_PADCFG(0, 86, 0x3, 0, 270, 0x1) +#define IOMUXC_PAD_GPIO_AD_23_GPIO4_IO23 IMXRT_PADCFG(0, 86, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_23_NETC_TMR_ALARM2 IMXRT_PADCFG(0, 86, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_23_FLEXIO2_FLEXIO23 IMXRT_PADCFG(0, 86, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_23_ECAT_LED_STATE_RUN IMXRT_PADCFG(0, 86, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_24_LPUART6_TX IMXRT_PADCFG(0, 87, 0x0, 0, 134, 0x1) +#define IOMUXC_PAD_GPIO_AD_24_LPI2C4_SCL IMXRT_PADCFG(0, 87, 0x1, 0, 84, 0x0) +#define IOMUXC_PAD_GPIO_AD_24_SINC2_MOD_CLK1 IMXRT_PADCFG(0, 87, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_24_FLEXPWM2_PWMA00 IMXRT_PADCFG(0, 87, 0x4, 0, 27, 0x1) +#define IOMUXC_PAD_GPIO_AD_24_GPIO4_IO24 IMXRT_PADCFG(0, 87, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_24_NETC_TMR_TRIG1 IMXRT_PADCFG(0, 87, 0x7, 0, 203, 0x1) +#define IOMUXC_PAD_GPIO_AD_24_FLEXIO2_FLEXIO24 IMXRT_PADCFG(0, 87, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_24_ECAT_LINK_ACT00 IMXRT_PADCFG(0, 87, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_25_LPUART6_RX IMXRT_PADCFG(0, 88, 0x0, 0, 133, 0x1) +#define IOMUXC_PAD_GPIO_AD_25_LPI2C4_SDA IMXRT_PADCFG(0, 88, 0x1, 0, 85, 0x0) +#define IOMUXC_PAD_GPIO_AD_25_LPSPI5_PCS3 IMXRT_PADCFG(0, 88, 0x2, 0, 104, 0x1) +#define IOMUXC_PAD_GPIO_AD_25_SINC2_MOD_CLK2 IMXRT_PADCFG(0, 88, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_25_FLEXPWM2_PWMB00 IMXRT_PADCFG(0, 88, 0x4, 0, 30, 0x1) +#define IOMUXC_PAD_GPIO_AD_25_GPIO4_IO25 IMXRT_PADCFG(0, 88, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_25_NETC_TMR_TRIG2 IMXRT_PADCFG(0, 88, 0x7, 0, 204, 0x1) +#define IOMUXC_PAD_GPIO_AD_25_FLEXIO2_FLEXIO25 IMXRT_PADCFG(0, 88, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_25_ECAT_LINK_ACT01 IMXRT_PADCFG(0, 88, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_26_LPUART6_CTS_B IMXRT_PADCFG(0, 89, 0x0, 0, 129, 0x1) +#define IOMUXC_PAD_GPIO_AD_26_LPUART5_TX IMXRT_PADCFG(0, 89, 0x1, 0, 128, 0x3) +#define IOMUXC_PAD_GPIO_AD_26_LPSPI5_PCS2 IMXRT_PADCFG(0, 89, 0x2, 0, 103, 0x1) +#define IOMUXC_PAD_GPIO_AD_26_SINC2_EMCLK00 IMXRT_PADCFG(0, 89, 0x3, 0, 279, 0x0) +#define IOMUXC_PAD_GPIO_AD_26_FLEXPWM2_PWMA01 IMXRT_PADCFG(0, 89, 0x4, 0, 28, 0x1) +#define IOMUXC_PAD_GPIO_AD_26_GPIO4_IO26 IMXRT_PADCFG(0, 89, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_26_KPP_ROW00 IMXRT_PADCFG(0, 89, 0x6, 0, 74, 0x1) +#define IOMUXC_PAD_GPIO_AD_26_NETC_TMR_PP1 IMXRT_PADCFG(0, 89, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_26_FLEXIO2_FLEXIO26 IMXRT_PADCFG(0, 89, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_26_USDHC2_CD_B IMXRT_PADCFG(0, 89, 0x9, 0, 291, 0x2) +#define IOMUXC_PAD_GPIO_AD_26_MIC_BITSTREAM02 IMXRT_PADCFG(0, 89, 0xc, 0, 142, 0x1) + +#define IOMUXC_PAD_GPIO_AD_27_LPUART6_RTS_B IMXRT_PADCFG(0, 90, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_LPUART5_RX IMXRT_PADCFG(0, 90, 0x1, 0, 127, 0x3) +#define IOMUXC_PAD_GPIO_AD_27_LPSPI5_PCS1 IMXRT_PADCFG(0, 90, 0x2, 0, 102, 0x2) +#define IOMUXC_PAD_GPIO_AD_27_SINC2_EMBIT00 IMXRT_PADCFG(0, 90, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_FLEXPWM2_PWMB01 IMXRT_PADCFG(0, 90, 0x4, 0, 31, 0x1) +#define IOMUXC_PAD_GPIO_AD_27_GPIO4_IO27 IMXRT_PADCFG(0, 90, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_KPP_COL00 IMXRT_PADCFG(0, 90, 0x6, 0, 66, 0x1) +#define IOMUXC_PAD_GPIO_AD_27_NETC_TMR_PP2 IMXRT_PADCFG(0, 90, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_FLEXIO2_FLEXIO27 IMXRT_PADCFG(0, 90, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_USDHC2_WP IMXRT_PADCFG(0, 90, 0x9, 0, 292, 0x2) +#define IOMUXC_PAD_GPIO_AD_27_MIC_CLK IMXRT_PADCFG(0, 90, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_28_LPSPI5_SCK IMXRT_PADCFG(0, 91, 0x0, 0, 105, 0x2) +#define IOMUXC_PAD_GPIO_AD_28_I3C1_PUR IMXRT_PADCFG(0, 91, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_SINC2_EMCLK01 IMXRT_PADCFG(0, 91, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_FLEXPWM2_PWMB02 IMXRT_PADCFG(0, 91, 0x4, 0, 32, 0x1) +#define IOMUXC_PAD_GPIO_AD_28_GPIO4_IO28 IMXRT_PADCFG(0, 91, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_KPP_ROW03 IMXRT_PADCFG(0, 91, 0x6, 0, 77, 0x1) +#define IOMUXC_PAD_GPIO_AD_28_NETC_TMR_PP3 IMXRT_PADCFG(0, 91, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_FLEXIO2_FLEXIO28 IMXRT_PADCFG(0, 91, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_USDHC2_RESET_B IMXRT_PADCFG(0, 91, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_MIC_BITSTREAM00 IMXRT_PADCFG(0, 91, 0xc, 0, 140, 0x1) + +#define IOMUXC_PAD_GPIO_AD_29_LPSPI5_PCS0 IMXRT_PADCFG(0, 92, 0x0, 0, 101, 0x2) +#define IOMUXC_PAD_GPIO_AD_29_USDHC2_CD_B IMXRT_PADCFG(0, 92, 0x2, 0, 291, 0x3) +#define IOMUXC_PAD_GPIO_AD_29_SINC2_EMBIT01 IMXRT_PADCFG(0, 92, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_FLEXPWM2_PWMA02 IMXRT_PADCFG(0, 92, 0x4, 0, 29, 0x1) +#define IOMUXC_PAD_GPIO_AD_29_GPIO4_IO29 IMXRT_PADCFG(0, 92, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_KPP_COL03 IMXRT_PADCFG(0, 92, 0x6, 0, 69, 0x1) +#define IOMUXC_PAD_GPIO_AD_29_EWM_EWM_OUT_B IMXRT_PADCFG(0, 92, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_FLEXIO2_FLEXIO29 IMXRT_PADCFG(0, 92, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_USDHC2_VSELECT IMXRT_PADCFG(0, 92, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_MIC_BITSTREAM01 IMXRT_PADCFG(0, 92, 0xc, 0, 141, 0x1) + +#define IOMUXC_PAD_GPIO_AD_30_LPSPI5_SDO IMXRT_PADCFG(0, 93, 0x0, 0, 107, 0x2) +#define IOMUXC_PAD_GPIO_AD_30_USB_OTG2_OC IMXRT_PADCFG(0, 93, 0x1, 0, 285, 0x1) +#define IOMUXC_PAD_GPIO_AD_30_CAN2_TX IMXRT_PADCFG(0, 93, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_30_SINC2_EMCLK02 IMXRT_PADCFG(0, 93, 0x3, 0, 280, 0x0) +#define IOMUXC_PAD_GPIO_AD_30_LPUART8_TX IMXRT_PADCFG(0, 93, 0x4, 0, 137, 0x0) +#define IOMUXC_PAD_GPIO_AD_30_GPIO4_IO30 IMXRT_PADCFG(0, 93, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_30_KPP_ROW02 IMXRT_PADCFG(0, 93, 0x6, 0, 76, 0x1) +#define IOMUXC_PAD_GPIO_AD_30_NETC_EMDC IMXRT_PADCFG(0, 93, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_30_FLEXIO2_FLEXIO30 IMXRT_PADCFG(0, 93, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_30_XBAR1_XBAR_INOUT24 IMXRT_PADCFG(0, 93, 0x9, 0, 302, 0x1) +#define IOMUXC_PAD_GPIO_AD_30_ECAT_MCLK IMXRT_PADCFG(0, 93, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_31_LPSPI5_SDI IMXRT_PADCFG(0, 94, 0x0, 0, 106, 0x2) +#define IOMUXC_PAD_GPIO_AD_31_USB_OTG2_PWR IMXRT_PADCFG(0, 94, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_31_CAN2_RX IMXRT_PADCFG(0, 94, 0x2, 0, 1, 0x1) +#define IOMUXC_PAD_GPIO_AD_31_SINC2_EMBIT02 IMXRT_PADCFG(0, 94, 0x3, 0, 277, 0x0) +#define IOMUXC_PAD_GPIO_AD_31_LPUART8_RX IMXRT_PADCFG(0, 94, 0x4, 0, 136, 0x0) +#define IOMUXC_PAD_GPIO_AD_31_GPIO4_IO31 IMXRT_PADCFG(0, 94, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_31_KPP_COL02 IMXRT_PADCFG(0, 94, 0x6, 0, 68, 0x1) +#define IOMUXC_PAD_GPIO_AD_31_NETC_EMDIO IMXRT_PADCFG(0, 94, 0x7, 0, 190, 0x4) +#define IOMUXC_PAD_GPIO_AD_31_FLEXIO2_FLEXIO31 IMXRT_PADCFG(0, 94, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_31_XBAR1_XBAR_INOUT25 IMXRT_PADCFG(0, 94, 0x9, 0, 303, 0x1) +#define IOMUXC_PAD_GPIO_AD_31_ECAT_MDIO IMXRT_PADCFG(0, 94, 0xc, 0, 19, 0x0) + +#define IOMUXC_PAD_GPIO_AD_32_LPI2C5_SCL IMXRT_PADCFG(0, 95, 0x0, 0, 86, 0x1) +#define IOMUXC_PAD_GPIO_AD_32_USBPHY2_OTG_ID IMXRT_PADCFG(0, 95, 0x1, 0, 288, 0x1) +#define IOMUXC_PAD_GPIO_AD_32_GPC_PMIC_RDY IMXRT_PADCFG(0, 95, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_32_SINC2_EMCLK03 IMXRT_PADCFG(0, 95, 0x3, 0, 281, 0x0) +#define IOMUXC_PAD_GPIO_AD_32_USDHC1_CD_B IMXRT_PADCFG(0, 95, 0x4, 0, 289, 0x0) +#define IOMUXC_PAD_GPIO_AD_32_GPIO5_IO00 IMXRT_PADCFG(0, 95, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_32_KPP_ROW01 IMXRT_PADCFG(0, 95, 0x6, 0, 75, 0x1) +#define IOMUXC_PAD_GPIO_AD_32_NETC_TMR_TRIG1 IMXRT_PADCFG(0, 95, 0x7, 0, 203, 0x2) +#define IOMUXC_PAD_GPIO_AD_32_LPUART10_TX IMXRT_PADCFG(0, 95, 0x8, 0, 116, 0x1) +#define IOMUXC_PAD_GPIO_AD_32_MIC_BITSTREAM03 IMXRT_PADCFG(0, 95, 0xc, 0, 143, 0x1) + +#define IOMUXC_PAD_GPIO_AD_33_LPI2C5_SDA IMXRT_PADCFG(0, 96, 0x0, 0, 87, 0x1) +#define IOMUXC_PAD_GPIO_AD_33_USBPHY1_OTG_ID IMXRT_PADCFG(0, 96, 0x1, 0, 287, 0x1) +#define IOMUXC_PAD_GPIO_AD_33_XBAR1_XBAR_INOUT17 IMXRT_PADCFG(0, 96, 0x2, 0, 295, 0x0) +#define IOMUXC_PAD_GPIO_AD_33_SINC2_EMBIT03 IMXRT_PADCFG(0, 96, 0x3, 0, 278, 0x0) +#define IOMUXC_PAD_GPIO_AD_33_USDHC1_WP IMXRT_PADCFG(0, 96, 0x4, 0, 290, 0x0) +#define IOMUXC_PAD_GPIO_AD_33_GPIO5_IO01 IMXRT_PADCFG(0, 96, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_33_KPP_COL01 IMXRT_PADCFG(0, 96, 0x6, 0, 67, 0x1) +#define IOMUXC_PAD_GPIO_AD_33_NETC_TMR_TRIG2 IMXRT_PADCFG(0, 96, 0x7, 0, 204, 0x2) +#define IOMUXC_PAD_GPIO_AD_33_LPUART10_RX IMXRT_PADCFG(0, 96, 0x8, 0, 115, 0x1) + +#define IOMUXC_PAD_GPIO_AD_34_I3C2_SCL IMXRT_PADCFG(0, 97, 0x0, 0, 64, 0x1) +#define IOMUXC_PAD_GPIO_AD_34_USB_OTG1_PWR IMXRT_PADCFG(0, 97, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_XBAR1_XBAR_INOUT18 IMXRT_PADCFG(0, 97, 0x2, 0, 296, 0x1) +#define IOMUXC_PAD_GPIO_AD_34_SINC_FILTER_GLUE2_BREAK IMXRT_PADCFG(0, 97, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_USDHC1_VSELECT IMXRT_PADCFG(0, 97, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_GPIO5_IO02 IMXRT_PADCFG(0, 97, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_NETC_TMR_ALARM1 IMXRT_PADCFG(0, 97, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_LPUART10_CTS_B IMXRT_PADCFG(0, 97, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_35_I3C2_SDA IMXRT_PADCFG(0, 98, 0x0, 0, 65, 0x1) +#define IOMUXC_PAD_GPIO_AD_35_USB_OTG1_OC IMXRT_PADCFG(0, 98, 0x1, 0, 286, 0x1) +#define IOMUXC_PAD_GPIO_AD_35_XBAR1_XBAR_INOUT19 IMXRT_PADCFG(0, 98, 0x2, 0, 297, 0x1) +#define IOMUXC_PAD_GPIO_AD_35_SINC2_MOD_CLK0 IMXRT_PADCFG(0, 98, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_35_USDHC1_RESET_B IMXRT_PADCFG(0, 98, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_35_GPIO5_IO03 IMXRT_PADCFG(0, 98, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_35_NETC_TMR_ALARM2 IMXRT_PADCFG(0, 98, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_35_LPUART10_RTS_B IMXRT_PADCFG(0, 98, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_00_USDHC1_CMD IMXRT_PADCFG(0, 99, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_00_SINC1_EMCLK02 IMXRT_PADCFG(0, 99, 0x1, 0, 275, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20 IMXRT_PADCFG(0, 99, 0x2, 0, 298, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_00_LPTMR2_ALT1 IMXRT_PADCFG(0, 99, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_00_XSPI_SLV_CS IMXRT_PADCFG(0, 99, 0x4, 0, 344, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_00_GPIO5_IO04 IMXRT_PADCFG(0, 99, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_00_LPSPI3_PCS0 IMXRT_PADCFG(0, 99, 0x6, 0, 90, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_00_KPP_ROW07 IMXRT_PADCFG(0, 99, 0x8, 0, 81, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_00_CCM_CLKO1 IMXRT_PADCFG(0, 99, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_01_USDHC1_CLK IMXRT_PADCFG(0, 100, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_01_SINC1_EMBIT02 IMXRT_PADCFG(0, 100, 0x1, 0, 271, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21 IMXRT_PADCFG(0, 100, 0x2, 0, 299, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_01_LPTMR2_ALT2 IMXRT_PADCFG(0, 100, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_01_XSPI_SLV_CLK IMXRT_PADCFG(0, 100, 0x4, 0, 354, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_01_GPIO5_IO05 IMXRT_PADCFG(0, 100, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_01_LPSPI3_SCK IMXRT_PADCFG(0, 100, 0x6, 0, 94, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_01_KPP_COL07 IMXRT_PADCFG(0, 100, 0x8, 0, 73, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_01_CCM_CLKO2 IMXRT_PADCFG(0, 100, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_02_USDHC1_DATA0 IMXRT_PADCFG(0, 101, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_02_SINC1_EMCLK03 IMXRT_PADCFG(0, 101, 0x1, 0, 276, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22 IMXRT_PADCFG(0, 101, 0x2, 0, 300, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_02_LPTMR2_ALT3 IMXRT_PADCFG(0, 101, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_02_XSPI_SLV_DATA04 IMXRT_PADCFG(0, 101, 0x4, 0, 350, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_02_GPIO5_IO06 IMXRT_PADCFG(0, 101, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_02_LPSPI3_SDO IMXRT_PADCFG(0, 101, 0x6, 0, 96, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_02_KPP_ROW06 IMXRT_PADCFG(0, 101, 0x8, 0, 80, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_02_FLEXSPI1_BUS2BIT_A_SS1_B IMXRT_PADCFG(0, 101, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_02_ECAT_RESET_OUT IMXRT_PADCFG(0, 101, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_03_USDHC1_DATA1 IMXRT_PADCFG(0, 102, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_03_SINC1_EMBIT03 IMXRT_PADCFG(0, 102, 0x1, 0, 272, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23 IMXRT_PADCFG(0, 102, 0x2, 0, 301, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_03_LPTMR3_ALT1 IMXRT_PADCFG(0, 102, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_03_XSPI_SLV_DATA05 IMXRT_PADCFG(0, 102, 0x4, 0, 351, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_03_GPIO5_IO07 IMXRT_PADCFG(0, 102, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_03_LPSPI3_SDI IMXRT_PADCFG(0, 102, 0x6, 0, 95, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_03_KPP_COL06 IMXRT_PADCFG(0, 102, 0x8, 0, 72, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_03_FLEXSPI1_BUS2BIT_B_SS1_B IMXRT_PADCFG(0, 102, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_04_USDHC1_DATA2 IMXRT_PADCFG(0, 103, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_SINC_FILTER_GLUE1_BREAK IMXRT_PADCFG(0, 103, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_SINC2_EMCLK02 IMXRT_PADCFG(0, 103, 0x2, 0, 280, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_04_LPTMR3_ALT2 IMXRT_PADCFG(0, 103, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_XSPI_SLV_DATA06 IMXRT_PADCFG(0, 103, 0x4, 0, 352, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_04_GPIO5_IO08 IMXRT_PADCFG(0, 103, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_LPSPI3_PCS1 IMXRT_PADCFG(0, 103, 0x6, 0, 91, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_04_FLEXSPI1_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 103, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_FLEXSPI1_BUS2BIT_A_SS1_B IMXRT_PADCFG(0, 103, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_05_USDHC1_DATA3 IMXRT_PADCFG(0, 104, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_05_SINC2_EMBIT02 IMXRT_PADCFG(0, 104, 0x2, 0, 277, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_05_LPTMR3_ALT3 IMXRT_PADCFG(0, 104, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_05_XSPI_SLV_DATA07 IMXRT_PADCFG(0, 104, 0x4, 0, 353, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_05_GPIO5_IO09 IMXRT_PADCFG(0, 104, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_05_LPSPI3_PCS2 IMXRT_PADCFG(0, 104, 0x6, 0, 92, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_05_FLEXSPI1_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 104, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_00_USDHC2_DATA3 IMXRT_PADCFG(0, 105, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_00_FLEXSPI1_BUS2BIT_B_DATA04 IMXRT_PADCFG(0, 105, 0x1, 0, 47, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_00_XSPI_SLV_DATA04 IMXRT_PADCFG(0, 105, 0x2, 0, 350, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_XBAR1_XBAR_INOUT17 IMXRT_PADCFG(0, 105, 0x3, 0, 295, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_KPP_ROW01 IMXRT_PADCFG(0, 105, 0x4, 0, 75, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_00_GPIO5_IO10 IMXRT_PADCFG(0, 105, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_00_LPSPI3_PCS3 IMXRT_PADCFG(0, 105, 0x6, 0, 93, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_NETC_1588_CLK IMXRT_PADCFG(0, 105, 0x8, 0, 205, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_LPUART8_TX IMXRT_PADCFG(0, 105, 0x9, 0, 137, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_MIC_BITSTREAM00 IMXRT_PADCFG(0, 105, 0xc, 0, 140, 0x2) + +#define IOMUXC_PAD_GPIO_SD_B2_01_USDHC2_DATA2 IMXRT_PADCFG(0, 106, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_01_FLEXSPI1_BUS2BIT_B_DATA05 IMXRT_PADCFG(0, 106, 0x1, 0, 48, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_01_XSPI_SLV_DATA05 IMXRT_PADCFG(0, 106, 0x2, 0, 351, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_01_QTIMER6_TIMER0 IMXRT_PADCFG(0, 106, 0x3, 0, 253, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_01_KPP_COL01 IMXRT_PADCFG(0, 106, 0x4, 0, 67, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_01_GPIO5_IO11 IMXRT_PADCFG(0, 106, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_01_NETC_TMR_GCLK IMXRT_PADCFG(0, 106, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_01_LPUART8_RX IMXRT_PADCFG(0, 106, 0x9, 0, 136, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_01_MIC_BITSTREAM01 IMXRT_PADCFG(0, 106, 0xc, 0, 141, 0x2) + +#define IOMUXC_PAD_GPIO_SD_B2_02_USDHC2_DATA1 IMXRT_PADCFG(0, 107, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_02_FLEXSPI1_BUS2BIT_B_DATA06 IMXRT_PADCFG(0, 107, 0x1, 0, 49, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_02_XSPI_SLV_DATA06 IMXRT_PADCFG(0, 107, 0x2, 0, 352, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_02_QTIMER6_TIMER1 IMXRT_PADCFG(0, 107, 0x3, 0, 254, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_02_KPP_ROW00 IMXRT_PADCFG(0, 107, 0x4, 0, 74, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_02_GPIO5_IO12 IMXRT_PADCFG(0, 107, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_02_NETC_TMR_ALARM1 IMXRT_PADCFG(0, 107, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_02_LPUART8_CTS_B IMXRT_PADCFG(0, 107, 0x9, 0, 135, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_02_MIC_BITSTREAM02 IMXRT_PADCFG(0, 107, 0xc, 0, 142, 0x2) + +#define IOMUXC_PAD_GPIO_SD_B2_03_USDHC2_DATA0 IMXRT_PADCFG(0, 108, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_03_FLEXSPI1_BUS2BIT_B_DATA07 IMXRT_PADCFG(0, 108, 0x1, 0, 50, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_03_XSPI_SLV_DATA07 IMXRT_PADCFG(0, 108, 0x2, 0, 353, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_03_QTIMER6_TIMER2 IMXRT_PADCFG(0, 108, 0x3, 0, 255, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_03_KPP_COL00 IMXRT_PADCFG(0, 108, 0x4, 0, 66, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_03_GPIO5_IO13 IMXRT_PADCFG(0, 108, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_03_NETC_TMR_ALARM2 IMXRT_PADCFG(0, 108, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_03_LPUART8_RTS_B IMXRT_PADCFG(0, 108, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_03_MIC_BITSTREAM03 IMXRT_PADCFG(0, 108, 0xc, 0, 143, 0x2) + +#define IOMUXC_PAD_GPIO_SD_B2_04_USDHC2_CLK IMXRT_PADCFG(0, 109, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_04_FLEXSPI1_BUS2BIT_B_SS1_B IMXRT_PADCFG(0, 109, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_04_QTIMER7_TIMER0 IMXRT_PADCFG(0, 109, 0x3, 0, 256, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_04_KPP_ROW03 IMXRT_PADCFG(0, 109, 0x4, 0, 77, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_04_GPIO5_IO14 IMXRT_PADCFG(0, 109, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_04_LPUART5_RI_B IMXRT_PADCFG(0, 109, 0x6, 0, 126, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_04_NETC_TMR_PP1 IMXRT_PADCFG(0, 109, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_04_MIC_CLK IMXRT_PADCFG(0, 109, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_05_USDHC2_CMD IMXRT_PADCFG(0, 110, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_05_FLEXSPI1_BUS2BIT_B_DQS IMXRT_PADCFG(0, 110, 0x1, 0, 42, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_05_XSPI_SLV_DQS IMXRT_PADCFG(0, 110, 0x2, 0, 345, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_05_QTIMER7_TIMER1 IMXRT_PADCFG(0, 110, 0x3, 0, 257, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_05_LPSPI4_PCS3 IMXRT_PADCFG(0, 110, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_05_GPIO5_IO15 IMXRT_PADCFG(0, 110, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_05_LPUART5_DTR_B IMXRT_PADCFG(0, 110, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_05_NETC_TMR_PP2 IMXRT_PADCFG(0, 110, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_06_USDHC2_RESET_B IMXRT_PADCFG(0, 111, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_FLEXSPI1_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 111, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_XSPI_SLV_CS IMXRT_PADCFG(0, 111, 0x2, 0, 344, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_06_QTIMER7_TIMER2 IMXRT_PADCFG(0, 111, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_LPSPI4_PCS2 IMXRT_PADCFG(0, 111, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_GPIO5_IO16 IMXRT_PADCFG(0, 111, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_LPUART5_CTS_B IMXRT_PADCFG(0, 111, 0x6, 0, 123, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_06_NETC_TMR_PP3 IMXRT_PADCFG(0, 111, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_07_USDHC2_STROBE IMXRT_PADCFG(0, 112, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_FLEXSPI1_BUS2BIT_B_SCLK IMXRT_PADCFG(0, 112, 0x1, 0, 51, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_07_XSPI_SLV_CLK IMXRT_PADCFG(0, 112, 0x2, 0, 354, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_07_QTIMER7_TIMER3 IMXRT_PADCFG(0, 112, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_LPSPI4_PCS1 IMXRT_PADCFG(0, 112, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_GPIO5_IO17 IMXRT_PADCFG(0, 112, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_LPUART5_RTS_B IMXRT_PADCFG(0, 112, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_NETC_TMR_ALARM1 IMXRT_PADCFG(0, 112, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_08_USDHC2_DATA4 IMXRT_PADCFG(0, 113, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_08_FLEXSPI1_BUS2BIT_B_DATA00 IMXRT_PADCFG(0, 113, 0x1, 0, 43, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_08_XSPI_SLV_DATA00 IMXRT_PADCFG(0, 113, 0x2, 0, 346, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_08_QTIMER8_TIMER0 IMXRT_PADCFG(0, 113, 0x3, 0, 258, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_08_LPSPI4_SCK IMXRT_PADCFG(0, 113, 0x4, 0, 98, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_08_GPIO5_IO18 IMXRT_PADCFG(0, 113, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_08_LPUART5_TX IMXRT_PADCFG(0, 113, 0x6, 0, 128, 0x4) +#define IOMUXC_PAD_GPIO_SD_B2_08_NETC_TMR_ALARM2 IMXRT_PADCFG(0, 113, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_08_NETC_TMR_PP2 IMXRT_PADCFG(0, 113, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_09_USDHC2_DATA5 IMXRT_PADCFG(0, 114, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_09_FLEXSPI1_BUS2BIT_B_DATA01 IMXRT_PADCFG(0, 114, 0x1, 0, 44, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_09_XSPI_SLV_DATA01 IMXRT_PADCFG(0, 114, 0x2, 0, 347, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_09_QTIMER8_TIMER1 IMXRT_PADCFG(0, 114, 0x3, 0, 259, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_09_LPSPI4_PCS0 IMXRT_PADCFG(0, 114, 0x4, 0, 97, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_09_GPIO5_IO19 IMXRT_PADCFG(0, 114, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_09_LPUART5_RX IMXRT_PADCFG(0, 114, 0x6, 0, 127, 0x4) +#define IOMUXC_PAD_GPIO_SD_B2_09_NETC_TMR_PP1 IMXRT_PADCFG(0, 114, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_10_USDHC2_DATA6 IMXRT_PADCFG(0, 115, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_10_FLEXSPI1_BUS2BIT_B_DATA02 IMXRT_PADCFG(0, 115, 0x1, 0, 45, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_10_XSPI_SLV_DATA02 IMXRT_PADCFG(0, 115, 0x2, 0, 348, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_10_QTIMER8_TIMER2 IMXRT_PADCFG(0, 115, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_10_LPSPI4_SDO IMXRT_PADCFG(0, 115, 0x4, 0, 100, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_10_GPIO5_IO20 IMXRT_PADCFG(0, 115, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_10_LPUART5_DCD_B IMXRT_PADCFG(0, 115, 0x6, 0, 124, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_10_NETC_TMR_TRIG2 IMXRT_PADCFG(0, 115, 0x8, 0, 204, 0x3) +#define IOMUXC_PAD_GPIO_SD_B2_10_NETC_TMR_PP3 IMXRT_PADCFG(0, 115, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_10_NETC_EMDIO IMXRT_PADCFG(0, 115, 0xa, 0, 190, 0x5) +#define IOMUXC_PAD_GPIO_SD_B2_10_ECAT_MDIO IMXRT_PADCFG(0, 115, 0xc, 0, 19, 0x1) + +#define IOMUXC_PAD_GPIO_SD_B2_11_USDHC2_DATA7 IMXRT_PADCFG(0, 116, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_FLEXSPI1_BUS2BIT_B_DATA03 IMXRT_PADCFG(0, 116, 0x1, 0, 46, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_11_XSPI_SLV_DATA03 IMXRT_PADCFG(0, 116, 0x2, 0, 349, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_11_QTIMER8_TIMER3 IMXRT_PADCFG(0, 116, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_LPSPI4_SDI IMXRT_PADCFG(0, 116, 0x4, 0, 99, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_11_GPIO5_IO21 IMXRT_PADCFG(0, 116, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_LPUART5_DSR_B IMXRT_PADCFG(0, 116, 0x6, 0, 125, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_11_SFA_ATX_CLK_OUT IMXRT_PADCFG(0, 116, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_NETC_TMR_TRIG1 IMXRT_PADCFG(0, 116, 0x8, 0, 203, 0x3) +#define IOMUXC_PAD_GPIO_SD_B2_11_NETC_EMDC IMXRT_PADCFG(0, 116, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_ECAT_MCLK IMXRT_PADCFG(0, 116, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_12_DUMMY_FLEXSPI1_BUS2BIT_A_DQS IMXRT_PADCFG(0, 117, 0x0, 0, 41, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_12_DUMMY_FLEXSPI1_BUS2BIT_B_DQS IMXRT_PADCFG(0, 117, 0x1, 0, 42, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_12_DUMMY_GPIO5_IO22 IMXRT_PADCFG(0, 117, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_00_NETC_PINMUX_ETH1_TXD00 IMXRT_PADCFG(0, 118, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_ADC2_CONV_D00 IMXRT_PADCFG(0, 118, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_SEMC_CSX01 IMXRT_PADCFG(0, 118, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_QTIMER1_TIMER0 IMXRT_PADCFG(0, 118, 0x3, 0, 238, 0x2) +#define IOMUXC_PAD_GPIO_B1_00_XBAR1_XBAR_INOUT26 IMXRT_PADCFG(0, 118, 0x4, 0, 304, 0x1) +#define IOMUXC_PAD_GPIO_B1_00_GPIO6_IO00 IMXRT_PADCFG(0, 118, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_TPM5_CH00 IMXRT_PADCFG(0, 118, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_NETC_PINMUX_ETH4_TXD00 IMXRT_PADCFG(0, 118, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_01_NETC_PINMUX_ETH1_TXD01 IMXRT_PADCFG(0, 119, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_ADC2_CONV_D01 IMXRT_PADCFG(0, 119, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_SEMC_CSX02 IMXRT_PADCFG(0, 119, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_QTIMER1_TIMER1 IMXRT_PADCFG(0, 119, 0x3, 0, 239, 0x2) +#define IOMUXC_PAD_GPIO_B1_01_XBAR1_XBAR_INOUT27 IMXRT_PADCFG(0, 119, 0x4, 0, 305, 0x1) +#define IOMUXC_PAD_GPIO_B1_01_GPIO6_IO01 IMXRT_PADCFG(0, 119, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_TPM5_CH01 IMXRT_PADCFG(0, 119, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_NETC_PINMUX_ETH4_TXD01 IMXRT_PADCFG(0, 119, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_SAI4_RX_DATA00 IMXRT_PADCFG(0, 119, 0xc, 0, 262, 0x1) + +#define IOMUXC_PAD_GPIO_B1_02_NETC_PINMUX_ETH1_TX_EN IMXRT_PADCFG(0, 120, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_ADC2_CONV_D02 IMXRT_PADCFG(0, 120, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_LPI2C6_SCL IMXRT_PADCFG(0, 120, 0x2, 0, 88, 0x0) +#define IOMUXC_PAD_GPIO_B1_02_QTIMER1_TIMER2 IMXRT_PADCFG(0, 120, 0x3, 0, 240, 0x1) +#define IOMUXC_PAD_GPIO_B1_02_XBAR1_XBAR_INOUT28 IMXRT_PADCFG(0, 120, 0x4, 0, 306, 0x1) +#define IOMUXC_PAD_GPIO_B1_02_GPIO6_IO02 IMXRT_PADCFG(0, 120, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_TPM5_CH02 IMXRT_PADCFG(0, 120, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_FLEXSPI1_BUS2BIT_B_SS1_B IMXRT_PADCFG(0, 120, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_NETC_PINMUX_ETH4_TX_EN IMXRT_PADCFG(0, 120, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_LPUART11_TX IMXRT_PADCFG(0, 120, 0x9, 0, 118, 0x1) +#define IOMUXC_PAD_GPIO_B1_02_SAI4_RX_DATA01 IMXRT_PADCFG(0, 120, 0xc, 0, 263, 0x0) + +#define IOMUXC_PAD_GPIO_B1_03_NETC_PINMUX_ETH1_TX_CLK IMXRT_PADCFG(0, 121, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_03_ADC2_CONV_D03 IMXRT_PADCFG(0, 121, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_03_LPI2C6_SDA IMXRT_PADCFG(0, 121, 0x2, 0, 89, 0x0) +#define IOMUXC_PAD_GPIO_B1_03_QTIMER2_TIMER0 IMXRT_PADCFG(0, 121, 0x3, 0, 241, 0x2) +#define IOMUXC_PAD_GPIO_B1_03_XBAR1_XBAR_INOUT29 IMXRT_PADCFG(0, 121, 0x4, 0, 307, 0x1) +#define IOMUXC_PAD_GPIO_B1_03_GPIO6_IO03 IMXRT_PADCFG(0, 121, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_03_TPM5_CH03 IMXRT_PADCFG(0, 121, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_03_FLEXSPI1_BUS2BIT_B_DQS IMXRT_PADCFG(0, 121, 0x7, 0, 42, 0x2) +#define IOMUXC_PAD_GPIO_B1_03_NETC_PINMUX_ETH4_TX_CLK IMXRT_PADCFG(0, 121, 0x8, 0, 237, 0x2) +#define IOMUXC_PAD_GPIO_B1_03_LPUART11_RX IMXRT_PADCFG(0, 121, 0x9, 0, 117, 0x1) +#define IOMUXC_PAD_GPIO_B1_03_SAI4_RX_DATA02 IMXRT_PADCFG(0, 121, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_04_NETC_PINMUX_ETH1_RXD00 IMXRT_PADCFG(0, 122, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_ADC2_CONV_D04 IMXRT_PADCFG(0, 122, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_LPUART9_RX IMXRT_PADCFG(0, 122, 0x2, 0, 138, 0x1) +#define IOMUXC_PAD_GPIO_B1_04_QTIMER2_TIMER1 IMXRT_PADCFG(0, 122, 0x3, 0, 242, 0x2) +#define IOMUXC_PAD_GPIO_B1_04_XBAR1_XBAR_INOUT30 IMXRT_PADCFG(0, 122, 0x4, 0, 308, 0x1) +#define IOMUXC_PAD_GPIO_B1_04_GPIO6_IO04 IMXRT_PADCFG(0, 122, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_TPM5_EXTCLK IMXRT_PADCFG(0, 122, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_FLEXSPI1_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 122, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_NETC_PINMUX_ETH4_RXD00 IMXRT_PADCFG(0, 122, 0x8, 0, 233, 0x2) +#define IOMUXC_PAD_GPIO_B1_04_SAI4_RX_DATA03 IMXRT_PADCFG(0, 122, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_05_NETC_PINMUX_ETH1_RXD01 IMXRT_PADCFG(0, 123, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_ADC2_CONV_D05 IMXRT_PADCFG(0, 123, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_LPUART9_CTS_B IMXRT_PADCFG(0, 123, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_QTIMER2_TIMER2 IMXRT_PADCFG(0, 123, 0x3, 0, 243, 0x1) +#define IOMUXC_PAD_GPIO_B1_05_XBAR1_XBAR_INOUT31 IMXRT_PADCFG(0, 123, 0x4, 0, 309, 0x1) +#define IOMUXC_PAD_GPIO_B1_05_GPIO6_IO05 IMXRT_PADCFG(0, 123, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_TPM6_EXTCLK IMXRT_PADCFG(0, 123, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_FLEXSPI1_BUS2BIT_B_SCLK IMXRT_PADCFG(0, 123, 0x7, 0, 51, 0x1) +#define IOMUXC_PAD_GPIO_B1_05_NETC_PINMUX_ETH4_RXD01 IMXRT_PADCFG(0, 123, 0x8, 0, 234, 0x2) +#define IOMUXC_PAD_GPIO_B1_05_SAI4_MCLK IMXRT_PADCFG(0, 123, 0xc, 0, 260, 0x1) + +#define IOMUXC_PAD_GPIO_B1_06_NETC_PINMUX_ETH1_RX_DV IMXRT_PADCFG(0, 124, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_06_ADC2_CONV_D06 IMXRT_PADCFG(0, 124, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_06_LPUART9_TX IMXRT_PADCFG(0, 124, 0x2, 0, 139, 0x1) +#define IOMUXC_PAD_GPIO_B1_06_QTIMER3_TIMER0 IMXRT_PADCFG(0, 124, 0x3, 0, 244, 0x2) +#define IOMUXC_PAD_GPIO_B1_06_XBAR1_XBAR_INOUT32 IMXRT_PADCFG(0, 124, 0x4, 0, 310, 0x1) +#define IOMUXC_PAD_GPIO_B1_06_GPIO6_IO06 IMXRT_PADCFG(0, 124, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_06_TPM6_CH00 IMXRT_PADCFG(0, 124, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_06_FLEXSPI1_BUS2BIT_B_DATA07 IMXRT_PADCFG(0, 124, 0x7, 0, 50, 0x1) +#define IOMUXC_PAD_GPIO_B1_06_NETC_PINMUX_ETH4_RX_DV IMXRT_PADCFG(0, 124, 0x8, 0, 231, 0x2) +#define IOMUXC_PAD_GPIO_B1_06_SAI4_RX_BCLK IMXRT_PADCFG(0, 124, 0xc, 0, 261, 0x1) + +#define IOMUXC_PAD_GPIO_B1_07_NETC_PINMUX_ETH1_TXD02 IMXRT_PADCFG(0, 125, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_ADC2_CONV_D07 IMXRT_PADCFG(0, 125, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_LPUART9_RTS_B IMXRT_PADCFG(0, 125, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_QTIMER3_TIMER1 IMXRT_PADCFG(0, 125, 0x3, 0, 245, 0x2) +#define IOMUXC_PAD_GPIO_B1_07_XBAR1_XBAR_INOUT33 IMXRT_PADCFG(0, 125, 0x4, 0, 311, 0x1) +#define IOMUXC_PAD_GPIO_B1_07_GPIO6_IO07 IMXRT_PADCFG(0, 125, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_TPM6_CH01 IMXRT_PADCFG(0, 125, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_FLEXSPI1_BUS2BIT_B_DATA06 IMXRT_PADCFG(0, 125, 0x7, 0, 49, 0x1) +#define IOMUXC_PAD_GPIO_B1_07_NETC_PINMUX_ETH4_TXD02 IMXRT_PADCFG(0, 125, 0x8, 0, 232, 0x2) +#define IOMUXC_PAD_GPIO_B1_07_LPSPI6_SDI IMXRT_PADCFG(0, 125, 0x9, 0, 113, 0x2) +#define IOMUXC_PAD_GPIO_B1_07_SAI4_RX_SYNC IMXRT_PADCFG(0, 125, 0xc, 0, 264, 0x1) + +#define IOMUXC_PAD_GPIO_B1_08_NETC_PINMUX_ETH1_TXD03 IMXRT_PADCFG(0, 126, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_ADC2_CONV_RDY_CLK IMXRT_PADCFG(0, 126, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_USDHC1_CD_B IMXRT_PADCFG(0, 126, 0x2, 0, 289, 0x1) +#define IOMUXC_PAD_GPIO_B1_08_QTIMER3_TIMER2 IMXRT_PADCFG(0, 126, 0x3, 0, 246, 0x1) +#define IOMUXC_PAD_GPIO_B1_08_XBAR1_XBAR_INOUT36 IMXRT_PADCFG(0, 126, 0x4, 0, 314, 0x1) +#define IOMUXC_PAD_GPIO_B1_08_GPIO6_IO08 IMXRT_PADCFG(0, 126, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_TPM6_CH02 IMXRT_PADCFG(0, 126, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_FLEXSPI1_BUS2BIT_B_DATA05 IMXRT_PADCFG(0, 126, 0x7, 0, 48, 0x1) +#define IOMUXC_PAD_GPIO_B1_08_NETC_PINMUX_ETH4_TXD03 IMXRT_PADCFG(0, 126, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_LPSPI6_SDO IMXRT_PADCFG(0, 126, 0x9, 0, 114, 0x2) +#define IOMUXC_PAD_GPIO_B1_08_SAI4_TX_BCLK IMXRT_PADCFG(0, 126, 0xc, 0, 265, 0x1) + +#define IOMUXC_PAD_GPIO_B1_09_NETC_PINMUX_ETH1_RXD02 IMXRT_PADCFG(0, 127, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_09_USDHC1_WP IMXRT_PADCFG(0, 127, 0x2, 0, 290, 0x1) +#define IOMUXC_PAD_GPIO_B1_09_QTIMER4_TIMER0 IMXRT_PADCFG(0, 127, 0x3, 0, 247, 0x2) +#define IOMUXC_PAD_GPIO_B1_09_XBAR1_XBAR_INOUT37 IMXRT_PADCFG(0, 127, 0x4, 0, 315, 0x1) +#define IOMUXC_PAD_GPIO_B1_09_GPIO6_IO09 IMXRT_PADCFG(0, 127, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_09_TPM6_CH03 IMXRT_PADCFG(0, 127, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_09_FLEXSPI1_BUS2BIT_B_DATA04 IMXRT_PADCFG(0, 127, 0x7, 0, 47, 0x1) +#define IOMUXC_PAD_GPIO_B1_09_NETC_PINMUX_ETH4_RXD02 IMXRT_PADCFG(0, 127, 0x8, 0, 235, 0x2) +#define IOMUXC_PAD_GPIO_B1_09_LPSPI6_PCS1 IMXRT_PADCFG(0, 127, 0x9, 0, 109, 0x2) +#define IOMUXC_PAD_GPIO_B1_09_SAI4_TX_SYNC IMXRT_PADCFG(0, 127, 0xc, 0, 266, 0x1) + +#define IOMUXC_PAD_GPIO_B1_10_NETC_PINMUX_ETH1_RXD03 IMXRT_PADCFG(0, 128, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_10_USDHC1_RESET_B IMXRT_PADCFG(0, 128, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_10_QTIMER4_TIMER1 IMXRT_PADCFG(0, 128, 0x3, 0, 248, 0x2) +#define IOMUXC_PAD_GPIO_B1_10_XBAR1_XBAR_INOUT34 IMXRT_PADCFG(0, 128, 0x4, 0, 312, 0x1) +#define IOMUXC_PAD_GPIO_B1_10_GPIO6_IO10 IMXRT_PADCFG(0, 128, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_10_FLEXSPI1_BUS2BIT_B_DATA03 IMXRT_PADCFG(0, 128, 0x7, 0, 46, 0x1) +#define IOMUXC_PAD_GPIO_B1_10_NETC_PINMUX_ETH4_RXD03 IMXRT_PADCFG(0, 128, 0x8, 0, 236, 0x2) +#define IOMUXC_PAD_GPIO_B1_10_LPSPI6_PCS2 IMXRT_PADCFG(0, 128, 0x9, 0, 110, 0x2) +#define IOMUXC_PAD_GPIO_B1_10_SAI4_TX_DATA00 IMXRT_PADCFG(0, 128, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_11_NETC_PINMUX_ETH1_RX_CLK IMXRT_PADCFG(0, 129, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_11_QTIMER4_TIMER2 IMXRT_PADCFG(0, 129, 0x3, 0, 249, 0x1) +#define IOMUXC_PAD_GPIO_B1_11_XBAR1_XBAR_INOUT35 IMXRT_PADCFG(0, 129, 0x4, 0, 313, 0x1) +#define IOMUXC_PAD_GPIO_B1_11_GPIO6_IO11 IMXRT_PADCFG(0, 129, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_11_FLEXSPI1_BUS2BIT_B_DATA02 IMXRT_PADCFG(0, 129, 0x7, 0, 45, 0x1) +#define IOMUXC_PAD_GPIO_B1_11_NETC_PINMUX_ETH4_RX_CLK IMXRT_PADCFG(0, 129, 0x8, 0, 230, 0x2) +#define IOMUXC_PAD_GPIO_B1_11_LPSPI6_PCS3 IMXRT_PADCFG(0, 129, 0x9, 0, 111, 0x1) +#define IOMUXC_PAD_GPIO_B1_11_SAI4_TX_DATA01 IMXRT_PADCFG(0, 129, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_12_NETC_PINMUX_ETH1_RX_ER IMXRT_PADCFG(0, 130, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_12_NETC_EMDIO IMXRT_PADCFG(0, 130, 0x1, 0, 190, 0x6) +#define IOMUXC_PAD_GPIO_B1_12_GPIO6_IO12 IMXRT_PADCFG(0, 130, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_12_FLEXSPI1_BUS2BIT_B_DATA01 IMXRT_PADCFG(0, 130, 0x7, 0, 44, 0x1) +#define IOMUXC_PAD_GPIO_B1_12_NETC_PINMUX_ETH4_RX_ER IMXRT_PADCFG(0, 130, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_12_LPSPI6_PCS0 IMXRT_PADCFG(0, 130, 0x9, 0, 108, 0x2) +#define IOMUXC_PAD_GPIO_B1_12_SAI4_TX_DATA02 IMXRT_PADCFG(0, 130, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_13_NETC_PINMUX_ETH1_TX_ER IMXRT_PADCFG(0, 131, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_NETC_EMDC IMXRT_PADCFG(0, 131, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_USDHC1_VSELECT IMXRT_PADCFG(0, 131, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_CCM_ENET_REF_CLK_25M IMXRT_PADCFG(0, 131, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_GPIO6_IO13 IMXRT_PADCFG(0, 131, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_FLEXSPI1_BUS2BIT_B_DATA00 IMXRT_PADCFG(0, 131, 0x7, 0, 43, 0x1) +#define IOMUXC_PAD_GPIO_B1_13_NETC_PINMUX_ETH4_TX_ER IMXRT_PADCFG(0, 131, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_LPSPI6_SCK IMXRT_PADCFG(0, 131, 0x9, 0, 112, 0x2) +#define IOMUXC_PAD_GPIO_B1_13_SAI4_TX_DATA03 IMXRT_PADCFG(0, 131, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_00_NETC_ETH1_CRS IMXRT_PADCFG(0, 132, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_00_SEMC_CSX03 IMXRT_PADCFG(0, 132, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_00_LPIT3_TRIGGER00 IMXRT_PADCFG(0, 132, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_00_SAI4_MCLK IMXRT_PADCFG(0, 132, 0x4, 0, 260, 0x2) +#define IOMUXC_PAD_GPIO_B2_00_GPIO6_IO14 IMXRT_PADCFG(0, 132, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_00_NETC_ETH4_CRS IMXRT_PADCFG(0, 132, 0x8, 0, 200, 0x2) +#define IOMUXC_PAD_GPIO_B2_00_LPSPI6_SDI IMXRT_PADCFG(0, 132, 0x9, 0, 113, 0x3) +#define IOMUXC_PAD_GPIO_B2_00_NETC_ETH2_SLV_MDIO IMXRT_PADCFG(0, 132, 0xa, 0, 194, 0x2) +#define IOMUXC_PAD_GPIO_B2_00_ECAT_CLK_ECAT_CLK25 IMXRT_PADCFG(0, 132, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_01_NETC_ETH1_COL IMXRT_PADCFG(0, 133, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_01_LPIT3_TRIGGER01 IMXRT_PADCFG(0, 133, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_01_SAI4_TX_BCLK IMXRT_PADCFG(0, 133, 0x4, 0, 265, 0x2) +#define IOMUXC_PAD_GPIO_B2_01_GPIO6_IO15 IMXRT_PADCFG(0, 133, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_01_FLEXSPI1_BUS2BIT_A_SS1_B IMXRT_PADCFG(0, 133, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_01_NETC_ETH4_COL IMXRT_PADCFG(0, 133, 0x8, 0, 199, 0x2) +#define IOMUXC_PAD_GPIO_B2_01_LPSPI6_SDO IMXRT_PADCFG(0, 133, 0x9, 0, 114, 0x3) +#define IOMUXC_PAD_GPIO_B2_01_NETC_ETH2_SLV_MDC IMXRT_PADCFG(0, 133, 0xa, 0, 193, 0x2) +#define IOMUXC_PAD_GPIO_B2_01_NETC_PINMUX_ETH2_RX_ER IMXRT_PADCFG(0, 133, 0xb, 0, 216, 0x1) +#define IOMUXC_PAD_GPIO_B2_01_ECAT_RX_ER_1 IMXRT_PADCFG(0, 133, 0xc, 0, 16, 0x2) + +#define IOMUXC_PAD_GPIO_B2_02_LPIT3_TRIGGER02 IMXRT_PADCFG(0, 134, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_02_NETC_EMDIO IMXRT_PADCFG(0, 134, 0x3, 0, 190, 0x7) +#define IOMUXC_PAD_GPIO_B2_02_SAI4_TX_SYNC IMXRT_PADCFG(0, 134, 0x4, 0, 266, 0x2) +#define IOMUXC_PAD_GPIO_B2_02_GPIO6_IO16 IMXRT_PADCFG(0, 134, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_02_FLEXSPI1_BUS2BIT_B_SCLK IMXRT_PADCFG(0, 134, 0x6, 0, 51, 0x2) +#define IOMUXC_PAD_GPIO_B2_02_CCM_ENET_REF_CLK_25M IMXRT_PADCFG(0, 134, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_02_EWM_EWM_OUT_B IMXRT_PADCFG(0, 134, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_02_NETC_PINMUX_ETH2_RXD02 IMXRT_PADCFG(0, 134, 0xb, 0, 219, 0x2) +#define IOMUXC_PAD_GPIO_B2_02_ECAT_RX_DATA2_1 IMXRT_PADCFG(0, 134, 0xc, 0, 10, 0x1) + +#define IOMUXC_PAD_GPIO_B2_03_LPIT3_TRIGGER03 IMXRT_PADCFG(0, 135, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_NETC_EMDC IMXRT_PADCFG(0, 135, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_SAI4_TX_DATA00 IMXRT_PADCFG(0, 135, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_GPIO6_IO17 IMXRT_PADCFG(0, 135, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_FLEXSPI1_BUS2BIT_A_DATA04 IMXRT_PADCFG(0, 135, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_XSPI_SLV_DATA04 IMXRT_PADCFG(0, 135, 0xa, 0, 350, 0x2) +#define IOMUXC_PAD_GPIO_B2_03_NETC_PINMUX_ETH2_RXD03 IMXRT_PADCFG(0, 135, 0xb, 0, 220, 0x2) +#define IOMUXC_PAD_GPIO_B2_03_ECAT_RX_DATA3_1 IMXRT_PADCFG(0, 135, 0xc, 0, 12, 0x1) + +#define IOMUXC_PAD_GPIO_B2_04_SINC1_MOD_CLK0 IMXRT_PADCFG(0, 136, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_SINC2_MOD_CLK0 IMXRT_PADCFG(0, 136, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_SINC3_MOD_CLK0 IMXRT_PADCFG(0, 136, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_SAI4_RX_SYNC IMXRT_PADCFG(0, 136, 0x4, 0, 264, 0x2) +#define IOMUXC_PAD_GPIO_B2_04_GPIO6_IO18 IMXRT_PADCFG(0, 136, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_FLEXSPI1_BUS2BIT_A_DATA05 IMXRT_PADCFG(0, 136, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_TPM3_EXTCLK IMXRT_PADCFG(0, 136, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_XSPI_SLV_DATA05 IMXRT_PADCFG(0, 136, 0xa, 0, 351, 0x2) +#define IOMUXC_PAD_GPIO_B2_04_NETC_PINMUX_ETH2_TXD02 IMXRT_PADCFG(0, 136, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_ECAT_TX_DATA2_1 IMXRT_PADCFG(0, 136, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_05_SINC1_MOD_CLK1 IMXRT_PADCFG(0, 137, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_SINC2_MOD_CLK1 IMXRT_PADCFG(0, 137, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_SINC3_MOD_CLK1 IMXRT_PADCFG(0, 137, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_SAI4_RX_BCLK IMXRT_PADCFG(0, 137, 0x4, 0, 261, 0x2) +#define IOMUXC_PAD_GPIO_B2_05_GPIO6_IO19 IMXRT_PADCFG(0, 137, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_MIC_CLK IMXRT_PADCFG(0, 137, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_FLEXSPI1_BUS2BIT_A_DATA06 IMXRT_PADCFG(0, 137, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_TPM3_CH00 IMXRT_PADCFG(0, 137, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_XSPI_SLV_DATA06 IMXRT_PADCFG(0, 137, 0xa, 0, 352, 0x2) +#define IOMUXC_PAD_GPIO_B2_05_NETC_PINMUX_ETH2_TXD03 IMXRT_PADCFG(0, 137, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_ECAT_TX_DATA3_1 IMXRT_PADCFG(0, 137, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_06_SINC1_MOD_CLK2 IMXRT_PADCFG(0, 138, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_SINC2_MOD_CLK2 IMXRT_PADCFG(0, 138, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_SINC3_MOD_CLK2 IMXRT_PADCFG(0, 138, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_LPUART6_DSR_B IMXRT_PADCFG(0, 138, 0x3, 0, 131, 0x1) +#define IOMUXC_PAD_GPIO_B2_06_SAI4_RX_DATA00 IMXRT_PADCFG(0, 138, 0x4, 0, 262, 0x2) +#define IOMUXC_PAD_GPIO_B2_06_GPIO6_IO20 IMXRT_PADCFG(0, 138, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_FLEXSPI1_BUS2BIT_A_DATA07 IMXRT_PADCFG(0, 138, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_TPM3_CH01 IMXRT_PADCFG(0, 138, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_LPUART11_TX IMXRT_PADCFG(0, 138, 0x9, 0, 118, 0x2) +#define IOMUXC_PAD_GPIO_B2_06_XSPI_SLV_DATA07 IMXRT_PADCFG(0, 138, 0xa, 0, 353, 0x2) +#define IOMUXC_PAD_GPIO_B2_06_NETC_PINMUX_ETH2_TXD00 IMXRT_PADCFG(0, 138, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_ECAT_TX_DATA0_1 IMXRT_PADCFG(0, 138, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_07_QTIMER5_TIMER0 IMXRT_PADCFG(0, 139, 0x0, 0, 250, 0x2) +#define IOMUXC_PAD_GPIO_B2_07_LPUART6_DCD_B IMXRT_PADCFG(0, 139, 0x3, 0, 130, 0x1) +#define IOMUXC_PAD_GPIO_B2_07_SAI4_TX_DATA01 IMXRT_PADCFG(0, 139, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_07_GPIO6_IO21 IMXRT_PADCFG(0, 139, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_07_SAI4_RX_DATA01 IMXRT_PADCFG(0, 139, 0x6, 0, 263, 0x1) +#define IOMUXC_PAD_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS IMXRT_PADCFG(0, 139, 0x7, 0, 41, 0x1) +#define IOMUXC_PAD_GPIO_B2_07_TPM3_CH02 IMXRT_PADCFG(0, 139, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_07_LPUART11_RX IMXRT_PADCFG(0, 139, 0x9, 0, 117, 0x2) +#define IOMUXC_PAD_GPIO_B2_07_XSPI_SLV_DQS IMXRT_PADCFG(0, 139, 0xa, 0, 345, 0x1) +#define IOMUXC_PAD_GPIO_B2_07_NETC_PINMUX_ETH2_TXD01 IMXRT_PADCFG(0, 139, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_07_ECAT_TX_DATA1_1 IMXRT_PADCFG(0, 139, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_08_QTIMER5_TIMER1 IMXRT_PADCFG(0, 140, 0x0, 0, 251, 0x2) +#define IOMUXC_PAD_GPIO_B2_08_SINC2_EMCLK02 IMXRT_PADCFG(0, 140, 0x1, 0, 280, 0x2) +#define IOMUXC_PAD_GPIO_B2_08_LPUART6_RI_B IMXRT_PADCFG(0, 140, 0x4, 0, 132, 0x1) +#define IOMUXC_PAD_GPIO_B2_08_GPIO6_IO22 IMXRT_PADCFG(0, 140, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_08_LPI2C6_SCL IMXRT_PADCFG(0, 140, 0x6, 0, 88, 0x1) +#define IOMUXC_PAD_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK IMXRT_PADCFG(0, 140, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_08_TPM3_CH03 IMXRT_PADCFG(0, 140, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_08_SPDIF_IN IMXRT_PADCFG(0, 140, 0x9, 0, 282, 0x2) +#define IOMUXC_PAD_GPIO_B2_08_XSPI_SLV_CLK IMXRT_PADCFG(0, 140, 0xa, 0, 354, 0x2) +#define IOMUXC_PAD_GPIO_B2_08_NETC_PINMUX_ETH2_TX_EN IMXRT_PADCFG(0, 140, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_08_ECAT_TX_EN_1 IMXRT_PADCFG(0, 140, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_09_QTIMER5_TIMER2 IMXRT_PADCFG(0, 141, 0x0, 0, 252, 0x1) +#define IOMUXC_PAD_GPIO_B2_09_SINC2_EMBIT02 IMXRT_PADCFG(0, 141, 0x1, 0, 277, 0x2) +#define IOMUXC_PAD_GPIO_B2_09_LPUART6_DTR_B IMXRT_PADCFG(0, 141, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_GPIO6_IO23 IMXRT_PADCFG(0, 141, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_LPI2C6_SDA IMXRT_PADCFG(0, 141, 0x6, 0, 89, 0x1) +#define IOMUXC_PAD_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B IMXRT_PADCFG(0, 141, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_TPM4_EXTCLK IMXRT_PADCFG(0, 141, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_SPDIF_OUT IMXRT_PADCFG(0, 141, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_XSPI_SLV_CS IMXRT_PADCFG(0, 141, 0xa, 0, 344, 0x2) +#define IOMUXC_PAD_GPIO_B2_09_NETC_PINMUX_ETH2_TX_CLK IMXRT_PADCFG(0, 141, 0xb, 0, 221, 0x2) +#define IOMUXC_PAD_GPIO_B2_09_ECAT_TX_CLK_1 IMXRT_PADCFG(0, 141, 0xc, 0, 18, 0x2) + +#define IOMUXC_PAD_GPIO_B2_10_MIC_BITSTREAM00 IMXRT_PADCFG(0, 142, 0x0, 0, 140, 0x3) +#define IOMUXC_PAD_GPIO_B2_10_SINC2_EMCLK03 IMXRT_PADCFG(0, 142, 0x1, 0, 281, 0x1) +#define IOMUXC_PAD_GPIO_B2_10_CAN3_TX IMXRT_PADCFG(0, 142, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_10_LPUART8_CTS_B IMXRT_PADCFG(0, 142, 0x3, 0, 135, 0x1) +#define IOMUXC_PAD_GPIO_B2_10_LPUART6_TX IMXRT_PADCFG(0, 142, 0x4, 0, 134, 0x2) +#define IOMUXC_PAD_GPIO_B2_10_GPIO6_IO24 IMXRT_PADCFG(0, 142, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_10_LPI2C4_SCL IMXRT_PADCFG(0, 142, 0x6, 0, 84, 0x1) +#define IOMUXC_PAD_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 IMXRT_PADCFG(0, 142, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_10_TPM4_CH00 IMXRT_PADCFG(0, 142, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_10_LPSPI4_SCK IMXRT_PADCFG(0, 142, 0x9, 0, 98, 0x2) +#define IOMUXC_PAD_GPIO_B2_10_XSPI_SLV_DATA00 IMXRT_PADCFG(0, 142, 0xa, 0, 346, 0x1) +#define IOMUXC_PAD_GPIO_B2_10_NETC_PINMUX_ETH2_RXD00 IMXRT_PADCFG(0, 142, 0xb, 0, 217, 0x2) +#define IOMUXC_PAD_GPIO_B2_10_ECAT_RX_DATA0_1 IMXRT_PADCFG(0, 142, 0xc, 0, 6, 0x2) + +#define IOMUXC_PAD_GPIO_B2_11_MIC_BITSTREAM01 IMXRT_PADCFG(0, 143, 0x0, 0, 141, 0x3) +#define IOMUXC_PAD_GPIO_B2_11_SINC2_EMBIT03 IMXRT_PADCFG(0, 143, 0x1, 0, 278, 0x1) +#define IOMUXC_PAD_GPIO_B2_11_CAN3_RX IMXRT_PADCFG(0, 143, 0x2, 0, 2, 0x1) +#define IOMUXC_PAD_GPIO_B2_11_LPUART8_RTS_B IMXRT_PADCFG(0, 143, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_11_LPUART6_RX IMXRT_PADCFG(0, 143, 0x4, 0, 133, 0x2) +#define IOMUXC_PAD_GPIO_B2_11_GPIO6_IO25 IMXRT_PADCFG(0, 143, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_11_LPI2C4_SDA IMXRT_PADCFG(0, 143, 0x6, 0, 85, 0x1) +#define IOMUXC_PAD_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 IMXRT_PADCFG(0, 143, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_11_TPM4_CH01 IMXRT_PADCFG(0, 143, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_11_LPSPI4_SDI IMXRT_PADCFG(0, 143, 0x9, 0, 99, 0x2) +#define IOMUXC_PAD_GPIO_B2_11_XSPI_SLV_DATA01 IMXRT_PADCFG(0, 143, 0xa, 0, 347, 0x1) +#define IOMUXC_PAD_GPIO_B2_11_NETC_PINMUX_ETH2_RXD01 IMXRT_PADCFG(0, 143, 0xb, 0, 218, 0x2) +#define IOMUXC_PAD_GPIO_B2_11_ECAT_RX_DATA1_1 IMXRT_PADCFG(0, 143, 0xc, 0, 8, 0x2) + +#define IOMUXC_PAD_GPIO_B2_12_MIC_BITSTREAM02 IMXRT_PADCFG(0, 144, 0x0, 0, 142, 0x3) +#define IOMUXC_PAD_GPIO_B2_12_SINC_FILTER_GLUE2_BREAK IMXRT_PADCFG(0, 144, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_LPUART8_TX IMXRT_PADCFG(0, 144, 0x2, 0, 137, 0x2) +#define IOMUXC_PAD_GPIO_B2_12_LPUART6_CTS_B IMXRT_PADCFG(0, 144, 0x4, 0, 129, 0x2) +#define IOMUXC_PAD_GPIO_B2_12_GPIO6_IO26 IMXRT_PADCFG(0, 144, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_CAN3_TX IMXRT_PADCFG(0, 144, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 IMXRT_PADCFG(0, 144, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_TPM4_CH02 IMXRT_PADCFG(0, 144, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_LPSPI4_SDO IMXRT_PADCFG(0, 144, 0x9, 0, 100, 0x2) +#define IOMUXC_PAD_GPIO_B2_12_XSPI_SLV_DATA02 IMXRT_PADCFG(0, 144, 0xa, 0, 348, 0x1) +#define IOMUXC_PAD_GPIO_B2_12_NETC_PINMUX_ETH2_RX_DV IMXRT_PADCFG(0, 144, 0xb, 0, 215, 0x2) +#define IOMUXC_PAD_GPIO_B2_12_ECAT_RX_DV_1 IMXRT_PADCFG(0, 144, 0xc, 0, 14, 0x2) + +#define IOMUXC_PAD_GPIO_B2_13_MIC_BITSTREAM03 IMXRT_PADCFG(0, 145, 0x0, 0, 143, 0x3) +#define IOMUXC_PAD_GPIO_B2_13_SINC2_EMCLK00 IMXRT_PADCFG(0, 145, 0x1, 0, 279, 0x1) +#define IOMUXC_PAD_GPIO_B2_13_LPUART8_RX IMXRT_PADCFG(0, 145, 0x2, 0, 136, 0x2) +#define IOMUXC_PAD_GPIO_B2_13_LPUART6_RTS_B IMXRT_PADCFG(0, 145, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_13_GPIO6_IO27 IMXRT_PADCFG(0, 145, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_13_CAN3_RX IMXRT_PADCFG(0, 145, 0x6, 0, 2, 0x2) +#define IOMUXC_PAD_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 IMXRT_PADCFG(0, 145, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_13_TPM4_CH03 IMXRT_PADCFG(0, 145, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_13_LPSPI4_PCS0 IMXRT_PADCFG(0, 145, 0x9, 0, 97, 0x2) +#define IOMUXC_PAD_GPIO_B2_13_XSPI_SLV_DATA03 IMXRT_PADCFG(0, 145, 0xa, 0, 349, 0x1) +#define IOMUXC_PAD_GPIO_B2_13_NETC_PINMUX_ETH2_RX_CLK IMXRT_PADCFG(0, 145, 0xb, 0, 214, 0x3) +#define IOMUXC_PAD_GPIO_B2_13_ECAT_RX_CLK_1 IMXRT_PADCFG(0, 145, 0xc, 0, 4, 0x1) + +#define IOMUXC_PAD_GPIO_AON_00_SRC_BOOT_MODE00 IMXRT_PADCFG(1, 0, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_00_CAN1_TX IMXRT_PADCFG(1, 0, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_00_LPTMR1_ALT1 IMXRT_PADCFG(1, 0, 0x4, 1, 17, 0x0) +#define IOMUXC_PAD_GPIO_AON_00_GPIO1_IO00 IMXRT_PADCFG(1, 0, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_00_LPUART2_TX IMXRT_PADCFG(1, 0, 0x6, 1, 28, 0x0) +#define IOMUXC_PAD_GPIO_AON_00_TPM1_EXTCLK IMXRT_PADCFG(1, 0, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_01_SRC_BOOT_MODE01 IMXRT_PADCFG(1, 1, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_01_CAN1_RX IMXRT_PADCFG(1, 1, 0x1, 0, 0, 0x1) +#define IOMUXC_PAD_GPIO_AON_01_LPTMR1_ALT2 IMXRT_PADCFG(1, 1, 0x4, 1, 18, 0x0) +#define IOMUXC_PAD_GPIO_AON_01_GPIO1_IO01 IMXRT_PADCFG(1, 1, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_01_LPUART2_RX IMXRT_PADCFG(1, 1, 0x6, 1, 27, 0x0) +#define IOMUXC_PAD_GPIO_AON_01_TPM1_CH00 IMXRT_PADCFG(1, 1, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_02_SRC_BOOT_MODE02 IMXRT_PADCFG(1, 2, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_CAN3_TX IMXRT_PADCFG(1, 2, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_LPSPI2_PCS3 IMXRT_PADCFG(1, 2, 0x2, 1, 13, 0x0) +#define IOMUXC_PAD_GPIO_AON_02_LPSPI2_SDO IMXRT_PADCFG(1, 2, 0x3, 1, 16, 0x0) +#define IOMUXC_PAD_GPIO_AON_02_LPTMR1_ALT3 IMXRT_PADCFG(1, 2, 0x4, 1, 19, 0x0) +#define IOMUXC_PAD_GPIO_AON_02_GPIO1_IO02 IMXRT_PADCFG(1, 2, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_LPUART2_RTS_B IMXRT_PADCFG(1, 2, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_TPM1_CH01 IMXRT_PADCFG(1, 2, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_ECAT_CLK_ECAT_CLK25 IMXRT_PADCFG(1, 2, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_03_CAN3_RX IMXRT_PADCFG(1, 3, 0x1, 0, 2, 0x3) +#define IOMUXC_PAD_GPIO_AON_03_LPSPI1_PCS1 IMXRT_PADCFG(1, 3, 0x2, 1, 7, 0x0) +#define IOMUXC_PAD_GPIO_AON_03_LPSPI2_SDI IMXRT_PADCFG(1, 3, 0x3, 1, 15, 0x0) +#define IOMUXC_PAD_GPIO_AON_03_LPSPI1_PCS3 IMXRT_PADCFG(1, 3, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_03_GPIO1_IO03 IMXRT_PADCFG(1, 3, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_03_LPUART2_CTS_B IMXRT_PADCFG(1, 3, 0x6, 1, 26, 0x0) +#define IOMUXC_PAD_GPIO_AON_03_TPM1_CH02 IMXRT_PADCFG(1, 3, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_03_ECAT_LED_STATE_RUN IMXRT_PADCFG(1, 3, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_04_LPSPI1_SCK IMXRT_PADCFG(1, 4, 0x0, 1, 8, 0x0) +#define IOMUXC_PAD_GPIO_AON_04_SAI1_TX_DATA00 IMXRT_PADCFG(1, 4, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_04_SAI1_RX_DATA01 IMXRT_PADCFG(1, 4, 0x3, 1, 35, 0x0) +#define IOMUXC_PAD_GPIO_AON_04_GPIO1_IO04 IMXRT_PADCFG(1, 4, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_04_LPUART7_CTS_B IMXRT_PADCFG(1, 4, 0x6, 1, 29, 0x0) +#define IOMUXC_PAD_GPIO_AON_04_TPM1_CH03 IMXRT_PADCFG(1, 4, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_04_ECAT_LED_RUN IMXRT_PADCFG(1, 4, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_05_LPSPI1_PCS0 IMXRT_PADCFG(1, 5, 0x0, 1, 6, 0x0) +#define IOMUXC_PAD_GPIO_AON_05_SAI1_TX_SYNC IMXRT_PADCFG(1, 5, 0x2, 1, 38, 0x0) +#define IOMUXC_PAD_GPIO_AON_05_GPIO1_IO05 IMXRT_PADCFG(1, 5, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_05_LPUART7_RTS_B IMXRT_PADCFG(1, 5, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_05_NMI_GLUE_NMI IMXRT_PADCFG(1, 5, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_05_ECAT_LED_ERR IMXRT_PADCFG(1, 5, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_06_LPSPI1_SDO IMXRT_PADCFG(1, 6, 0x0, 1, 10, 0x0) +#define IOMUXC_PAD_GPIO_AON_06_I3C1_PUR IMXRT_PADCFG(1, 6, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_06_SAI1_TX_BCLK IMXRT_PADCFG(1, 6, 0x2, 1, 37, 0x0) +#define IOMUXC_PAD_GPIO_AON_06_LPI2C1_SDA IMXRT_PADCFG(1, 6, 0x3, 1, 3, 0x0) +#define IOMUXC_PAD_GPIO_AON_06_GPIO1_IO06 IMXRT_PADCFG(1, 6, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_06_CAN1_TX IMXRT_PADCFG(1, 6, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_06_ECAT_SDA IMXRT_PADCFG(1, 6, 0xc, 0, 20, 0x1) + +#define IOMUXC_PAD_GPIO_AON_07_LPSPI1_SDI IMXRT_PADCFG(1, 7, 0x0, 1, 9, 0x0) +#define IOMUXC_PAD_GPIO_AON_07_SAI1_MCLK IMXRT_PADCFG(1, 7, 0x2, 1, 32, 0x0) +#define IOMUXC_PAD_GPIO_AON_07_LPI2C1_SCL IMXRT_PADCFG(1, 7, 0x3, 1, 2, 0x0) +#define IOMUXC_PAD_GPIO_AON_07_GPIO1_IO07 IMXRT_PADCFG(1, 7, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_07_CAN1_RX IMXRT_PADCFG(1, 7, 0x6, 0, 0, 0x2) +#define IOMUXC_PAD_GPIO_AON_07_ECAT_SCL IMXRT_PADCFG(1, 7, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_08_LPUART1_TX IMXRT_PADCFG(1, 8, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_08_S400_TX IMXRT_PADCFG(1, 8, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_08_SAI1_RX_DATA00 IMXRT_PADCFG(1, 8, 0x2, 1, 34, 0x0) +#define IOMUXC_PAD_GPIO_AON_08_SAI1_TX_DATA01 IMXRT_PADCFG(1, 8, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_08_GPIO1_IO08 IMXRT_PADCFG(1, 8, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_08_LPI2C1_SDA IMXRT_PADCFG(1, 8, 0x6, 1, 3, 0x1) +#define IOMUXC_PAD_GPIO_AON_08_LPSPI1_PCS1 IMXRT_PADCFG(1, 8, 0x8, 1, 7, 0x1) +#define IOMUXC_PAD_GPIO_AON_08_ECAT_LINK_ACT00 IMXRT_PADCFG(1, 8, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_09_LPUART1_RX IMXRT_PADCFG(1, 9, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_S400_RX IMXRT_PADCFG(1, 9, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_SAI1_RX_BCLK IMXRT_PADCFG(1, 9, 0x2, 1, 33, 0x0) +#define IOMUXC_PAD_GPIO_AON_09_LPIT1_TRIGGER00 IMXRT_PADCFG(1, 9, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_GPIO1_IO09 IMXRT_PADCFG(1, 9, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_LPI2C1_SCL IMXRT_PADCFG(1, 9, 0x6, 1, 2, 0x1) +#define IOMUXC_PAD_GPIO_AON_09_LPSPI1_PCS2 IMXRT_PADCFG(1, 9, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_ECAT_LINK_ACT01 IMXRT_PADCFG(1, 9, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_10_JTAG_MUX_TRSTB IMXRT_PADCFG(1, 10, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_10_LPSPI2_PCS0 IMXRT_PADCFG(1, 10, 0x1, 1, 11, 0x0) +#define IOMUXC_PAD_GPIO_AON_10_SAI1_RX_SYNC IMXRT_PADCFG(1, 10, 0x2, 1, 36, 0x0) +#define IOMUXC_PAD_GPIO_AON_10_LPIT1_TRIGGER01 IMXRT_PADCFG(1, 10, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_10_TPM2_EXTCLK IMXRT_PADCFG(1, 10, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_10_GPIO1_IO10 IMXRT_PADCFG(1, 10, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_10_LPI2C1_SCLS IMXRT_PADCFG(1, 10, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_11_JTAG_MUX_TDO IMXRT_PADCFG(1, 11, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_11_LPUART1_CTS_B IMXRT_PADCFG(1, 11, 0x2, 1, 20, 0x0) +#define IOMUXC_PAD_GPIO_AON_11_LPIT1_TRIGGER02 IMXRT_PADCFG(1, 11, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_11_TPM2_CH00 IMXRT_PADCFG(1, 11, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_11_GPIO1_IO11 IMXRT_PADCFG(1, 11, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_11_LPI2C1_SDAS IMXRT_PADCFG(1, 11, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_12_JTAG_MUX_TDI IMXRT_PADCFG(1, 12, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_LPUART1_RTS_B IMXRT_PADCFG(1, 12, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_LPIT1_TRIGGER03 IMXRT_PADCFG(1, 12, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_TPM2_CH01 IMXRT_PADCFG(1, 12, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_GPIO1_IO12 IMXRT_PADCFG(1, 12, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_LPI2C1_HREQ IMXRT_PADCFG(1, 12, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_LPSPI1_SCK IMXRT_PADCFG(1, 12, 0x8, 1, 8, 0x1) + +#define IOMUXC_PAD_GPIO_AON_13_JTAG_MUX_TCK IMXRT_PADCFG(1, 13, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_13_LPUART12_CTS_B IMXRT_PADCFG(1, 13, 0x2, 1, 23, 0x0) +#define IOMUXC_PAD_GPIO_AON_13_LPUART1_DSR_B IMXRT_PADCFG(1, 13, 0x3, 1, 22, 0x0) +#define IOMUXC_PAD_GPIO_AON_13_TPM2_CH02 IMXRT_PADCFG(1, 13, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_13_GPIO1_IO13 IMXRT_PADCFG(1, 13, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_13_LPTMR1_ALT1 IMXRT_PADCFG(1, 13, 0x6, 1, 17, 0x1) +#define IOMUXC_PAD_GPIO_AON_13_LPSPI1_PCS0 IMXRT_PADCFG(1, 13, 0x8, 1, 6, 0x1) + +#define IOMUXC_PAD_GPIO_AON_14_JTAG_MUX_TMS IMXRT_PADCFG(1, 14, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_14_LPUART12_RTS_B IMXRT_PADCFG(1, 14, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_14_LPUART1_DCD_B IMXRT_PADCFG(1, 14, 0x3, 1, 21, 0x0) +#define IOMUXC_PAD_GPIO_AON_14_TPM2_CH03 IMXRT_PADCFG(1, 14, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_14_GPIO1_IO14 IMXRT_PADCFG(1, 14, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_14_LPTMR1_ALT2 IMXRT_PADCFG(1, 14, 0x6, 1, 18, 0x1) +#define IOMUXC_PAD_GPIO_AON_14_LPSPI1_SDO IMXRT_PADCFG(1, 14, 0x8, 1, 10, 0x1) + +#define IOMUXC_PAD_GPIO_AON_15_FLEXSPI2_BUS2BIT_B_DATA03 IMXRT_PADCFG(1, 15, 0x0, 0, 61, 0x2) +#define IOMUXC_PAD_GPIO_AON_15_LPSPI2_PCS1 IMXRT_PADCFG(1, 15, 0x1, 1, 12, 0x0) +#define IOMUXC_PAD_GPIO_AON_15_LPUART12_TX IMXRT_PADCFG(1, 15, 0x2, 1, 25, 0x0) +#define IOMUXC_PAD_GPIO_AON_15_LPUART1_RI_B IMXRT_PADCFG(1, 15, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_15_LPI2C2_SDA IMXRT_PADCFG(1, 15, 0x4, 1, 5, 0x0) +#define IOMUXC_PAD_GPIO_AON_15_GPIO1_IO15 IMXRT_PADCFG(1, 15, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_15_LPTMR1_ALT3 IMXRT_PADCFG(1, 15, 0x6, 1, 19, 0x1) +#define IOMUXC_PAD_GPIO_AON_15_LPSPI1_SDI IMXRT_PADCFG(1, 15, 0x8, 1, 9, 0x1) +#define IOMUXC_PAD_GPIO_AON_15_I3C1_SDA IMXRT_PADCFG(1, 15, 0x9, 1, 1, 0x0) + +#define IOMUXC_PAD_GPIO_AON_16_FLEXSPI2_BUS2BIT_B_DATA02 IMXRT_PADCFG(1, 16, 0x0, 0, 60, 0x2) +#define IOMUXC_PAD_GPIO_AON_16_LPSPI2_PCS0 IMXRT_PADCFG(1, 16, 0x1, 1, 11, 0x1) +#define IOMUXC_PAD_GPIO_AON_16_LPUART12_RX IMXRT_PADCFG(1, 16, 0x2, 1, 24, 0x0) +#define IOMUXC_PAD_GPIO_AON_16_LPUART1_DTR_B IMXRT_PADCFG(1, 16, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_16_LPI2C2_SCL IMXRT_PADCFG(1, 16, 0x4, 1, 4, 0x0) +#define IOMUXC_PAD_GPIO_AON_16_GPIO1_IO16 IMXRT_PADCFG(1, 16, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_16_CAN1_TX IMXRT_PADCFG(1, 16, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_16_LPUART7_CTS_B IMXRT_PADCFG(1, 16, 0x8, 1, 29, 0x1) +#define IOMUXC_PAD_GPIO_AON_16_I3C1_SCL IMXRT_PADCFG(1, 16, 0x9, 1, 0, 0x0) + +#define IOMUXC_PAD_GPIO_AON_17_FLEXSPI2_BUS2BIT_B_DATA01 IMXRT_PADCFG(1, 17, 0x0, 0, 59, 0x2) +#define IOMUXC_PAD_GPIO_AON_17_LPSPI2_SDI IMXRT_PADCFG(1, 17, 0x1, 1, 15, 0x1) +#define IOMUXC_PAD_GPIO_AON_17_LPUART7_TX IMXRT_PADCFG(1, 17, 0x2, 1, 31, 0x0) +#define IOMUXC_PAD_GPIO_AON_17_LPI2C2_SDA IMXRT_PADCFG(1, 17, 0x3, 1, 5, 0x1) +#define IOMUXC_PAD_GPIO_AON_17_LPUART1_DSR_B IMXRT_PADCFG(1, 17, 0x4, 1, 22, 0x1) +#define IOMUXC_PAD_GPIO_AON_17_GPIO1_IO17 IMXRT_PADCFG(1, 17, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_17_CAN1_RX IMXRT_PADCFG(1, 17, 0x6, 0, 0, 0x3) + +#define IOMUXC_PAD_GPIO_AON_18_FLEXSPI2_BUS2BIT_B_DATA00 IMXRT_PADCFG(1, 18, 0x0, 0, 58, 0x2) +#define IOMUXC_PAD_GPIO_AON_18_LPSPI2_SDO IMXRT_PADCFG(1, 18, 0x1, 1, 16, 0x1) +#define IOMUXC_PAD_GPIO_AON_18_LPUART7_RX IMXRT_PADCFG(1, 18, 0x2, 1, 30, 0x0) +#define IOMUXC_PAD_GPIO_AON_18_LPI2C2_SCL IMXRT_PADCFG(1, 18, 0x3, 1, 4, 0x1) +#define IOMUXC_PAD_GPIO_AON_18_LPUART1_DCD_B IMXRT_PADCFG(1, 18, 0x4, 1, 21, 0x1) +#define IOMUXC_PAD_GPIO_AON_18_GPIO1_IO18 IMXRT_PADCFG(1, 18, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_18_CAN3_TX IMXRT_PADCFG(1, 18, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_19_FLEXSPI2_BUS2BIT_B_SCLK IMXRT_PADCFG(1, 19, 0x0, 0, 63, 0x1) +#define IOMUXC_PAD_GPIO_AON_19_LPSPI2_SCK IMXRT_PADCFG(1, 19, 0x1, 1, 14, 0x0) +#define IOMUXC_PAD_GPIO_AON_19_FLEXSPI2_BUS2BIT_A_SS1_B IMXRT_PADCFG(1, 19, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_19_LPUART1_CTS_B IMXRT_PADCFG(1, 19, 0x4, 1, 20, 0x1) +#define IOMUXC_PAD_GPIO_AON_19_GPIO1_IO19 IMXRT_PADCFG(1, 19, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_19_CAN3_RX IMXRT_PADCFG(1, 19, 0x6, 0, 2, 0x4) +#define IOMUXC_PAD_GPIO_AON_19_LPUART7_RTS_B IMXRT_PADCFG(1, 19, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_19_LPUART12_TX IMXRT_PADCFG(1, 19, 0x9, 1, 25, 0x1) +#define IOMUXC_PAD_GPIO_AON_19_ADC1_CONV_D00 IMXRT_PADCFG(1, 19, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_20_FLEXSPI2_BUS2BIT_B_DQS IMXRT_PADCFG(1, 20, 0x0, 0, 53, 0x2) +#define IOMUXC_PAD_GPIO_AON_20_FLEXSPI2_BUS2BIT_A_SS1_B IMXRT_PADCFG(1, 20, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_20_LPI2C1_SDA IMXRT_PADCFG(1, 20, 0x2, 1, 3, 0x2) +#define IOMUXC_PAD_GPIO_AON_20_I3C1_SDA IMXRT_PADCFG(1, 20, 0x3, 1, 1, 0x1) +#define IOMUXC_PAD_GPIO_AON_20_LPUART1_RTS_B IMXRT_PADCFG(1, 20, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_20_GPIO1_IO20 IMXRT_PADCFG(1, 20, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_20_LPUART12_RX IMXRT_PADCFG(1, 20, 0x9, 1, 24, 0x1) +#define IOMUXC_PAD_GPIO_AON_20_ADC1_CONV_D01 IMXRT_PADCFG(1, 20, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_21_FLEXSPI2_BUS2BIT_B_SS0_B IMXRT_PADCFG(1, 21, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_21_LPSPI2_PCS1 IMXRT_PADCFG(1, 21, 0x1, 1, 12, 0x1) +#define IOMUXC_PAD_GPIO_AON_21_LPI2C1_SCL IMXRT_PADCFG(1, 21, 0x2, 1, 2, 0x2) +#define IOMUXC_PAD_GPIO_AON_21_I3C1_SCL IMXRT_PADCFG(1, 21, 0x3, 1, 0, 0x1) +#define IOMUXC_PAD_GPIO_AON_21_SAI1_TX_DATA00 IMXRT_PADCFG(1, 21, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_21_GPIO1_IO21 IMXRT_PADCFG(1, 21, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_21_FLEXSPI2_BUS2BIT_A_DQS IMXRT_PADCFG(1, 21, 0x8, 0, 52, 0x1) +#define IOMUXC_PAD_GPIO_AON_21_SAI1_RX_DATA01 IMXRT_PADCFG(1, 21, 0x9, 1, 35, 0x1) +#define IOMUXC_PAD_GPIO_AON_21_ADC1_CONV_D02 IMXRT_PADCFG(1, 21, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_22_FLEXSPI2_BUS2BIT_A_SS0_B IMXRT_PADCFG(1, 22, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_22_LPI2C2_SDA IMXRT_PADCFG(1, 22, 0x1, 1, 5, 0x2) +#define IOMUXC_PAD_GPIO_AON_22_LPUART7_TX IMXRT_PADCFG(1, 22, 0x2, 1, 31, 0x1) +#define IOMUXC_PAD_GPIO_AON_22_LPUART12_CTS_B IMXRT_PADCFG(1, 22, 0x3, 1, 23, 0x1) +#define IOMUXC_PAD_GPIO_AON_22_SAI1_TX_SYNC IMXRT_PADCFG(1, 22, 0x4, 1, 38, 0x1) +#define IOMUXC_PAD_GPIO_AON_22_GPIO1_IO22 IMXRT_PADCFG(1, 22, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_22_LPSPI2_SCK IMXRT_PADCFG(1, 22, 0x6, 1, 14, 0x1) +#define IOMUXC_PAD_GPIO_AON_22_CCMSRCGPC_CCMOBS1 IMXRT_PADCFG(1, 22, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_22_ADC1_CONV_D03 IMXRT_PADCFG(1, 22, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_23_FLEXSPI2_BUS2BIT_A_SCLK IMXRT_PADCFG(1, 23, 0x0, 0, 62, 0x1) +#define IOMUXC_PAD_GPIO_AON_23_LPI2C2_SCL IMXRT_PADCFG(1, 23, 0x1, 1, 4, 0x2) +#define IOMUXC_PAD_GPIO_AON_23_LPUART7_RX IMXRT_PADCFG(1, 23, 0x2, 1, 30, 0x1) +#define IOMUXC_PAD_GPIO_AON_23_LPUART12_RTS_B IMXRT_PADCFG(1, 23, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_23_SAI1_TX_BCLK IMXRT_PADCFG(1, 23, 0x4, 1, 37, 0x1) +#define IOMUXC_PAD_GPIO_AON_23_GPIO1_IO23 IMXRT_PADCFG(1, 23, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_23_LPSPI2_SDO IMXRT_PADCFG(1, 23, 0x6, 1, 16, 0x2) +#define IOMUXC_PAD_GPIO_AON_23_CCMSRCGPC_CCMOBS2 IMXRT_PADCFG(1, 23, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_23_ADC1_CONV_D04 IMXRT_PADCFG(1, 23, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_24_FLEXSPI2_BUS2BIT_A_DATA00 IMXRT_PADCFG(1, 24, 0x0, 0, 54, 0x1) +#define IOMUXC_PAD_GPIO_AON_24_LPI2C1_SDA IMXRT_PADCFG(1, 24, 0x1, 1, 3, 0x3) +#define IOMUXC_PAD_GPIO_AON_24_LPUART2_RTS_B IMXRT_PADCFG(1, 24, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_24_LPUART7_CTS_B IMXRT_PADCFG(1, 24, 0x3, 1, 29, 0x2) +#define IOMUXC_PAD_GPIO_AON_24_SAI1_MCLK IMXRT_PADCFG(1, 24, 0x4, 1, 32, 0x1) +#define IOMUXC_PAD_GPIO_AON_24_GPIO1_IO24 IMXRT_PADCFG(1, 24, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_24_LPSPI2_SDI IMXRT_PADCFG(1, 24, 0x6, 1, 15, 0x2) +#define IOMUXC_PAD_GPIO_AON_24_ADC1_CONV_D05 IMXRT_PADCFG(1, 24, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_25_FLEXSPI2_BUS2BIT_A_DATA01 IMXRT_PADCFG(1, 25, 0x0, 0, 55, 0x1) +#define IOMUXC_PAD_GPIO_AON_25_LPI2C1_SCL IMXRT_PADCFG(1, 25, 0x1, 1, 2, 0x3) +#define IOMUXC_PAD_GPIO_AON_25_LPUART2_CTS_B IMXRT_PADCFG(1, 25, 0x2, 1, 26, 0x1) +#define IOMUXC_PAD_GPIO_AON_25_LPUART7_RTS_B IMXRT_PADCFG(1, 25, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_25_SAI1_RX_DATA00 IMXRT_PADCFG(1, 25, 0x4, 1, 34, 0x1) +#define IOMUXC_PAD_GPIO_AON_25_GPIO1_IO25 IMXRT_PADCFG(1, 25, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_25_LPSPI2_PCS0 IMXRT_PADCFG(1, 25, 0x6, 1, 11, 0x2) +#define IOMUXC_PAD_GPIO_AON_25_SAI1_TX_DATA01 IMXRT_PADCFG(1, 25, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_25_ADC1_CONV_D06 IMXRT_PADCFG(1, 25, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_26_FLEXSPI2_BUS2BIT_A_DATA02 IMXRT_PADCFG(1, 26, 0x0, 0, 56, 0x1) +#define IOMUXC_PAD_GPIO_AON_26_LPSPI2_PCS2 IMXRT_PADCFG(1, 26, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_26_LPUART2_TX IMXRT_PADCFG(1, 26, 0x2, 1, 28, 0x1) +#define IOMUXC_PAD_GPIO_AON_26_SAI1_RX_BCLK IMXRT_PADCFG(1, 26, 0x4, 1, 33, 0x1) +#define IOMUXC_PAD_GPIO_AON_26_GPIO1_IO26 IMXRT_PADCFG(1, 26, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_26_ADC1_CONV_D07 IMXRT_PADCFG(1, 26, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_27_FLEXSPI2_BUS2BIT_A_DATA03 IMXRT_PADCFG(1, 27, 0x0, 0, 57, 0x1) +#define IOMUXC_PAD_GPIO_AON_27_LPSPI2_PCS3 IMXRT_PADCFG(1, 27, 0x1, 1, 13, 0x1) +#define IOMUXC_PAD_GPIO_AON_27_LPUART2_RX IMXRT_PADCFG(1, 27, 0x2, 1, 27, 0x1) +#define IOMUXC_PAD_GPIO_AON_27_SAI1_RX_SYNC IMXRT_PADCFG(1, 27, 0x4, 1, 36, 0x1) +#define IOMUXC_PAD_GPIO_AON_27_GPIO1_IO27 IMXRT_PADCFG(1, 27, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_27_EWM_EWM_OUT_B IMXRT_PADCFG(1, 27, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_27_ADC1_CONV_RDY_CLK IMXRT_PADCFG(1, 27, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_28_DUMMY_FLEXSPI2_BUS2BIT_A_DQS IMXRT_PADCFG(1, 28, 0x0, 0, 52, 0x2) +#define IOMUXC_PAD_GPIO_AON_28_DUMMY_FLEXSPI2_BUS2BIT_B_DQS IMXRT_PADCFG(1, 28, 0x1, 0, 53, 0x3) +#define IOMUXC_PAD_GPIO_AON_28_DUMMY_GPIO1_IO28 IMXRT_PADCFG(1, 28, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_PINMUX_H */ \ No newline at end of file diff --git a/arch/arm/src/imxrt/imxrt_gpio.h b/arch/arm/src/imxrt/imxrt_gpio.h index 049e43d850e..5523cdbbc56 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.h +++ b/arch/arm/src/imxrt/imxrt_gpio.h @@ -33,6 +33,17 @@ #include #include "chip.h" + +#ifdef CONFIG_IMXRT_RGPIO + +/* The RGPIO IP block (used by RT118x) has its public interface in a + * separate header and driver source. + */ + +# include "imxrt_rgpio.h" + +#else + #include "hardware/imxrt_gpio.h" /**************************************************************************** @@ -380,4 +391,6 @@ int imxrt_dump_gpio(uint32_t pinset, const char *msg); #if defined(__cplusplus) } #endif + +#endif /* CONFIG_IMXRT_RGPIO */ #endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H */ diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.h b/arch/arm/src/imxrt/imxrt_iomuxc.h index 2d32f56f653..d6973891de7 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/imxrt_iomuxc.h @@ -30,10 +30,13 @@ #include /* IMXRT117X IOMUX Differs too much from IMXRT10XX - * hence we use a VER2 driver + * hence we use a VER2 driver. IMXRT118x uses another (generation 3) + * IOMUXC IP; that is IMXRT_IOMUX_VER3. */ -#ifdef CONFIG_IMXRT_IOMUX_VER2 +#ifdef CONFIG_IMXRT_IOMUX_VER3 +#include "imxrt_iomuxc_ver3.h" +#elif defined(CONFIG_IMXRT_IOMUX_VER2) #include "imxrt_iomuxc_ver2.h" #else #include "imxrt_iomuxc_ver1.h" diff --git a/arch/arm/src/imxrt/imxrt_iomuxc_ver3.c b/arch/arm/src/imxrt/imxrt_iomuxc_ver3.c new file mode 100644 index 00000000000..995328d2e1f --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_iomuxc_ver3.c @@ -0,0 +1,194 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_iomuxc_ver3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/imxrt_memorymap.h" +#include "imxrt_iomuxc_ver3.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Descriptors for the two IOMUXC instances on RT1180. These four numbers + * per bank are all we need to derive MUX_CTL, PAD_CTL and DAISY register + * addresses from a packed IMXRT_PADCFG value using pure arithmetic. + * + * ctl_first : offset of MUX_CTL[0] within the bank + * pad_delta : PAD_CTL[i] = MUX_CTL[i] + pad_delta (constant per bank) + * dsy_first : offset of DAISY[0] within the bank + */ + +static const struct imxrt_iomux_bank_s g_bank[IMXRT_PADCFG_NBANKS] = +{ + [IMXRT_PADCFG_BANK_MAIN] = + { + .base = IMXRT_IOMUXC_WKUP_BASE, /* 0x42a1_0000 */ + .ctl_first = 0x010u, + .pad_delta = 0x248u, + .dsy_first = 0x4a0u, + }, + [IMXRT_PADCFG_BANK_AON] = + { + .base = IMXRT_IOMUXC_AON_BASE, /* 0x443c_0000 */ + .ctl_first = 0x000u, + .pad_delta = 0x074u, + .dsy_first = 0x0e8u, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_iomux_ctlreg + * + * Description: + * Compute the SW_MUX_CTL register address for a packed padcfg value. + * + ****************************************************************************/ + +static inline uintptr_t imxrt_iomux_ctlreg(uint32_t padcfg) +{ + const struct imxrt_iomux_bank_s *b = &g_bank[IMXRT_PADCFG_PADBANK(padcfg)]; + + return (uintptr_t)b->base + b->ctl_first + + IMXRT_PADCFG_PADIDX(padcfg) * 4u; +} + +/**************************************************************************** + * Name: imxrt_iomux_padreg + * + * Description: + * Compute the SW_PAD_CTL register address for a packed padcfg value. + * + ****************************************************************************/ + +static inline uintptr_t imxrt_iomux_padreg(uint32_t padcfg) +{ + const struct imxrt_iomux_bank_s *b = &g_bank[IMXRT_PADCFG_PADBANK(padcfg)]; + + return imxrt_iomux_ctlreg(padcfg) + b->pad_delta; +} + +/**************************************************************************** + * Name: imxrt_iomux_dsyreg + * + * Description: + * Compute the DAISY (input) register address for a packed padcfg value, + * or 0 if the pad/alt has no input daisy. Note that the daisy bank + * may differ from the pad bank (a pin on one IOMUXC can route to a + * peripheral whose input mux lives on the other IOMUXC). + * + ****************************************************************************/ + +static inline uintptr_t imxrt_iomux_dsyreg(uint32_t padcfg) +{ + uint32_t dsy_idx = IMXRT_PADCFG_DSYIDX(padcfg); + const struct imxrt_iomux_bank_s *b; + + if (dsy_idx == IMXRT_PADCFG_NO_DSYIDX) + { + return 0; + } + + b = &g_bank[IMXRT_PADCFG_DSYBANK(padcfg)]; + return (uintptr_t)b->base + b->dsy_first + dsy_idx * 4u; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_iomux_configure + ****************************************************************************/ + +int imxrt_iomux_configure(imxrt_pinset_t pinset) +{ + uint32_t padcfg = IMXRT_PINSET_PADCFG(pinset); + uintptr_t ctlreg = imxrt_iomux_ctlreg(padcfg); + uintptr_t padreg = imxrt_iomux_padreg(padcfg); + uintptr_t dsyreg = imxrt_iomux_dsyreg(padcfg); + uint32_t mux = IMXRT_PADCFG_MUX(padcfg); + uint32_t mux_side = IMXRT_PINSET_MUXSIDE(pinset); + + /* Write MUX_CTL: ALT | mux side-band bits (currently only SION) */ + + putreg32(IOMUXC_MUX_MODE_ALT(mux) | mux_side, ctlreg); + + /* Write PAD_CTL */ + + putreg32(IMXRT_PINSET_PADCTL(pinset), padreg); + + /* Route the peripheral input mux (daisy) if this alt uses one */ + + if (dsyreg != 0) + { + putreg32(IMXRT_PADCFG_DSY(padcfg), dsyreg); + } + + return OK; +} + +/**************************************************************************** + * Name: imxrt_iomux_gpio + * + * Description: + * Force a pad to GPIO mode. On RT1180 dedicated GPIO_IOxx pads on the + * main IOMUXC take ALT0 for GPIO; all other pads (including AON pads) + * use ALT5. + * + ****************************************************************************/ + +int imxrt_iomux_gpio(imxrt_pinset_t pinset, bool sion) +{ + uint32_t padcfg = IMXRT_PINSET_PADCFG(pinset); + uintptr_t ctlreg = imxrt_iomux_ctlreg(padcfg); + uintptr_t padreg = imxrt_iomux_padreg(padcfg); + uint32_t reg_sion = sion ? IOMUXC_MUX_SION_ON : 0; + uint32_t alt; + + /* On the main IOMUXC, the dedicated GPIO_IO pads (there is no other + * function on ALT0) select GPIO via ALT0. Every other pad selects GPIO + * via ALT5. The IOMUXC_PAD_..._GPIOx_IOn macros generated from the SDK + * already carry the correct ALT (0 or 5) in the padcfg field, so we + * simply write the pre-encoded ALT and SION. + */ + + alt = IMXRT_PADCFG_MUX(padcfg); + + putreg32(IOMUXC_MUX_MODE_ALT(alt) | reg_sion, ctlreg); + putreg32(IMXRT_PINSET_PADCTL(pinset), padreg); + + return OK; +} diff --git a/arch/arm/src/imxrt/imxrt_iomuxc_ver3.h b/arch/arm/src/imxrt/imxrt_iomuxc_ver3.h new file mode 100644 index 00000000000..7df1c027acd --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_iomuxc_ver3.h @@ -0,0 +1,159 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_iomuxc_ver3.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_IOMUXC_VER3_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_IOMUXC_VER3_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "hardware/rt118x/imxrt118x_iomuxc.h" +#include "hardware/rt118x/imxrt118x_pinmux.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* imxrt_pinset_t is a 64-bit descriptor packing all four sub-fields + * needed to fully program a physical pad: + * + * bits 0..31 : padcfg IMXRT_PADCFG(...) constant (pad_bank, + * pad_idx, ALT, dsy_bank, dsy_idx, dsy_val). + * bits 32..39 : pad_ctl SW_PAD_CTL byte. + * bits 40..47 : mux_side SW_MUX_CTL side-band bits in register order + * (currently only SION at bit 4). + * bits 48..63 : gpio 16-bit gpio pinset (port | pin | mode | + * output value | int cfg | int both). + */ + +#define IMXRT_PINSET_PADCFG_SHIFT (0) +#define IMXRT_PINSET_PADCTL_SHIFT (32) +#define IMXRT_PINSET_MUXSIDE_SHIFT (40) +#define IMXRT_PINSET_GPIO_SHIFT (48) + +#define IMXRT_PINSET_PADCFG(_p) ((uint32_t)(_p)) +#define IMXRT_PINSET_PADCTL(_p) ((uint8_t)((_p) >> IMXRT_PINSET_PADCTL_SHIFT)) +#define IMXRT_PINSET_MUXSIDE(_p) ((uint8_t)((_p) >> IMXRT_PINSET_MUXSIDE_SHIFT)) +#define IMXRT_PINSET_GPIO(_p) ((uint16_t)((_p) >> IMXRT_PINSET_GPIO_SHIFT)) + +/* Compose a full 64-bit pinset from its four sub-fields. See + * IOMUX_PIN and IOMUX_GPIO below for the convenient wrappers. + */ + +#define IOMUX_CFG(_padcfg, _pad_ctl, _mux_side, _gpio) \ + (((uint64_t)(uint32_t)(_padcfg)) | \ + (((uint64_t)(uint8_t)(_pad_ctl)) << IMXRT_PINSET_PADCTL_SHIFT) | \ + (((uint64_t)(uint8_t)(_mux_side)) << IMXRT_PINSET_MUXSIDE_SHIFT) | \ + (((uint64_t)(uint16_t)(_gpio)) << IMXRT_PINSET_GPIO_SHIFT)) + +/* Peripheral pin: no GPIO fields. `mux_side' is OR'd into SW_MUX_CTL + * verbatim; the only defined bit is IOMUXC_MUX_SION_ON. + */ + +#define IOMUX_PIN(_padcfg, _pad_ctl, _mux_side) \ + IOMUX_CFG(_padcfg, _pad_ctl, _mux_side, 0xc000u) + +/* GPIO pin: caller supplies pad_ctl and a 16-bit gpio pinset built from + * GPIO_INPUT / GPIO_OUTPUT / GPIO_PORTn / GPIO_PINn / etc. SION is 0 + * because a GPIO output only needs to sample the pad when the ALT is + * routed elsewhere. + */ + +#define IOMUX_GPIO(_padcfg, _pad_ctl, _gpio) \ + IOMUX_CFG(_padcfg, _pad_ctl, 0, _gpio) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Packed 64-bit pad + GPIO descriptor. See IOMUX_CFG above for the + * bit layout. Peripheral drivers and board files should treat this + * type as opaque and use the IOMUX_PIN / IOMUX_GPIO macros to build + * values and the IMXRT_PINSET_* macros (or the driver entry points) to + * consume them. + */ + +typedef uint64_t imxrt_pinset_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: imxrt_iomux_configure + * + * Description: + * Program a pad's SW_MUX_CTL, SW_PAD_CTL and (if applicable) input + * DAISY select register from a packed pinset. + * + * Input Parameters: + * pinset - the pad configuration built with IOMUX_PIN() or IOMUX_GPIO() + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imxrt_iomux_configure(imxrt_pinset_t pinset); + +/**************************************************************************** + * Name: imxrt_iomux_gpio + * + * Description: + * Forcibly set a pad to GPIO mode. This overrides and disconnects any + * peripheral that was previously routed through the pad. The GPIO ALT + * is selected automatically based on the pad (ALT5 for most pads, ALT0 + * for dedicated GPIO_IO pads on the main IOMUXC). + * + * Input Parameters: + * pinset - the pad configuration. Only the padcfg and pad_ctl fields + * are used to identify the pad and program SW_PAD_CTL. + * sion - if true; sets SION, otherwise clears it. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imxrt_iomux_gpio(imxrt_pinset_t pinset, bool sion); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_IOMUXC_VER3_H */ diff --git a/arch/arm/src/imxrt/imxrt_rgpio.c b/arch/arm/src/imxrt/imxrt_rgpio.c new file mode 100644 index 00000000000..c07986fe2d2 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_rgpio.c @@ -0,0 +1,275 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_rgpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "imxrt_rgpio.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Look-up table that maps GPIO1..GPIOn indexes into RGPIO base addresses. + * GPIO1 lives in the AON domain; GPIO2..GPIO6 are in the WAKEUPMIX. + */ + +const uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] = +{ + IMXRT_GPIO1_BASE, + IMXRT_GPIO2_BASE, + IMXRT_GPIO3_BASE, + IMXRT_GPIO4_BASE, + IMXRT_GPIO5_BASE, + IMXRT_GPIO6_BASE, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpio_dirout + ****************************************************************************/ + +static inline void imxrt_gpio_dirout(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMXRT_GPIO_PDDR(port)); + + regval |= GPIO_PIN(pin); + putreg32(regval, IMXRT_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imxrt_gpio_dirin + ****************************************************************************/ + +static inline void imxrt_gpio_dirin(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMXRT_GPIO_PDDR(port)); + + regval &= ~GPIO_PIN(pin); + putreg32(regval, IMXRT_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imxrt_gpio_setoutput + ****************************************************************************/ + +static void imxrt_gpio_setoutput(uint32_t port, uint32_t pin, bool value) +{ + uintptr_t regaddr = value ? IMXRT_GPIO_PSOR(port) : IMXRT_GPIO_PCOR(port); + + putreg32(GPIO_PIN(pin), regaddr); +} + +/**************************************************************************** + * Name: imxrt_gpio_get_pinstatus + ****************************************************************************/ + +static inline bool imxrt_gpio_get_pinstatus(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMXRT_GPIO_PDOR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imxrt_gpio_getinput + ****************************************************************************/ + +static inline bool imxrt_gpio_getinput(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMXRT_GPIO_PDIR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imxrt_gpio_configinput + ****************************************************************************/ + +static int imxrt_gpio_configinput(uint16_t gpio) +{ + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS); + + imxrt_gpio_dirin(port, pin); + + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpio_configoutput + ****************************************************************************/ + +static inline int imxrt_gpio_configoutput(uint16_t gpio) +{ + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value = ((gpio & GPIO_OUTPUT_ONE) != 0); + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS); + + imxrt_gpio_setoutput(port, pin, value); + imxrt_gpio_dirout(port, pin); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_config_gpio + * + * Description: + * Configure a GPIO pin based on pin-encoded description of the pin. + * + ****************************************************************************/ + +int imxrt_config_gpio(gpio_pinset_t pinset) +{ + irqstate_t flags; + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + int ret; + + flags = enter_critical_section(); + + ret = imxrt_iomux_configure(pinset); + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + switch (gpio & GPIO_MODE_MASK) + { + case GPIO_INPUT: + { + ret = imxrt_gpio_configinput(gpio); + } + break; + + case GPIO_OUTPUT: + { + ret = imxrt_gpio_configinput(gpio); + if (ret >= 0) + { + ret = imxrt_gpio_configoutput(gpio); + } + } + break; + +#ifdef CONFIG_IMXRT_GPIO_IRQ + case GPIO_INTERRUPT: + { + ret = imxrt_gpio_configinput(gpio); + if (ret == OK) + { + ret = imxrt_gpioirq_configure(pinset); + } + } + break; +#endif + + default: + ret = OK; + break; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: imxrt_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void imxrt_gpio_write(gpio_pinset_t pinset, bool value) +{ + irqstate_t flags; + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS); + + flags = enter_critical_section(); + imxrt_gpio_setoutput(port, pin, value); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: imxrt_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool imxrt_gpio_read(gpio_pinset_t pinset) +{ + irqstate_t flags; + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS); + + flags = enter_critical_section(); + if ((gpio & GPIO_MODE_MASK) == GPIO_OUTPUT) + { + value = imxrt_gpio_get_pinstatus(port, pin); + } + else + { + value = imxrt_gpio_getinput(port, pin); + } + + leave_critical_section(flags); + return value; +} diff --git a/arch/arm/src/imxrt/imxrt_rgpio.h b/arch/arm/src/imxrt/imxrt_rgpio.h new file mode 100644 index 00000000000..3b52b26f487 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_rgpio.h @@ -0,0 +1,253 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_rgpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_RGPIO_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_RGPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "hardware/rt118x/imxrt118x_gpio.h" +#include "imxrt_iomuxc_ver3.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 16-bit gpio pinset bit layout (lives in bits 48..63 of imxrt_pinset_t): + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ENCODING MMVX BEEG GGGP PPPP + * GPIO INPUT 00.. BEEG GGGP PPPP + * INT INPUT 11.. BEEG GGGP PPPP + * GPIO OUTPUT 01V. ...G GGGP PPPP + */ + +/* Input/Output Selection: bits 14-15 */ + +#define GPIO_MODE_SHIFT (14) +#define GPIO_MODE_MASK (0x3u << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0u << GPIO_MODE_SHIFT) +# define GPIO_OUTPUT (1u << GPIO_MODE_SHIFT) +# define GPIO_INTERRUPT (2u << GPIO_MODE_SHIFT) +# define GPIO_NONE (3u << GPIO_MODE_SHIFT) + +/* Initial Output Value: bit 13 (only meaningful for GPIO_OUTPUT) */ + +#define GPIO_OUTPUT_SHIFT (13) +#define GPIO_OUTPUT_MASK (0x1u << GPIO_OUTPUT_SHIFT) +# define GPIO_OUTPUT_ZERO (0u << GPIO_OUTPUT_SHIFT) +# define GPIO_OUTPUT_ONE (1u << GPIO_OUTPUT_SHIFT) + +/* Interrupt "both edges" flag: bit 11 (only for GPIO_INTERRUPT) */ + +#define GPIO_INTBOTHCFG_SHIFT (11) +#define GPIO_INTBOTHCFG_MASK (1u << GPIO_INTBOTHCFG_SHIFT) +# define GPIO_INTBOTH_EDGES (1u << GPIO_INTBOTHCFG_SHIFT) + +/* Interrupt edge/level configuration: bits 9-10 (only for GPIO_INTERRUPT) */ + +#define GPIO_INTCFG_SHIFT (9) +#define GPIO_INTCFG_MASK (0x3u << GPIO_INTCFG_SHIFT) +# define GPIO_INT_LOWLEVEL (0u << GPIO_INTCFG_SHIFT) +# define GPIO_INT_HIGHLEVEL (1u << GPIO_INTCFG_SHIFT) +# define GPIO_INT_RISINGEDGE (2u << GPIO_INTCFG_SHIFT) +# define GPIO_INT_FALLINGEDGE (3u << GPIO_INTCFG_SHIFT) + +/* GPIO Port Number: bits 5-8 (GPIO1..GPIO6) */ + +#define GPIO_PORT_SHIFT (5) +#define GPIO_PORT_MASK (0xfu << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) +# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) +# define GPIO_PORT6 (GPIO6 << GPIO_PORT_SHIFT) + +/* GPIO Pin Number: bits 0-4 */ + +#define GPIO_PIN_SHIFT (0) +#define GPIO_PIN_MASK (0x1fu << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0u << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1u << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2u << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3u << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4u << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5u << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6u << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7u << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8u << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9u << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10u << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11u << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12u << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13u << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14u << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15u << GPIO_PIN_SHIFT) +# define GPIO_PIN16 (16u << GPIO_PIN_SHIFT) +# define GPIO_PIN17 (17u << GPIO_PIN_SHIFT) +# define GPIO_PIN18 (18u << GPIO_PIN_SHIFT) +# define GPIO_PIN19 (19u << GPIO_PIN_SHIFT) +# define GPIO_PIN20 (20u << GPIO_PIN_SHIFT) +# define GPIO_PIN21 (21u << GPIO_PIN_SHIFT) +# define GPIO_PIN22 (22u << GPIO_PIN_SHIFT) +# define GPIO_PIN23 (23u << GPIO_PIN_SHIFT) +# define GPIO_PIN24 (24u << GPIO_PIN_SHIFT) +# define GPIO_PIN25 (25u << GPIO_PIN_SHIFT) +# define GPIO_PIN26 (26u << GPIO_PIN_SHIFT) +# define GPIO_PIN27 (27u << GPIO_PIN_SHIFT) +# define GPIO_PIN28 (28u << GPIO_PIN_SHIFT) +# define GPIO_PIN29 (29u << GPIO_PIN_SHIFT) +# define GPIO_PIN30 (30u << GPIO_PIN_SHIFT) +# define GPIO_PIN31 (31u << GPIO_PIN_SHIFT) + +#define GPIO_SION_ENABLE (((imxrt_pinset_t)IOMUXC_MUX_SION_ON) << IMXRT_PINSET_MUXSIDE_SHIFT) + +/* Port access via global LUT */ + +#define IMXRT_GPIO_BASE(n) g_gpio_base[n] + +#define IMXRT_GPIO_VERID(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_VERID_OFFSET) +#define IMXRT_GPIO_PARAM(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PARAM_OFFSET) +#define IMXRT_GPIO_LOCK(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_LOCK_OFFSET) +#define IMXRT_GPIO_PCNS(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PCNS_OFFSET) +#define IMXRT_GPIO_ICNS(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICNS_OFFSET) +#define IMXRT_GPIO_PCNP(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PCNP_OFFSET) +#define IMXRT_GPIO_ICNP(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICNP_OFFSET) +#define IMXRT_GPIO_PDOR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PDOR_OFFSET) +#define IMXRT_GPIO_PSOR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PSOR_OFFSET) +#define IMXRT_GPIO_PCOR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PCOR_OFFSET) +#define IMXRT_GPIO_PTOR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PTOR_OFFSET) +#define IMXRT_GPIO_PDIR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PDIR_OFFSET) +#define IMXRT_GPIO_PDDR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PDDR_OFFSET) +#define IMXRT_GPIO_PIDR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PIDR_OFFSET) +#define IMXRT_GPIO_GICLR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GICLR_OFFSET) +#define IMXRT_GPIO_GICHR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GICHR_OFFSET) + +/* Interrupt status flag registers (two channels). Channel selected via + * ICRN.IRQS. + */ + +#define IMXRT_GPIO_ISFR0(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISFR0_OFFSET) +#define IMXRT_GPIO_ISFR1(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISFR1_OFFSET) + +/* Per-pin ICR and PDR at n*4 offsets */ + +#define IMXRT_GPIO_P0DR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_P0DR_OFFSET) +#define IMXRT_GPIO_PNDR(n, p) (IMXRT_GPIO_P0DR(n) + ((p) * 0x4)) +#define IMXRT_GPIO_ICR0(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR0_OFFSET) +#define IMXRT_GPIO_ICRN(n, p) (IMXRT_GPIO_ICR0(n) + ((p) * 0x4)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef imxrt_pinset_t gpio_pinset_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Look-up table that maps GPIO1..GPIOn indexes into RGPIO instance base + * addresses. + */ + +EXTERN const uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpioirq_initialize + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO_IRQ +void imxrt_gpioirq_initialize(void); +#else +# define imxrt_gpioirq_initialize() +#endif + +/**************************************************************************** + * Name: imxrt_config_gpio + * + * Description: + * Configure the pad routing and (for GPIO pins) the RGPIO direction, + * initial output value and interrupt configuration. + * + ****************************************************************************/ + +int imxrt_config_gpio(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imxrt_gpio_write + ****************************************************************************/ + +void imxrt_gpio_write(gpio_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: imxrt_gpio_read + ****************************************************************************/ + +bool imxrt_gpio_read(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imxrt_gpioirq_attach / imxrt_gpioirq_configure / + * imxrt_gpioirq_enable / imxrt_gpioirq_disable + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO_IRQ +int imxrt_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg); +int imxrt_gpioirq_configure(gpio_pinset_t pinset); +int imxrt_gpioirq_enable(gpio_pinset_t pinset); +int imxrt_gpioirq_disable(gpio_pinset_t pinset); +#else +# define imxrt_gpioirq_attach(pinset, isr, arg) 0 +# define imxrt_gpioirq_configure(pinset) 0 +# define imxrt_gpioirq_enable(pinset) 0 +# define imxrt_gpioirq_disable(pinset) 0 +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_RGPIO_H */ diff --git a/arch/arm/src/imxrt/imxrt_rgpioirq.c b/arch/arm/src/imxrt/imxrt_rgpioirq.c new file mode 100644 index 00000000000..3065f5c2eec --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_rgpioirq.c @@ -0,0 +1,268 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_rgpioirq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "imxrt_gpio.h" + +#ifdef CONFIG_IMXRT_GPIO_IRQ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imxrt_portisr_s +{ + struct + { + xcpt_t isr; + void *arg; + } + pins[IMXRT_GPIO_NPINS]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct imxrt_portisr_s g_isrtab[IMXRT_GPIO_NPORTS]; + +/* NVIC IRQ per RGPIO instance (channel 0). RGPIO1..3 also expose a + * second interrupt (channel 1) at IMXRT_IRQ_GPIOn_1; the driver uses + * channel 0 for all pins by leaving ICRN.IRQS at reset (0). + */ + +static const int g_gpio_irq[IMXRT_GPIO_NPORTS] = +{ + IMXRT_IRQ_GPIO1_0, + IMXRT_IRQ_GPIO2_0, + IMXRT_IRQ_GPIO3_0, + IMXRT_IRQ_GPIO4, + IMXRT_IRQ_GPIO5, + IMXRT_IRQ_GPIO6, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpio_interrupt + * + * Description: + * Common ISR shared by every RGPIO instance. Scans the port's ISFR0 + * flag word and dispatches per-pin user handlers. + * + ****************************************************************************/ + +static int imxrt_gpio_interrupt(int irq, void *context, void *arg) +{ + uint32_t port = (uint32_t)((uintptr_t)arg); + uint32_t status; + uint32_t pin; + uintptr_t regaddr; + + regaddr = IMXRT_GPIO_ISFR0(port); + status = getreg32(regaddr); + + for (pin = 0; pin < IMXRT_GPIO_NPINS && status != 0; pin++) + { + uint32_t mask = (1u << pin); + + if ((status & mask) != 0) + { + struct imxrt_portisr_s *isrtab; + + putreg32(mask, regaddr); + status &= ~mask; + + isrtab = &g_isrtab[port]; + if (isrtab->pins[pin].isr != NULL) + { + isrtab->pins[pin].isr(irq, context, isrtab->pins[pin].arg); + } + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpioirq_initialize + ****************************************************************************/ + +void imxrt_gpioirq_initialize(void) +{ + uint32_t port; + uint32_t pin; + + /* Reset every pin's ICR so no interrupt configuration survives across + * a warm reset from the M33. + */ + + for (port = 0; port < IMXRT_GPIO_NPORTS; port++) + { + for (pin = 0; pin < IMXRT_GPIO_NPINS; pin++) + { + putreg32(0, IMXRT_GPIO_ICRN(port, pin)); + } + } + + /* Attach the common ISR to every RGPIO NVIC line. */ + + for (port = 0; port < IMXRT_GPIO_NPORTS; port++) + { + up_disable_irq(g_gpio_irq[port]); + DEBUGVERIFY(irq_attach(g_gpio_irq[port], + imxrt_gpio_interrupt, + (void *)(uintptr_t)port)); + up_enable_irq(g_gpio_irq[port]); + } +} + +/**************************************************************************** + * Name: imxrt_gpioirq_attach + ****************************************************************************/ + +int imxrt_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg) +{ + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + irqstate_t flags; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS && pin < IMXRT_GPIO_NPINS); + + flags = enter_critical_section(); + + g_isrtab[port].pins[pin].isr = isr; + g_isrtab[port].pins[pin].arg = arg; + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpioirq_configure + * + * Description: + * Reset ICRN for the pin. Interrupt is enabled by imxrt_gpioirq_enable(). + * + ****************************************************************************/ + +int imxrt_gpioirq_configure(gpio_pinset_t pinset) +{ + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS && pin < IMXRT_GPIO_NPINS); + + putreg32(0, IMXRT_GPIO_ICRN(port, pin)); + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpioirq_enable + ****************************************************************************/ + +int imxrt_gpioirq_enable(gpio_pinset_t pinset) +{ + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t both = (gpio & GPIO_INTBOTHCFG_MASK) >> GPIO_INTBOTHCFG_SHIFT; + uint32_t icr = (gpio & GPIO_INTCFG_MASK); + uint32_t regval; + uintptr_t regaddr; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS && pin < IMXRT_GPIO_NPINS); + + regaddr = IMXRT_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMXRT_GPIO_ICRN_MASK; + + if (both) + { + regval |= IMXRT_GPIO_ICRN_BOTH; + } + else if (icr == GPIO_INT_LOWLEVEL) + { + regval |= IMXRT_GPIO_ICRN_ZERO; + } + else if (icr == GPIO_INT_HIGHLEVEL) + { + regval |= IMXRT_GPIO_ICRN_ONE; + } + else if (icr == GPIO_INT_RISINGEDGE) + { + regval |= IMXRT_GPIO_ICRN_RISING; + } + else + { + regval |= IMXRT_GPIO_ICRN_FALLING; + } + + putreg32(regval, regaddr); + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpioirq_disable + ****************************************************************************/ + +int imxrt_gpioirq_disable(gpio_pinset_t pinset) +{ + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t regval; + uintptr_t regaddr; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS && pin < IMXRT_GPIO_NPINS); + + regaddr = IMXRT_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMXRT_GPIO_ICRN_MASK; + + putreg32(regval, regaddr); + return OK; +} + +#endif /* CONFIG_IMXRT_GPIO_IRQ */