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!arm/stm32wl5: standardize public API/type prefix to stm32_

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BREAKING CHANGE: Public STM32WL5 interfaces were renamed from stm32wl5_*
forms to canonical stm32_* forms across arch and board headers/sources.

Public type names in STM32WL5 timer/GPIO/EXTI and related API-facing
declarations were normalized to stm32_* equivalents.

The STM32WL5 root family header was renamed from stm32wl5.h to stm32.h;
all STM32WL5 arch/board includes were updated accordingly.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-05-29 16:28:59 +02:00 • committed by Xiang Xiao
parent 6e7db8dada
commit 80312dbb2d
46 changed files with 854 additions and 907 deletions
Download patch file Download diff file Expand all files Collapse all files

6
arch/arm/src/stm32wl5/stm32wl5.h → arch/arm/src/stm32wl5/stm32.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32wl5/stm32wl5.h
* arch/arm/src/stm32wl5/stm32.h
*
* SPDX-License-Identifier: Apache-2.0
*
@ -55,13 +55,13 @@
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_spidev_initialize
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins.
*
****************************************************************************/
void stm32wl5_spidev_initialize(void);
void stm32_spidev_initialize(void);
#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_H */

4
arch/arm/src/stm32wl5/stm32wl5_allocateheap.c
View file

@ -192,7 +192,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size)
/* Allow user-mode access to the user heap memory */
stm32wl5_mpu_uheap((uintptr_t)ubase, usize);
stm32_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
@ -270,7 +270,7 @@ void arm_addregion(void)
/* Allow user-mode access to the SRAM2 heap */
stm32wl5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START);
stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START);
#endif
/* Colorize the heap for debug */

16
arch/arm/src/stm32wl5/stm32wl5_exti.h
View file

@ -54,7 +54,7 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_gpiosetevent
* Name: stm32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
@ -73,11 +73,11 @@ extern "C"
*
****************************************************************************/
int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
/****************************************************************************
* Name: stm32wl5_exti_alarm
* Name: stm32_exti_alarm
*
* Description:
* Sets/clears EXTI alarm interrupt.
@ -95,12 +95,12 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int stm32wl5_exti_alarm(bool risingedge, bool fallingedge, bool event,
int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg);
#endif
/****************************************************************************
* Name: stm32wl5_exti_wakeup
* Name: stm32_exti_wakeup
*
* Description:
* Sets/clears EXTI wakeup interrupt.
@ -118,12 +118,12 @@ int stm32wl5_exti_alarm(bool risingedge, bool fallingedge, bool event,
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
int stm32wl5_exti_wakeup(bool risingedge, bool fallingedge, bool event,
int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg);
#endif
/****************************************************************************
* Name: stm32wl5_exti_comp
* Name: stm32_exti_comp
*
* Description:
* Sets/clears comparator based events and interrupt triggers.
@ -142,7 +142,7 @@ int stm32wl5_exti_wakeup(bool risingedge, bool fallingedge, bool event,
****************************************************************************/
#ifdef CONFIG_STM32WL5_COMP
int stm32wl5_exti_comp(int cmp, bool risingedge, bool fallingedge,
int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
#endif

40
arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c
View file

@ -66,7 +66,7 @@ static struct gpio_callback_s g_gpio_handlers[16];
* Interrupt Service Routines - Dispatchers
****************************************************************************/
static int stm32wl5_exti0_isr(int irq, void *context, void *arg)
static int stm32_exti0_isr(int irq, void *context, void *arg)
{
int ret = OK;
@ -87,7 +87,7 @@ static int stm32wl5_exti0_isr(int irq, void *context, void *arg)
return ret;
}
static int stm32wl5_exti1_isr(int irq, void *context, void *arg)
static int stm32_exti1_isr(int irq, void *context, void *arg)
{
int ret = OK;
@ -108,7 +108,7 @@ static int stm32wl5_exti1_isr(int irq, void *context, void *arg)
return ret;
}
static int stm32wl5_exti2_isr(int irq, void *context, void *arg)
static int stm32_exti2_isr(int irq, void *context, void *arg)
{
int ret = OK;
@ -129,7 +129,7 @@ static int stm32wl5_exti2_isr(int irq, void *context, void *arg)
return ret;
}
static int stm32wl5_exti3_isr(int irq, void *context, void *arg)
static int stm32_exti3_isr(int irq, void *context, void *arg)
{
int ret = OK;
@ -150,7 +150,7 @@ static int stm32wl5_exti3_isr(int irq, void *context, void *arg)
return ret;
}
static int stm32wl5_exti4_isr(int irq, void *context, void *arg)
static int stm32_exti4_isr(int irq, void *context, void *arg)
{
int ret = OK;
@ -171,7 +171,7 @@ static int stm32wl5_exti4_isr(int irq, void *context, void *arg)
return ret;
}
static int stm32wl5_exti_multiisr(int irq, void *context, void *arg,
static int stm32_exti_multiisr(int irq, void *context, void *arg,
int first, int last)
{
uint32_t pr;
@ -215,14 +215,14 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg,
return ret;
}
static int stm32wl5_exti95_isr(int irq, void *context, void *arg)
static int stm32_exti95_isr(int irq, void *context, void *arg)
{
return stm32wl5_exti_multiisr(irq, context, arg, 5, 9);
return stm32_exti_multiisr(irq, context, arg, 5, 9);
}
static int stm32wl5_exti1510_isr(int irq, void *context, void *arg)
static int stm32_exti1510_isr(int irq, void *context, void *arg)
{
return stm32wl5_exti_multiisr(irq, context, arg, 10, 15);
return stm32_exti_multiisr(irq, context, arg, 10, 15);
}
/****************************************************************************
@ -230,7 +230,7 @@ static int stm32wl5_exti1510_isr(int irq, void *context, void *arg)
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_gpiosetevent
* Name: stm32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
@ -252,7 +252,7 @@ static int stm32wl5_exti1510_isr(int irq, void *context, void *arg)
*
****************************************************************************/
int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg)
{
struct gpio_callback_s *shared_cbs;
@ -273,37 +273,37 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
switch (pin)
{
case 0:
handler = stm32wl5_exti0_isr;
handler = stm32_exti0_isr;
break;
case 1:
handler = stm32wl5_exti1_isr;
handler = stm32_exti1_isr;
break;
case 2:
handler = stm32wl5_exti2_isr;
handler = stm32_exti2_isr;
break;
case 3:
handler = stm32wl5_exti3_isr;
handler = stm32_exti3_isr;
break;
default:
handler = stm32wl5_exti4_isr;
handler = stm32_exti4_isr;
break;
}
}
else if (pin < 10)
{
irq = STM32_IRQ_EXTI95;
handler = stm32wl5_exti95_isr;
handler = stm32_exti95_isr;
shared_cbs = &g_gpio_handlers[5];
nshared = 5;
}
else
{
irq = STM32_IRQ_EXTI1510;
handler = stm32wl5_exti1510_isr;
handler = stm32_exti1510_isr;
shared_cbs = &g_gpio_handlers[10];
nshared = 6;
}
@ -349,7 +349,7 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
pinset |= GPIO_EXTI;
}
stm32wl5_configgpio(pinset);
stm32_configgpio(pinset);
/* Configure rising/falling edges */

16
arch/arm/src/stm32wl5/stm32wl5_flash.c
View file

@ -95,7 +95,7 @@ static void flash_unlock(void)
{
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
stm32wl5_waste();
stm32_waste();
}
if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK)
@ -145,7 +145,7 @@ static inline void flash_erase(size_t page)
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
stm32wl5_waste();
stm32_waste();
}
modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0);
@ -155,7 +155,7 @@ static inline void flash_erase(size_t page)
* Public Functions
****************************************************************************/
int stm32wl5_flash_unlock(void)
int stm32_flash_unlock(void)
{
int ret;
@ -171,7 +171,7 @@ int stm32wl5_flash_unlock(void)
return ret;
}
int stm32wl5_flash_lock(void)
int stm32_flash_lock(void)
{
int ret;
@ -188,7 +188,7 @@ int stm32wl5_flash_lock(void)
}
/****************************************************************************
* Name: stm32wl5_flash_user_optbytes
* Name: stm32_flash_user_optbytes
*
* Description:
* Modify the contents of the user option bytes (USR OPT) on the flash.
@ -204,7 +204,7 @@ int stm32wl5_flash_lock(void)
*
****************************************************************************/
uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
{
uint32_t regval;
int ret;
@ -242,7 +242,7 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
stm32wl5_waste();
stm32_waste();
}
flash_optbytes_lock();
@ -457,7 +457,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
stm32wl5_waste();
stm32_waste();
}
/* Verify */

8
arch/arm/src/stm32wl5/stm32wl5_flash.h
View file

@ -36,11 +36,11 @@
* Public Functions Prototypes
****************************************************************************/
int stm32wl5_flash_lock(void);
int stm32wl5_flash_unlock(void);
int stm32_flash_lock(void);
int stm32_flash_unlock(void);
/****************************************************************************
* Name: stm32wl5_flash_user_optbytes
* Name: stm32_flash_user_optbytes
*
* Description:
* Modify the contents of the user option bytes (USR OPT) on the flash.
@ -56,6 +56,6 @@ int stm32wl5_flash_unlock(void);
*
****************************************************************************/
uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits);
uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits);
#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_FLASH_H */

28
arch/arm/src/stm32wl5/stm32wl5_gpio.c
View file

@ -80,13 +80,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] =
****************************************************************************/
/****************************************************************************
* Function: stm32wl5_gpioinit
* Function: stm32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32wl5_start().
* Typically called from stm32_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
@ -94,17 +94,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] =
*
****************************************************************************/
void stm32wl5_gpioinit(void)
void stm32_gpioinit(void)
{
}
/****************************************************************************
* Name: stm32wl5_configgpio
* Name: stm32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32wl5_unconfiggpio() with
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
@ -115,7 +115,7 @@ void stm32wl5_gpioinit(void)
* To-Do: Auto Power Enable
****************************************************************************/
int stm32wl5_configgpio(uint32_t cfgset)
int stm32_configgpio(uint32_t cfgset)
{
uintptr_t base;
uint32_t regval;
@ -158,7 +158,7 @@ int stm32wl5_configgpio(uint32_t cfgset)
/* Set the initial output value */
stm32wl5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
pinmode = GPIO_MODER_OUTPUT;
break;
@ -317,7 +317,7 @@ int stm32wl5_configgpio(uint32_t cfgset)
}
/****************************************************************************
* Name: stm32wl5_unconfiggpio
* Name: stm32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
@ -337,7 +337,7 @@ int stm32wl5_configgpio(uint32_t cfgset)
* To-Do: Auto Power Disable
****************************************************************************/
int stm32wl5_unconfiggpio(uint32_t cfgset)
int stm32_unconfiggpio(uint32_t cfgset)
{
/* Reuse port and pin number and set it to default HiZ INPUT */
@ -346,18 +346,18 @@ int stm32wl5_unconfiggpio(uint32_t cfgset)
/* To-Do: Mark its unuse for automatic power saving options */
return stm32wl5_configgpio(cfgset);
return stm32_configgpio(cfgset);
}
/****************************************************************************
* Name: stm32wl5_gpiowrite
* Name: stm32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void stm32wl5_gpiowrite(uint32_t pinset, bool value)
void stm32_gpiowrite(uint32_t pinset, bool value)
{
uint32_t base;
uint32_t bit;
@ -391,14 +391,14 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value)
}
/****************************************************************************
* Name: stm32wl5_gpioread
* Name: stm32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool stm32wl5_gpioread(uint32_t pinset)
bool stm32_gpioread(uint32_t pinset)
{
uint32_t base;
unsigned int port;

36
arch/arm/src/stm32wl5/stm32wl5_gpio.h
View file

@ -49,7 +49,7 @@
* Pre-Processor Declarations
****************************************************************************/
/* Bit-encoded input to stm32wl5_configgpio() */
/* Bit-encoded input to stm32_configgpio() */
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually
* configured by software in several modes:
@ -244,12 +244,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS];
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_configgpio
* Name: stm32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32wl5_unconfiggpio() with
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
@ -258,10 +258,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS];
*
****************************************************************************/
int stm32wl5_configgpio(uint32_t cfgset);
int stm32_configgpio(uint32_t cfgset);
/****************************************************************************
* Name: stm32wl5_unconfiggpio
* Name: stm32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
@ -280,30 +280,30 @@ int stm32wl5_configgpio(uint32_t cfgset);
*
****************************************************************************/
int stm32wl5_unconfiggpio(uint32_t cfgset);
int stm32_unconfiggpio(uint32_t cfgset);
/****************************************************************************
* Name: stm32wl5_gpiowrite
* Name: stm32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void stm32wl5_gpiowrite(uint32_t pinset, bool value);
void stm32_gpiowrite(uint32_t pinset, bool value);
/****************************************************************************
* Name: stm32wl5_gpioread
* Name: stm32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool stm32wl5_gpioread(uint32_t pinset);
bool stm32_gpioread(uint32_t pinset);
/****************************************************************************
* Name: stm32wl5_gpiosetevent
* Name: stm32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
@ -322,11 +322,11 @@ bool stm32wl5_gpioread(uint32_t pinset);
*
****************************************************************************/
int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
/****************************************************************************
* Function: stm32wl5_dumpgpio
* Function: stm32_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
@ -334,23 +334,23 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
int stm32wl5_dumpgpio(uint32_t pinset, const char *msg);
int stm32_dumpgpio(uint32_t pinset, const char *msg);
#else
# define stm32wl5_dumpgpio(p,m)
# define stm32_dumpgpio(p,m)
#endif
/****************************************************************************
* Function: stm32wl5_gpioinit
* Function: stm32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32wl5_start().
* Typically called from stm32_start().
*
****************************************************************************/
void stm32wl5_gpioinit(void);
void stm32_gpioinit(void);
#undef EXTERN
#if defined(__cplusplus)

110
arch/arm/src/stm32wl5/stm32wl5_ipcc.c
View file

@ -35,7 +35,7 @@
#include <arch/stm32wl5/stm32wl5xxx_cpu1_irq.h>
#include "hardware/stm32wl5_ipcc.h"
#include "stm32wl5.h"
#include "stm32.h"
#include "stm32wl5_ipcc.h"
/****************************************************************************
@ -44,7 +44,7 @@
/* This structure describes tx or rx of single channel in memory */
struct stm32wl5_ipcc_chan_mem_s
struct stm32_ipcc_chan_mem_s
{
unsigned len; /* Number of valid bytes in data[] */
char data[]; /* Data in IPCC memory */
@ -52,7 +52,7 @@ struct stm32wl5_ipcc_chan_mem_s
/* Internal stm32wl5 ipcc structure describing channel state. */
struct stm32wl5_ipcc_s
struct stm32_ipcc_s
{
/* Pointer to API connecting upper and lower half of the driver */
@ -65,14 +65,14 @@ struct stm32wl5_ipcc_s
char *rxmem;
/* Maximum length of data that rxmem can hold. It is size of the
* reserved space for rxmem minus sizeof(stm32wl5_ipcc_chan_mem_s.len)
* reserved space for rxmem minus sizeof(stm32_ipcc_chan_mem_s.len)
*/
unsigned rxlen;
/* Number of bytes copied from IPCC memory to buffer. Can be less than
* stm32wl5_ipcc_chan_mem_s.len after copy operation when buffer is full.
* Value can persist between multiple ISR and stm32wl5_ipcc_buffer_data()
* stm32_ipcc_chan_mem_s.len after copy operation when buffer is full.
* Value can persist between multiple ISR and stm32_ipcc_buffer_data()
* calls, until all data from IPCC memory is successfully buffered.
*
* When unbuffered version is used, this holds number of bytes already
@ -89,7 +89,7 @@ struct stm32wl5_ipcc_s
char *txmem;
/* Maximum length of data that txmem can hold. It is size of the
* reserved space for txmem minus sizeof(stm32wl5_ipcc_chan_mem_s.len)
* reserved space for txmem minus sizeof(stm32_ipcc_chan_mem_s.len)
*/
unsigned txlen;
@ -99,24 +99,24 @@ struct stm32wl5_ipcc_s
* Private Function Prototypes
****************************************************************************/
static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc,
static ssize_t stm32_ipcc_read(struct ipcc_lower_s *ipcc,
char *buffer, size_t buflen);
static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc,
static ssize_t stm32_ipcc_write(struct ipcc_lower_s *ipcc,
const char *buffer, size_t buflen);
#ifdef CONFIG_IPCC_BUFFERED
static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
static ssize_t stm32_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
struct circbuf_s *rxbuf);
static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan,
static ssize_t stm32_ipcc_copy_to_buffer(int chan,
struct circbuf_s *rxbuf);
#endif
static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg);
static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg);
static int stm32_ipcc_rx_isr(int irq, void *context, void *arg);
static int stm32_ipcc_tx_isr(int irq, void *context, void *arg);
/****************************************************************************
* Private Data
****************************************************************************/
struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] =
struct stm32_ipcc_s g_ipccpriv[IPCC_NCHAN] =
{
/* Channel 1 is always enabled when IPCC is enabled */
@ -183,7 +183,7 @@ struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] =
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_ipcc_tx_isr
* Name: stm32_ipcc_tx_isr
*
* Description:
* IPCC TX interrupt service routine. This interrupt is called when
@ -209,16 +209,16 @@ struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] =
*
****************************************************************************/
static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg)
static int stm32_ipcc_tx_isr(int irq, void *context, void *arg)
{
int chan;
uint32_t mr;
uint32_t sr;
uint32_t status;
struct stm32wl5_ipcc_s *priv;
struct stm32_ipcc_s *priv;
#ifdef CONFIG_IPCC_BUFFERED
size_t nwritten;
struct stm32wl5_ipcc_chan_mem_s *txmem;
struct stm32_ipcc_chan_mem_s *txmem;
#endif
UNUSED(context);
@ -251,7 +251,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg)
priv = &g_ipccpriv[chan];
#ifdef CONFIG_IPCC_BUFFERED
txmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->txmem;
txmem = (struct stm32_ipcc_chan_mem_s *)priv->txmem;
/* Copy as much as we can into IPCC memory, circbuf won't copy
* more than there is in the buffer.
@ -297,7 +297,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg)
}
/****************************************************************************
* Name: stm32wl5_ipcc_write
* Name: stm32_ipcc_write
*
* Description:
* Function writes buffer to IPCC memory that will be later read by
@ -316,12 +316,12 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg)
*
****************************************************************************/
static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc,
static ssize_t stm32_ipcc_write(struct ipcc_lower_s *ipcc,
const char *buffer, size_t buflen)
{
size_t to_copy;
struct stm32wl5_ipcc_s *priv;
struct stm32wl5_ipcc_chan_mem_s *txmem;
struct stm32_ipcc_s *priv;
struct stm32_ipcc_chan_mem_s *txmem;
uint32_t sr;
sr = getreg32(STM32_IPCC_C1TOC2SR);
@ -339,7 +339,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc,
}
priv = &g_ipccpriv[ipcc->chan];
txmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->txmem;
txmem = (struct stm32_ipcc_chan_mem_s *)priv->txmem;
/* Disable TX interrupt since we will modify shared data */
@ -366,7 +366,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc,
}
/****************************************************************************
* Name: stm32wl5_ipcc_rx_isr
* Name: stm32_ipcc_rx_isr
*
* Description:
* Interrupt service routine - this function is called when another CPU
@ -389,13 +389,13 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc,
*
****************************************************************************/
static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg)
static int stm32_ipcc_rx_isr(int irq, void *context, void *arg)
{
int chan;
uint32_t mr;
uint32_t sr;
uint32_t status;
struct stm32wl5_ipcc_s *priv;
struct stm32_ipcc_s *priv;
#ifdef CONFIG_IPCC_BUFFERED
ssize_t nread;
#endif
@ -429,7 +429,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg)
priv = &g_ipccpriv[chan];
#ifdef CONFIG_IPCC_BUFFERED
nread = stm32wl5_ipcc_copy_to_buffer(chan, &priv->ipcc->rxbuf);
nread = stm32_ipcc_copy_to_buffer(chan, &priv->ipcc->rxbuf);
if (nread)
#endif /* CONFIG_IPCC_BUFFERED */
@ -454,7 +454,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg)
}
/****************************************************************************
* Name: stm32wl5_ipcc_read
* Name: stm32_ipcc_read
*
* Description:
* Function will copy requests number of bytes to buffer. If there is not
@ -477,13 +477,13 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg)
*
****************************************************************************/
static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc,
static ssize_t stm32_ipcc_read(struct ipcc_lower_s *ipcc,
char *buffer, size_t buflen)
{
size_t to_copy;
uint32_t sr;
struct stm32wl5_ipcc_s *priv;
struct stm32wl5_ipcc_chan_mem_s *rxmem;
struct stm32_ipcc_s *priv;
struct stm32_ipcc_chan_mem_s *rxmem;
sr = getreg32(STM32_IPCC_C2TOC1SR);
@ -498,7 +498,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc,
}
priv = &g_ipccpriv[ipcc->chan];
rxmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->rxmem;
rxmem = (struct stm32_ipcc_chan_mem_s *)priv->rxmem;
/* Disable RX interrupt since we will modify shared data */
@ -541,7 +541,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc,
}
/****************************************************************************
* Name: stm32wl5_ipcc_copy_to_buffer
* Name: stm32_ipcc_copy_to_buffer
*
* Description:
* Copies as much bytes from channel as possible to rxbuf circ buffer.
@ -560,13 +560,13 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc,
****************************************************************************/
#ifdef CONFIG_IPCC_BUFFERED
static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan,
static ssize_t stm32_ipcc_copy_to_buffer(int chan,
struct circbuf_s *rxbuf)
{
size_t to_copy;
size_t rxbuf_space;
struct stm32wl5_ipcc_s *priv;
struct stm32wl5_ipcc_chan_mem_s *rxmem;
struct stm32_ipcc_s *priv;
struct stm32_ipcc_chan_mem_s *rxmem;
uint32_t sr;
sr = getreg32(STM32_IPCC_C2TOC1SR);
@ -582,7 +582,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan,
}
priv = &g_ipccpriv[chan];
rxmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->rxmem;
rxmem = (struct stm32_ipcc_chan_mem_s *)priv->rxmem;
/* If buffer is full, it's possible we did not copy everything from
* IPCC memory to buffer in previous interrupt. Then when another
@ -641,7 +641,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan,
#endif
/****************************************************************************
* Name: stm32wl5_ipcc_buffer_data
* Name: stm32_ipcc_buffer_data
*
* Description:
* Copies as many bytes as possible from ipcc channel to rxbuf.
@ -658,7 +658,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan,
****************************************************************************/
#ifdef CONFIG_IPCC_BUFFERED
static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
static ssize_t stm32_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
struct circbuf_s *rxbuf)
{
int ret;
@ -669,7 +669,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
/* Copy data to buffer */
ret = stm32wl5_ipcc_copy_to_buffer(ipcc->chan, rxbuf);
ret = stm32_ipcc_copy_to_buffer(ipcc->chan, rxbuf);
/* Re-enable interrupt */
@ -682,7 +682,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
#endif
/****************************************************************************
* Name: stm32wl5_ipcc_write_notify
* Name: stm32_ipcc_write_notify
*
* Description:
* This function is called when there is new data on circ buffer.
@ -699,7 +699,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
****************************************************************************/
#ifdef CONFIG_IPCC_BUFFERED
static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc)
static ssize_t stm32_ipcc_write_notify(struct ipcc_lower_s *ipcc)
{
modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0);
return 0;
@ -707,10 +707,10 @@ static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc)
#endif
/****************************************************************************
* Name: stm32wl5_ipcc_cleanup
* Name: stm32_ipcc_cleanup
*
* Description:
* Cleans up resources initialized by stm32wl5_ipcc_init(). This will
* Cleans up resources initialized by stm32_ipcc_init(). This will
* free() ipcc pointer!
*
* Input Parameters:
@ -721,7 +721,7 @@ static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc)
*
****************************************************************************/
static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc)
static int stm32_ipcc_cleanup(struct ipcc_lower_s *ipcc)
{
DEBUGASSERT(ipcc);
DEBUGASSERT(ipcc->chan <= IPCC_NCHAN);
@ -743,7 +743,7 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc)
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_ipcc_init
* Name: stm32_ipcc_init
*
* Description:
* Function initializes runtime options for IPCC. This function is called
@ -762,7 +762,7 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc)
*
****************************************************************************/
struct ipcc_lower_s *stm32wl5_ipcc_init(int chan)
struct ipcc_lower_s *stm32_ipcc_init(int chan)
{
int ret;
static int ipcc_fti;
@ -786,12 +786,12 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan)
* upper half needs to call to work properly.
*/
ipcc->ops.read = stm32wl5_ipcc_read;
ipcc->ops.write = stm32wl5_ipcc_write;
ipcc->ops.cleanup = stm32wl5_ipcc_cleanup;
ipcc->ops.read = stm32_ipcc_read;
ipcc->ops.write = stm32_ipcc_write;
ipcc->ops.cleanup = stm32_ipcc_cleanup;
#ifdef CONFIG_IPCC_BUFFERED
ipcc->ops.buffer_data = stm32wl5_ipcc_buffer_data;
ipcc->ops.write_notify = stm32wl5_ipcc_write_notify;
ipcc->ops.buffer_data = stm32_ipcc_buffer_data;
ipcc->ops.write_notify = stm32_ipcc_write_notify;
#endif
ipcc->chan = chan;
@ -810,14 +810,14 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan)
* interrupt functions
*/
ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL);
ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32_ipcc_rx_isr, NULL);
if (ret)
{
kmm_free(ipcc);
return NULL;
}
ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL);
ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32_ipcc_tx_isr, NULL);
if (ret)
{
kmm_free(ipcc);

2
arch/arm/src/stm32wl5/stm32wl5_ipcc.h
View file

@ -142,6 +142,6 @@
IPCC_CHAN3_SIZE + IPCC_CHAN4_SIZE + \
IPCC_CHAN5_SIZE + IPCC_CHAN6_SIZE)
struct ipcc_lower_s *stm32wl5_ipcc_init(int chan);
struct ipcc_lower_s *stm32_ipcc_init(int chan);
#endif /* __ARCH_ARM_SRC_STM32WL5_IPCC_H */

40
arch/arm/src/stm32wl5/stm32wl5_irq.c
View file

@ -38,7 +38,7 @@
#include "nvic.h"
#include "ram_vectors.h"
#include "arm_internal.h"
#include "stm32wl5.h"
#include "stm32.h"
/****************************************************************************
* Pre-processor Definitions
@ -64,7 +64,7 @@
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_dumpnvic
* Name: stm32_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
@ -72,7 +72,7 @@
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void stm32wl5_dumpnvic(const char *msg, int irq)
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
@ -128,11 +128,11 @@ static void stm32wl5_dumpnvic(const char *msg, int irq)
leave_critical_section(flags);
}
#else
# define stm32wl5_dumpnvic(msg, irq)
# define stm32_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: stm32wl5_nmi, stm32wl5_pendsv, stm32wl5_pendsv, stm32wl5_reserved
* Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved
*
* Description:
* Handlers for various exceptions. None are handled and all are fatal
@ -142,7 +142,7 @@ static void stm32wl5_dumpnvic(const char *msg, int irq)
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int stm32wl5_nmi(int irq, void *context, void *arg)
static int stm32_nmi(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! NMI received\n");
@ -150,7 +150,7 @@ static int stm32wl5_nmi(int irq, void *context, void *arg)
return 0;
}
static int stm32wl5_pendsv(int irq, void *context, void *arg)
static int stm32_pendsv(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! PendSV received\n");
@ -158,7 +158,7 @@ static int stm32wl5_pendsv(int irq, void *context, void *arg)
return 0;
}
static int stm32wl5_reserved(int irq, void *context, void *arg)
static int stm32_reserved(int irq, void *context, void *arg)
{
up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
@ -168,7 +168,7 @@ static int stm32wl5_reserved(int irq, void *context, void *arg)
#endif
/****************************************************************************
* Name: stm32wl5_prioritize_syscall
* Name: stm32_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
@ -176,7 +176,7 @@ static int stm32wl5_reserved(int irq, void *context, void *arg)
*
****************************************************************************/
static inline void stm32wl5_prioritize_syscall(int priority)
static inline void stm32_prioritize_syscall(int priority)
{
uint32_t regval;
@ -189,7 +189,7 @@ static inline void stm32wl5_prioritize_syscall(int priority)
}
/****************************************************************************
* Name: stm32wl5_irqinfo
* Name: stm32_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
@ -197,7 +197,7 @@ static inline void stm32wl5_prioritize_syscall(int priority)
*
****************************************************************************/
static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
@ -323,7 +323,7 @@ void up_irqinitialize(void)
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
stm32wl5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
@ -337,19 +337,19 @@ void up_irqinitialize(void)
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(STM32_IRQ_NMI, stm32wl5_nmi, NULL);
irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
#endif
irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL);
irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL);
irq_attach(STM32_IRQ_PENDSV, stm32wl5_pendsv, NULL);
irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL);
arm_enable_dbgmonitor();
irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL);
irq_attach(STM32_IRQ_RESERVED, stm32wl5_reserved, NULL);
irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL);
#endif
stm32wl5_dumpnvic("initial", NR_IRQS);
stm32_dumpnvic("initial", NR_IRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
@ -374,7 +374,7 @@ void up_disable_irq(int irq)
uint32_t regval;
uint32_t bit;
if (stm32wl5_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
if (stm32_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
@ -409,7 +409,7 @@ void up_enable_irq(int irq)
uint32_t regval;
uint32_t bit;
if (stm32wl5_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
if (stm32_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
@ -486,7 +486,7 @@ int up_prioritize_irq(int irq, int priority)
regval |= (priority << shift);
putreg32(regval, regaddr);
stm32wl5_dumpnvic("prioritize", irq);
stm32_dumpnvic("prioritize", irq);
return OK;
}
#endif

20
arch/arm/src/stm32wl5/stm32wl5_lowputc.c
View file

@ -34,7 +34,7 @@
#include "chip.h"
#include "stm32wl5.h"
#include "stm32.h"
#include "stm32wl5_rcc.h"
#include "stm32wl5_gpio.h"
#include "stm32wl5_uart.h"
@ -241,7 +241,7 @@ void arm_lowputc(char ch)
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
USART_ISR_TXE) == 0);
#ifdef STM32_CONSOLE_RS485_DIR
stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR,
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
@ -252,7 +252,7 @@ void arm_lowputc(char ch)
#ifdef STM32_CONSOLE_RS485_DIR
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
USART_ISR_TC) == 0);
stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR,
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
!STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
@ -260,7 +260,7 @@ void arm_lowputc(char ch)
}
/****************************************************************************
* Name: stm32wl5_lowsetup
* Name: stm32_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
@ -269,7 +269,7 @@ void arm_lowputc(char ch)
*
****************************************************************************/
void stm32wl5_lowsetup(void)
void stm32_lowsetup(void)
{
#if defined(HAVE_UART)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
@ -285,19 +285,19 @@ void stm32wl5_lowsetup(void)
/* Enable the console USART and configure GPIO pins needed for rx/tx.
*
* NOTE: Clocking for selected U[S]ARTs was already provided in
* stm32wl5_rcc.c
* stm32_rcc.c
*/
#ifdef STM32_CONSOLE_TX
stm32wl5_configgpio(STM32_CONSOLE_TX);
stm32_configgpio(STM32_CONSOLE_TX);
#endif
#ifdef STM32_CONSOLE_RX
stm32wl5_configgpio(STM32_CONSOLE_RX);
stm32_configgpio(STM32_CONSOLE_RX);
#endif
#ifdef STM32_CONSOLE_RS485_DIR
stm32wl5_configgpio(STM32_CONSOLE_RS485_DIR);
stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR,
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
!STM32_CONSOLE_RS485_DIR_POLARITY);
#endif

4
arch/arm/src/stm32wl5/stm32wl5_lowputc.h
View file

@ -47,7 +47,7 @@ extern "C"
#endif
/****************************************************************************
* Name: stm32wl5_lowsetup
* Name: stm32_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
@ -55,7 +55,7 @@ extern "C"
*
****************************************************************************/
void stm32wl5_lowsetup(void);
void stm32_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)

10
arch/arm/src/stm32wl5/stm32wl5_lse.c
View file

@ -69,14 +69,14 @@ static const uint32_t drives[4] =
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_rcc_enablelse
* Name: stm32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) oscillator and the LSE system clock.
*
****************************************************************************/
void stm32wl5_rcc_enablelse(void)
void stm32_rcc_enablelse(void)
{
int writable;
uint32_t regval;
@ -101,7 +101,7 @@ void stm32wl5_rcc_enablelse(void)
* the PWR CR register before to configuring the LSE.
*/
writable = stm32wl5_pwr_enablebkp(true);
writable = stm32_pwr_enablebkp(true);
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON
* bit the RCC BDCR register.
@ -174,7 +174,7 @@ void stm32wl5_rcc_enablelse(void)
while (!((regval = getreg32(STM32_RCC_BDCR)) &
RCC_BDCR_LSESYSRDY))
{
stm32wl5_waste();
stm32_waste();
}
}
@ -189,6 +189,6 @@ void stm32wl5_rcc_enablelse(void)
/* Disable backup domain access if it was disabled on entry */
(void)stm32wl5_pwr_enablebkp(writable);
(void)stm32_pwr_enablebkp(writable);
}
}

8
arch/arm/src/stm32wl5/stm32wl5_lsi.c
View file

@ -33,14 +33,14 @@
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_rcc_enablelsi
* Name: stm32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32wl5_rcc_enablelsi(void)
void stm32_rcc_enablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.
@ -54,14 +54,14 @@ void stm32wl5_rcc_enablelsi(void)
}
/****************************************************************************
* Name: stm32wl5_rcc_disablelsi
* Name: stm32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32wl5_rcc_disablelsi(void)
void stm32_rcc_disablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.

8
arch/arm/src/stm32wl5/stm32wl5_mpuinit.c
View file

@ -41,7 +41,7 @@
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_mpuinitialize
* Name: stm32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3U
@ -49,7 +49,7 @@
*
****************************************************************************/
void stm32wl5_mpuinitialize(void)
void stm32_mpuinitialize(void)
{
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
@ -74,7 +74,7 @@ void stm32wl5_mpuinitialize(void)
}
/****************************************************************************
* Name: stm32wl5_mpu_uheap
* Name: stm32_mpu_uheap
*
* Description:
* Map the user-heap region.
@ -83,7 +83,7 @@ void stm32wl5_mpuinitialize(void)
*
****************************************************************************/
void stm32wl5_mpu_uheap(uintptr_t start, size_t size)
void stm32_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}

12
arch/arm/src/stm32wl5/stm32wl5_mpuinit.h
View file

@ -34,7 +34,7 @@
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_mpuinitialize
* Name: stm32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted MCU
@ -43,13 +43,13 @@
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void stm32wl5_mpuinitialize(void);
void stm32_mpuinitialize(void);
#else
# define stm32wl5_mpuinitialize()
# define stm32_mpuinitialize()
#endif
/****************************************************************************
* Name: stm32wl5_mpu_uheap
* Name: stm32_mpu_uheap
*
* Description:
* Map the user heap region.
@ -57,9 +57,9 @@ void stm32wl5_mpuinitialize(void);
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void stm32wl5_mpu_uheap(uintptr_t start, size_t size);
void stm32_mpu_uheap(uintptr_t start, size_t size);
#else
# define stm32wl5_mpu_uheap(start,size)
# define stm32_mpu_uheap(start,size)
#endif
#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_MPUINIT_H */

20
arch/arm/src/stm32wl5/stm32wl5_pwr.c
View file

@ -40,17 +40,17 @@
* Private Functions
****************************************************************************/
static inline uint16_t stm32wl5_pwr_getreg(uint8_t offset)
static inline uint16_t stm32_pwr_getreg(uint8_t offset)
{
return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset);
}
static inline void stm32wl5_pwr_putreg(uint8_t offset, uint16_t value)
static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value)
{
putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset);
}
static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits,
static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits,
uint16_t setbits)
{
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits,
@ -62,7 +62,7 @@ static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits,
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_pwr_enablebkp
* Name: stm32_pwr_enablebkp
*
* Description:
* Enables access to the backup domain (RTC registers, RTC backup data
@ -76,14 +76,14 @@ static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits,
*
****************************************************************************/
bool stm32wl5_pwr_enablebkp(bool writable)
bool stm32_pwr_enablebkp(bool writable)
{
uint16_t regval;
bool waswritable;
/* Get the current state of the STM32WL5 PWR control register 1 */
regval = stm32wl5_pwr_getreg(STM32_PWR_CR1_OFFSET);
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
waswritable = ((regval & PWR_CR1_DBP) != 0);
/* Enable or disable the ability to write */
@ -93,14 +93,14 @@ bool stm32wl5_pwr_enablebkp(bool writable)
/* Disable backup domain access */
regval &= ~PWR_CR1_DBP;
stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
}
else if (!waswritable && writable)
{
/* Enable backup domain access */
regval |= PWR_CR1_DBP;
stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
/* Enable does not happen right away */
@ -111,7 +111,7 @@ bool stm32wl5_pwr_enablebkp(bool writable)
}
/****************************************************************************
* Name: stm32wl5_pwr_boot_c2
* Name: stm32_pwr_boot_c2
*
* Description:
* Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby
@ -119,7 +119,7 @@ bool stm32wl5_pwr_enablebkp(bool writable)
*
****************************************************************************/
void stm32wl5_pwr_boot_c2(void)
void stm32_pwr_boot_c2(void)
{
modifyreg32(STM32_PWR_CR4, 0, PWR_CR4_C2BOOT);
}

8
arch/arm/src/stm32wl5/stm32wl5_pwr.h
View file

@ -54,7 +54,7 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_pwr_enablebkp
* Name: stm32_pwr_enablebkp
*
* Description:
* Enables access to the backup domain (RTC registers, RTC backup data
@ -68,10 +68,10 @@ extern "C"
*
****************************************************************************/
bool stm32wl5_pwr_enablebkp(bool writable);
bool stm32_pwr_enablebkp(bool writable);
/****************************************************************************
* Name: stm32wl5_pwr_boot_c2
* Name: stm32_pwr_boot_c2
*
* Description:
* Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby
@ -79,7 +79,7 @@ bool stm32wl5_pwr_enablebkp(bool writable);
*
****************************************************************************/
void stm32wl5_pwr_boot_c2(void);
void stm32_pwr_boot_c2(void);
#undef EXTERN
#if defined(__cplusplus)

66
arch/arm/src/stm32wl5/stm32wl5_rcc.c
View file

@ -38,7 +38,7 @@
#include "chip.h"
#include "stm32wl5_rcc.h"
#include "stm32wl5_flash.h"
#include "stm32wl5.h"
#include "stm32.h"
#include "stm32wl5_waste.h"
/****************************************************************************
@ -75,13 +75,13 @@
****************************************************************************/
#if defined(CONFIG_STM32WL5_PWR) && defined(CONFIG_STM32WL5_RTC)
static inline void stm32wl5_rcc_resetbkp(void)
static inline void stm32_rcc_resetbkp(void)
{
bool init_stat;
/* Check if the RTC is already configured */
init_stat = stm32wl5_rtc_is_initialized();
init_stat = stm32_rtc_is_initialized();
if (!init_stat)
{
uint32_t bkregs[STM32_RTC_BKCOUNT];
@ -98,7 +98,7 @@ static inline void stm32wl5_rcc_resetbkp(void)
* backup data registers and backup SRAM).
*/
(void)stm32wl5_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
* reset the backup domain (having backed up the RTC_MAGIC token)
@ -119,7 +119,7 @@ static inline void stm32wl5_rcc_resetbkp(void)
putreg32(bkregs[i], STM32_RTC_BKR(i));
}
(void)stm32wl5_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
}
}
#else
@ -141,7 +141,7 @@ static inline void stm32wl5_rcc_resetbkp(void)
*
* If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32wl5_board_clockconfig().
* function called stm32_board_clockconfig().
*
* Input Parameters
* None
@ -151,7 +151,7 @@ static inline void stm32wl5_rcc_resetbkp(void)
*
****************************************************************************/
void stm32wl5_clockconfig(void)
void stm32_clockconfig(void)
{
#if 0
/* Make sure that we are starting in the reset state */
@ -166,7 +166,7 @@ void stm32wl5_clockconfig(void)
/* Invoke Board Custom Clock Configuration */
stm32wl5_board_clockconfig();
stm32_board_clockconfig();
#else
@ -174,13 +174,13 @@ void stm32wl5_clockconfig(void)
* board.h
*/
stm32wl5_stdclockconfig();
stm32_stdclockconfig();
#endif
/* Enable peripheral clocking */
stm32wl5_rcc_enableperipherals();
stm32_rcc_enableperipherals();
}
/****************************************************************************
@ -191,7 +191,7 @@ void stm32wl5_clockconfig(void)
*
****************************************************************************/
static void stm32wl5_rcc_enableahb1(void)
static void stm32_rcc_enableahb1(void)
{
uint32_t regval;
@ -230,7 +230,7 @@ static void stm32wl5_rcc_enableahb1(void)
*
****************************************************************************/
static inline void stm32wl5_rcc_enableahb2(void)
static inline void stm32_rcc_enableahb2(void)
{
uint32_t regval;
@ -267,7 +267,7 @@ static inline void stm32wl5_rcc_enableahb2(void)
*
****************************************************************************/
static inline void stm32wl5_rcc_enableahb3(void)
static inline void stm32_rcc_enableahb3(void)
{
uint32_t regval;
@ -312,7 +312,7 @@ static inline void stm32wl5_rcc_enableahb3(void)
*
****************************************************************************/
static inline void stm32wl5_rcc_enableapb1(void)
static inline void stm32_rcc_enableapb1(void)
{
uint32_t regval;
@ -405,7 +405,7 @@ static inline void stm32wl5_rcc_enableapb1(void)
*
****************************************************************************/
static inline void stm32wl5_rcc_enableapb2(void)
static inline void stm32_rcc_enableapb2(void)
{
uint32_t regval;
@ -462,7 +462,7 @@ static inline void stm32wl5_rcc_enableapb2(void)
*
****************************************************************************/
static inline void stm32wl5_rcc_enableccip(void)
static inline void stm32_rcc_enableccip(void)
{
uint32_t regval;
@ -545,12 +545,12 @@ static inline void stm32wl5_rcc_enableccip(void)
* re-enable/re-start the PLL
*
* This function performs a subset of the operations performed by
* stm32wl5_clockconfig()
* stm32_clockconfig()
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32wl5_board_clockconfig().
* function called stm32_board_clockconfig().
*
* Input Parameters
* None
@ -561,13 +561,13 @@ static inline void stm32wl5_rcc_enableccip(void)
****************************************************************************/
#ifdef CONFIG_PM
void stm32wl5_clockenable(void)
void stm32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
stm32wl5_board_clockconfig();
stm32_board_clockconfig();
#else
@ -575,28 +575,28 @@ void stm32wl5_clockenable(void)
* board.h
*/
stm32wl5_stdclockconfig();
stm32_stdclockconfig();
#endif
}
#endif
/****************************************************************************
* Name: stm32wl5_rcc_enableperipherals
* Name: stm32_rcc_enableperipherals
****************************************************************************/
void stm32wl5_rcc_enableperipherals(void)
void stm32_rcc_enableperipherals(void)
{
stm32wl5_rcc_enableccip();
stm32wl5_rcc_enableahb1();
stm32wl5_rcc_enableahb2();
stm32wl5_rcc_enableahb3();
stm32wl5_rcc_enableapb1();
stm32wl5_rcc_enableapb2();
stm32_rcc_enableccip();
stm32_rcc_enableahb1();
stm32_rcc_enableahb2();
stm32_rcc_enableahb3();
stm32_rcc_enableapb1();
stm32_rcc_enableapb2();
}
/****************************************************************************
* Name: stm32wl5_stdclockconfig
* Name: stm32_stdclockconfig
*
* Description:
* Called to change to new clock based on settings in board.h
@ -606,7 +606,7 @@ void stm32wl5_rcc_enableperipherals(void)
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG
void stm32wl5_stdclockconfig(void)
void stm32_stdclockconfig(void)
{
uint32_t regval;
@ -704,7 +704,7 @@ void stm32wl5_stdclockconfig(void)
}
#else
# error stm32wl5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined
# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined
#endif
@ -852,7 +852,7 @@ void stm32wl5_stdclockconfig(void)
#if defined(CONFIG_STM32WL5_IWDG) || defined(CONFIG_STM32WL5_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32wl5_rcc_enablelsi();
stm32_rcc_enablelsi();
#endif
}
#endif

42
arch/arm/src/stm32wl5/stm32wl5_rcc.h
View file

@ -54,7 +54,7 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_mcoconfig
* Name: stm32_mcoconfig
*
* Description:
* Selects the clock source to output on MC pin (PA8) for stm32wl562xx
@ -71,7 +71,7 @@ extern "C"
*
****************************************************************************/
static inline void stm32wl5_mcoconfig(uint32_t source)
static inline void stm32_mcoconfig(uint32_t source)
{
uint32_t regval;
@ -88,7 +88,7 @@ static inline void stm32wl5_mcoconfig(uint32_t source)
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_clockconfig
* Name: stm32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
@ -98,7 +98,7 @@ static inline void stm32wl5_mcoconfig(uint32_t source)
*
* If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32wl5_board_clockconfig().
* function called stm32_board_clockconfig().
*
* Input Parameters:
* None
@ -108,10 +108,10 @@ static inline void stm32wl5_mcoconfig(uint32_t source)
*
****************************************************************************/
void stm32wl5_clockconfig(void);
void stm32_clockconfig(void);
/****************************************************************************
* Name: stm32wl5_board_clockconfig
* Name: stm32_board_clockconfig
*
* Description:
* Any STM32WL5 board may replace the "standard" board clock configuration
@ -120,11 +120,11 @@ void stm32wl5_clockconfig(void);
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG
void stm32wl5_board_clockconfig(void);
void stm32_board_clockconfig(void);
#endif
/****************************************************************************
* Name: stm32wl5_stdclockconfig
* Name: stm32_stdclockconfig
*
* Description:
* The standard logic to configure the clocks based on settings in board.h.
@ -135,11 +135,11 @@ void stm32wl5_board_clockconfig(void);
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG
void stm32wl5_stdclockconfig(void);
void stm32_stdclockconfig(void);
#endif
/****************************************************************************
* Name: stm32wl5_clockenable
* Name: stm32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
@ -148,12 +148,12 @@ void stm32wl5_stdclockconfig(void);
* re-enable/re-start the PLL
*
* This function performs a subset of the operations performed by
* stm32wl5_clockconfig(): It does not reset any devices, and it does not
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32wl5_board_clockconfig().
* function called stm32_board_clockconfig().
*
* Input Parameters:
* None
@ -164,11 +164,11 @@ void stm32wl5_stdclockconfig(void);
****************************************************************************/
#ifdef CONFIG_PM
void stm32wl5_clockenable(void);
void stm32_clockenable(void);
#endif
/****************************************************************************
* Name: stm32wl5_rcc_enablelse
* Name: stm32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) Oscillator.
@ -181,30 +181,30 @@ void stm32wl5_clockenable(void);
*
****************************************************************************/
void stm32wl5_rcc_enablelse(void);
void stm32_rcc_enablelse(void);
/****************************************************************************
* Name: stm32wl5_rcc_enablelsi
* Name: stm32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32wl5_rcc_enablelsi(void);
void stm32_rcc_enablelsi(void);
/****************************************************************************
* Name: stm32wl5_rcc_disablelsi
* Name: stm32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32wl5_rcc_disablelsi(void);
void stm32_rcc_disablelsi(void);
/****************************************************************************
* Name: stm32wl5_rcc_enableperipherals
* Name: stm32_rcc_enableperipherals
*
* Description:
* Enable all the chip peripherals according to configuration. This is
@ -213,7 +213,7 @@ void stm32wl5_rcc_disablelsi(void);
*
****************************************************************************/
void stm32wl5_rcc_enableperipherals(void);
void stm32_rcc_enableperipherals(void);
#undef EXTERN
#if defined(__cplusplus)

198
arch/arm/src/stm32wl5/stm32wl5_serial.c
View file

@ -182,7 +182,7 @@
* Private Types
****************************************************************************/
struct stm32wl5_serial_s
struct stm32_serial_s
{
struct uart_dev_s dev; /* Generic UART device */
uint16_t ie; /* Saved interrupt mask bits value */
@ -297,9 +297,9 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev);
static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev);
static int stm32wl5serial_dmareceive(struct uart_dev_s *dev,
unsigned int *status);
static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv);
static void stm32wl5serial_dmareenable(struct stm32_serial_s *priv);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv);
static bool stm32wl5serial_dmaiflowrestart(struct stm32_serial_s *priv);
#endif
static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable);
static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev);
@ -393,7 +393,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
static struct stm32wl5_serial_s g_lpuart1priv =
static struct stm32_serial_s g_lpuart1priv =
{
.dev =
{
@ -453,7 +453,7 @@ static struct stm32wl5_serial_s g_lpuart1priv =
#endif
#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER
static struct stm32wl5_serial_s g_usart1priv =
static struct stm32_serial_s g_usart1priv =
{
.dev =
{
@ -515,7 +515,7 @@ static struct stm32wl5_serial_s g_usart1priv =
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER
static struct stm32wl5_serial_s g_usart2priv =
static struct stm32_serial_s g_usart2priv =
{
.dev =
{
@ -576,7 +576,7 @@ static struct stm32wl5_serial_s g_usart2priv =
/* This table lets us iterate over the configured USARTs */
static struct stm32wl5_serial_s * const
static struct stm32_serial_s * const
g_uart_devs[STM32_NLPUART + STM32_NUSART] =
{
#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
@ -614,7 +614,7 @@ static struct serialpm_s g_serialpm =
****************************************************************************/
static inline
uint32_t stm32wl5serial_getreg(struct stm32wl5_serial_s *priv, int offset)
uint32_t stm32wl5serial_getreg(struct stm32_serial_s *priv, int offset)
{
return getreg32(priv->usartbase + offset);
}
@ -624,7 +624,7 @@ uint32_t stm32wl5serial_getreg(struct stm32wl5_serial_s *priv, int offset)
****************************************************************************/
static inline
void stm32wl5serial_putreg(struct stm32wl5_serial_s *priv,
void stm32wl5serial_putreg(struct stm32_serial_s *priv,
int offset, uint32_t value)
{
putreg32(value, priv->usartbase + offset);
@ -635,7 +635,7 @@ void stm32wl5serial_putreg(struct stm32wl5_serial_s *priv,
****************************************************************************/
static inline
void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie)
void stm32wl5serial_setusartint(struct stm32_serial_s *priv, uint16_t ie)
{
uint32_t cr;
@ -662,7 +662,7 @@ void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie)
* Name: up_restoreusartint
****************************************************************************/
static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv,
static void stm32wl5serial_restoreusartint(struct stm32_serial_s *priv,
uint16_t ie)
{
irqstate_t flags;
@ -678,7 +678,7 @@ static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv,
* Name: stm32wl5serial_disableusartint
****************************************************************************/
static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv,
static void stm32wl5serial_disableusartint(struct stm32_serial_s *priv,
uint16_t *ie)
{
irqstate_t flags;
@ -739,11 +739,11 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv,
****************************************************************************/
#ifdef SERIAL_HAVE_DMA
static int stm32wl5serial_dmanextrx(struct stm32wl5_serial_s *priv)
static int stm32wl5serial_dmanextrx(struct stm32_serial_s *priv)
{
size_t dmaresidual;
dmaresidual = stm32wl5_dmaresidual(priv->rxdma);
dmaresidual = stm32_dmaresidual(priv->rxdma);
return (RXDMA_BUFFER_SIZE - (int)dmaresidual);
}
@ -760,8 +760,8 @@ static int stm32wl5serial_dmanextrx(struct stm32wl5_serial_s *priv)
#ifndef CONFIG_SUPPRESS_UART_CONFIG
static void stm32wl5serial_setformat(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
uint32_t regval;
/* This first implementation is for U[S]ARTs that support oversampling
@ -921,7 +921,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev)
#ifdef CONFIG_PM
static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend)
{
struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv;
#ifdef SERIAL_HAVE_DMA
bool dmarestored = false;
#endif
@ -940,7 +940,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend)
{
/* Force RTS high to prevent further Rx. */
stm32wl5_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK)
stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK)
| (GPIO_OUTPUT | GPIO_OUTPUT_SET));
}
#endif
@ -969,7 +969,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend)
{
/* Suspend Rx DMA. */
stm32wl5_dmastop(priv->rxdma);
stm32_dmastop(priv->rxdma);
priv->rxdmasusp = true;
}
}
@ -1010,7 +1010,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend)
{
/* Restore peripheral RTS control. */
stm32wl5_configgpio(priv->rts_gpio);
stm32_configgpio(priv->rts_gpio);
}
#endif
}
@ -1059,7 +1059,7 @@ static void stm32wl5serial_pm_setsuspend(bool suspend)
for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++)
{
struct stm32wl5_serial_s *priv = g_uart_devs[n];
struct stm32_serial_s *priv = g_uart_devs[n];
if (!priv || !priv->initialized)
{
@ -1085,8 +1085,8 @@ static void stm32wl5serial_pm_setsuspend(bool suspend)
static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
uint32_t rcc_en;
uint32_t regaddr;
@ -1139,14 +1139,14 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on)
static int stm32wl5serial_setup(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
#ifndef CONFIG_SUPPRESS_UART_CONFIG
uint32_t regval;
/* Note: The logic here depends on the fact that that the USART module
* was enabled in stm32wl5_lowsetup().
* was enabled in stm32_lowsetup().
*/
/* Enable USART APB1/2 clock */
@ -1157,18 +1157,18 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev)
if (priv->tx_gpio != 0)
{
stm32wl5_configgpio(priv->tx_gpio);
stm32_configgpio(priv->tx_gpio);
}
if (priv->rx_gpio != 0)
{
stm32wl5_configgpio(priv->rx_gpio);
stm32_configgpio(priv->rx_gpio);
}
#ifdef CONFIG_SERIAL_OFLOWCONTROL
if (priv->cts_gpio != 0)
{
stm32wl5_configgpio(priv->cts_gpio);
stm32_configgpio(priv->cts_gpio);
}
#endif
@ -1182,15 +1182,15 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev)
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
#endif
stm32wl5_configgpio(config);
stm32_configgpio(config);
}
#endif
#ifdef HAVE_RS485
if (priv->rs485_dir_gpio != 0)
{
stm32wl5_configgpio(priv->rs485_dir_gpio);
stm32wl5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
stm32_configgpio(priv->rs485_dir_gpio);
stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
}
#endif
@ -1265,8 +1265,8 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev)
#ifdef SERIAL_HAVE_DMA
static int stm32wl5serial_dmasetup(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
int result;
uint32_t regval;
@ -1283,14 +1283,14 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev)
/* Acquire the DMA channel. This should always succeed. */
priv->rxdma = stm32wl5_dmachannel(priv->rxdma_channel);
priv->rxdma = stm32_dmachannel(priv->rxdma_channel);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
if (priv->iflow)
{
/* Configure for non-circular DMA reception into the RX FIFO */
stm32wl5_dmasetup(priv->rxdma,
stm32_dmasetup(priv->rxdma,
priv->usartbase + STM32_USART_RDR_OFFSET,
(uint32_t)priv->rxfifo,
RXDMA_BUFFER_SIZE,
@ -1301,7 +1301,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev)
{
/* Configure for circular DMA reception into the RX FIFO */
stm32wl5_dmasetup(priv->rxdma,
stm32_dmasetup(priv->rxdma,
priv->usartbase + STM32_USART_RDR_OFFSET,
(uint32_t)priv->rxfifo,
RXDMA_BUFFER_SIZE,
@ -1328,7 +1328,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev)
* in and DMA transfer is stopped.
*/
stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback,
stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback,
(void *)priv, false);
}
else
@ -1339,7 +1339,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev)
* worth of time to claim bytes before they are overwritten.
*/
stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback,
stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback,
(void *)priv, true);
}
@ -1358,8 +1358,8 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev)
static void stm32wl5serial_shutdown(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
uint32_t regval;
/* Mark device as uninitialized. */
@ -1390,32 +1390,32 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev)
if (priv->tx_gpio != 0)
{
stm32wl5_unconfiggpio(priv->tx_gpio);
stm32_unconfiggpio(priv->tx_gpio);
}
if (priv->rx_gpio != 0)
{
stm32wl5_unconfiggpio(priv->rx_gpio);
stm32_unconfiggpio(priv->rx_gpio);
}
#ifdef CONFIG_SERIAL_OFLOWCONTROL
if (priv->cts_gpio != 0)
{
stm32wl5_unconfiggpio(priv->cts_gpio);
stm32_unconfiggpio(priv->cts_gpio);
}
#endif
#ifdef CONFIG_SERIAL_IFLOWCONTROL
if (priv->rts_gpio != 0)
{
stm32wl5_unconfiggpio(priv->rts_gpio);
stm32_unconfiggpio(priv->rts_gpio);
}
#endif
#ifdef HAVE_RS485
if (priv->rs485_dir_gpio != 0)
{
stm32wl5_unconfiggpio(priv->rs485_dir_gpio);
stm32_unconfiggpio(priv->rs485_dir_gpio);
}
#endif
}
@ -1432,8 +1432,8 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev)
#ifdef SERIAL_HAVE_DMA
static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
/* Perform the normal UART shutdown */
@ -1441,11 +1441,11 @@ static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev)
/* Stop the DMA channel */
stm32wl5_dmastop(priv->rxdma);
stm32_dmastop(priv->rxdma);
/* Release the DMA channel */
stm32wl5_dmafree(priv->rxdma);
stm32_dmafree(priv->rxdma);
priv->rxdma = NULL;
}
#endif
@ -1468,8 +1468,8 @@ static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev)
static int stm32wl5serial_attach(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
int ret;
/* Attach and enable the IRQ */
@ -1500,8 +1500,8 @@ static int stm32wl5serial_attach(struct uart_dev_s *dev)
static void stm32wl5serial_detach(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
up_disable_irq(priv->irq);
irq_detach(priv->irq);
}
@ -1521,7 +1521,7 @@ static void stm32wl5serial_detach(struct uart_dev_s *dev)
static int stm32wl5serial_interrupt(int irq, void *context,
void *arg)
{
struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)arg;
struct stm32_serial_s *priv = (struct stm32_serial_s *)arg;
int passes;
bool handled;
@ -1581,7 +1581,7 @@ static int stm32wl5serial_interrupt(int irq, void *context,
(priv->ie & USART_CR1_TCIE) != 0 &&
(priv->ie & USART_CR1_TXEIE) == 0)
{
stm32wl5_gpiowrite(priv->rs485_dir_gpio,
stm32_gpiowrite(priv->rs485_dir_gpio,
!priv->rs485_dir_polarity);
stm32wl5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE);
}
@ -1648,8 +1648,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
struct uart_dev_s *dev = inode->i_private;
#endif
#if defined(CONFIG_SERIAL_TERMIOS)
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
#endif
int ret = OK;
@ -1658,9 +1658,9 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
case TIOCSERGSTRUCT:
{
struct stm32wl5_serial_s *user;
struct stm32_serial_s *user;
user = (struct stm32wl5_serial_s *)arg;
user = (struct stm32_serial_s *)arg;
if (!user)
{
@ -1668,7 +1668,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
}
else
{
memcpy(user, dev, sizeof(struct stm32wl5_serial_s));
memcpy(user, dev, sizeof(struct stm32_serial_s));
}
}
break;
@ -1723,7 +1723,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
if (priv->tx_gpio != 0)
{
stm32wl5_configgpio((priv->tx_gpio &
stm32_configgpio((priv->tx_gpio &
~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) |
gpio_val);
}
@ -1734,7 +1734,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
{
if (priv->tx_gpio != 0)
{
stm32wl5_configgpio((priv->tx_gpio &
stm32_configgpio((priv->tx_gpio &
~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) |
GPIO_PUSHPULL);
}
@ -1960,7 +1960,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
{
uint32_t tx_break = GPIO_OUTPUT |
(~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio);
stm32wl5_configgpio(tx_break);
stm32_configgpio(tx_break);
}
leave_critical_section(flags);
@ -1977,7 +1977,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
if (priv->tx_gpio != 0)
{
stm32wl5_configgpio(priv->tx_gpio);
stm32_configgpio(priv->tx_gpio);
}
priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS;
@ -2040,8 +2040,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
static int stm32wl5serial_receive(struct uart_dev_s *dev,
unsigned int *status)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
uint32_t rdr;
/* Get the Rx byte */
@ -2070,8 +2070,8 @@ static int stm32wl5serial_receive(struct uart_dev_s *dev,
#ifndef SERIAL_HAVE_ONLY_DMA
static void stm32wl5serial_rxint(struct uart_dev_s *dev, bool enable)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
irqstate_t flags;
uint16_t ie;
@ -2130,8 +2130,8 @@ static void stm32wl5serial_rxint(struct uart_dev_s *dev, bool enable)
#ifndef SERIAL_HAVE_ONLY_DMA
static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) &
USART_ISR_RXNE) != 0);
@ -2165,8 +2165,8 @@ static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev)
static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev,
unsigned int nbuffered, bool upper)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN)
@ -2174,7 +2174,7 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev,
{
/* Assert/de-assert nRTS set it high resume/stop sending */
stm32wl5_gpiowrite(priv->rts_gpio, upper);
stm32_gpiowrite(priv->rts_gpio, upper);
if (upper)
{
@ -2249,8 +2249,8 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev,
static int stm32wl5serial_dmareceive(struct uart_dev_s *dev,
unsigned int *status)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
int c = 0;
if (stm32wl5serial_dmanextrx(priv) != priv->rxdmanext)
@ -2288,14 +2288,14 @@ static int stm32wl5serial_dmareceive(struct uart_dev_s *dev,
****************************************************************************/
#if defined(SERIAL_HAVE_DMA)
static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv)
static void stm32wl5serial_dmareenable(struct stm32_serial_s *priv)
{
#ifdef CONFIG_SERIAL_IFLOWCONTROL
if (priv->iflow)
{
/* Configure for non-circular DMA reception into the RX FIFO */
stm32wl5_dmasetup(priv->rxdma,
stm32_dmasetup(priv->rxdma,
priv->usartbase + STM32_USART_RDR_OFFSET,
(uint32_t)priv->rxfifo,
RXDMA_BUFFER_SIZE,
@ -2306,7 +2306,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv)
{
/* Configure for circular DMA reception into the RX FIFO */
stm32wl5_dmasetup(priv->rxdma,
stm32_dmasetup(priv->rxdma,
priv->usartbase + STM32_USART_RDR_OFFSET,
(uint32_t)priv->rxfifo,
RXDMA_BUFFER_SIZE,
@ -2327,7 +2327,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv)
* in and DMA transfer is stopped.
*/
stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback,
stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback,
(void *)priv, false);
}
else
@ -2338,7 +2338,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv)
* worth of time to claim bytes before they are overwritten.
*/
stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback,
stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback,
(void *)priv, true);
}
@ -2359,7 +2359,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv)
****************************************************************************/
#if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL)
static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv)
static bool stm32wl5serial_dmaiflowrestart(struct stm32_serial_s *priv)
{
if (!priv->rxenable)
{
@ -2410,8 +2410,8 @@ static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv)
#ifdef SERIAL_HAVE_DMA
static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
/* En/disable DMA reception.
*
@ -2445,8 +2445,8 @@ static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable)
#ifdef SERIAL_HAVE_DMA
static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
/* Compare our receive pointer to the current DMA pointer, if they
* do not match, then there are bytes to be received.
@ -2466,13 +2466,13 @@ static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev)
static void stm32wl5serial_send(struct uart_dev_s *dev, int ch)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
#ifdef HAVE_RS485
if (priv->rs485_dir_gpio != 0)
{
stm32wl5_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity);
stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity);
}
#endif
@ -2489,8 +2489,8 @@ static void stm32wl5serial_send(struct uart_dev_s *dev, int ch)
static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
irqstate_t flags;
/* USART transmit interrupts:
@ -2558,8 +2558,8 @@ static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable)
static bool stm32wl5serial_txready(struct uart_dev_s *dev)
{
struct stm32wl5_serial_s *priv =
(struct stm32wl5_serial_s *)dev->priv;
struct stm32_serial_s *priv =
(struct stm32_serial_s *)dev->priv;
return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) &
USART_ISR_TXE) != 0);
@ -2578,7 +2578,7 @@ static bool stm32wl5serial_txready(struct uart_dev_s *dev)
static void stm32wl5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status,
void *arg)
{
struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)arg;
struct stm32_serial_s *priv = (struct stm32_serial_s *)arg;
if (priv->rxenable && stm32wl5serial_dmarxavailable(&priv->dev))
{
@ -2736,7 +2736,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain,
* buffers.
*/
stm32wl5_serial_dma_poll();
stm32_serial_dma_poll();
#endif
/* Check if any of the active ports have data pending on Tx/Rx
@ -2745,7 +2745,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain,
for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++)
{
struct stm32wl5_serial_s *priv = g_uart_devs[n];
struct stm32_serial_s *priv = g_uart_devs[n];
if (!priv || !priv->initialized)
{
@ -2909,7 +2909,7 @@ void arm_serialinit(void)
}
/****************************************************************************
* Name: stm32wl5_serial_dma_poll
* Name: stm32_serial_dma_poll
*
* Description:
* Checks receive DMA buffers for received bytes that have not accumulated
@ -2920,7 +2920,7 @@ void arm_serialinit(void)
****************************************************************************/
#ifdef SERIAL_HAVE_DMA
void stm32wl5_serial_dma_poll(void)
void stm32_serial_dma_poll(void)
{
irqstate_t flags;
@ -2962,7 +2962,7 @@ void stm32wl5_serial_dma_poll(void)
void up_putc(int ch)
{
#if CONSOLE_UART > 0
struct stm32wl5_serial_s *priv = g_uart_devs[CONSOLE_UART - 1];
struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1];
uint16_t ie;
stm32wl5serial_disableusartint(priv, &ie);

162
arch/arm/src/stm32wl5/stm32wl5_spi.c
View file

@ -21,22 +21,22 @@
****************************************************************************/
/****************************************************************************
* The external functions, stm32wl5_spi1/2select and stm32wl5_spi1/2status
* The external functions, stm32_spi1/2select and stm32_spi1/2status
* must be provided by board-specific logic. They are implementations of the
* select and status methods of the SPI interface defined by struct spi_ops_s
* (see include/nuttx/spi/spi.h).
* All other methods (including stm32wl5_spibus_initialize()) are provided
* All other methods (including stm32_spibus_initialize()) are provided
* by common STM32 logic. To use this common SPI logic on your board:
*
* 1. Provide logic in stm32wl5_boardinitialize() to configure SPI chip
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip
* select pins.
* 2. Provide stm32wl5_spi1/2select() and stm32wl5_spi1/2() functions
* 2. Provide stm32_spi1/2select() and stm32_spi1/2() functions
* in your board-specific logic. These functions will perform chip
* selection and status operations using GPIOs in the way your board is
* configured.
* 3. Add a calls to stm32wl5_spibus_initialize() in your low level
* 3. Add a calls to stm32_spibus_initialize() in your low level
* application initialization logic
* 4. The handle returned by stm32wl5_spibus_initialize() may then be used
* 4. The handle returned by stm32_spibus_initialize() may then be used
* to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
@ -67,7 +67,7 @@
#include "arm_internal.h"
#include "chip.h"
#include "stm32wl5.h"
#include "stm32.h"
#include "stm32wl5_gpio.h"
#ifdef CONFIG_STM32WL5_SPI_DMA
#include "stm32wl5_dma.h"
@ -155,7 +155,7 @@
* Private Types
****************************************************************************/
struct stm32wl5_spidev_s
struct stm32_spidev_s
{
struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
uint32_t spibase; /* SPIn base address */
@ -196,45 +196,45 @@ struct stm32wl5_spidev_s
/* Helpers */
static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv,
static inline uint16_t spi_getreg(struct stm32_spidev_s *priv,
uint8_t offset);
static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv,
static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv,
uint8_t offset);
static inline void spi_putreg(struct stm32wl5_spidev_s *priv,
static inline void spi_putreg(struct stm32_spidev_s *priv,
uint8_t offset,
uint16_t value);
static inline void spi_putreg8(struct stm32wl5_spidev_s *priv,
static inline void spi_putreg8(struct stm32_spidev_s *priv,
uint8_t offset,
uint8_t value);
static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv);
static inline void spi_writeword(struct stm32wl5_spidev_s *priv,
static inline uint16_t spi_readword(struct stm32_spidev_s *priv);
static inline void spi_writeword(struct stm32_spidev_s *priv,
uint16_t byte);
/* DMA support */
#ifdef CONFIG_STM32WL5_SPI_DMA
static int spi_dmarxwait(struct stm32wl5_spidev_s *priv);
static int spi_dmatxwait(struct stm32wl5_spidev_s *priv);
static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv);
static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv);
static int spi_dmarxwait(struct stm32_spidev_s *priv);
static int spi_dmatxwait(struct stm32_spidev_s *priv);
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv);
static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv);
static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr,
void *arg);
static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr,
void *arg);
static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv,
static void spi_dmarxsetup(struct stm32_spidev_s *priv,
void *rxbuffer,
void *rxdummy,
size_t nwords);
static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv,
static void spi_dmatxsetup(struct stm32_spidev_s *priv,
const void *txbuffer,
const void *txdummy,
size_t nwords);
static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv);
static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv);
static inline void spi_dmarxstart(struct stm32_spidev_s *priv);
static inline void spi_dmatxstart(struct stm32_spidev_s *priv);
#endif
/* SPI methods */
@ -267,7 +267,7 @@ static void spi_recvblock(struct spi_dev_s *dev,
/* Initialization */
static void spi_bus_initialize(struct stm32wl5_spidev_s *priv);
static void spi_bus_initialize(struct stm32_spidev_s *priv);
/****************************************************************************
* Private Data
@ -277,16 +277,16 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv);
static const struct spi_ops_s g_sp1iops =
{
.lock = spi_lock,
.select = stm32wl5_spi1select,
.select = stm32_spi1select,
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = spi_hwfeatures,
#endif
.status = stm32wl5_spi1status,
.status = stm32_spi1status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32wl5_spi1cmddata,
.cmddata = stm32_spi1cmddata,
#endif
.send = spi_send,
#ifdef CONFIG_SPI_EXCHANGE
@ -299,7 +299,7 @@ static const struct spi_ops_s g_sp1iops =
.trigger = spi_trigger,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = stm32wl5_spi1register, /* Provided externally */
.registercallback = stm32_spi1register, /* Provided externally */
#else
.registercallback = 0, /* Not implemented */
#endif
@ -310,7 +310,7 @@ static uint8_t g_spi1_txbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN;
static uint8_t g_spi1_rxbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN;
#endif
static struct stm32wl5_spidev_s g_spi1dev =
static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
@ -345,16 +345,16 @@ static struct stm32wl5_spidev_s g_spi1dev =
static const struct spi_ops_s g_sp2iops =
{
.lock = spi_lock,
.select = stm32wl5_spi2s2select,
.select = stm32_spi2s2select,
.setfrequency = spi_setfrequency,
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = spi_hwfeatures,
#endif
.status = stm32wl5_spi2s2status,
.status = stm32_spi2s2status,
#ifdef CONFIG_SPI_CMDDATA
.cmddata = stm32wl5_spi2s2cmddata,
.cmddata = stm32_spi2s2cmddata,
#endif
.send = spi_send,
#ifdef CONFIG_SPI_EXCHANGE
@ -367,7 +367,7 @@ static const struct spi_ops_s g_sp2iops =
.trigger = spi_trigger,
#endif
#ifdef CONFIG_SPI_CALLBACK
.registercallback = stm32wl5_s2register, /* provided externally */
.registercallback = stm32_s2register, /* provided externally */
#else
.registercallback = 0, /* not implemented */
#endif
@ -380,7 +380,7 @@ static uint8_t g_spi2s2_rxbuf[SPI2S2_DMABUFSIZE_ADJUSTED]
SPI2S2_DMABUFSIZE_ALGN;
#endif
static struct stm32wl5_spidev_s g_spi2s2dev =
static struct stm32_spidev_s g_spi2s2dev =
{
.spidev =
{
@ -427,7 +427,7 @@ static struct stm32wl5_spidev_s g_spi2s2dev =
*
****************************************************************************/
static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv,
static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv,
uint8_t offset)
{
return getreg8(priv->spibase + offset);
@ -448,7 +448,7 @@ static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv,
*
****************************************************************************/
static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv,
static inline uint16_t spi_getreg(struct stm32_spidev_s *priv,
uint8_t offset)
{
return getreg16(priv->spibase + offset);
@ -470,7 +470,7 @@ static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv,
*
****************************************************************************/
static inline void spi_putreg(struct stm32wl5_spidev_s *priv,
static inline void spi_putreg(struct stm32_spidev_s *priv,
uint8_t offset,
uint16_t value)
{
@ -493,7 +493,7 @@ static inline void spi_putreg(struct stm32wl5_spidev_s *priv,
*
****************************************************************************/
static inline void spi_putreg8(struct stm32wl5_spidev_s *priv,
static inline void spi_putreg8(struct stm32_spidev_s *priv,
uint8_t offset,
uint8_t value)
{
@ -514,7 +514,7 @@ static inline void spi_putreg8(struct stm32wl5_spidev_s *priv,
*
****************************************************************************/
static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv)
static inline uint16_t spi_readword(struct stm32_spidev_s *priv)
{
/* Wait until the receive buffer is not empty */
@ -563,7 +563,7 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv)
*
****************************************************************************/
static inline void spi_writeword(struct stm32wl5_spidev_s *priv,
static inline void spi_writeword(struct stm32_spidev_s *priv,
uint16_t word)
{
/* Wait until the transmit buffer is empty */
@ -593,7 +593,7 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv,
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
static int spi_dmarxwait(struct stm32wl5_spidev_s *priv)
static int spi_dmarxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -626,7 +626,7 @@ static int spi_dmarxwait(struct stm32wl5_spidev_s *priv)
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
static int spi_dmatxwait(struct stm32wl5_spidev_s *priv)
static int spi_dmatxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -659,7 +659,7 @@ static int spi_dmatxwait(struct stm32wl5_spidev_s *priv)
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv)
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->rxsem);
}
@ -674,7 +674,7 @@ static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv)
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv)
static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->txsem);
}
@ -691,7 +691,7 @@ static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv)
#ifdef CONFIG_STM32WL5_SPI_DMA
static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
/* Wake-up the SPI driver */
@ -711,7 +711,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
#ifdef CONFIG_STM32WL5_SPI_DMA
static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
/* Wake-up the SPI driver */
@ -729,7 +729,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv,
static void spi_dmarxsetup(struct stm32_spidev_s *priv,
void *rxbuffer,
void *rxdummy, size_t nwords)
{
@ -766,7 +766,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv,
/* Configure the RX DMA */
stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET,
stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET,
(uint32_t)rxbuffer, nwords, priv->rxccr);
}
#endif
@ -780,7 +780,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv,
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv,
static void spi_dmatxsetup(struct stm32_spidev_s *priv,
const void *txbuffer,
const void *txdummy, size_t nwords)
{
@ -817,7 +817,7 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv,
/* Setup the TX DMA */
stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET,
stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET,
(uint32_t)txbuffer, nwords, priv->txccr);
}
#endif
@ -831,10 +831,10 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv,
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv)
static inline void spi_dmarxstart(struct stm32_spidev_s *priv)
{
priv->rxresult = 0;
stm32wl5_dmastart(priv->rxdma, spi_dmarxcallback, priv, false);
stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false);
}
#endif
@ -847,10 +847,10 @@ static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv)
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv)
static inline void spi_dmatxstart(struct stm32_spidev_s *priv)
{
priv->txresult = 0;
stm32wl5_dmastart(priv->txdma, spi_dmatxcallback, priv, false);
stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false);
}
#endif
@ -870,7 +870,7 @@ static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv)
*
****************************************************************************/
static void spi_modifycr1(struct stm32wl5_spidev_s *priv,
static void spi_modifycr1(struct stm32_spidev_s *priv,
uint16_t setbits,
uint16_t clrbits)
{
@ -900,7 +900,7 @@ static void spi_modifycr1(struct stm32wl5_spidev_s *priv,
*
****************************************************************************/
static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits,
static void spi_modifycr2(struct stm32_spidev_s *priv, uint16_t setbits,
uint16_t clrbits)
{
uint16_t cr2;
@ -935,7 +935,7 @@ static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits,
static int spi_lock(struct spi_dev_s *dev, bool lock)
{
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
int ret;
if (lock)
@ -968,7 +968,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
static uint32_t spi_setfrequency(struct spi_dev_s *dev,
uint32_t frequency)
{
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
uint16_t setbits;
uint32_t actual;
@ -1069,7 +1069,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev,
static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
{
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
uint16_t setbits;
uint16_t clrbits;
@ -1168,7 +1168,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
static void spi_setbits(struct spi_dev_s *dev, int nbits)
{
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
uint16_t setbits;
uint16_t clrbits;
@ -1237,7 +1237,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev,
spi_hwfeatures_t features)
{
#if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER)
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
#endif
#ifdef CONFIG_SPI_BITORDER
@ -1301,7 +1301,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev,
static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
{
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
uint32_t regval;
uint32_t ret;
@ -1359,7 +1359,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
void *rxbuffer, size_t nwords)
#endif
{
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@ -1460,7 +1460,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
void *xbuffer = rxbuffer;
int ret;
@ -1495,9 +1495,9 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
#ifdef CONFIG_STM32WL5_DMACAPABLE
if ((txbuffer != NULL && priv->txbuf == NULL &&
!stm32wl5_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) ||
!stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) ||
(rxbuffer != NULL && priv->rxbuf == NULL &&
!stm32wl5_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr)))
!stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr)))
{
/* Unsupported memory region fall back to non-DMA method. */
@ -1602,7 +1602,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
static int spi_trigger(struct spi_dev_s *dev)
{
#ifdef CONFIG_STM32WL5_SPI_DMA
struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev;
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
if (!priv->trigarmed)
{
@ -1695,7 +1695,7 @@ static void spi_recvblock(struct spi_dev_s *dev,
*
****************************************************************************/
static void spi_bus_initialize(struct stm32wl5_spidev_s *priv)
static void spi_bus_initialize(struct stm32_spidev_s *priv)
{
uint16_t setbits;
uint16_t clrbits;
@ -1736,18 +1736,18 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv)
#ifdef CONFIG_STM32WL5_SPI_DMA
if (priv->rxch && priv->txch)
{
/* Get DMA channels. NOTE: stm32wl5_dmachannel() will always assign
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign
* the DMA channel. If the channel is not available, then
* stm32wl5_dmachannel() will block and wait until the channel becomes
* stm32_dmachannel() will block and wait until the channel becomes
* available.
* WARNING: If you have another device sharing a DMA channel with
* SPI and the code never releases that channel, then the call to
* stm32wl5_dmachannel() will hang forever in this function!
* stm32_dmachannel() will hang forever in this function!
* Don't let your design do that!
*/
priv->rxdma = stm32wl5_dmachannel(priv->rxch);
priv->txdma = stm32wl5_dmachannel(priv->txch);
priv->rxdma = stm32_dmachannel(priv->rxch);
priv->txdma = stm32_dmachannel(priv->txch);
DEBUGASSERT(priv->rxdma && priv->txdma);
spi_modifycr2(priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0);
@ -1769,7 +1769,7 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv)
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_spibus_initialize
* Name: stm32_spibus_initialize
*
* Description:
* Initialize the selected SPI bus
@ -1782,9 +1782,9 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv)
*
****************************************************************************/
struct spi_dev_s *stm32wl5_spibus_initialize(int bus)
struct spi_dev_s *stm32_spibus_initialize(int bus)
{
struct stm32wl5_spidev_s *priv = NULL;
struct stm32_spidev_s *priv = NULL;
irqstate_t flags = enter_critical_section();
@ -1801,9 +1801,9 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus)
{
/* Configure SPI1 pins: SCK, MISO, and MOSI */
stm32wl5_configgpio(GPIO_SPI1_SCK);
stm32wl5_configgpio(GPIO_SPI1_MISO);
stm32wl5_configgpio(GPIO_SPI1_MOSI);
stm32_configgpio(GPIO_SPI1_SCK);
stm32_configgpio(GPIO_SPI1_MISO);
stm32_configgpio(GPIO_SPI1_MOSI);
/* Set up default configuration: Master, 8-bit, etc. */
@ -1826,9 +1826,9 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus)
{
/* Configure SPI2S2 pins: SCK, MISO, and MOSI */
stm32wl5_configgpio(GPIO_SPI2S2_SCK);
stm32wl5_configgpio(GPIO_SPI2S2_MISO);
stm32wl5_configgpio(GPIO_SPI2S2_MOSI);
stm32_configgpio(GPIO_SPI2S2_SCK);
stm32_configgpio(GPIO_SPI2S2_MISO);
stm32_configgpio(GPIO_SPI2S2_MOSI);
/* Set up default configuration: Master, 8-bit, etc. */

40
arch/arm/src/stm32wl5/stm32wl5_spi.h
View file

@ -61,7 +61,7 @@ struct spi_dev_s;
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_spibus_initialize
* Name: stm32_spibus_initialize
*
* Description:
* Initialize the selected SPI bus
@ -74,33 +74,33 @@ struct spi_dev_s;
*
****************************************************************************/
struct spi_dev_s *stm32wl5_spibus_initialize(int bus);
struct spi_dev_s *stm32_spibus_initialize(int bus);
/****************************************************************************
* Name: stm32wl5_spi1/2select and stm32wl5_spi1/2status
* Name: stm32_spi1/2select and stm32_spi1/2status
*
* Description:
* The external functions, stm32wl5_spi1/2select, stm32wl5_spi1/2status,
* and stm32wl5_spi1/2cmddata must be provided by board-specific logic.
* The external functions, stm32_spi1/2select, stm32_spi1/2status,
* and stm32_spi1/2cmddata must be provided by board-specific logic.
* These are implementations of the select, status, and cmddata methods of
* the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including
* stm32wl5_spibus_initialize()) are provided by common STM32 logic.
* stm32_spibus_initialize()) are provided by common STM32 logic.
* To use this common SPI logic on your board:
*
* 1. Provide logic in stm32wl5_boardinitialize() to configure SPI chip
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip
* select pins.
* 2. Provide stm32wl5_spi1/2select() and stm32wl5_spi1/2status()
* 2. Provide stm32_spi1/2select() and stm32_spi1/2status()
* functions in your board-specific logic. These functions will
* perform chip selection and status operations using GPIOs in the way
* your board is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
* then provide stm32wl5_spi1/2cmddata() functions in your board-
* then provide stm32_spi1/2cmddata() functions in your board-
* specific logic. These functions will perform cmd/data selection
* operations using GPIOs in the way your board is configured.
* 4. Add a calls to stm32wl5_spibus_initialize() in your low level
* 4. Add a calls to stm32_spibus_initialize() in your low level
* application initialization logic
* 5. The handle returned by stm32wl5_spibus_initialize() may then be used
* 5. The handle returned by stm32_spibus_initialize() may then be used
* to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
@ -108,21 +108,21 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus);
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI1
void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid,
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid);
int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid,
void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32wl5_spi2s2status(struct spi_dev_s *dev, uint32_t devid);
int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
/****************************************************************************
* Name: stm32wl5_spi1/2s2register
* Name: stm32_spi1/2s2register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based
@ -143,12 +143,12 @@ int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32WL5_SPI1
int stm32wl5_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
int stm32wl5_spi2s2register(struct spi_dev_s *dev,
int stm32_spi2s2register(struct spi_dev_s *dev,
spi_mediachange_t callback,
void *arg);
#endif

12
arch/arm/src/stm32wl5/stm32wl5_start.c
View file

@ -36,7 +36,7 @@
#include "arm_internal.h"
#include "nvic.h"
#include "stm32wl5.h"
#include "stm32.h"
#include "stm32wl5_gpio.h"
#include "stm32wl5_userspace.h"
#include "stm32wl5_start.h"
@ -153,9 +153,9 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32wl5_clockconfig();
stm32wl5_lowsetup();
stm32wl5_gpioinit();
stm32_clockconfig();
stm32_lowsetup();
stm32_gpioinit();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
@ -202,13 +202,13 @@ void __start(void)
*/
#ifdef CONFIG_BUILD_PROTECTED
stm32wl5_userspace();
stm32_userspace();
showprogress('E');
#endif
/* Initialize onboard resources */
stm32wl5_board_initialize();
stm32_board_initialize();
showprogress('F');
/* Then start NuttX */

4
arch/arm/src/stm32wl5/stm32wl5_start.h
View file

@ -32,7 +32,7 @@
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_board_initialize
* Name: stm32_board_initialize
*
* Description:
* All STM32WL5 architectures must provide the following entry point. This
@ -42,6 +42,6 @@
*
****************************************************************************/
void stm32wl5_board_initialize(void);
void stm32_board_initialize(void);
#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_START_H */

460
arch/arm/src/stm32wl5/stm32wl5_tim.c
View file

File diff suppressed because it is too large Load diff

54
arch/arm/src/stm32wl5/stm32wl5_tim.h
View file

@ -72,14 +72,14 @@ extern "C"
/* TIM Device Structure */
struct stm32wl5_tim_dev_s
struct stm32_tim_dev_s
{
struct stm32wl5_tim_ops_s *ops;
struct stm32_tim_ops_s *ops;
};
/* TIM Modes of Operation */
enum stm32wl5_tim_mode_e
enum stm32_tim_mode_e
{
STM32_TIM_MODE_UNUSED = -1,
@ -116,7 +116,7 @@ enum stm32wl5_tim_mode_e
/* TIM Channel Modes */
enum stm32wl5_tim_channel_e
enum stm32_tim_channel_e
{
STM32_TIM_CH_DISABLED = 0x00,
@ -139,36 +139,36 @@ enum stm32wl5_tim_channel_e
/* TIM Operations */
struct stm32wl5_tim_ops_s
struct stm32_tim_ops_s
{
/* Basic Timers */
void (*enable)(struct stm32wl5_tim_dev_s *dev);
void (*disable)(struct stm32wl5_tim_dev_s *dev);
int (*setmode)(struct stm32wl5_tim_dev_s *dev,
enum stm32wl5_tim_mode_e mode);
int (*setclock)(struct stm32wl5_tim_dev_s *dev, uint32_t freq);
uint32_t (*getclock)(struct stm32wl5_tim_dev_s *dev);
void (*setperiod)(struct stm32wl5_tim_dev_s *dev, uint32_t period);
uint32_t (*getperiod)(struct stm32wl5_tim_dev_s *dev);
uint32_t (*getcounter)(struct stm32wl5_tim_dev_s *dev);
void (*enable)(struct stm32_tim_dev_s *dev);
void (*disable)(struct stm32_tim_dev_s *dev);
int (*setmode)(struct stm32_tim_dev_s *dev,
enum stm32_tim_mode_e mode);
int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq);
uint32_t (*getclock)(struct stm32_tim_dev_s *dev);
void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period);
uint32_t (*getperiod)(struct stm32_tim_dev_s *dev);
uint32_t (*getcounter)(struct stm32_tim_dev_s *dev);
/* General and Advanced Timers Adds */
int (*setchannel)(struct stm32wl5_tim_dev_s *dev, uint8_t channel,
enum stm32wl5_tim_channel_e mode);
int (*setcompare)(struct stm32wl5_tim_dev_s *dev, uint8_t channel,
int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel,
enum stm32_tim_channel_e mode);
int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel,
uint32_t compare);
int (*getcapture)(struct stm32wl5_tim_dev_s *dev, uint8_t channel);
int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel);
/* Timer interrupts */
int (*setisr)(struct stm32wl5_tim_dev_s *dev,
int (*setisr)(struct stm32_tim_dev_s *dev,
xcpt_t handler, void *arg, int source);
void (*enableint)(struct stm32wl5_tim_dev_s *dev, int source);
void (*disableint)(struct stm32wl5_tim_dev_s *dev, int source);
void (*ackint)(struct stm32wl5_tim_dev_s *dev, int source);
int (*checkint)(struct stm32wl5_tim_dev_s *dev, int source);
void (*enableint)(struct stm32_tim_dev_s *dev, int source);
void (*disableint)(struct stm32_tim_dev_s *dev, int source);
void (*ackint)(struct stm32_tim_dev_s *dev, int source);
int (*checkint)(struct stm32_tim_dev_s *dev, int source);
};
/****************************************************************************
@ -177,14 +177,14 @@ struct stm32wl5_tim_ops_s
/* Power-up timer and get its structure */
struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer);
struct stm32_tim_dev_s *stm32_tim_init(int timer);
/* Power-down timer, mark it as unused */
int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev);
int stm32_tim_deinit(struct stm32_tim_dev_s *dev);
/****************************************************************************
* Name: stm32wl5_timer_initialize
* Name: stm32_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
@ -202,7 +202,7 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev);
****************************************************************************/
#ifdef CONFIG_TIMER
int stm32wl5_timer_initialize(const char *devpath, int timer);
int stm32_timer_initialize(const char *devpath, int timer);
#endif
#undef EXTERN

110
arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c
View file

@ -73,10 +73,10 @@
* timer_lowerhalf_s structure.
*/
struct stm32wl5_lowerhalf_s
struct stm32_lowerhalf_s
{
const struct timer_ops_s *ops; /* Lower half operations */
struct stm32wl5_tim_dev_s *tim; /* stm32 timer driver */
struct stm32_tim_dev_s *tim; /* stm32 timer driver */
tccb_t callback; /* Current upper half interrupt callback */
void *arg; /* Argument passed to upper half callback */
bool started; /* True: Timer has been started */
@ -89,17 +89,17 @@ struct stm32wl5_lowerhalf_s
/* Interrupt handling *******************************************************/
static int stm32wl5_timer_handler(int irq, void *context, void *arg);
static int stm32_timer_handler(int irq, void *context, void *arg);
/* "Lower half" driver methods **********************************************/
static int stm32wl5_start(struct timer_lowerhalf_s *lower);
static int stm32wl5_stop(struct timer_lowerhalf_s *lower);
static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower,
static int stm32_start(struct timer_lowerhalf_s *lower);
static int stm32_stop(struct timer_lowerhalf_s *lower);
static int stm32_getstatus(struct timer_lowerhalf_s *lower,
struct timer_status_s *status);
static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower,
static int stm32_settimeout(struct timer_lowerhalf_s *lower,
uint32_t timeout);
static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower,
static void stm32_setcallback(struct timer_lowerhalf_s *lower,
tccb_t callback, void *arg);
/****************************************************************************
@ -110,16 +110,16 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower,
static const struct timer_ops_s g_timer_ops =
{
.start = stm32wl5_start,
.stop = stm32wl5_stop,
.getstatus = stm32wl5_getstatus,
.settimeout = stm32wl5_settimeout,
.setcallback = stm32wl5_setcallback,
.start = stm32_start,
.stop = stm32_stop,
.getstatus = stm32_getstatus,
.settimeout = stm32_settimeout,
.setcallback = stm32_setcallback,
.ioctl = NULL,
};
#ifdef CONFIG_STM32WL5_TIM1
static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf =
static struct stm32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM1_RES,
@ -127,7 +127,7 @@ static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM2
static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf =
static struct stm32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM2_RES,
@ -135,7 +135,7 @@ static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM3
static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf =
static struct stm32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM3_RES,
@ -143,7 +143,7 @@ static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM4
static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf =
static struct stm32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM4_RES,
@ -151,7 +151,7 @@ static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM5
static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf =
static struct stm32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM5_RES,
@ -159,7 +159,7 @@ static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM6
static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf =
static struct stm32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM6_RES,
@ -167,7 +167,7 @@ static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM7
static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf =
static struct stm32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM7_RES,
@ -175,7 +175,7 @@ static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM8
static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf =
static struct stm32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM8_RES,
@ -183,7 +183,7 @@ static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM15
static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf =
static struct stm32_lowerhalf_s g_tim15_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM15_RES,
@ -191,7 +191,7 @@ static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM16
static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf =
static struct stm32_lowerhalf_s g_tim16_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM16_RES,
@ -199,7 +199,7 @@ static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf =
#endif
#ifdef CONFIG_STM32WL5_TIM17
static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf =
static struct stm32_lowerhalf_s g_tim17_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32_TIM17_RES,
@ -211,7 +211,7 @@ static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf =
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_timer_handler
* Name: stm32_timer_handler
*
* Description:
* timer interrupt handler
@ -222,10 +222,10 @@ static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf =
*
****************************************************************************/
static int stm32wl5_timer_handler(int irq, void *context, void *arg)
static int stm32_timer_handler(int irq, void *context, void *arg)
{
struct stm32wl5_lowerhalf_s *lower =
(struct stm32wl5_lowerhalf_s *)arg;
struct stm32_lowerhalf_s *lower =
(struct stm32_lowerhalf_s *)arg;
uint32_t next_interval_us = 0;
STM32_TIM_ACKINT(lower->tim, 0);
@ -239,14 +239,14 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg)
}
else
{
stm32wl5_stop((struct timer_lowerhalf_s *)lower);
stm32_stop((struct timer_lowerhalf_s *)lower);
}
return OK;
}
/****************************************************************************
* Name: stm32wl5_start
* Name: stm32_start
*
* Description:
* Start the timer, resetting the time to the current timeout,
@ -260,10 +260,10 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg)
*
****************************************************************************/
static int stm32wl5_start(struct timer_lowerhalf_s *lower)
static int stm32_start(struct timer_lowerhalf_s *lower)
{
struct stm32wl5_lowerhalf_s *priv =
(struct stm32wl5_lowerhalf_s *)lower;
struct stm32_lowerhalf_s *priv =
(struct stm32_lowerhalf_s *)lower;
if (!priv->started)
{
@ -271,7 +271,7 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower)
if (priv->callback != NULL)
{
STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0);
STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0);
STM32_TIM_ENABLEINT(priv->tim, 0);
}
@ -285,7 +285,7 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower)
}
/****************************************************************************
* Name: stm32wl5_stop
* Name: stm32_stop
*
* Description:
* Stop the timer
@ -299,10 +299,10 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower)
*
****************************************************************************/
static int stm32wl5_stop(struct timer_lowerhalf_s *lower)
static int stm32_stop(struct timer_lowerhalf_s *lower)
{
struct stm32wl5_lowerhalf_s *priv =
(struct stm32wl5_lowerhalf_s *)lower;
struct stm32_lowerhalf_s *priv =
(struct stm32_lowerhalf_s *)lower;
if (priv->started)
{
@ -319,7 +319,7 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower)
}
/****************************************************************************
* Name: stm32wl5_getstatus
* Name: stm32_getstatus
*
* Description:
* get timer status
@ -334,11 +334,11 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower)
*
****************************************************************************/
static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower,
static int stm32_getstatus(struct timer_lowerhalf_s *lower,
struct timer_status_s *status)
{
struct stm32wl5_lowerhalf_s *priv =
(struct stm32wl5_lowerhalf_s *)lower;
struct stm32_lowerhalf_s *priv =
(struct stm32_lowerhalf_s *)lower;
uint64_t maxtimeout;
uint32_t timeout;
uint32_t clock;
@ -386,7 +386,7 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower,
}
/****************************************************************************
* Name: stm32wl5_settimeout
* Name: stm32_settimeout
*
* Description:
* Set a new timeout value (and reset the timer)
@ -401,11 +401,11 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower,
*
****************************************************************************/
static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower,
static int stm32_settimeout(struct timer_lowerhalf_s *lower,
uint32_t timeout)
{
struct stm32wl5_lowerhalf_s *priv =
(struct stm32wl5_lowerhalf_s *)lower;
struct stm32_lowerhalf_s *priv =
(struct stm32_lowerhalf_s *)lower;
uint64_t maxtimeout;
if (priv->started)
@ -430,7 +430,7 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower,
}
/****************************************************************************
* Name: stm32wl5_sethandler
* Name: stm32_sethandler
*
* Description:
* Call this user provided timeout handler.
@ -449,11 +449,11 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower,
*
****************************************************************************/
static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower,
static void stm32_setcallback(struct timer_lowerhalf_s *lower,
tccb_t callback, void *arg)
{
struct stm32wl5_lowerhalf_s *priv =
(struct stm32wl5_lowerhalf_s *)lower;
struct stm32_lowerhalf_s *priv =
(struct stm32_lowerhalf_s *)lower;
irqstate_t flags = enter_critical_section();
/* Save the new callback */
@ -463,7 +463,7 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower,
if (callback != NULL && priv->started)
{
STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0);
STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0);
STM32_TIM_ENABLEINT(priv->tim, 0);
}
else
@ -480,7 +480,7 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower,
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_timer_initialize
* Name: stm32_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
@ -497,9 +497,9 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower,
*
****************************************************************************/
int stm32wl5_timer_initialize(const char *devpath, int timer)
int stm32_timer_initialize(const char *devpath, int timer)
{
struct stm32wl5_lowerhalf_s *lower;
struct stm32_lowerhalf_s *lower;
switch (timer)
{
@ -576,7 +576,7 @@ int stm32wl5_timer_initialize(const char *devpath, int timer)
lower->started = false;
lower->callback = NULL;
lower->tim = stm32wl5_tim_init(timer);
lower->tim = stm32_tim_init(timer);
if (lower->tim == NULL)
{

8
arch/arm/src/stm32wl5/stm32wl5_timerisr.c
View file

@ -38,7 +38,7 @@
#include "arm_internal.h"
#include "chip.h"
#include "stm32wl5.h"
#include "stm32.h"
/****************************************************************************
* Pre-processor Definitions
@ -80,7 +80,7 @@
****************************************************************************/
/****************************************************************************
* Function: stm32wl5_timerisr
* Function: stm32_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
@ -88,7 +88,7 @@
*
****************************************************************************/
static int stm32wl5_timerisr(int irq, uint32_t *regs, void *arg)
static int stm32_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
@ -138,7 +138,7 @@ void up_timer_initialize(void)
/* Attach the timer interrupt vector */
(void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL);
(void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL);
/* Enable SysTick interrupts */

4
arch/arm/src/stm32wl5/stm32wl5_uart.h
View file

@ -202,7 +202,7 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_serial_dma_poll
* Name: stm32_serial_dma_poll
*
* Description:
* Must be called periodically if any STM32 UART is configured for DMA.
@ -215,7 +215,7 @@ extern "C"
****************************************************************************/
#ifdef SERIAL_HAVE_DMA
void stm32wl5_serial_dma_poll(void);
void stm32_serial_dma_poll(void);
#endif
#undef EXTERN

2
arch/arm/src/stm32wl5/stm32wl5_uid.c
View file

@ -50,7 +50,7 @@
* Public Functions
****************************************************************************/
void stm32wl5_get_uniqueid(uint8_t uniqueid[12])
void stm32_get_uniqueid(uint8_t uniqueid[12])
{
int i;

2
arch/arm/src/stm32wl5/stm32wl5_uid.h
View file

@ -48,6 +48,6 @@
* Public Function Prototypes
****************************************************************************/
void stm32wl5_get_uniqueid(uint8_t uniqueid[12]);
void stm32_get_uniqueid(uint8_t uniqueid[12]);
#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_UID_H */

6
arch/arm/src/stm32wl5/stm32wl5_userspace.c
View file

@ -41,7 +41,7 @@
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_userspace
* Name: stm32_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
@ -51,7 +51,7 @@
*
****************************************************************************/
void stm32wl5_userspace(void)
void stm32_userspace(void)
{
uint8_t *src;
uint8_t *dest;
@ -87,7 +87,7 @@ void stm32wl5_userspace(void)
/* Configure the MPU to permit user-space access to its FLASH and RAM */
stm32wl5_mpuinitialize();
stm32_mpuinitialize();
}
#endif /* CONFIG_BUILD_PROTECTED */

4
arch/arm/src/stm32wl5/stm32wl5_userspace.h
View file

@ -34,7 +34,7 @@
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_userspace
* Name: stm32_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
@ -45,7 +45,7 @@
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void stm32wl5_userspace(void);
void stm32_userspace(void);
#endif
#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_USERSPACE_H */

2
arch/arm/src/stm32wl5/stm32wl5_waste.c
View file

@ -38,7 +38,7 @@ uint32_t idle_wastecounter = 0;
* Public Functions
****************************************************************************/
void stm32wl5_waste(void)
void stm32_waste(void)
{
idle_wastecounter++;
}

4
arch/arm/src/stm32wl5/stm32wl5_waste.h
View file

@ -46,7 +46,7 @@ extern "C"
/* Waste CPU Time
*
* stm32wl5_waste() is the logic that will be executed when portions of
* stm32_waste() is the logic that will be executed when portions of
* kernel or user-app is polling some register or similar, waiting for
* desired status. This time is wasted away. This function offers a measure
* of badly written piece of software or some undesired behavior. At
@ -54,7 +54,7 @@ extern "C"
* be used for other purposes (yet).
*/
void stm32wl5_waste(void);
void stm32_waste(void);
#undef EXTERN
#if defined(__cplusplus)

4
boards/arm/stm32wl5/nucleo-wl55jc/include/board.h
View file

@ -231,7 +231,7 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_board_initialize
* Name: stm32_board_initialize
*
* Description:
* All STM32WL5 architectures must provide the following entry point.
@ -241,7 +241,7 @@ extern "C"
*
****************************************************************************/
void stm32wl5_board_initialize(void);
void stm32_board_initialize(void);
#undef EXTERN
#if defined(__cplusplus)

10
boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h
View file

@ -31,7 +31,7 @@
#include <nuttx/compiler.h>
#include <stdint.h>
#include <stm32wl5.h>
#include <stm32.h>
/****************************************************************************
* Pre-processor Definitions
@ -148,24 +148,24 @@
void board_leds_initialize(void);
/****************************************************************************
* Name: stm32wl5_flash_init
* Name: stm32_flash_init
*
* Description:
* Initialize on-board FLASH partition table
*
****************************************************************************/
int stm32wl5_flash_init(void);
int stm32_flash_init(void);
/****************************************************************************
* Name: stm32wl5_spidev_initialize
* Name: stm32_spidev_initialize
*
* Description:
* Initialize SPIs
*
****************************************************************************/
void stm32wl5_spidev_initialize(void);
void stm32_spidev_initialize(void);
/****************************************************************************
* Name: ipcc_init

16
boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c
View file

@ -47,7 +47,7 @@
#include <nuttx/video/fb.h>
#endif
#include <stm32wl5.h>
#include <stm32.h>
#include <stm32wl5_uart.h>
#include <stm32wl5_pwr.h>
@ -73,7 +73,7 @@
****************************************************************************/
/****************************************************************************
* Name: stm32wl5_board_initialize
* Name: stm32_board_initialize
*
* Description:
* All STM32WL5 architectures must provide the following entry point.
@ -83,7 +83,7 @@
*
****************************************************************************/
void stm32wl5_board_initialize(void)
void stm32_board_initialize(void)
{
/* Configure on-board LEDs, which are always enabled */
@ -109,7 +109,7 @@ void board_late_initialize(void)
int ret;
#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2)
stm32wl5_spidev_initialize();
stm32_spidev_initialize();
#endif
#if defined(CONFIG_LCD_SSD1680) && !defined(CONFIG_VIDEO_FB)
@ -161,10 +161,10 @@ void board_late_initialize(void)
#if defined(CONFIG_ARCH_BOARD_FLASH_MOUNT)
/* Register partition table for on-board FLASH memory */
ret = stm32wl5_flash_init();
ret = stm32_flash_init();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: stm32wl5_flash_init() failed: %d\n", ret);
syslog(LOG_ERR, "ERROR: stm32_flash_init() failed: %d\n", ret);
}
#endif
@ -181,7 +181,7 @@ void board_late_initialize(void)
#if defined(CONFIG_ARCH_BOARD_ENABLE_CPU2)
/* Start second CPU */
stm32wl5_pwr_boot_c2();
stm32_pwr_boot_c2();
#endif
UNUSED(ret);
@ -203,7 +203,7 @@ int board_uniqueid(uint8_t *uniqueid)
return -EINVAL;
}
stm32wl5_get_uniqueid(uniqueid);
stm32_get_uniqueid(uniqueid);
return OK;
}
#endif

18
boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c
View file

@ -57,10 +57,10 @@ uint32_t board_button_initialize(void)
* also configured for the pin.
*/
stm32wl5_configgpio(GPIO_BUTTON1);
stm32wl5_configgpio(GPIO_BUTTON2);
stm32_configgpio(GPIO_BUTTON1);
stm32_configgpio(GPIO_BUTTON2);
#ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ
stm32wl5_configgpio(GPIO_BUTTON3);
stm32_configgpio(GPIO_BUTTON3);
return 3; /* number of buttons */
#else
return 2; /* number of buttons */
@ -81,18 +81,18 @@ uint32_t board_buttons(void)
state = 0;
if (stm32wl5_gpioread(GPIO_BUTTON1) == 0)
if (stm32_gpioread(GPIO_BUTTON1) == 0)
{
state |= BUTTON1_BIT;
}
if (stm32wl5_gpioread(GPIO_BUTTON2) == 0)
if (stm32_gpioread(GPIO_BUTTON2) == 0)
{
state |= BUTTON2_BIT;
}
#ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ
if (stm32wl5_gpioread(GPIO_BUTTON3) == 0)
if (stm32_gpioread(GPIO_BUTTON3) == 0)
{
state |= BUTTON3_BIT;
}
@ -130,20 +130,20 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg)
if (id == BOARD_BUTTON1)
{
ret = stm32wl5_gpiosetevent(GPIO_BUTTON1, true, true, false,
ret = stm32_gpiosetevent(GPIO_BUTTON1, true, true, false,
irqhandler, arg);
}
if (id == BOARD_BUTTON2)
{
ret = stm32wl5_gpiosetevent(GPIO_BUTTON2, true, true, false,
ret = stm32_gpiosetevent(GPIO_BUTTON2, true, true, false,
irqhandler, arg);
}
#ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ
if (id == BOARD_BUTTON3)
{
ret = stm32wl5_gpiosetevent(GPIO_BUTTON3, true, true, false,
ret = stm32_gpiosetevent(GPIO_BUTTON3, true, true, false,
irqhandler, arg);
}
#endif

2
boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c
View file

@ -173,7 +173,7 @@ static const struct part_table part_table[] =
* Public Functions
****************************************************************************/
int stm32wl5_flash_init(void)
int stm32_flash_init(void)
{
struct mtd_dev_s *mtd;
struct mtd_dev_s *mtd_part;

4
boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c
View file

@ -116,9 +116,9 @@ static int init_ipcc(int chan, size_t rxbuflen, size_t txbuflen)
struct ipcc_lower_s *ipcc;
int ret;
if ((ipcc = stm32wl5_ipcc_init(chan)) == NULL)
if ((ipcc = stm32_ipcc_init(chan)) == NULL)
{
syslog(LOG_ERR, "ERROR: stm32wl5_ipcc_init(%d) failed\n", chan);
syslog(LOG_ERR, "ERROR: stm32_ipcc_init(%d) failed\n", chan);
return -1;
}

20
boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c
View file

@ -35,7 +35,7 @@
#include "chip.h"
#include "arm_internal.h"
#include "stm32wl5.h"
#include "stm32.h"
#include "nucleo-wl55jc.h"
#include <stdio.h>
@ -64,17 +64,17 @@ static void led_state(int state, unsigned int leds)
{
if (leds & BOARD_LED_BLUE_BIT)
{
stm32wl5_gpiowrite(GPIO_LED_BLUE, state);
stm32_gpiowrite(GPIO_LED_BLUE, state);
}
if (leds & BOARD_LED_RED_BIT)
{
stm32wl5_gpiowrite(GPIO_LED_RED, state);
stm32_gpiowrite(GPIO_LED_RED, state);
}
if (leds & BOARD_LED_GREEN_BIT)
{
stm32wl5_gpiowrite(GPIO_LED_GREEN, state);
stm32_gpiowrite(GPIO_LED_GREEN, state);
}
}
@ -93,12 +93,12 @@ static int button3_led(int irq, void *context, void *arg)
(void)arg;
int state;
state = stm32wl5_gpioread(GPIO_LED_RED);
state = stm32_gpioread(GPIO_LED_RED);
/* toggle state */
state = !state;
stm32wl5_gpiowrite(GPIO_LED_RED, state);
stm32_gpiowrite(GPIO_LED_RED, state);
return 0;
}
#endif
@ -113,9 +113,9 @@ static int button3_led(int irq, void *context, void *arg)
void board_leds_initialize(void)
{
stm32wl5_configgpio(GPIO_LED_BLUE);
stm32wl5_configgpio(GPIO_LED_RED);
stm32wl5_configgpio(GPIO_LED_GREEN);
stm32_configgpio(GPIO_LED_BLUE);
stm32_configgpio(GPIO_LED_RED);
stm32_configgpio(GPIO_LED_GREEN);
}
/****************************************************************************
@ -222,7 +222,7 @@ uint32_t board_userled_initialize(void)
#ifdef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ
/* Configure B3 button to fire an interrupt on falling edge (on press) */
stm32wl5_gpiosetevent(GPIO_BUTTON3, false, true, false, button3_led, NULL);
stm32_gpiosetevent(GPIO_BUTTON3, false, true, false, button3_led, NULL);
#endif
return BOARD_NLEDS;

97
boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c
View file

@ -37,7 +37,7 @@
#include "arm_internal.h"
#include "chip.h"
#include "stm32wl5.h"
#include "stm32.h"
#include "nucleo-wl55jc.h"
#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2)
@ -68,12 +68,12 @@ struct spi_dev_s *g_spi2;
*
****************************************************************************/
void weak_function stm32wl5_spidev_initialize(void)
void weak_function stm32_spidev_initialize(void)
{
#ifdef CONFIG_STM32WL5_SPI1
/* Configure SPI-based devices */
g_spi1 = stm32wl5_spibus_initialize(1);
g_spi1 = stm32_spibus_initialize(1);
if (!g_spi1)
{
spierr("ERROR: FAILED to initialize SPI port 1\n");
@ -82,15 +82,15 @@ void weak_function stm32wl5_spidev_initialize(void)
#ifdef CONFIG_LCD_SSD1680
spiinfo("Preparing additional lines for SSD1680 device\n");
stm32wl5_configgpio(GPIO_SSD1680_CS); /* SSD1680 chip select */
stm32wl5_configgpio(GPIO_SSD1680_CMD); /* SSD1680 data/!command */
stm32wl5_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */
stm32wl5_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */
stm32_configgpio(GPIO_SSD1680_CS); /* SSD1680 chip select */
stm32_configgpio(GPIO_SSD1680_CMD); /* SSD1680 data/!command */
stm32_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */
stm32_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */
#endif
#endif
#ifdef CONFIG_STM32_SPI2S2
#ifdef CONFIG_STM32WL5_SPI2S2
/* Configure SPI-based devices */
g_spi2 = stm32_spibus_initialize(2);
@ -105,7 +105,7 @@ void weak_function stm32wl5_spidev_initialize(void)
* must be provided by board-specific logic. They are implementations of
* the select and status methods of the SPI interface defined by struct
* spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including
* stm32wl5_spibus_initialize()) are provided by common STM32 logic.
* stm32_spibus_initialize()) are provided by common STM32 logic.
* To use this common SPI logic on your board:
*
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
@ -114,9 +114,9 @@ void weak_function stm32wl5_spidev_initialize(void)
* in your board-specific logic. These functions will perform chip
* selection and status operations using GPIOs in the way your board is
* configured.
* 3. Add a calls to stm32wl5_spibus_initialize() in your low level
* 3. Add a calls to stm32_spibus_initialize() in your low level
* application initialization logic
* 4. The handle returned by stm32wl5_spibus_initialize() may then be used
* 4. The handle returned by stm32_spibus_initialize() may then be used
* to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
@ -124,7 +124,7 @@ void weak_function stm32wl5_spidev_initialize(void)
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI1
void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid,
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" :
@ -133,26 +133,26 @@ void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid,
#if defined(CONFIG_LCD_SSD1680)
if (devid == SPIDEV_DISPLAY(0))
{
stm32wl5_gpiowrite(GPIO_SSD1680_CS, !selected);
stm32_gpiowrite(GPIO_SSD1680_CS, !selected);
}
#endif
#if defined(CONFIG_CAN_MCP2515)
if (devid == SPIDEV_CANBUS(0))
{
stm32wl5_gpiowrite(GPIO_MCP2515_CS, !selected);
stm32_gpiowrite(GPIO_MCP2515_CS, !selected);
}
#endif
#ifdef HAVE_MMCSD
if (devid == SPIDEV_MMCSD(0))
{
stm32wl5_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected);
stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected);
}
#endif
}
uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid)
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid)
{
#if defined(CONFIG_LCD_SSD1680)
if (devid == SPIDEV_DISPLAY(0))
@ -164,12 +164,12 @@ uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid)
return 0;
}
int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
#if defined(CONFIG_LCD_SSD1680)
if (devid == SPIDEV_DISPLAY(0))
{
stm32wl5_gpiowrite(GPIO_SSD1680_CMD, !cmd);
stm32_gpiowrite(GPIO_SSD1680_CMD, !cmd);
}
#endif
@ -179,76 +179,23 @@ int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid,
void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" :
"de-assert");
}
uint8_t stm32wl5_spi2s2status(struct spi_dev_s *dev, uint32_t devid)
uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return OK;
}
#endif
/****************************************************************************
* Name: stm32_spi1cmddata
*
* Description:
* Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
* or command (false). This function must be provided by platform-specific
* logic. This is an implementation of the cmddata method of the SPI
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
*
* Input Parameters:
*
* spi - SPI device that controls the bus the device that requires the CMD/
* DATA selection.
* devid - If there are multiple devices on the bus, this selects which one
* to select cmd or data. NOTE: This design restricts, for example,
* one one SPI display per SPI bus.
* cmd - true: select command; false: select data
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_STM32_SPI1
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
#if defined(CONFIG_LCD_SSD16800)
if (devid == SPIDEV_DISPLAY(0))
{
stm32_gpiowrite(GPIO_SSD1680_CMD, !cmd);
}
#endif
return OK;
}
#endif
#ifdef CONFIG_STM32_SPI2
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return OK;
}
#endif
#ifdef CONFIG_STM32_SPI3
int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return OK;
}
#endif
#endif /* CONFIG_SPI_CMDDATA */
#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */
#endif /* CONFIG_STM32WL5_SPI1 || CONFIG_STM32WL5_SPI2S2 */

14
boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c
View file

@ -33,7 +33,7 @@
#include <nuttx/lcd/ssd1680.h>
#include <nuttx/spi/spi.h>
#include "stm32wl5.h"
#include "stm32.h"
#include "nucleo-wl55jc.h"
#include "stm32wl5_gpio.h"
#include "stm32wl5_ssd1680.h"
@ -59,7 +59,7 @@ static bool ssd1680_set_vcc(bool state)
#if defined(CONFIG_SSD1680_GPIO_PIN_RST)
static bool ssd1680_set_rst(bool state)
{
stm32wl5_gpiowrite(GPIO_SSD1680_RST, state);
stm32_gpiowrite(GPIO_SSD1680_RST, state);
return true;
}
#endif
@ -67,7 +67,7 @@ static bool ssd1680_set_rst(bool state)
#if defined(CONFIG_SSD1680_GPIO_PIN_BUSY)
static bool ssd1680_check_busy(void)
{
return stm32wl5_gpioread(GPIO_SSD1680_BUSY);
return stm32_gpioread(GPIO_SSD1680_BUSY);
}
#endif
@ -106,20 +106,20 @@ int board_lcd_initialize(void)
/* Initialize additional I/O for e-ink display */
#if defined(GPIO_SSD1680_PWR)
stm32wl5_configgpio(GPIO_SSD1680_PWR); /* SSD1680 pwr */
stm32_configgpio(GPIO_SSD1680_PWR); /* SSD1680 pwr */
lcdinfo("SSD1680 power line is available (0x%08x)\n", GPIO_SSD1680_PWR);
#else
lcdinfo("PWR control line is disabled\n");
#endif
#if defined(GPIO_SSD1680_RST)
stm32wl5_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */
stm32_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */
lcdinfo("SSD1680 reset line is available (0x%08x)\n", GPIO_SSD1680_RST);
#elif
lcdinfo("SSD1680 RESET line is disabled\n");
#endif
#if defined(GPIO_SSD1680_BUSY)
stm32wl5_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */
stm32_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */
lcdinfo("SSD1680 Line for reading busy state is available (0x%08x)\n",
GPIO_SSD1680_BUSY);
#elif
@ -128,7 +128,7 @@ int board_lcd_initialize(void)
/* Initialize SPI */
spi = stm32wl5_spibus_initialize(CONFIG_SSD1680_SPI_BUS);
spi = stm32_spibus_initialize(CONFIG_SSD1680_SPI_BUS);
if (!spi)
{
lcderr("ERROR: Failed to initialize SPI port %d\n",