From 7f2ae8ffeca8c718a5a6dc3bae25e463afc7ab91 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 23 Sep 2026 09:31:25 +0200 Subject: [PATCH] arm/stm32h7: add STM32H735 support add STM32H735 support Assisted-by: Codex:GPT-6 Signed-off-by: raiden00pl --- Documentation/platforms/arm/stm32h7/index.rst | 2 +- arch/arm/include/stm32h7/chip.h | 15 +++ arch/arm/src/common/stm32/Kconfig.have | 3 + arch/arm/src/stm32h7/Kconfig | 95 +++++++++++++++++-- .../src/stm32h7/hardware/stm32h7x3xx_gpio.h | 2 +- .../stm32h7/hardware/stm32h7x3xx_memorymap.h | 3 + .../src/stm32h7/hardware/stm32h7x3xx_pinmap.h | 8 ++ .../src/stm32h7/hardware/stm32h7x3xx_rcc.h | 3 + arch/arm/src/stm32h7/stm32_gpio.c | 2 +- arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 2 +- 10 files changed, 125 insertions(+), 10 deletions(-) diff --git a/Documentation/platforms/arm/stm32h7/index.rst b/Documentation/platforms/arm/stm32h7/index.rst index e8e0e06a540..7bf075612fe 100644 --- a/Documentation/platforms/arm/stm32h7/index.rst +++ b/Documentation/platforms/arm/stm32h7/index.rst @@ -27,7 +27,7 @@ STM32H743 Yes STM32H753 Yes STM32H742 No STM32H725 No -STM32H735 No +STM32H735 Yes STM32H723 No STM32H733 No STM32H7R3 Yes diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index b25bfe466a4..dd5712438c2 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -58,6 +58,11 @@ #if defined(CONFIG_STM32_STM32H7RSXX) || \ defined (CONFIG_ARCH_CHIP_STM32H723VG) || \ defined (CONFIG_ARCH_CHIP_STM32H723ZG) || \ + defined (CONFIG_ARCH_CHIP_STM32H735AG) || \ + defined (CONFIG_ARCH_CHIP_STM32H735IG) || \ + defined (CONFIG_ARCH_CHIP_STM32H735RG) || \ + defined (CONFIG_ARCH_CHIP_STM32H735VG) || \ + defined (CONFIG_ARCH_CHIP_STM32H735ZG) || \ defined (CONFIG_ARCH_CHIP_STM32H743AG) || \ defined (CONFIG_ARCH_CHIP_STM32H743AI) || \ defined (CONFIG_ARCH_CHIP_STM32H743BG) || \ @@ -153,11 +158,21 @@ /* Peripherals */ # if defined(CONFIG_STM32H7_IO_CONFIG_A) +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ +# else # define STM32_NGPIO (10) /* GPIOA-GPIOJ */ +# endif # elif defined(CONFIG_STM32H7_IO_CONFIG_B) # define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_I) +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX +# define STM32_NGPIO (11) /* GPIOA-H, GPIOJ-K */ +# else # define STM32_NGPIO (9) /* GPIOA-GPIOI */ +# endif +# elif defined(CONFIG_STM32H7_IO_CONFIG_R) +# define STM32_NGPIO (8) /* GPIOA-D, GPIOH */ # elif defined(CONFIG_STM32H7_IO_CONFIG_V) # define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ # elif defined(CONFIG_STM32H7_IO_CONFIG_X) diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index cb7fa87d3fa..a873604e66e 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -425,6 +425,9 @@ config STM32_HAVE_GPIOF config STM32_HAVE_GPIOG bool +config STM32_HAVE_GPIOI + bool + # HRTIM capabilities config STM32_HAVE_HRTIM1 diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 3709e48cb98..5313b48b952 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -25,7 +25,7 @@ config STM32_H7_LEGACY select STM32_HAVE_TIM8 select STM32_HAVE_I2C4 select STM32_HAVE_SYSCFG - select STM32_HAVE_USART6 + select STM32_HAVE_USART6 if !STM32H7_IO_CONFIG_R select STM32_HAVE_HSEM select STM32_HAVE_DAC1 @@ -66,12 +66,12 @@ config STM32_H7_PERIPHERALS select STM32_HAVE_SPI1 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 + select STM32_HAVE_SPI4 if !STM32H7_IO_CONFIG_R select STM32_HAVE_SPI6 select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_UART7 - select STM32_HAVE_UART8 + select STM32_HAVE_UART8 if !STM32H7_IO_CONFIG_R select STM32_HAVE_USART1 select STM32_HAVE_USART2 select STM32_HAVE_USART3 @@ -273,6 +273,81 @@ config ARCH_CHIP_STM32H723ZG STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM, LQFP144 +config ARCH_CHIP_STM32H735AG + bool "STM32H735AG" + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_A + select STM32_HAVE_SMPS + select STM32_HAVE_FDCAN3 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 + select STM32_HAVE_HASH + ---help--- + STM32 H7 Cortex-M7, 1024 KiB FLASH, 564 KiB SRAM, + with cryptographic and hash accelerators, UFBGA169. + +config ARCH_CHIP_STM32H735IG + bool "STM32H735IG" + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_I + select STM32_HAVE_SMPS + select STM32_HAVE_FDCAN3 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 + select STM32_HAVE_HASH + ---help--- + STM32 H7 Cortex-M7, 1024 KiB FLASH, 564 KiB SRAM, + with cryptographic and hash accelerators, LQFP176 or TFBGA176+25. + +config ARCH_CHIP_STM32H735RG + bool "STM32H735RG" + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_R + select STM32_HAVE_SMPS + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 + select STM32_HAVE_HASH + ---help--- + STM32 H7 Cortex-M7, 1024 KiB FLASH, 564 KiB SRAM, + with cryptographic and hash accelerators, VFQFPN68. + +config ARCH_CHIP_STM32H735VG + bool "STM32H735VG" + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_V + select STM32_HAVE_SMPS + select STM32_HAVE_FDCAN3 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 + select STM32_HAVE_HASH + ---help--- + STM32 H7 Cortex-M7, 1024 KiB FLASH, 564 KiB SRAM, + with cryptographic and hash accelerators, + LQFP100, TFBGA100 or WLCSP115. + +config ARCH_CHIP_STM32H735ZG + bool "STM32H735ZG" + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G + select STM32H7_IO_CONFIG_Z + select STM32_HAVE_SMPS + select STM32_HAVE_FDCAN3 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 + select STM32_HAVE_HASH + ---help--- + STM32 H7 Cortex-M7, 1024 KiB FLASH, 564 KiB SRAM, + with cryptographic and hash accelerators, LQFP144. + config ARCH_CHIP_STM32H743AG bool "STM32H743AG" select STM32_STM32H7X3XX @@ -739,6 +814,7 @@ config STM32_STM32H7X0XX select STM32_HAVE_LTDC select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOI select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V config STM32_STM32H7RSXX @@ -761,9 +837,10 @@ config STM32_STM32H7X3XX select STM32_HAVE_FDCAN1 select STM32_HAVE_FDCAN2 select STM32_HAVE_LTDC - select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V && !STM32H7_IO_CONFIG_R + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V && !STM32H7_IO_CONFIG_R + select STM32_HAVE_GPIOI if !STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V && !STM32H7_IO_CONFIG_R config STM32_STM32H7B3XX bool @@ -771,6 +848,7 @@ config STM32_STM32H7B3XX select STM32_H7_LEGACY select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOI select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V config STM32_STM32H7X5XX @@ -783,6 +861,7 @@ config STM32_STM32H7X5XX select STM32_HAVE_LTDC select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOI select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V select STM32_HAVE_SMPS @@ -794,12 +873,16 @@ config STM32_STM32H7X7XX select STM32_HAVE_LTDC select STM32_HAVE_GPIOF select STM32_HAVE_GPIOG + select STM32_HAVE_GPIOI select STM32_HAVE_SPI5 # The reduced SRAM configuration STM32H72X and STM32H73X config STM32_STM32H72XXX_OR_STM32H73XXX bool default n + select STM32_HAVE_OCTOSPIM + select STM32_HAVE_OCTOSPI1 + select STM32_HAVE_OCTOSPI2 config STM32_FLASH_CR_PSIZE int "Flash program size width" diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h index a8e0a3d5a5f..591f47b4cb1 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h @@ -161,7 +161,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#ifdef STM32_GPIOI_BASE +#ifdef CONFIG_STM32_HAVE_GPIOI # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h index 1e3737d13e3..792d141d603 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h @@ -195,9 +195,12 @@ #define STM32_NANDC_BASE 0x52004000 /* NAND Flash controller */ #define STM32_SDRAMC_BASE 0x52004000 /* SDRAM controller */ #define STM32_QUADSPI_BASE 0x52005000 /* 0x52005000-0x52005fff QUADSPI control */ +#define STM32_OCTOSPI1_BASE 0x52005000 /* OCTOSPI1 control */ #define STM32_DLYBQUADSPI_BASE 0x52006000 /* 0x52006000-0x52006fff QUADSPI Delay Block */ #define STM32_SDMMC1_BASE 0x52007000 /* 0x52007000-0x52007fff SDMMC1 */ #define STM32_DLYBSDMMC1_BASE 0x52008000 /* 0x52008000-0x52008fff Delay Block SDMMC1 */ +#define STM32_OCTOSPI2_BASE 0x5200a000 /* 0x5200a000-0x5200afff OCTOSPI2 control */ +#define STM32_OCTOSPIM_BASE 0x5200b400 /* 0x5200b400-0x5200b7ff OCTOSPI I/O manager */ /* APB4 Base Addresses ******************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h index 3974629f516..7374d494b7f 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h @@ -684,6 +684,14 @@ #define GPIO_LTDC_VSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN13) #define GPIO_LTDC_VSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9) +/* Additional STM32H72x/73x LTDC pins */ + +#ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX +# define GPIO_LTDC_B1_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) +# define GPIO_LTDC_R0_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) +# define GPIO_LTDC_R6_5 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) +#endif + /* Low Power Timer */ #define GPIO_LPTIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h index 308dc30f621..65a17a068f2 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h @@ -693,6 +693,7 @@ #define RCC_AHB3RSTR_FMCRST (1 << 12) /* RCC AHB3RSTR: FMCRST */ #define RCC_AHB3RSTR_QSPIRST (1 << 14) /* RCC AHB3RSTR: QSPIRST */ #define RCC_AHB3RSTR_SDMMC1RST (1 << 16) /* RCC AHB3RSTR: SDMMC1RST */ +#define RCC_AHB3RSTR_OSPI2RST (1 << 19) /* RCC AHB3RSTR: OSPI2RST */ #define RCC_AHB3RSTR_CPURST (1 << 31) /* RCC AHB3RSTR: CPURST */ /* AHB1 peripheral reset register */ @@ -865,6 +866,8 @@ #define RCC_AHB3ENR_FMCEN (1 << 12) /* RCC AHB3ENR: FMCEN */ #define RCC_AHB3ENR_QSPIEN (1 << 14) /* RCC AHB3ENR: QSPIEN */ #define RCC_AHB3ENR_SDMMC1EN (1 << 16) /* RCC AHB3ENR: SDMMC1EN */ +#define RCC_AHB3ENR_OSPI2EN (1 << 19) /* RCC AHB3ENR: OSPI2EN */ +#define RCC_AHB3ENR_IOMNGREN (1 << 21) /* RCC AHB3ENR: IOMNGREN */ /* AHB1 Peripheral Clock enable register */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index ddf5ad8b616..0e448b85ae0 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -99,7 +99,7 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; # define GPIOG_BASE 0 #endif -#ifdef STM32_GPIOI_BASE +#ifdef CONFIG_STM32_HAVE_GPIOI # define GPIOI_BASE STM32_GPIOI_BASE #else # define GPIOI_BASE 0 diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index 13737b7b0b7..9e3c4afaa64 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -437,7 +437,7 @@ static inline void rcc_enableahb4(void) #if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32_NGPIO > 8 +#if (STM32_NGPIO > 8) && (defined(CONFIG_STM32_HAVE_GPIOI)) | RCC_AHB4ENR_GPIOIEN #endif #if STM32_NGPIO > 9