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boards/mps2-an521: Correct the swapped UART0 TX and RX interrupts.

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The SSE-200 subsystem the AN521 image implements lists the UART interrupts
receive first: UART0 RX is external interrupt 32 and UART0 TX is 33, which
in NuttX numbering are 48 and 49.  The configuration had those two the wrong
way round, so the TX interrupt was dispatched to uart_cmsdk_rx_interrupt.

That handler clears only UART_INTSTATUS_RX, so the asserted TX status bit
survived the acknowledgement and the interrupt re-fired immediately.  The
board live-locked in the interrupt handler as soon as the console emitted its
first character: the NSH banner appeared, and nothing ran afterwards, console
input included.

Note that the overflow interrupt already sits at 63, external 47, which is
where the SSE-200 map puts it only if the pair below it is receive first --
the two corrected values are the ones consistent with it.  mps2-an500 already
follows the same order with RX at 16 and TX at 17.

Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
This commit is contained in:
Marco Casaroli 2026-07-25 21:03:13 +02:00 • committed by Xiang Xiao
parent 57d384f466
commit 7d319ab389
1 changed files with 2 additions and 2 deletions
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4
boards/arm/mps/mps2-an521/configs/nsh/defconfig
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@ -23,9 +23,9 @@ CONFIG_CMSDK_UART0=y
CONFIG_CMSDK_UART0_BASE=0x50200000
CONFIG_CMSDK_UART0_CLOCK=25000000
CONFIG_CMSDK_UART0_OV_IRQ=63
CONFIG_CMSDK_UART0_RX_IRQ=49
CONFIG_CMSDK_UART0_RX_IRQ=48
CONFIG_CMSDK_UART0_SERIAL_CONSOLE=y
CONFIG_CMSDK_UART0_TX_IRQ=48
CONFIG_CMSDK_UART0_TX_IRQ=49
CONFIG_CMSDK_UART=y
CONFIG_DEBUG_ASSERTIONS=y
CONFIG_DEBUG_FEATURES=y