arch/arm/rp23xx: Erase and program the flash in small steps.

The flash MTD driver disabled interrupts for a whole request.  A
multi-block erase or a large write kept them off for seconds.

Erase one 64K block (or one 4K sector where the range is not block
aligned) and program one 256 byte page per step.  Enable interrupts and
release the other core between steps.  A single block erase is still
long, but that is the limit of the flash.

Also, on SMP:

- Do not send the pause call to the CPU that does the operation.
  nxsched_smp_call_single_async() runs it at once on that CPU.
- Keep the isolation data in a static, not on the stack.  The other
  CPU spins on it while the flash is busy.

Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>

Documentation/platforms/arm/rp23xx/index.rst

@@ -326,8 +326,10 @@ offset fails at boot instead of corrupting the running firmware.
 
 Erase and program go through the bootrom flash routines.  Because those
 operations stall instruction fetch from the same flash, the driver runs them
-from SRAM with interrupts disabled and, on SMP builds, the other core parked;
-expect interrupt latency to suffer for the duration of a write.  Afterwards the
+from SRAM with interrupts disabled and, on SMP builds, the other core parked.
+It does so for one 64K block erase or one 256 byte page program at a time, and
+enables interrupts between them; expect interrupt latency to suffer for that
+long (a block erase can take hundreds of milliseconds).  Afterwards the
 QSPI interface is put back into execute-in-place mode -- by default with a
 copy of the XIP setup function that the bootrom leaves in boot RAM, which
 restores the read mode found at boot, or, with