From 756e6050e488160a1179ca18aaef35ec2487b5a1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 31 Mar 2016 09:18:55 -0600 Subject: [PATCH] ARMv7-A: Need to set bits in the ICDDCR to enable forwarding of interrupts --- arch/arm/src/armv7-a/arm_gicv2.c | 13 ++++++++++++- arch/arm/src/armv7-a/gic.h | 10 +++++++--- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index 2df7c81cf62..0d2a61b0b61 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -169,6 +169,7 @@ void arm_gic0_initialize(void) void arm_gic_initialize(void) { uint32_t iccicr; + uint32_t icddcr; /* Initialize PPIs. The following steps need to be done by all CPUs */ @@ -302,6 +303,7 @@ void arm_gic_initialize(void) */ iccicr |= GIC_ICCICR_ENABLE; + icddcr = GIC_ICDDCR_ENABLE; #elif defined(CONFIG_ARCH_TRUSTZONE_SECURE) /* Enable the Group 0 interrupts, FIQEn and disable Group 0/1 @@ -311,6 +313,7 @@ void arm_gic_initialize(void) iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1); + icddcr = GIC_ICDDCR_ENABLEGRP0; #elif defined(CONFIG_ARCH_TRUSTZONE_BOTH) /* Enable the Group 0/1 interrupts, FIQEn and disable Group 0/1 @@ -320,16 +323,18 @@ void arm_gic_initialize(void) iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 | GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1); + icddcr = (GIC_ICDDCR_ENABLEGRP0 | GIC_ICDDCR_ENABLEGRP1); #else /* defined(CONFIG_ARCH_TRUSTZONE_NONSECURE) */ /* Enable the Group 1 interrupts and disable Group 1 bypass. */ iccicr |= (GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_IRQBYPDISGRP1); + icddcr = GIC_ICDDCR_ENABLEGRP1; #endif - /* Write the final ICCICR value */ + /* Write the final ICCICR value to enable the GIC. */ putreg32(iccicr, GIC_ICCICR); @@ -342,6 +347,12 @@ void arm_gic_initialize(void) # warning Missing logic #endif + + /* Write the ICDDCR value to enable the forwarding of interrupt by the + * distributor. + */ + + putreg32(icddcr, GIC_ICDDCR); } /**************************************************************************** diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h index a833c324bcf..c3a15da4028 100644 --- a/arch/arm/src/armv7-a/gic.h +++ b/arch/arm/src/armv7-a/gic.h @@ -327,10 +327,14 @@ #define GIC_ICCIDR_PARTNO_MASK (0xfff << GIC_ICCIDR_PARTNO_SHIFT) /* Distributor Registers */ -/* Distributor Control Register */ +/* Distributor Control Register -- without security extensions */ -#define GIC_ICDDCR_NONSECENAB (1 << 0) /* Bit 0: Enable distributor for Non-secure interrupts */ -#define GIC_ICDDCR_SECENABLE (1 << 1) /* Bit 1: Enable distributor for Secure interrupts */ +#define GIC_ICDDCR_ENABLE (1 << 0) /* Bit 0: Enable forwarding of interrupts */ + /* Bits 1-31: Reserved */ +/* Distributor Control Register -- with security extensions */ + +#define GIC_ICDDCR_ENABLEGRP0 (1 << 0) /* Bit 0: Enable forwarding of Group 0 interrupts */ +#define GIC_ICDDCR_ENABLEGRP1 (1 << 1) /* Bit 1: Enable forwarding of Group 1 interrupts */ /* Bits 2-31: Reserved */ /* Interrupt Controller Type Register */