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arch/risc-v/src: Cosmetic change

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Yoshinori Sugino 2020-08-14 15:10:28 +09:00 • committed by Abdelatif Guettouche
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commit 728d5efed6
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arch/risc-v/src/rv32im/riscv_syscall.S
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@ -95,7 +95,7 @@ sys_call5: /* a0 holds the syscall number, arguments in a1, a2, a3, a4 and a5 */
/* Issue the ECALL opcode to perform a SW interrupt to the OS */
ecall
ecall
/* The actual interrupt may not a occur for a few more cycles. Let's
* put a few nop's here in hope that the SW interrupt occurs during