From 7246fb2aefbee89ae589c838deb083bc995133d8 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 25 Nov 2009 13:50:26 +0000 Subject: [PATCH] Fix block read/write return values; SDIO error reporting; slow down clock if interrupt mode git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2278 42af7a65-404d-4744-a932-0658087f49c3 --- configs/stm3210e-eval/include/board.h | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/configs/stm3210e-eval/include/board.h b/configs/stm3210e-eval/include/board.h index c753d065055..4792ab6affa 100755 --- a/configs/stm3210e-eval/include/board.h +++ b/configs/stm3210e-eval/include/board.h @@ -45,6 +45,7 @@ # include #endif #include "stm32_rcc.h" +#include "stm32_sdio.h" #include "stm32_internal.h" /************************************************************************************ @@ -89,6 +90,36 @@ #define STM32_CFGR_USBPRE 0 +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + /* LED definitions ******************************************************************/ /* The STM3210E-EVAL board has 4 LEDs that we will encode as: */