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Squashed commit of the following:

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arch/arm/src/samd5e5:  Completes GCLK configuration logic.  Still FDPLL and FDLL support.
    arch/arm/src/samd5e5:  A little more GCLK configuratino logic.  Still incomplete.
    arch/arm/src/smad5e5:  Beginning of GCLK configuration logic.
    arch/arm/src/samd5e5:  Add MCLK configuration logic.
    arch/arm/src/samd5e5:  Add XOSC0/1 configuration logic.
    arch/arm/src/samd5e5:  Add XOSC32 configuration logic.
    arch/arm/src/samd5e5:  Rip out all of the leveraged clock configuration logic and start from scratch.
This commit is contained in:
Gregory Nutt 2018-07-27 15:52:02 -06:00
parent 01eec62598
commit 6e1c292400
18 changed files with 1048 additions and 1711 deletions
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14
arch/arm/src/samd5e5/Kconfig
View file

@ -474,20 +474,6 @@ config SAMD5E5_DMAC_NDESC
Each additional DMA descriptor will require 16-bytes for LPRAM
memory.
config SAMD5E5_EIC_CLKGEN
int "EIC Clock Generator"
default 2
range 0 11
---help---
Some optional functions need a peripheral clock, which can either be
a generic clock (GCLK_EIC, for wider frequency selection) or a Ultra
Low Power 32KHz clock (CLK_ULP32K, for highest power efficiency). One
of the clock sources must be configured and enabled before using the
peripheral.
This option assumes that GCLK will be used and provides the GCL
number to be used
choice
prompt "SERCOM0 mode"
default SAMD5E5_SERCOM0_ISUSART

7
arch/arm/src/samd5e5/Make.defs
View file

@ -87,11 +87,8 @@ endif
# Required SAMD5x/E5x files
CHIP_ASRCS =
# REVISIT: sam_clockconfig.c and sam_eic.c
#CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_gclk.c sam_irq.c
CHIP_CSRCS = sam_cmcc.c sam_gclk.c sam_irq.c
CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c
CHIP_CSRCS += sam_supc.c sam_usart.c
CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_eic.c sam_gclk.c sam_irq.c
CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c sam_usart.c
# Configuration-dependent SAMD5x/E5x files

12
arch/arm/src/samd5e5/chip/sam_eic.h
View file

@ -145,12 +145,12 @@
#define EIC_CONFIG0_FILTEN(n) (3 + ((n) << 2)) /* Filter n enable, n=0-7 */
#define EIC_CONFIG0_SENSE_SHIFT(n) ((n) << 2) /* Filter n input sense, n=0-7 */
#define EIC_CONFIG0_SENSE_MASK(n) (7 << EIC_CONFIG0_SENSE_SHIFT(n))
# define EIC_CONFIG0_SENSE_NONE (0 << EIC_CONFIG0_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG0_SENSE_RISE (1 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG0_SENSE_FALL (2 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG0_SENSE_BOTH (3 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG0_SENSE_HIGH (4 << EIC_CONFIG0_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG0_SENSE_LOW (5 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Low level detection */
# define EIC_CONFIG0_SENSE_NONE(n) (0 << EIC_CONFIG0_SENSE_SHIFT(n)) /* No detection */
# define EIC_CONFIG0_SENSE_RISE(n) (1 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Rising edge detection */
# define EIC_CONFIG0_SENSE_FALL(n) (2 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Falling edge detection */
# define EIC_CONFIG0_SENSE_BOTH(n) (3 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Both edge detection */
# define EIC_CONFIG0_SENSE_HIGH(n) (4 << EIC_CONFIG0_SENSE_SHIFT(n)) /* High level detection */
# define EIC_CONFIG0_SENSE_LOW(n) (5 << EIC_CONFIG0_SENSE_SHIFT(n)) /* Low level detection */
/* Configuration 1 register */

8
arch/arm/src/samd5e5/chip/sam_gclk.h
View file

@ -47,6 +47,10 @@
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
#define SAM_NGLCK 12 /* 12 Clock generators, 0-11 */
#define SAM_NCHANNELS 48 /* 48 Clock generators, 0..47 */
/* GCLK register offsets ********************************************************************/
#define SAM_GCLK_CTRLA_OFFSET 0x0000 /* Control register */
@ -61,7 +65,7 @@
#define SAM_GCLK_SYNCHBUSY (SAM_GCLK_BASE + SAM_GCLK_SYNCHBUSY_OFFSET)
#define SAM_GCLK_GENCTRL(n) (SAM_GCLK_BASE + SAM_GCLK_GENCTRL_OFFSET(n))
#define SAM_GCLK_PCHCTRL(m) (SAM_GCLK_BASE + SAM_GCLK_PCHCTRL_OFFSET(m))
#define SAM_GCLK_PCHCTRL(n) (SAM_GCLK_BASE + SAM_GCLK_PCHCTRL_OFFSET(n))
/* GCLK register bit definitions ************************************************************/
@ -84,11 +88,13 @@
# define GCLK_SYNCHBUSY_GENCTRL8 (1 << 10) /* Bit 10: Generator control 8 busy */
# define GCLK_SYNCHBUSY_GENCTRL9 (1 << 11) /* Bit 11: Generator control 9 busy */
# define GCLK_SYNCHBUSY_GENCTRL10 (1 << 12) /* Bit 12: Generator control 10 busy */
# define GCLK_SYNCHBUSY_GENCTRL11 (1 << 13) /* Bit 13: Generator control 11 busy */
/* General clock generator n */
#define GCLK_GENCTRL_SRC_SHIFT (0) /* Bits 0-4: Generator source selection */
#define GCLK_GENCTRL_SRC_MASK (31 << GCLK_GENCTRL_SRC_SHIFT)
# define GCLK_GENCTRL_SRC(n) ((uint32_t)(n) << GCLK_GENCTRL_SRC_SHIFT)
# define GCLK_GENCTRL_SRC_XOSC0 (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 0 oscillator input */
# define GCLK_GENCTRL_SRC_XOSC1 (1 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC 1 oscillator input */
# define GCLK_GENCTRL_SRC_GCLK_IN (2 << GCLK_GENCTRL_SRC_SHIFT) /* Generator input pad */

1
arch/arm/src/samd5e5/chip/sam_osc32kctrl.h
View file

@ -88,6 +88,7 @@
#define OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT (0) /* Bits 0-2: RTC clock source selection */
#define OSC32KCTRL_RTCCTRL_RTCSEL_MASK (7 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT)
# define OSC32KCTRL_RTCCTRL_RTCSEL(n) ((uint8_t)(n) << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT)
# define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (0 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz from 32HKz internal ULP oscillator */
# define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (1 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz internal ULP oscillator */
# define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (4 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024kHz from 32KHz external oscillator */

3
arch/arm/src/samd5e5/chip/sam_oscctrl.h
View file

@ -168,6 +168,9 @@
# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
#define OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT (24) /* Bits 24-27: Clock Failure Detector Prescaler */
#define OSCCTRL_XOSCCTRL_CFDPRESC_MASK (15 << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT)
# define OSCCTRL_XOSCCTRL_CFDPRESC(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT)
/* DFLL48M control register A */

9
arch/arm/src/samd5e5/chip/sam_pinmap.h
View file

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
/************************************************************************************
* Included Files
@ -43,10 +43,9 @@
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
# include "chip/samd5e5_memorymap.h"
# include "chip/samd5e5_pinmap.h"
#else
# error "Unsupported SAMD5/E5 family"
#endif
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H */

6
arch/arm/src/samd5e5/chip/samd5e5_pinmap.h
View file

@ -33,8 +33,8 @@
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_PINMAP_H
#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_PINMAP_H
/********************************************************************************************
* Included Files
@ -787,4 +787,4 @@
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H */
#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_PINMAP_H */

1798
arch/arm/src/samd5e5/sam_clockconfig.c
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File diff suppressed because it is too large Load diff

135
arch/arm/src/samd5e5/sam_clockconfig.h
View file

@ -50,6 +50,118 @@
* Public Types
************************************************************************************/
#ifdef BOARD_HAVE_CLKDEFS
/* This structure defines the configuration of the 32.768KHz XOSC32 */
struct sam_xosc32_config_s
{
uint8_t enable : 1; /* True: Enable XOSC32 */
uint8_t highspeed : 1; /* Controls gain of the external oscillator */
uint8_t extalen : 1; /* Crystal oscillator enable
* false: External clock connected on XIN32
* true: Crystal connected to XIN32/XOUT32 */
uint8_t en32k : 1; /* Enable 32KHz output */
uint8_t en1k : 1; /* Enable 1KHz output */
uint8_t runstdby : 1; /* Run in standby */
uint8_t ondemand : 1; /* On-demand control */
uint8_t cfden : 1; /* Clock failure detection */
uint8_t cfdeo : 1; /* Clock failure event enable */
uint8_t caliben : 1; /* OSCULP32K calibration enable */
uint8_t startup; /* Start-up time:
* 0: 62592us 4: 2000092us
* 1: 125092us 5: 4000092us
* 2: 500092us 6: 8000092us
* 3: 1000092us */
uint8_t calib; /* OSCULP32K calibration value (0-31) */
uint8_t rtcsel; /* RTC clock selection
* 0 ULP1K 1.024kHz from 32KHz internal ULP
* oscillator
* 1 ULP32K 32.768kHz from 32KHz internal ULP
* oscillator
* 4 XOSC1K 1.024kHz from 32KHz external
* oscillator
* 5 XOSC32K 32.768kHz from 32KHz external crystal
* oscillator */
};
/* This structure defines the configuration of XOSC0/1 */
struct sam_xosc_config_s
{
uint8_t enable : 1; /* True: Enable XOSC32 */
uint8_t extalen : 1; /* Crystal oscillator enable
* false: External clock connected
* true: Crystal connected */
uint8_t runstdby : 1; /* Run in standby */
uint8_t ondemand : 1; /* On-demand control */
uint8_t lowgain : 1; /* Low buffer gain enable */
uint8_t enalc : 1; /* Automatic loop control enable */
uint8_t cfden : 1; /* Clock failure detection */
uint8_t swben : 1; /* XOSC clock switch enable */
uint8_t startup; /* Start-up time:
* 0 31us 8 7813us
* 1 61us 9 15625us
* 2 122us 10 31250us
* 3 244us 11 62500us
* 4 488us 12 125000us
* 5 977us 13 250000us
* 6 1953us 14 500000us
* 7 3906us 15 1000000us */
uint32_t xosc_frequency; /* XOSC frequency */
};
/* This structure defines the configuration of the FDPLL0/1 */
struct sam_fdpll_config_s
{
};
/* This structure defines the configuration of a GCLK */
struct sam_gclk_config_s
{
uint8_t enable : 1; /* True: Enable GCLK */
uint8_t idc : 1; /* True: Improve duty cycle */
uint8_t oov : 1; /* True: Clock output selection */
uint8_t oe : 1; /* True: Output enable */
uint8_t divsel : 1; /* True: Clock source divider */
uint8_t runstdby : 1; /* Run in standby */
uint8_t source; /* GLCK clock source:
* 0 XOSC 0 oscillator input
* 1 XOSC 1 oscillator input
* 2 Generator input pad
* 3 Generic clock generator 1 output
* 4 OSCULP32K oscillator output
* 5 XOSC32K oscillator output
* 6 DFLL oscillator output
* 7 DPLL0 output
* 8 DPLL1 output */
uint16_t div; /* Division factor: 8-bits for all but GCLK1 */
};
/* This structure defines the configuration of the clock sus-system */
struct sam_clockconfig_s
{
uint8_t waitstates; /* NVM read wait states 9-15 */
uint8_t cpudiv; /* MCLK divider to get CPU frequency */
uint16_t glckset1; /* GLCKs to initialize prior to FDPLL init */
uint16_t glckset2; /* GLCKs to initialize after to FDPLL init */
uint32_t cpu_frequency; /* Resulting CPU frequency */
#if BOARD_HAVE_XOSC32K != 0
struct sam_xosc32_config_s xosc32k; /* XOSC32 configuration */
#endif
#if BOARD_HAVE_XOSC0 != 0
struct sam_xosc_config_s xosc0; /* XOSC0 configuration */
#endif
#if BOARD_HAVE_XOSC1 != 0
struct sam_xosc_config_s xosc1; /* XOSC1 configuration */
#endif
struct sam_fdpll_config_s fdpll[2]; /* FDPLL0/1 configurations */
struct sam_gclk_config_s gclk[12]; /* GLCK configurations */
};
#endif /* BOARD_HAVE_CLKDEFS */
/************************************************************************************
* Inline Functions
************************************************************************************/
@ -74,16 +186,29 @@ extern "C"
************************************************************************************/
/************************************************************************************
* Name: sam_clockconfig
* Name: sam_clock_configure
*
* Description:
* Called to initialize the SAM3/4. This does whatever setup is needed to put the
* SoC in a usable state. This includes the initialization of clocking using the
* settings in board.h.
* Configure the clock sub-system per the provided configuration data.
*
* This should be called only (1) early in the initialization sequence, or (2)
* later but within a critical section.
*
************************************************************************************/
void sam_clockconfig(void);
struct sam_clockconfig_s;
void sam_clock_configure(const struct sam_clockconfig_s *config);
/************************************************************************************
* Name: sam_clock_initialize
*
* Description:
* Configure the initial power-up clocking. This function may be called
* only once by the power-up reset logic.
*
************************************************************************************/
void sam_clock_initialize(void);
#undef EXTERN
#if defined(__cplusplus)

25
arch/arm/src/samd5e5/sam_eic.c
View file

@ -39,8 +39,10 @@
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include "up_arch.h"
#include "sam_gclk.h"
@ -97,7 +99,7 @@ void sam_eic_dumpregs(void)
{
irqinfo("EIC:\n");
irqinfo(" CTRLA: %02x\n", getreg8(SAM_EIC_CTRLA));
irqinfo(" NMICTRL: %02x\n", getreg8(SAM_EIC_NVMICTRL));
irqinfo(" NMICTRL: %02x\n", getreg8(SAM_EIC_NMICTRL));
irqinfo(" NMIFLAG: %04x\n", getreg16(SAM_EIC_NMIFLAG));
irqinfo(" SYNCBUSY: %08x\n", getreg32(SAM_EIC_SYNCBUSY));
irqinfo(" EVCTRL: %08x\n", getreg32(SAM_EIC_EVCTRL));
@ -128,21 +130,27 @@ void sam_eic_dumpregs(void)
int sam_eic_initialize(void)
{
uint16_t regval;
uintptr_t regaddr;
uint32_t regval;
/* Configure the EIC APB clock */
sam_apb_eic_enableperiph();
regval = GCLK_CLKCTRL_ID_EIC |
GCLK_CLKCTRL_GEN(CONFIG_SAMD5E5_EIC_GCLKGEN) |
GCLK_CLKCTRL_CLKEN;
/* Use the selected GCLK_EIC. Some optional functions need a peripheral
* clock, which can either be a generic clock (GCLK_EIC, for wider
* frequency selection) or a Ultra Low Power 32KHz clock (CLK_ULP32K, for
* highest power efficiency). One of the clock sources must be configured
* and enabled before using the peripheral.
*/
putreg16(regval, SAM_GCLK_CLKCTRL);
regaddr = SAM_GCLK_PCHCTRL(GCLK_CHAN_EIC);
regval = GCLK_PCHCTRL_GEN(BOARD_GLCK_EIC) | GCLK_PCHCTRL_CHEN;
putreg32(regval, regaddr);
/* Enable the EIC APB clock */
/* Enable the EIC, selecting clocking via the GLCK_EIC */
putreg8(EIC_CTRLA_ENABLE, SAM_EIC_CTRLA);
putreg8(EIC_CTRLA_ENABLE | EIC_CTRLA_ENABLE, SAM_EIC_CTRLA);
sam_eic_syncwait();
sam_eic_dumpregs();
@ -241,6 +249,7 @@ int sam_eic_irq_ack(int irq)
int eirq = irq - SAM_IRQ_EXTINT0;
putreg32(EIC_EXTINT(eirq), SAM_EIC_INTENCLR);
return OK;
}
#endif /* CONFIG_SAMD5E5_EIC */

14
arch/arm/src/samd5e5/sam_lowputc.c
View file

@ -293,18 +293,10 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
/* Configure the GCLKs for the SERCOM module */
sercom_coreclk_configure(config->sercom, config->gclkgen, false);
sercom_coreclk_configure(config->sercom, config->coregen, false);
if (config->sercom == 5)
{
channel = GCLK_CHAN_SERCOM5_CORE;
}
else
{
channel = config->sercom + GCLK_CHAN_SERCOM0_CORE;
}
sam_gclk_chan_enable(channel, config->gclkgen);
channel = config->sercom + GCLK_CHAN_SERCOM0_CORE;
sam_gclk_chan_enable(channel, config->coregen);
sercom_slowclk_configure(config->sercom, config->slowgen);

1
arch/arm/src/samd5e5/sam_sercom.h
View file

@ -47,7 +47,6 @@
#include "up_arch.h"
#include "sam_config.h"
#include "sam_periphclks.h"
#include "chip/sam_sercom.h"
/****************************************************************************
* Pre-processor Definitions

23
arch/arm/src/samd5e5/sam_serial.c
View file

@ -782,16 +782,21 @@ static int sam_attach(struct uart_dev_s *dev)
const struct sam_usart_config_s * const config = priv->config;
int ret;
/* Attach and enable the IRQ */
/* Attach and enable the Tx and Rx IRQs */
ret = irq_attach(config->irq, sam_interrupt, dev);
ret = irq_attach(config->txirq, sam_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the USART
*/
ret = irq_attach(config->rxirq, sam_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the USART
*/
up_enable_irq(config->irq);
up_enable_irq(config->txirq);
up_enable_irq(config->rxirq);
}
}
return ret;
@ -815,11 +820,13 @@ static void sam_detach(struct uart_dev_s *dev)
/* Disable interrupts at the SERCOM device and at the NVIC */
sam_disableallints(priv);
up_disable_irq(config->irq);
up_disable_irq(config->txirq);
up_disable_irq(config->rxirq);
/* Detach the interrupt handler */
irq_detach(config->irq);
irq_detach(config->txirq);
irq_detach(config->rxirq);
}
/****************************************************************************

18
arch/arm/src/samd5e5/sam_start.c
View file

@ -94,7 +94,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void sam_fpuconfig(void);
static inline void sam_fpu_configure(void);
#endif
#ifdef CONFIG_STACK_COLORATION
static void go_os_start(void *pv, unsigned int nbytes)
@ -126,7 +126,7 @@ void __start(void) __attribute__ ((no_instrument_function));
#endif
/****************************************************************************
* Name: sam_fpuconfig
* Name: sam_fpu_configure
*
* Description:
* Configure the FPU. Relative bit settings:
@ -151,7 +151,7 @@ void __start(void) __attribute__ ((no_instrument_function));
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void sam_fpuconfig(void)
static inline void sam_fpu_configure(void)
{
uint32_t regval;
@ -181,7 +181,7 @@ static inline void sam_fpuconfig(void)
#else
static inline void sam_fpuconfig(void)
static inline void sam_fpu_configure(void)
{
uint32_t regval;
@ -212,7 +212,7 @@ static inline void sam_fpuconfig(void)
#endif
#else
# define sam_fpuconfig()
# define sam_fpu_configure()
#endif
/****************************************************************************
@ -312,10 +312,12 @@ void __start(void)
}
#endif
/* Configure the UART so that we can get debug output as soon as possible */
/* Initialize clocking and the FPU. Configure the console UART so that
* we can get debug output as soon as possible.
*/
sam_clockconfig();
sam_fpuconfig();
sam_clock_initialize();
sam_fpu_configure();
sam_lowsetup();
showprogress('A');

91
arch/arm/src/samd5e5/sam_usart.c
View file

@ -42,10 +42,13 @@
#include <stdint.h>
#include <assert.h>
#include <arch/irq.h>
#include <arch/samd5e5/chip.h>
#include "sam_pinmap.h"
#include "chip/sam_memorymap.h"
#include "chip/sam_pinmap.h"
#include "sam_gclk.h"
#include "sam_sercom.h"
#include "sam_usart.h"
#include <arch/board/board.h>
@ -64,9 +67,10 @@ const struct sam_usart_config_s g_usart0config =
.sercom = 0,
.parity = CONFIG_USART0_PARITY,
.bits = CONFIG_USART0_BITS,
.irq = SAM_IRQ_SERCOM0,
.gclkgen = BOARD_SERCOM0_GCLKGEN,
.slowgen = BOARD_SERCOM0_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM0,
.rxirq = BOARD_RXIRQ_SERCOM0,
.coregen = BOARD_SERCOM0_COREGEN,
.slowgen = BOARD_SERCOM0_SLOWGEN,
.stopbits2 = CONFIG_USART0_2STOP,
.baud = CONFIG_USART0_BAUD,
.pad0 = BOARD_SERCOM0_PINMAP_PAD0,
@ -85,9 +89,10 @@ const struct sam_usart_config_s g_usart1config =
.sercom = 1,
.parity = CONFIG_USART1_PARITY,
.bits = CONFIG_USART1_BITS,
.irq = SAM_IRQ_SERCOM1,
.gclkgen = BOARD_SERCOM1_GCLKGEN,
.slowgen = BOARD_SERCOM1_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM1,
.rxirq = BOARD_RXIRQ_SERCOM1,
.coregen = BOARD_SERCOM1_COREGEN,
.slowgen = BOARD_SERCOM1_SLOWGEN,
.stopbits2 = CONFIG_USART1_2STOP,
.baud = CONFIG_USART1_BAUD,
.pad0 = BOARD_SERCOM1_PINMAP_PAD0,
@ -106,9 +111,10 @@ const struct sam_usart_config_s g_usart2config =
.sercom = 2,
.parity = CONFIG_USART2_PARITY,
.bits = CONFIG_USART2_BITS,
.irq = SAM_IRQ_SERCOM2,
.gclkgen = BOARD_SERCOM2_GCLKGEN,
.slowgen = BOARD_SERCOM2_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM2,
.rxirq = BOARD_RXIRQ_SERCOM2,
.coregen = BOARD_SERCOM2_COREGEN,
.slowgen = BOARD_SERCOM2_SLOWGEN,
.stopbits2 = CONFIG_USART2_2STOP,
.baud = CONFIG_USART2_BAUD,
.pad0 = BOARD_SERCOM2_PINMAP_PAD0,
@ -127,9 +133,10 @@ const struct sam_usart_config_s g_usart3config =
.sercom = 3,
.parity = CONFIG_USART3_PARITY,
.bits = CONFIG_USART3_BITS,
.irq = SAM_IRQ_SERCOM3,
.gclkgen = BOARD_SERCOM3_GCLKGEN,
.slowgen = BOARD_SERCOM3_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM3,
.rxirq = BOARD_RXIRQ_SERCOM3,
.coregen = BOARD_SERCOM3_COREGEN,
.slowgen = BOARD_SERCOM3_SLOWGEN,
.stopbits2 = CONFIG_USART3_2STOP,
.baud = CONFIG_USART3_BAUD,
.pad0 = BOARD_SERCOM3_PINMAP_PAD0,
@ -148,9 +155,10 @@ const struct sam_usart_config_s g_usart4config =
.sercom = 4,
.parity = CONFIG_USART4_PARITY,
.bits = CONFIG_USART4_BITS,
.irq = SAM_IRQ_SERCOM4,
.gclkgen = BOARD_SERCOM4_GCLKGEN,
.slowgen = BOARD_SERCOM4_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM4,
.rxirq = BOARD_RXIRQ_SERCOM4,
.coregen = BOARD_SERCOM4_COREGEN,
.slowgen = BOARD_SERCOM4_SLOWGEN,
.stopbits2 = CONFIG_USART4_2STOP,
.baud = CONFIG_USART4_BAUD,
.pad0 = BOARD_SERCOM4_PINMAP_PAD0,
@ -169,9 +177,10 @@ const struct sam_usart_config_s g_usart5config =
.sercom = 5,
.parity = CONFIG_USART5_PARITY,
.bits = CONFIG_USART5_BITS,
.irq = SAM_IRQ_SERCOM5,
.gclkgen = BOARD_SERCOM5_GCLKGEN,
.slowgen = BOARD_SERCOM5_SLOW_GCLKGEN,
.txirq = BOARD_TXIRQ_SERCOM5,
.rxirq = BOARD_RXIRQ_SERCOM5,
.coregen = BOARD_SERCOM5_COREGEN,
.slowgen = BOARD_SERCOM5_SLOWGEN,
.stopbits2 = CONFIG_USART5_2STOP,
.baud = CONFIG_USART5_BAUD,
.pad0 = BOARD_SERCOM5_PINMAP_PAD0,
@ -184,6 +193,50 @@ const struct sam_usart_config_s g_usart5config =
};
#endif
#ifdef SAMD5E5_HAVE_USART6
const struct sam_usart_config_s g_usart6config =
{
.sercom = 6,
.parity = CONFIG_USART6_PARITY,
.bits = CONFIG_USART6_BITS,
.txirq = BOARD_TXIRQ_SERCOM6,
.rxirq = BOARD_RXIRQ_SERCOM6,
.coregen = BOARD_SERCOM6_COREGEN,
.slowgen = BOARD_SERCOM6_SLOWGEN,
.stopbits2 = CONFIG_USART6_2STOP,
.baud = CONFIG_USART6_BAUD,
.pad0 = BOARD_SERCOM6_PINMAP_PAD0,
.pad1 = BOARD_SERCOM6_PINMAP_PAD1,
.pad2 = BOARD_SERCOM6_PINMAP_PAD2,
.pad3 = BOARD_SERCOM6_PINMAP_PAD3,
.muxconfig = BOARD_SERCOM6_MUXCONFIG,
.frequency = BOARD_SERCOM6_FREQUENCY,
.base = SAM_SERCOM6_BASE,
};
#endif
#ifdef SAMD5E5_HAVE_USART7
const struct sam_usart_config_s g_usart7config =
{
.sercom = 7,
.parity = CONFIG_USART7_PARITY,
.bits = CONFIG_USART7_BITS,
.txirq = BOARD_TXIRQ_SERCOM7,
.rxirq = BOARD_RXIRQ_SERCOM7,
.coregen = BOARD_SERCOM7_COREGEN,
.slowgen = BOARD_SERCOM7_SLOWGEN,
.stopbits2 = CONFIG_USART7_2STOP,
.baud = CONFIG_USART7_BAUD,
.pad0 = BOARD_SERCOM7_PINMAP_PAD0,
.pad1 = BOARD_SERCOM7_PINMAP_PAD1,
.pad2 = BOARD_SERCOM7_PINMAP_PAD2,
.pad3 = BOARD_SERCOM7_PINMAP_PAD3,
.muxconfig = BOARD_SERCOM7_MUXCONFIG,
.frequency = BOARD_SERCOM7_FREQUENCY,
.base = SAM_SERCOM7_BASE,
};
#endif
const struct sam_usart_config_s *g_usartconfig[SAMD5E5_NSERCOM] =
{
#if SAMD5E5_NSERCOM > 0

5
arch/arm/src/samd5e5/sam_usart.h
View file

@ -89,8 +89,9 @@ struct sam_usart_config_s
uint8_t sercom; /* Identifies the SERCOM peripheral */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (5-9) */
uint8_t irq; /* SERCOM IRQ number */
uint8_t gclkgen; /* Source GCLK generator */
uint8_t txirq; /* Tx SERCOM IRQ number */
uint8_t rxirq; /* Rx SERCOM IRQ number */
uint8_t coregen; /* Core GCLK generator */
uint8_t slowgen; /* Slow GCLK generator */
bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
uint32_t baud; /* Configured baud */

589
configs/metro-m4/include/board.h
View file

@ -52,445 +52,217 @@
************************************************************************************/
/* Clocking *************************************************************************/
/* Overview
*
* Since there is no high speed crystal, we will run from the OSC16M clock source.
* We will use its default, POR frequency of 4MHz to avoid an additional clock
* switch.
*
* OSC16M Output = 4MHz
* `- GCLK1 Input = 4MHz Prescaler = 1 output = 4MHz
* `- DFLL Input = 4MHz Multiplier = 12 output = 48MHz
* `- GCLK0 Input = 48MHz Prescaler = 1 output = 48MHz
* `- MCLK Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz
* APBA divider = 1 APBA frequency = 48MHz
* APBB divider = 1 APBB frequency = 48MHz
* APBC divider = 1 APBC frequency = 48MHz
* APBD divider = 1 APBD frequency = 48MHz
* APBE divider = 1 APBE frequency = 48MHz
*
* The Adafruit Metro M4 has one on-board crystal:
*
* X4 32.768KHz XOSC32
*
* REVISIT: Not currently used, may want to use as GCLK1 source with
* DFLL multiplier of ((48000000+16384)/32768) = 1465 which would yield
* a clock of 48,005,120 MHz.
*/
/* XOSC Configuration -- Not available
*
* BOARD_XOSC_ENABLE - Boolean (defined / not defined)
* BOARD_XOSC_FREQUENCY - In Hz
* BOARD_XOSC_STARTUPTIME - See SYSCTRL_XOSC_STARTUP_* definitions
* BOARD_XOSC_ISCRYSTAL - Boolean (defined / not defined)
* BOARD_XOSC_AMPGC - Boolean (defined / not defined)
* BOARD_XOSC_ONDEMAND - Boolean (defined / not defined)
* BOARD_XOSC_RUNINSTANDBY - Boolean (defined / not defined)
*/
#define BOARD_HAVE_CLKDEFS 1
#undef BOARD_XOSC_ENABLE
#define BOARD_XOSC_FREQUENCY 12000000UL
#define BOARD_XOSC_STARTUPTIME SYSCTRL_XOSC_STARTUP_1S
#define BOARD_XOSC_ISCRYSTAL 1
#define BOARD_XOSC_AMPGC 1
#define BOARD_XOSC_ONDEMAND 1
#undef BOARD_XOSC_RUNINSTANDBY
/* XOSC32 */
/* XOSC32 Configuration -- Not used
*
* BOARD_XOSC32K_ENABLE - Boolean (defined / not defined)
* BOARD_XOSC32K_FREQUENCY - In Hz
* BOARD_XOSC32K_STARTUPTIME - See SYSCTRL_XOSC32K_STARTUP_* definitions
* BOARD_XOSC32K_ISCRYSTAL - Boolean (defined / not defined)
* BOARD_XOSC32K_AAMPEN - Boolean (defined / not defined)
* BOARD_XOSC32K_EN1KHZ - Boolean (defined / not defined)
* BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined)
* BOARD_XOSC32K_WRITELOCK - Boolean (defined / not defined)
*/
#define BOARD_HAVE_XOSC32K 1 /* 32.768KHz XOSC32 crystal installed */
#define BOARD_XOSC32K_ENABLE false /* Don't enable XOSC32 */
#define BOARD_XOSC32K_XTALEN false /* External clock connected on XIN32 */
#define BOARD_XOSC32K_EN32K false /* No 32KHz output */
#define BOARD_XOSC32K_EN1K false /* No 1KHz output */
#define BOARD_XOSC32K_HIGHSPEED true /* High speed mode */
#define BOARD_XOSC32K_RUNSTDBY false /* Don't run in standby */
#define BOARD_XOSC32K_ONDEMAND true /* Enable on-demand control */
#define BOARD_XOSC32K_CFDEN false /* Clock failure detector not enabled */
#define BOARD_XOSC32K_CFDEO false /* No clock failure event */
#define BOARD_XOSC32K_CALIBEN false /* No OSCULP32K calibration */
#define BOARD_XOSC32K_STARTUP 0 /* Startup time: 62592us */
#define BOARD_XOSC32K_CALIB 0 /* Dummy OSCULP32K calibration value */
#define BOARD_XOSC32K_RTCSEL 0 /* RTC clock = ULP1K */
#define BOARD_XOSC32K_FREQUENCY 32768 /* XOSC32K frequency 32.768 KHz */
#undef BOARD_XOSC32K_ENABLE
#ifdef CONFIG_METRO_M4_XOSC32K
# define BOARD_XOSC32K_ENABLE 1
# define BOARD_XOSC32K_FREQUENCY 32768 /* 32.768KHz XTAL */
# define BOARD_XOSC32K_STARTUPTIME OSC32KCTRL_XOSC32K_STARTUP_100MS
# define BOARD_XOSC32K_ISCRYSTAL 1
# undef BOARD_XOSC32K_EN1KHZ
# define BOARD_XOSC32K_EN32KHZ 1
# define BOARD_XOSC32K_ONDEMAND 1
# undef BOARD_XOSC32K_RUNINSTANDBY
# undef BOARD_XOSC32K_WRITELOCK
#endif
/* XOSC0 */
/* OSC32 Configuration -- not used
*
* BOARD_OSC32K_ENABLE - Boolean (defined / not defined)
* BOARD_OSC32K_FREQUENCY - In Hz
* BOARD_OSC32K_STARTUPTIME - See SYSCTRL_OSC32K_STARTUP_* definitions
* BOARD_OSC32K_EN1KHZ - Boolean (defined / not defined)
* BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined)
* BOARD_OSC32K_WRITELOCK - Boolean (defined / not defined)
*/
#define BOARD_HAVE_XOSC0 0 /* No XOSC0 clock/crystal installed */
#define BOARD_XOSC0_ENABLE false /* Don't enable XOSC0 */
#define BOARD_XOSC0_XTALEN false /* External clock connected */
#define BOARD_XOSC0_RUNSTDBY false /* Don't run in standby */
#define BOARD_XOSC0_ONDEMAND true /* Disable on-demand control */
#define BOARD_XOSC0_LOWGAIN false /* Disable low buffer gain */
#define BOARD_XOSC0_ENALC false /* Disable automatic loop control */
#define BOARD_XOSC0_CFDEN false /* Clock failure detector not enabled */
#define BOARD_XOSC0_SWBEN false /* XOSC clock switch not enabled */
#define BOARD_XOSC0_STARTUP 0 /* XOSC0 start-up time 31µs */
#define BOARD_XOSC0_FREQUENCY 12000000 /* XOSC0 frequency 12MHz */
#undef BOARD_OSC32K_ENABLE
#define BOARD_OSC32K_FREQUENCY 32768 /* 32.768kHz internal oscillator */
#define BOARD_OSC32K_STARTUPTIME SYSCTRL_OSC32K_STARTUP_4MS
#define BOARD_OSC32K_EN1KHZ 1
#define BOARD_OSC32K_EN32KHZ 1
#define BOARD_OSC32K_ONDEMAND 1
#undef BOARD_OSC32K_RUNINSTANDBY
#undef BOARD_OSC32K_WRITELOCK
/* XOSC1 */
/* OSC16M Configuration -- always enabled
*
* BOARD_OSC16M_FSEL - See OSCCTRL_OSC16MCTRL_FSEL_* definitions
* BOARD_OSC16M_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC16M_RUNINSTANDBY - Boolean (defined / not defined)
*/
#define BOARD_HAVE_XOSC1 0 /* No XOSC0 clock/crystal installed */
#define BOARD_XOSC1_ENABLE false /* Don't enable XOSC1 */
#define BOARD_XOSC1_XTALEN true /* External crystal connected */
#define BOARD_XOSC1_RUNSTDBY false /* Don't run in standby */
#define BOARD_XOSC1_ONDEMAND true /* Disable on-demand control */
#define BOARD_XOSC1_LOWGAIN false /* Disable low buffer gain */
#define BOARD_XOSC1_ENALC false /* Disable automatic loop control */
#define BOARD_XOSC1_CFDEN false /* Clock failure detector not enabled */
#define BOARD_XOSC1_SWBEN false /* XOSC clock switch not enabled */
#define BOARD_XOSC1_STARTUP 0 /* XOSC0 start-up time 31µs */
#define BOARD_XOSC1_FREQUENCY 12000000 /* XOSC0 frequency 12MHz */
/* Master Clock (MCLK) */
#if defined(CONFIG_METRO_M4_OSC16M_4MHZ)
# define BOARD_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4MHZ
# define BOARD_OSC16M_ONDEMAND 1
# undef BOARD_OSC16M_RUNINSTANDBY
# define BOARD_OSC16M_FREQUENCY 4000000 /* 4MHz high-accuracy internal oscillator */
#define BOARD_MCLK_CPUDIV 1 /* MCLK divder to get CPU frequency */
#define BOARD_CPU_FREQUENCY 120000000 /* CPU frequency 120MHz */
#elif defined(CONFIG_METRO_M4_OSC16M_8MHZ)
# define BOARD_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_8MHZ
# define BOARD_OSC16M_ONDEMAND 1
# undef BOARD_OSC16M_RUNINSTANDBY
# define BOARD_OSC16M_FREQUENCY 8000000 /* 8MHz high-accuracy internal oscillator */
/* FDPLL0/1 -- To be provided */
#elif defined(CONFIG_METRO_M4_OSC16M_12MHZ)
# define BOARD_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_12MHZ
# define BOARD_OSC16M_ONDEMAND 1
# undef BOARD_OSC16M_RUNINSTANDBY
# define BOARD_OSC16M_FREQUENCY 12000000 /* 12MHz high-accuracy internal oscillator */
#define BOARD_FDPLL0_FREQUENCY 0
#define BOARD_FDPLL1_FREQUENCY 0
#elif defined(CONFIG_METRO_M4_OSC16M_16MHZ)
# define BOARD_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_16MHZ
# define BOARD_OSC16M_ONDEMAND 1
# undef BOARD_OSC16M_RUNINSTANDBY
# define BOARD_OSC16M_FREQUENCY 16000000 /* 18MHz high-accuracy internal oscillator */
/* FDLL -- To be provided */
#else
# error OSC16M operating freqency not defined (CONFIG_METRO_M4_OSC16M_*MHZ)
#endif
#define BOARD_DFLL_FREQUENCY 0
/* OSCULP32K Configuration -- not used. */
/* GCLK */
#define BOARD_OSCULP32K_FREQUENCY 32000 /* 32kHz ultra-low-power internal oscillator */
#define BOARD_GCLK_SET1 0x0000 /* The empty set */
#define BOARD_GCLK_SET2 0x0fff /* All GCLKs */
/* Digital Frequency Locked Loop configuration. In closed-loop mode, the
* DFLL output frequency (Fdfll) is given by:
*
* Fdfll = DFLLmul * Frefclk
* = 12 * 4000000 = 48MHz
*
* Where the reference clock is Generic Clock Channel 0 output of GLCK1.
* GCLCK1 provides OSC16M, undivided.
*
* When operating in open-loop mode, the output frequency of the DFLL will
* be determined by the values written to the DFLL Coarse Value bit group
* and the DFLL Fine Value bit group in the DFLL Value register.
*
* BOARD_DFLL48M_CLOSEDLOOP - Boolean (defined / not defined)
* BOARD_DFLL48M_OPENLOOP - Boolean (defined / not defined)
* BOARD_DFLL48M_RECOVERY - Boolean (defined / not defined)
* BOARD_DFLL48M_TRACKAFTERFINELOCK - Boolean (defined / not defined)
* BOARD_DFLL48M_KEEPLOCKONWAKEUP - Boolean (defined / not defined)
* BOARD_DFLL48M_ENABLECHILLCYCLE - Boolean (defined / not defined)
* BOARD_DFLL48M_QUICKLOCK - Boolean (defined / not defined)
* BOARD_DFLL48M_RUNINSTDBY - Boolean (defined / not defined)
* BOARD_DFLL48M_ONDEMAND - Boolean (defined / not defined)
* BOARD_DFLL48M_COARSEVALUE - Value
* BOARD_DFLL48M_FINEVALUE - Value
*
* Open Loop mode only:
* BOARD_DFLL48M_COARSEVALUE - Value
* BOARD_DFLL48M_FINEVALUE - Value
*
* Closed loop mode only:
* BOARD_DFLL48M_REFCLK_CLKGEN - GCLK index in the range {0..8}
* BOARD_DFLL48M_MULTIPLIER - Value
* BOARD_DFLL48M_MAXCOARSESTEP - Value
* BOARD_DFLL48M_MAXFINESTEP - Value
*
* BOARD_DFLL48M_FREQUENCY - The resulting frequency
*/
#define BOARD_GCLK0_ENABLE true /* Enable GCLK0 */
#define BOARD_GCLK0_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK0_OOV false /* Clock output will be LOW */
#define BOARD_GCLK0_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK0_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK0_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK0_SOURCE 7 /* Select DPLL0 output as GLCK0 source */
#define BOARD_GCLK0_DIV 1 /* Division factor */
#define BOARD_GCLK0_FREQUENCY BOARD_DPLL0_FREQUENCY
#undef BOARD_DFLL48M_ENABLE 1 /* Assume not using the DFLL48M */
#undef BOARD_DFLL48M_CLOSEDLOOP
#undef BOARD_DFLL48M_OPENLOOP
#undef BOARD_DFLL48M_RECOVERY
#define BOARD_GCLK1_ENABLE true /* Enable GCLK1 */
#define BOARD_GCLK1_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK1_OOV false /* Clock output will be LOW */
#define BOARD_GCLK1_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK1_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK1_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GLCK1 source */
#define BOARD_GCLK1_DIV 1 /* Division factor */
#define BOARD_GCLK1_FREQUENCY BOARD_DFLL_FREQUENCY
#ifdef CONFIG_METRO_M4_DFLL
# define BOARD_DFLL48M_ENABLE 1 /* Using the DFLL48M */
#define BOARD_GCLK2_ENABLE false /* Don't enable GCLK2 */
#define BOARD_GCLK2_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK2_OOV false /* Clock output will be LOW */
#define BOARD_GCLK2_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK2_DIVSEL 1 /* GCLK frequency is source/(2^(N+1) */
#define BOARD_GCLK2_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GLCK2 source */
#define BOARD_GCLK2_DIV 1 /* Division factor */
#define BOARD_GCLK2_FREQUENCY (BOARD_XOSC32K_FREQUENCY / 4)
/* DFLL mode of operation */
#define BOARD_GCLK3_ENABLE false /* Don't enable GCLK3 */
#define BOARD_GCLK3_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK3_OOV false /* Clock output will be LOW */
#define BOARD_GCLK3_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK3_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK3_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GLCK3 source */
#define BOARD_GCLK3_DIV 1 /* Division factor */
#define BOARD_GCLK3_FREQUENCY BOARD_XOSC32K_FREQUENCY
# if defined(CONFIG_METRO_M4_DFLL_OPENLOOP)
# define BOARD_DFLL48M_OPENLOOP 1 /* In open loop mode */
# elif defined(CONFIG_METRO_M4_DFLL_CLOSEDLOOP)
# define BOARD_DFLL48M_CLOSEDLOOP 1 /* In closed loop mode */
# elif defined(CONFIG_METRO_M4_DFLL_RECOVERY)
# define BOARD_DFLL48M_RECOVERY 1 /* In USB recover mode */
# else
# error DFLL mode not provided
# endif
#define BOARD_GCLK4_ENABLE true /* Enable GCLK4 */
#define BOARD_GCLK4_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK4_OOV false /* Clock output will be LOW */
#define BOARD_GCLK4_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK4_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK4_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GLCK4 source */
#define BOARD_GCLK4_DIV 1 /* Division factor */
#define BOARD_GCLK4_FREQUENCY BOARD_DPLL0_FREQUENCY
/* DFLL source clock selection */
#define BOARD_GCLK5_ENABLE true /* Enable GCLK5 */
#define BOARD_GCLK5_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK5_OOV false /* Clock output will be LOW */
#define BOARD_GCLK5_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK5_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK5_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GLCK5 source */
#define BOARD_GCLK5_DIV 24 /* Division factor */
#define BOARD_GCLK5_FREQUENCY BOARD_DFLL_FREQUENCY
# if defined(CONFIG_METRO_M4_DFLL_OSC16MSRC)
# define BOARD_DFLL_SRC_FREQUENCY BOARD_OSC16M_FREQUENCY
# elif defined(CONFIG_METRO_M4_DFLL_XOSC32KSRC)
# define BOARD_DFLL_SRC_FREQUENCY BOARD_XOSC32K_FREQUENCY
# else
# error DFLL clock source not provided
# endif
#define BOARD_GCLK6_ENABLE false /* Don't enable GCLK6 */
#define BOARD_GCLK6_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK6_OOV false /* Clock output will be LOW */
#define BOARD_GCLK6_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK6_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK6_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GLCK5 source */
#define BOARD_GCLK6_DIV 1 /* Division factor */
#define BOARD_GCLK6_FREQUENCY BOARD_XOSC1_FREQUENCY
/* Mode-independent options */
#define BOARD_GCLK7_ENABLE false /* Don't enable GCLK7 */
#define BOARD_GCLK7_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK7_OOV false /* Clock output will be LOW */
#define BOARD_GCLK7_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK7_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK7_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GLCK5 source */
#define BOARD_GCLK7_DIV 1 /* Division factor */
#define BOARD_GCLK7_FREQUENCY BOARD_XOSC1_FREQUENCY
# undef BOARD_DFLL48M_RUNINSTDBY
# undef BOARD_DFLL48M_ONDEMAND
#define BOARD_GCLK8_ENABLE false /* Don't enable GCLK8 */
#define BOARD_GCLK8_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK8_OOV false /* Clock output will be LOW */
#define BOARD_GCLK8_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK8_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK8_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GLCK5 source */
#define BOARD_GCLK8_DIV 1 /* Division factor */
#define BOARD_GCLK8_FREQUENCY BOARD_XOSC1_FREQUENCY
/* DFLL open loop mode configuration */
#define BOARD_GCLK9_ENABLE false /* Don't enable GCLK9 */
#define BOARD_GCLK9_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK9_OOV false /* Clock output will be LOW */
#define BOARD_GCLK9_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK9_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK9_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GLCK5 source */
#define BOARD_GCLK9_DIV 1 /* Division factor */
#define BOARD_GCLK10_FREQUENCY BOARD_XOSC1_FREQUENCY
# define BOARD_DFLL48M_COARSEVALUE (0x1f / 4)
# define BOARD_DFLL48M_FINEVALUE (0xff / 4)
#define BOARD_GCLK10_ENABLE false /* Don't enable GCLK10 */
#define BOARD_GCLK10_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK10_OOV false /* Clock output will be LOW */
#define BOARD_GCLK10_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK10_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK10_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GLCK5 source */
#define BOARD_GCLK10_DIV 1 /* Division factor */
#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY
/* DFLL closed loop mode configuration */
#define BOARD_GCLK11_ENABLE false /* Don't enable GCLK11 */
#define BOARD_GCLK11_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK11_OOV false /* Clock output will be LOW */
#define BOARD_GCLK11_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK11_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK11_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GLCK5 source */
#define BOARD_GCLK11_DIV 1 /* Division factor */
#define BOARD_GCLK0_FREQUENCY BOARD_XOSC1_FREQUENCY
# define BOARD_DFLL48M_REFCLK_CLKGEN 1
# define BOARD_DFLL48M_MULTIPLIER (48000000 / BOARD_DFLL_SRC_FREQUENCY)
# define BOARD_DFLL48M_QUICKLOCK 1
# define BOARD_DFLL48M_TRACKAFTERFINELOCK 1
# define BOARD_DFLL48M_KEEPLOCKONWAKEUP 1
# define BOARD_DFLL48M_ENABLECHILLCYCLE 1
# define BOARD_DFLL48M_MAXCOARSESTEP (0x1f / 4)
# define BOARD_DFLL48M_MAXFINESTEP (0xff / 4)
/* Peripheral clocking */
# ifdef CONFIG_METRO_M4_DFLL_OPENLOOP
# define BOARD_DFLL48M_FREQUENCY (13720000) /* REVISIT: Needs to be measured */
# else
# define BOARD_DFLL48M_FREQUENCY (BOARD_DFLL48M_MULTIPLIER * BOARD_DFLL_SRC_FREQUENCY)
# endif
#endif
/* Fractional Digital Phase Locked Loop configuration.
*
* BOARD_FDPLL96M_ENABLE - Boolean (defined / not defined)
* BOARD_FDPLL96M_RUNINSTDBY - Boolean (defined / not defined)
* BOARD_FDPLL96M_ONDEMAND - Boolean (defined / not defined)
* BOARD_FDPLL96M_LBYPASS - Boolean (defined / not defined)
* BOARD_FDPLL96M_WUF - Boolean (defined / not defined)
* BOARD_FDPLL96M_LPEN - Boolean (defined / not defined)
* BOARD_FDPLL96M_FILTER - See OSCCTRL_DPLLCTRLB_FILTER_* definitions
* BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* definitions
* BOARD_FDPLL96M_REFCLK_CLKGEN - GCLK index in the range {0..8}
* BOARD_FDPLL96M_LOCKTIME_ENABLE - Boolean (defined / not defined)
* BOARD_FDPLL96M_LOCKTIME - See OSCCTRL_DPLLCTRLB_LTIME_* definitions
* BOARD_FDPLL96M_LOCKTIME_CLKGEN - GCLK index in the range {0..8}
* BOARD_FDPLL96M_REFDIV - Numeric value, 1 - 2047
* BOARD_FDPLL96M_PRESCALER - See OSCCTRL_DPLLPRESC_* definitions
* BOARD_FDPLL96M_REFFREQ - Numeric value
* BOARD_FDPLL96M_FREQUENCY - Numeric value
*/
#undef BOARD_FDPLL96M_ENABLE
#undef BOARD_FDPLL96M_RUNINSTDBY
#define BOARD_FDPLL96M_ONDEMAND 1
#undef BOARD_FDPLL96M_LBYPASS
#undef BOARD_FDPLL96M_WUF
#undef BOARD_FDPLL96M_LPEN
#define BOARD_FDPLL96M_FILTER OSCCTRL_DPLLCTRLB_FILTER_DEFAULT
#define BOARD_FDPLL96M_REFCLK OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K
#define BOARD_FDPLL96M_REFCLK_CLKGEN 1
#undef BOARD_FDPLL96M_LOCKTIME_ENABLE
#define BOARD_FDPLL96M_LOCKTIME OSCCTRL_DPLLCTRLB_LTIME_NONE
#define BOARD_FDPLL96M_LOCKTIME_CLKGEN 1
#define BOARD_FDPLL96M_REFDIV 1
#define BOARD_FDPLL96M_PRESCALER OSCCTRL_DPLLPRESC_DIV1
#define BOARD_FDPLL96M_REFFREQ 32768
#define BOARD_FDPLL96M_FREQUENCY 48000000
/* GCLK Configuration
*
* Global enable/disable.
*
* BOARD_GCLK_ENABLE - *MUST* be defined
*
* For n=1-7:
* BOARD_GCLKn_ENABLE - Boolean (defined / not defined)
*
* For n=0-8:
* BOARD_GCLKn_RUN_IN_STANDBY - Boolean (defined / not defined)
* BOARD_GCLKn_CLOCK_SOURCE - See GCLK_GENCTRL_SRC_* definitions
* BOARD_GCLKn_PRESCALER - Value
* BOARD_GCLKn_OUTPUT_ENABLE - Boolean (defined / not defined)
*/
#define BOARD_GCLK_ENABLE 1
/* GCLK generator 0 (Main Clock) - Source is the DFLL */
#ifdef CONFIG_METRO_M4_DFLL
# undef BOARD_GCLK0_RUN_IN_STANDBY
# define BOARD_GCLK0_CLOCK_SOURCE GCLK_GENCTRL_SRC_DFLL48M
# define BOARD_GCLK0_PRESCALER 1
# undef BOARD_GCLK0_OUTPUT_ENABLE
# define BOARD_GCLK0_FREQUENCY (BOARD_DFLL48M_FREQUENCY / BOARD_GCLK0_PRESCALER)
#else
# undef BOARD_GCLK0_RUN_IN_STANDBY
# define BOARD_GCLK0_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
# define BOARD_GCLK0_PRESCALER 1
# undef BOARD_GCLK0_OUTPUT_ENABLE
# define BOARD_GCLK0_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK0_PRESCALER)
#endif
/* Configure GCLK generator 1 - Drives the DFLL */
#if defined(CONFIG_METRO_M4_DFLL_OSC16MSRC)
# define BOARD_GCLK1_ENABLE 1
# undef BOARD_GCLK1_RUN_IN_STANDBY
# define BOARD_GCLK1_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
# define BOARD_GCLK1_PRESCALER 1
# undef BOARD_GCLK1_OUTPUT_ENABLE
# define BOARD_GCLK1_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK1_PRESCALER)
#elif defined(CONFIG_METRO_M4_DFLL_XOSC32KSRC)
# define BOARD_GCLK1_ENABLE 1
# undef BOARD_GCLK1_RUN_IN_STANDBY
# define BOARD_GCLK1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
# define BOARD_GCLK1_PRESCALER 1
# undef BOARD_GCLK1_OUTPUT_ENABLE
# define BOARD_GCLK1_FREQUENCY (BOARD_XOSC32K_FREQUENCY / BOARD_GCLK1_PRESCALER)
#else
# error DFLL clock source not provided
#endif
/* Configure GCLK generator 2 (RTC) */
#undef BOARD_GCLK2_ENABLE
#undef BOARD_GCLK2_RUN_IN_STANDBY
#define BOARD_GCLK2_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC32K
#define BOARD_GCLK2_PRESCALER 32
#undef BOARD_GCLK2_OUTPUT_ENABLE
#define BOARD_GCLK2_FREQUENCY (BOARD_OSC32K_FREQUENCY / BOARD_GCLK2_PRESCALER)
/* Configure GCLK generator 3 */
#undef BOARD_GCLK3_ENABLE
#undef BOARD_GCLK3_RUN_IN_STANDBY
#define BOARD_GCLK3_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
#define BOARD_GCLK3_PRESCALER 1
#undef BOARD_GCLK3_OUTPUT_ENABLE
#define BOARD_GCLK3_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK3_PRESCALER)
/* Configure GCLK generator 4 */
#undef BOARD_GCLK4_ENABLE
#undef BOARD_GCLK4_RUN_IN_STANDBY
#define BOARD_GCLK4_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
#define BOARD_GCLK4_PRESCALER 1
#undef BOARD_GCLK4_OUTPUT_ENABLE
#define BOARD_GCLK4_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK4_PRESCALER)
/* Configure GCLK generator 5 */
#undef BOARD_GCLK5_ENABLE
#undef BOARD_GCLK5_RUN_IN_STANDBY
#define BOARD_GCLK5_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
#define BOARD_GCLK5_PRESCALER 1
#undef BOARD_GCLK5_OUTPUT_ENABLE
#define BOARD_GCLK5_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK5_PRESCALER)
/* Configure GCLK generator 6 */
#undef BOARD_GCLK6_ENABLE
#undef BOARD_GCLK6_RUN_IN_STANDBY
#define BOARD_GCLK6_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
#define BOARD_GCLK6_PRESCALER 1
#undef BOARD_GCLK6_OUTPUT_ENABLE
#define BOARD_GCLK6_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK6_PRESCALER)
/* Configure GCLK generator 7 */
#undef BOARD_GCLK7_ENABLE
#undef BOARD_GCLK7_RUN_IN_STANDBY
#define BOARD_GCLK7_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
#define BOARD_GCLK7_PRESCALER 1
#undef BOARD_GCLK7_OUTPUT_ENABLE
#define BOARD_GCLK7_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK7_PRESCALER)
/* Configure GCLK generator 8 */
#undef BOARD_GCLK8_ENABLE
#undef BOARD_GCLK8_RUN_IN_STANDBY
#define BOARD_GCLK8_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
#define BOARD_GCLK8_PRESCALER 1
#undef BOARD_GCLK8_OUTPUT_ENABLE
#define BOARD_GCLK8_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK8_PRESCALER)
/* The source of the main clock is always GCLK_MAIN. Also called GCLKGEN[0], this is
* the clock feeding the Power Manager. The Power Manager, in turn, generates main
* clock which is divided down to produce the CPU, AHB, and APB clocks.
*
* The main clock is initially OSC16M divided by 8.
*/
#define BOARD_GCLK_MAIN_FREQUENCY BOARD_GCLK0_FREQUENCY
/* Main clock dividers
*
* BOARD_CPU_DIVIDER - See MCLK_CPUDIV_DIV* definitions
* BOARD_CPU_FRQUENCY - In Hz
* BOARD_CPU_FAILDECT - Boolean (defined / not defined)
* BOARD_LOWPOWER_DIVIDER - See MCLK_LPDIV_DIV_* definitions
* BOARD_LOWPOWER_FREQUENCY - In Hz
* BOARD_BACKUP_DIVIDER - See MCLK_BUPDIV_DIV_* definitions
* BOARD_BACKUP_FREQUENCY - In Hz
*/
#undef BOARD_CPU_FAILDECT
#define BOARD_CPU_DIVIDER MCLK_CPUDIV_DIV1
#define BOARD_LOWPOWER_DIVIDER MCLK_LPDIV_DIV1
#define BOARD_BACKUP_DIVIDER MCLK_BUPDIV_DIV1
/* Resulting frequencies */
#define BOARD_MCK_FREQUENCY (BOARD_GCLK_MAIN_FREQUENCY)
#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY)
#define BOARD_LOWPOWER_FREQUENCY (BOARD_MCK_FREQUENCY)
#define BOARD_BACKUP_FREQUENCY (BOARD_MCK_FREQUENCY)
#define BOARD_APBA_FREQUENCY (BOARD_MCK_FREQUENCY)
#define BOARD_APBB_FREQUENCY (BOARD_MCK_FREQUENCY)
#define BOARD_APBC_FREQUENCY (BOARD_MCK_FREQUENCY)
#define BOARD_APBD_FREQUENCY (BOARD_MCK_FREQUENCY)
#define BOARD_APBE_FREQUENCY (BOARD_MCK_FREQUENCY)
#define BOARD_GLCK_EIC 4 /* EIC GLCK index */
/* FLASH wait states
*
* REVISIT: These values come from the SAMD20
* Vdd Range Wait states Maximum Operating Frequency
* ------------- -------------- ---------------------------
* 1.62V to 2.7V 0 14 MHz
* 1 28 MHz
* 2 42 MHz
* 3 48 MHz
* 2.7V to 3.63V 0 24 MHz
* 1 48 MHz
* Vdd Range Wait states Maximum Operating Frequency
* --------- ----------- ---------------------------
* > 2.7V 0 24 MHz
* 1 51 MHz
* 2 77 MHz
* 3 101 MHz
* 4 119 MHz
* 5 120 MHz
* >1.71V 0 22 MHz
* 1 44 MHz
* 2 67 MHz
* 3 89 MHz
* 4 111 MHz
* 5 120 MHz
*/
#if 0
# define BOARD_FLASH_WAITSTATES 3
#else
# define BOARD_FLASH_WAITSTATES 1
#endif
#define BOARD_FLASH_WAITSTATES 6
/* LED definitions ******************************************************************/
/* The Adafruit Metro M4 has four LEDs, but only two are controllable by software:
@ -574,6 +346,11 @@
#define BOARD_SERCOM3_PINMAP_PAD2 0 /* (not used) */
#define BOARD_SERCOM3_PINMAP_PAD3 0 /* (not used) */
#define BOARD_SERCOM3_FREQUENCY BOARD_GCLK0_FREQUENCY
#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0
#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_2
#define BOARD_SERCOM3_COREGEN 1
#define BOARD_SERCOM3_SLOWGEN 3
#define BOARD_SERCOM3_FREQUENCY BOARD_GCLK1_FREQUENCY
#endif /* __CONFIG_METRO_M4_INCLUDE_BOARD_H */