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functions and definitions renamed from lm_ to tiva_

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This commit is contained in:
Gregory Nutt 2014-03-08 15:50:26 -06:00
parent 8f5dfc3541
commit 6cd5f3d321
34 changed files with 3343 additions and 3340 deletions
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180
arch/arm/include/tiva/chip.h
View file

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/tiva/chip.h
*
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Jose Pablo Carballo <jcarballo@nx-engineering.com>
*
@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LM_CHIP_H
#define __ARCH_ARM_INCLUDE_LM_CHIP_H
#ifndef __ARCH_ARM_INCLUDE_TIVA_CHIP_H
#define __ARCH_ARM_INCLUDE_TIVA_CHIP_H
/************************************************************************************
* Included Files
@ -50,94 +50,100 @@
/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# define LM_NTIMERS 4 /* Four general purpose timers */
# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM_ETHTS /* No timestamp register */
# define LM_NSSI 2 /* Two SSI modules */
# define LM_NUARTS 2 /* Two UART modules */
# define LM_NI2C 2 /* Two I2C modules */
# define LM_NADC 1 /* One ADC module */
# define LM_NPWM 0 /* No PWM generator modules */
# define LM_NQEI 0 /* No quadrature encoders */
# define LM_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
# define LM_NCANCONTROLLER 0 /* No CAN controllers */
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 4 /* Four general purpose timers */
# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef TIVA_ETHTS /* No timestamp register */
# define TIVA_NSSI 2 /* Two SSI modules */
# define TIVA_NUARTS 2 /* Two UART modules */
# define TIVA_NI2C 2 /* Two I2C modules */
# define TIVA_NADC 1 /* One ADC module */
# define TIVA_NPWM 0 /* No PWM generator modules */
# define TIVA_NQEI 0 /* No quadrature encoders */
# define TIVA_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# define LM_NTIMERS 3 /* Three general purpose timers */
# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM_ETHTS /* No timestamp register */
# define LM_NSSI 1 /* One SSI module */
# define LM_NUARTS 2 /* Two UART modules */
# define LM_NI2C 1 /* Two I2C modules */
# define LM_NADC 1 /* One ADC module */
# define LM_NPWM 1 /* One PWM generator module */
# define LM_NQEI 0 /* No quadrature encoders */
# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
# define LM_NCANCONTROLLER 0 /* No CAN controllers */
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 3 /* Three general purpose timers */
# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef TIVA_ETHTS /* No timestamp register */
# define TIVA_NSSI 1 /* One SSI module */
# define TIVA_NUARTS 2 /* Two UART modules */
# define TIVA_NI2C 1 /* Two I2C modules */
# define TIVA_NADC 1 /* One ADC module */
# define TIVA_NPWM 1 /* One PWM generator module */
# define TIVA_NQEI 0 /* No quadrature encoders */
# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# define LM_NTIMERS 4 /* Four general purpose timers */
# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM_ETHTS /* No timestamp register */
# define LM_NSSI 1 /* One SSI module */
# define LM_NUARTS 3 /* Three UART modules */
# define LM_NI2C 2 /* Two I2C modules */
# define LM_NADC 1 /* One ADC module */
# define LM_NPWM 3 /* Three PWM generator modules */
# define LM_NQEI 2 /* Two quadrature encoders */
# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
# define LM_NCANCONTROLLER 0 /* No CAN controllers */
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 4 /* Four general purpose timers */
# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef TIVA_ETHTS /* No timestamp register */
# define TIVA_NSSI 1 /* One SSI module */
# define TIVA_NUARTS 3 /* Three UART modules */
# define TIVA_NI2C 2 /* Two I2C modules */
# define TIVA_NADC 1 /* One ADC module */
# define TIVA_NPWM 3 /* Three PWM generator modules */
# define TIVA_NQEI 2 /* Two quadrature encoders */
# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# define LM_NTIMERS 4 /* Four general purpose timers */
# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM_ETHTS /* No timestamp register */
# define LM_NSSI 2 /* Two SSI modules */
# define LM_NUARTS 3 /* Three UART modules */
# define LM_NI2C 2 /* Two I2C modules */
# define LM_NADC 2 /* Two ADC module */
# define LM_CAN 2 /* Two CAN module */
# define LM_NPWM 4 /* Four PWM generator modules */
# define LM_NQEI 2 /* Two quadrature encoders */
# define LM_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
# define LM_NCANCONTROLLER 0 /* No CAN controllers */
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 4 /* Four general purpose timers */
# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef TIVA_ETHTS /* No timestamp register */
# define TIVA_NSSI 2 /* Two SSI modules */
# define TIVA_NUARTS 3 /* Three UART modules */
# define TIVA_NI2C 2 /* Two I2C modules */
# define TIVA_NADC 2 /* Two ADC module */
# define TIVA_CAN 2 /* Two CAN module */
# define TIVA_NPWM 4 /* Four PWM generator modules */
# define TIVA_NQEI 2 /* Two quadrature encoders */
# define TIVA_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# define LM_NTIMERS 6 /* Four general purpose timers */
# define LM_NWIDETIMERS 0 /* No general purpose wide timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LM_NSSI 1 /* One SSI module */
# define LM_NUARTS 3 /* Two UART modules */
# define LM_NI2C 2 /* One I2C module */
# define LM_NADC 1 /* One ADC module */
# define LM_NPWM 3 /* Three PWM generator modules */
# define LM_NQEI 2 /* Two quadrature encoders */
# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
# define LM_NCANCONTROLLER 1 /* One CAN controller */
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 6 /* Four general purpose timers */
# define TIVA_NWIDETIMERS 0 /* No general purpose wide timers */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# define TIVA_NSSI 1 /* One SSI module */
# define TIVA_NUARTS 3 /* Two UART modules */
# define TIVA_NI2C 2 /* One I2C module */
# define TIVA_NADC 1 /* One ADC module */
# define TIVA_NPWM 3 /* Three PWM generator modules */
# define TIVA_NQEI 2 /* Two quadrature encoders */
# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
#elif defined(CONFIG_ARCH_CHIP_LM4F120)
# undef LM3S /* Not LM3S family */
# define LM4F 1 /* LM4F family */
# define LM_NTIMERS 6 /* Six general purpose timers */
# define LM_NWIDETIMERS 6 /* Six general purpose wide timers */
# define LM_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LM_NSSI 4 /* Four SSI module */
# define LM_NUARTS 8 /* Eight UART modules */
# define LM_NI2C 4 /* Four I2C modules */
# define LM_NADC 2 /* Two ADC modules */
# define LM_NPWM 0 /* No PWM generator modules */
# define LM_NQEI 0 /* No quadrature encoders */
# define LM_NPORTS 6 /* 6 Ports (GPIOA-F), 0-43 GPIOs */
# define LM_NCANCONTROLLER 1 /* One CAN controller */
# undef LM3S /* Not LM3S family */
# define LM4F 1 /* LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 6 /* Six general purpose timers */
# define TIVA_NWIDETIMERS 6 /* Six general purpose wide timers */
# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
# define TIVA_NSSI 4 /* Four SSI module */
# define TIVA_NUARTS 8 /* Eight UART modules */
# define TIVA_NI2C 4 /* Four I2C modules */
# define TIVA_NADC 2 /* Two ADC modules */
# define TIVA_NPWM 0 /* No PWM generator modules */
# define TIVA_NQEI 0 /* No quadrature encoders */
# define TIVA_NPORTS 6 /* 6 Ports (GPIOA-F), 0-43 GPIOs */
# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
#else
# error "Capabilities not specified for this Stellaris chip"
#endif
@ -214,4 +220,4 @@
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LM_CHIP_H */
#endif /* __ARCH_ARM_INCLUDE_TIVA_CHIP_H */

268
arch/arm/include/tiva/irq.h
View file

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LM_IRQ_H
#define __ARCH_ARM_INCLUDE_LM_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_TIVA_IRQ_H
#define __ARCH_ARM_INCLUDE_TIVA_IRQ_H
/************************************************************************************
* Included Files
@ -49,41 +49,41 @@
************************************************************************************/
/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
#if LM_NPORTS < 1 && !defined(CONFIG_LM_DISABLE_GPIOA_IRQS)
# define CONFIG_LM_DISABLE_GPIOA_IRQS
#elif LM_NPORTS < 2 && !defined(CONFIG_LM_DISABLE_GPIOB_IRQS)
# define CONFIG_LM_DISABLE_GPIOB_IRQS
#elif LM_NPORTS < 3 && !defined(CONFIG_LM_DISABLE_GPIOC_IRQS)
# define CONFIG_LM_DISABLE_GPIOC_IRQS
#elif LM_NPORTS < 4 && !defined(CONFIG_LM_DISABLE_GPIOD_IRQS)
# define CONFIG_LM_DISABLE_GPIOD_IRQS
#elif LM_NPORTS < 5 && !defined(CONFIG_LM_DISABLE_GPIOE_IRQS)
# define CONFIG_LM_DISABLE_GPIOE_IRQS
#elif LM_NPORTS < 6 && !defined(CONFIG_LM_DISABLE_GPIOF_IRQS)
# define CONFIG_LM_DISABLE_GPIOF_IRQS
#elif LM_NPORTS < 7 && !defined(CONFIG_LM_DISABLE_GPIOG_IRQS)
# define CONFIG_LM_DISABLE_GPIOG_IRQS
#elif LM_NPORTS < 8 && !defined(CONFIG_LM_DISABLE_GPIOH_IRQS)
# define CONFIG_LM_DISABLE_GPIOH_IRQS
#elif LM_NPORTS < 9 && !defined(CONFIG_LM_DISABLE_GPIOJ_IRQS)
# define CONFIG_LM_DISABLE_GPIOJ_IRQS
#if TIVA_NPORTS < 1 && !defined(CONFIG_TIVA_DISABLE_GPIOA_IRQS)
# define CONFIG_TIVA_DISABLE_GPIOA_IRQS
#elif TIVA_NPORTS < 2 && !defined(CONFIG_TIVA_DISABLE_GPIOB_IRQS)
# define CONFIG_TIVA_DISABLE_GPIOB_IRQS
#elif TIVA_NPORTS < 3 && !defined(CONFIG_TIVA_DISABLE_GPIOC_IRQS)
# define CONFIG_TIVA_DISABLE_GPIOC_IRQS
#elif TIVA_NPORTS < 4 && !defined(CONFIG_TIVA_DISABLE_GPIOD_IRQS)
# define CONFIG_TIVA_DISABLE_GPIOD_IRQS
#elif TIVA_NPORTS < 5 && !defined(CONFIG_TIVA_DISABLE_GPIOE_IRQS)
# define CONFIG_TIVA_DISABLE_GPIOE_IRQS
#elif TIVA_NPORTS < 6 && !defined(CONFIG_TIVA_DISABLE_GPIOF_IRQS)
# define CONFIG_TIVA_DISABLE_GPIOF_IRQS
#elif TIVA_NPORTS < 7 && !defined(CONFIG_TIVA_DISABLE_GPIOG_IRQS)
# define CONFIG_TIVA_DISABLE_GPIOG_IRQS
#elif TIVA_NPORTS < 8 && !defined(CONFIG_TIVA_DISABLE_GPIOH_IRQS)
# define CONFIG_TIVA_DISABLE_GPIOH_IRQS
#elif TIVA_NPORTS < 9 && !defined(CONFIG_TIVA_DISABLE_GPIOJ_IRQS)
# define CONFIG_TIVA_DISABLE_GPIOJ_IRQS
#endif
/* Processor Exceptions (vectors 0-15) */
#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */
#define TIVA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define TIVA_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define TIVA_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define TIVA_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define TIVA_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define TIVA_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define TIVA_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define TIVA_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define TIVA_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define TIVA_IRQ_SYSTICK (15) /* Vector 15: System tick */
#if defined(CONFIG_ARCH_CHIP_LM3S)
# include <arch/tiva/lm3s_irq.h>
@ -97,133 +97,133 @@
* be disabled in order to reduce the size of the implemenation.
*/
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
# define LM_IRQ_GPIOA_0 (NR_IRQS + 0)
# define LM_IRQ_GPIOA_1 (NR_IRQS + 1)
# define LM_IRQ_GPIOA_2 (NR_IRQS + 2)
# define LM_IRQ_GPIOA_3 (NR_IRQS + 3)
# define LM_IRQ_GPIOA_4 (NR_IRQS + 4)
# define LM_IRQ_GPIOA_5 (NR_IRQS + 5)
# define LM_IRQ_GPIOA_6 (NR_IRQS + 6)
# define LM_IRQ_GPIOA_7 (NR_IRQS + 7)
# define _NGPIOAIRQS (NR_IRQS + 8)
#ifndef CONFIG_TIVA_DISABLE_GPIOA_IRQS
# define TIVA_IRQ_GPIOA_0 (NR_IRQS + 0)
# define TIVA_IRQ_GPIOA_1 (NR_IRQS + 1)
# define TIVA_IRQ_GPIOA_2 (NR_IRQS + 2)
# define TIVA_IRQ_GPIOA_3 (NR_IRQS + 3)
# define TIVA_IRQ_GPIOA_4 (NR_IRQS + 4)
# define TIVA_IRQ_GPIOA_5 (NR_IRQS + 5)
# define TIVA_IRQ_GPIOA_6 (NR_IRQS + 6)
# define TIVA_IRQ_GPIOA_7 (NR_IRQS + 7)
# define _NGPIOAIRQS (NR_IRQS + 8)
#else
# define _NGPIOAIRQS NR_IRQS
# define _NGPIOAIRQS NR_IRQS
#endif
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
# define LM_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
# define LM_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
# define LM_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
# define LM_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
# define LM_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
# define LM_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
# define LM_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
# define LM_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
# define _NGPIOBIRQS (_NGPIOAIRQS + 8)
#ifndef CONFIG_TIVA_DISABLE_GPIOB_IRQS
# define TIVA_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
# define TIVA_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
# define TIVA_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
# define TIVA_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
# define TIVA_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
# define TIVA_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
# define TIVA_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
# define TIVA_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
# define _NGPIOBIRQS (_NGPIOAIRQS + 8)
#else
# define _NGPIOBIRQS _NGPIOAIRQS
# define _NGPIOBIRQS _NGPIOAIRQS
#endif
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
# define LM_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
# define LM_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
# define LM_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
# define LM_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
# define LM_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
# define LM_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
# define LM_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
# define LM_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
#ifndef CONFIG_TIVA_DISABLE_GPIOC_IRQS
# define TIVA_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
# define TIVA_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
# define TIVA_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
# define TIVA_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
# define TIVA_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
# define TIVA_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
# define TIVA_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
# define TIVA_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
#else
# define _NGPIOCIRQS _NGPIOBIRQS
# define _NGPIOCIRQS _NGPIOBIRQS
#endif
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
# define LM_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
# define LM_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
# define LM_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
# define LM_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
# define LM_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
# define LM_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
# define LM_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
# define LM_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
#ifndef CONFIG_TIVA_DISABLE_GPIOD_IRQS
# define TIVA_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
# define TIVA_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
# define TIVA_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
# define TIVA_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
# define TIVA_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
# define TIVA_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
# define TIVA_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
# define TIVA_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
#else
# define _NGPIODIRQS _NGPIOCIRQS
# define _NGPIODIRQS _NGPIOCIRQS
#endif
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
# define LM_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
# define LM_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
# define LM_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
# define LM_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
# define LM_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
# define LM_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
# define LM_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
# define LM_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
#ifndef CONFIG_TIVA_DISABLE_GPIOE_IRQS
# define TIVA_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
# define TIVA_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
# define TIVA_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
# define TIVA_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
# define TIVA_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
# define TIVA_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
# define TIVA_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
# define TIVA_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
#else
# define _NGPIOEIRQS _NGPIODIRQS
# define _NGPIOEIRQS _NGPIODIRQS
#endif
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
# define LM_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
# define LM_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
# define LM_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
# define LM_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
# define LM_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
# define LM_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
# define LM_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
# define LM_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
#ifndef CONFIG_TIVA_DISABLE_GPIOF_IRQS
# define TIVA_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
# define TIVA_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
# define TIVA_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
# define TIVA_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
# define TIVA_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
# define TIVA_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
# define TIVA_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
# define TIVA_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
#else
# define _NGPIOFIRQS _NGPIOEIRQS
# define _NGPIOFIRQS _NGPIOEIRQS
#endif
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
# define LM_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
# define LM_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
# define LM_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
# define LM_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
# define LM_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
# define LM_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
# define LM_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
# define LM_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
# define _NGPIOGIRQS (_NGPIOFIRQS + 8)
#ifndef CONFIG_TIVA_DISABLE_GPIOG_IRQS
# define TIVA_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
# define TIVA_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
# define TIVA_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
# define TIVA_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
# define TIVA_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
# define TIVA_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
# define TIVA_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
# define TIVA_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
# define _NGPIOGIRQS (_NGPIOFIRQS + 8)
#else
# define _NGPIOGIRQS _NGPIOFIRQS
# define _NGPIOGIRQS _NGPIOFIRQS
#endif
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
# define LM_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
# define LM_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
# define LM_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
# define LM_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
# define LM_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
# define LM_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
# define LM_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
# define LM_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
# define _NGPIOHIRQS (_NGPIOGIRQS + 8)
#ifndef CONFIG_TIVA_DISABLE_GPIOH_IRQS
# define TIVA_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
# define TIVA_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
# define TIVA_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
# define TIVA_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
# define TIVA_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
# define TIVA_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
# define TIVA_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
# define TIVA_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
# define _NGPIOHIRQS (_NGPIOGIRQS + 8)
#else
# define _NGPIOHIRQS _NGPIOGIRQS
# define _NGPIOHIRQS _NGPIOGIRQS
#endif
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
# define LM_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
# define LM_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
# define LM_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
# define LM_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
# define LM_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
# define LM_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
# define LM_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
# define LM_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
# define _NGPIOJIRQS (_NGPIOHIRQS + 8)
#ifndef CONFIG_TIVA_DISABLE_GPIOJ_IRQS
# define TIVA_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
# define TIVA_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
# define TIVA_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
# define TIVA_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
# define TIVA_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
# define TIVA_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
# define TIVA_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
# define TIVA_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
# define _NGPIOJIRQS (_NGPIOHIRQS + 8)
#else
# define _NGPIOJIRQS _NGPIOHIRQS
# define _NGPIOJIRQS _NGPIOHIRQS
#endif
#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS)
#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS)
/************************************************************************************
* Public Types
@ -279,4 +279,4 @@ void gpio_irqdisable(int irq);
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_LM_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_TIVA_IRQ_H */

581
arch/arm/include/tiva/lm3s_irq.h
View file

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LM_LM3S_IRQ_H
#define __ARCH_ARM_INCLUDE_LM_LM3S_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_TIVA_LM3S_IRQ_H
#define __ARCH_ARM_INCLUDE_TIVA_LM3S_IRQ_H
/************************************************************************************
* Included Files
@ -53,338 +53,338 @@
/* External interrupts (vectors >= 16) */
#define LM_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define LM_RESERVED_25 (25) /* Vector 25: Reserved */
# define LM_RESERVED_26 (26) /* Vector 26: Reserved */
# define LM_RESERVED_27 (27) /* Vector 27: Reserved */
# define LM_RESERVED_28 (28) /* Vector 28: Reserved */
# define LM_RESERVED_29 (29) /* Vector 29: Reserved */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_RESERVED_25 (25) /* Vector 25: Reserved */
# define TIVA_RESERVED_26 (26) /* Vector 26: Reserved */
# define TIVA_RESERVED_27 (27) /* Vector 27: Reserved */
# define TIVA_RESERVED_28 (28) /* Vector 28: Reserved */
# define TIVA_RESERVED_29 (29) /* Vector 29: Reserved */
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define LM_RESERVED_43 (43) /* Vector 43: Reserved */
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
# define LM_RESERVED_49 (49) /* Vector 49: Reserved */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
# define TIVA_RESERVED_49 (49) /* Vector 49: Reserved */
# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define LM_RESERVED_54 (54) /* Vector 54: Reserved */
# define LM_RESERVED_55 (55) /* Vector 55: Reserved */
# define LM_RESERVED_56 (56) /* Vector 56: Reserved */
# define LM_RESERVED_57 (57) /* Vector 57: Reserved */
# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_RESERVED_54 (54) /* Vector 54: Reserved */
# define TIVA_RESERVED_55 (55) /* Vector 55: Reserved */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define LM_RESERVED_60 (60) /* Vector 60: Reserved */
# define LM_RESERVED_61 (61) /* Vector 61: Reserved */
# define LM_RESERVED_62 (62) /* Vector 62: Reserved */
# define LM_RESERVED_63 (63) /* Vector 63: Reserved */
# define LM_RESERVED_64 (64) /* Vector 64: Reserved */
# define LM_RESERVED_65 (65) /* Vector 65: Reserved */
# define LM_RESERVED_66 (66) /* Vector 66: Reserved */
# define LM_RESERVED_67 (67) /* Vector 67: Reserved */
# define LM_RESERVED_68 (68) /* Vector 68: Reserved */
# define LM_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_RESERVED_60 (60) /* Vector 60: Reserved */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_RESERVED_62 (62) /* Vector 62: Reserved */
# define TIVA_RESERVED_63 (63) /* Vector 63: Reserved */
# define TIVA_RESERVED_64 (64) /* Vector 64: Reserved */
# define TIVA_RESERVED_65 (65) /* Vector 65: Reserved */
# define TIVA_RESERVED_66 (66) /* Vector 66: Reserved */
# define TIVA_RESERVED_67 (67) /* Vector 67: Reserved */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define LM_RESERVED_25 (25) /* Vector 25: Reserved */
# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define LM_RESERVED_27 (27) /* Vector 27: Reserved */
# define LM_RESERVED_28 (28) /* Vector 28: Reserved */
# define LM_RESERVED_29 (29) /* Vector 29: Reserved */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_RESERVED_25 (25) /* Vector 25: Reserved */
# define TIVA_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define TIVA_RESERVED_27 (27) /* Vector 27: Reserved */
# define TIVA_RESERVED_28 (28) /* Vector 28: Reserved */
# define TIVA_RESERVED_29 (29) /* Vector 29: Reserved */
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define LM_RESERVED_43 (43) /* Vector 43: Reserved */
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define LM_RESERVED_48 (48) /* Vector 48: Reserved */
# define LM_RESERVED_49 (49) /* Vector 49: Reserved */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
# define TIVA_RESERVED_49 (49) /* Vector 49: Reserved */
# define LM_RESERVED_50 (50) /* Vector 50: Reserved */
# define LM_RESERVED_51 (51) /* Vector 51: Reserved */
# define LM_RESERVED_52 (52) /* Vector 52: Reserved */
# define LM_RESERVED_53 (53) /* Vector 53: Reserved */
# define LM_RESERVED_54 (54) /* Vector 54: Reserved */
# define LM_RESERVED_55 (55) /* Vector 55: Reserved */
# define LM_RESERVED_56 (56) /* Vector 56: Reserved */
# define LM_RESERVED_57 (57) /* Vector 57: Reserved */
# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define LM_RESERVED_59 (59) /* Vector 59: Reserved */
# define TIVA_RESERVED_50 (50) /* Vector 50: Reserved */
# define TIVA_RESERVED_51 (51) /* Vector 51: Reserved */
# define TIVA_RESERVED_52 (52) /* Vector 52: Reserved */
# define TIVA_RESERVED_53 (53) /* Vector 53: Reserved */
# define TIVA_RESERVED_54 (54) /* Vector 54: Reserved */
# define TIVA_RESERVED_55 (55) /* Vector 55: Reserved */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_RESERVED_59 (59) /* Vector 59: Reserved */
# define LM_RESERVED_60 (60) /* Vector 60: Reserved */
# define LM_RESERVED_61 (61) /* Vector 61: Reserved */
# define LM_RESERVED_62 (62) /* Vector 62: Reserved */
# define LM_RESERVED_63 (63) /* Vector 63: Reserved */
# define LM_RESERVED_64 (64) /* Vector 64: Reserved */
# define LM_RESERVED_65 (65) /* Vector 65: Reserved */
# define LM_RESERVED_66 (66) /* Vector 66: Reserved */
# define LM_RESERVED_67 (67) /* Vector 67: Reserved */
# define LM_RESERVED_68 (68) /* Vector 68: Reserved */
# define LM_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_RESERVED_60 (60) /* Vector 60: Reserved */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_RESERVED_62 (62) /* Vector 62: Reserved */
# define TIVA_RESERVED_63 (63) /* Vector 63: Reserved */
# define TIVA_RESERVED_64 (64) /* Vector 64: Reserved */
# define TIVA_RESERVED_65 (65) /* Vector 65: Reserved */
# define TIVA_RESERVED_66 (66) /* Vector 66: Reserved */
# define TIVA_RESERVED_67 (67) /* Vector 67: Reserved */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define TIVA_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define TIVA_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define TIVA_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define LM_RESERVED_43 (43) /* Vector 43: Reserved */
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define LM_RESERVED_48 (48) /* Vector 48: Reserved */
# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
# define LM_RESERVED_50 (50) /* Vector 50: Reserved */
# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define LM_RESERVED_55 (55) /* Vector 55: Reserved */
# define LM_RESERVED_56 (56) /* Vector 56: Reserved */
# define LM_RESERVED_57 (57) /* Vector 57: Reserved */
# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_RESERVED_50 (50) /* Vector 50: Reserved */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define TIVA_RESERVED_55 (55) /* Vector 55: Reserved */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define LM_RESERVED_60 (60) /* Vector 60: Reserved */
# define LM_RESERVED_61 (61) /* Vector 61: Reserved */
# define LM_RESERVED_62 (62) /* Vector 62: Reserved */
# define LM_RESERVED_63 (63) /* Vector 63: Reserved */
# define LM_RESERVED_64 (64) /* Vector 64: Reserved */
# define LM_RESERVED_65 (65) /* Vector 65: Reserved */
# define LM_RESERVED_66 (66) /* Vector 66: Reserved */
# define LM_RESERVED_67 (67) /* Vector 67: Reserved */
# define LM_RESERVED_68 (68) /* Vector 68: Reserved */
# define LM_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_RESERVED_60 (60) /* Vector 60: Reserved */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_RESERVED_62 (62) /* Vector 62: Reserved */
# define TIVA_RESERVED_63 (63) /* Vector 63: Reserved */
# define TIVA_RESERVED_64 (64) /* Vector 64: Reserved */
# define TIVA_RESERVED_65 (65) /* Vector 65: Reserved */
# define TIVA_RESERVED_66 (66) /* Vector 66: Reserved */
# define TIVA_RESERVED_67 (67) /* Vector 67: Reserved */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define TIVA_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define TIVA_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define TIVA_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define LM_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define LM_IRQ_CAN0 (55) /* Vector 55: CAN 1 */
# define LM_IRQ_CAN1 (56) /* Vector 56: CAN 2 */
# define LM_RESERVED_57 (57) /* Vector 57: Reserved */
# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define LM_RESERVED_59 (59) /* Vector 59: Reserved */
# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define TIVA_IRQ_CAN0 (55) /* Vector 55: CAN 1 */
# define TIVA_IRQ_CAN1 (56) /* Vector 56: CAN 2 */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_RESERVED_59 (59) /* Vector 59: Reserved */
# define LM_IRQ_USB (60) /* Vector 60: USB */
# define LM_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */
# define LM_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
# define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
# define LM_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
# define LM_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
# define LM_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
# define LM_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
# define LM_IRQ_I2S0 (68) /* Vector 68: I2S0 */
# define LM_IRQ_EPI (69) /* Vector 69: EPI */
# define TIVA_IRQ_USB (60) /* Vector 60: USB */
# define TIVA_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */
# define TIVA_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
# define TIVA_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
# define TIVA_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
# define TIVA_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
# define TIVA_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
# define TIVA_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
# define TIVA_IRQ_I2S0 (68) /* Vector 68: I2S0 */
# define TIVA_IRQ_EPI (69) /* Vector 69: EPI */
# define LM_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
# define LM_RESERVED_71 (71) /* Vector 71: Reserved */
# define TIVA_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
# define TIVA_RESERVED_71 (71) /* Vector 71: Reserved */
# define NR_VECTORS (72)
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
# define NR_VECTORS (72)
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define TIVA_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define TIVA_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define TIVA_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define LM_RESERVED_42 (42) /* Vector 42: Reserved */
# define LM_RESERVED_43 (43) /* Vector 43: Reserved */
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define LM_RESERVED_48 (48) /* Vector 48: Reserved */
# define LM_RESERVED_49 (49) /* Vector 49: Reserved */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_RESERVED_42 (42) /* Vector 42: Reserved */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
# define TIVA_RESERVED_49 (49) /* Vector 49: Reserved */
# define LM_RESERVED_50 (50) /* Vector 50: Reserved */
# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define LM_IRQ_CAN0 (54) /* Vector 55: CAN0 */
# define LM_RESERVED_56 (56) /* Vector 56: Reserved */
# define LM_RESERVED_57 (57) /* Vector 57: Reserved */
# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_RESERVED_50 (50) /* Vector 50: Reserved */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define TIVA_IRQ_CAN0 (54) /* Vector 55: CAN0 */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define LM_RESERVED_60 (60) /* Vector 60: Reserved */
# define LM_RESERVED_61 (61) /* Vector 61: Reserved */
# define LM_RESERVED_62 (62) /* Vector 62: Reserved */
# define LM_RESERVED_63 (63) /* Vector 63: Reserved */
# define LM_RESERVED_64 (64) /* Vector 64: Reserved */
# define LM_RESERVED_65 (65) /* Vector 65: Reserved */
# define LM_RESERVED_66 (66) /* Vector 66: Reserved */
# define LM_RESERVED_67 (67) /* Vector 67: Reserved */
# define LM_RESERVED_68 (68) /* Vector 68: Reserved */
# define LM_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_RESERVED_60 (60) /* Vector 60: Reserved */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_RESERVED_62 (62) /* Vector 62: Reserved */
# define TIVA_RESERVED_63 (63) /* Vector 63: Reserved */
# define TIVA_RESERVED_64 (64) /* Vector 64: Reserved */
# define TIVA_RESERVED_65 (65) /* Vector 65: Reserved */
# define TIVA_RESERVED_66 (66) /* Vector 66: Reserved */
# define TIVA_RESERVED_67 (67) /* Vector 67: Reserved */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
# define NR_VECTORS (71)
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
#else
# error "IRQ Numbers not specified for this Stellaris chip"
@ -413,5 +413,4 @@ extern "C"
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_LM_LM3S_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_TIVA_LM3S_IRQ_H */

290
arch/arm/include/tiva/lm4f_irq.h
View file

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LM_LM4F_IRQ_H
#define __ARCH_ARM_INCLUDE_LM_LM4F_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_TIVA_LM4F_IRQ_H
#define __ARCH_ARM_INCLUDE_TIVA_LM4F_IRQ_H
/************************************************************************************
* Included Files
@ -53,166 +53,166 @@
/* External interrupts (vectors >= 16) */
#define LM_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_LM4F120)
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define LM_RESERVED_25 (25) /* Vector 25: Reserved */
# define LM_RESERVED_26 (26) /* Vector 26: Reserved */
# define LM_RESERVED_27 (27) /* Vector 27: Reserved */
# define LM_RESERVED_28 (28) /* Vector 28: Reserved */
# define LM_RESERVED_29 (29) /* Vector 29: Reserved */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_RESERVED_25 (25) /* Vector 25: Reserved */
# define TIVA_RESERVED_26 (26) /* Vector 26: Reserved */
# define TIVA_RESERVED_27 (27) /* Vector 27: Reserved */
# define TIVA_RESERVED_28 (28) /* Vector 28: Reserved */
# define TIVA_RESERVED_29 (29) /* Vector 29: Reserved */
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
# define LM_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
# define LM_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
# define LM_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
# define LM_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
# define LM_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
# define LM_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define LM_RESERVED_43 (43) /* Vector 43: Reserved */
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define LM_RESERVED_47 (47) /* Vector 47: Reserved */
# define LM_RESERVED_48 (48) /* Vector 48: Reserved */
# define LM_IRQ_UART2 (49) /* Vector 22: UART 2 */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_RESERVED_47 (47) /* Vector 47: Reserved */
# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
# define TIVA_IRQ_UART2 (49) /* Vector 22: UART 2 */
# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define LM_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
# define LM_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define LM_RESERVED_54 (54) /* Vector 54: Reserved */
# define LM_IRQ_CAN0 (55) /* Vector 55: CAN 0 */
# define LM_RESERVED_56 (56) /* Vector 56: Reserved */
# define LM_RESERVED_57 (57) /* Vector 57: Reserved */
# define LM_RESERVED_58 (58) /* Vector 58: Reserved */
# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_RESERVED_54 (54) /* Vector 54: Reserved */
# define TIVA_IRQ_CAN0 (55) /* Vector 55: CAN 0 */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_RESERVED_58 (58) /* Vector 58: Reserved */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define LM_IRQ_USB (60) /* Vector 60: USB */
# define LM_RESERVED_61 (61) /* Vector 61: Reserved */
# define LM_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
# define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
# define LM_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
# define LM_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
# define LM_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
# define LM_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
# define LM_RESERVED_68 (68) /* Vector 68: Reserved */
# define LM_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_IRQ_USB (60) /* Vector 60: USB */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
# define TIVA_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
# define TIVA_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
# define TIVA_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
# define TIVA_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
# define TIVA_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define LM_RESERVED_70 (70) /* Vector 70: Reserved */
# define LM_RESERVED_71 (71) /* Vector 71: Reserved */
# define LM_RESERVED_72 (72) /* Vector 72: Reserved */
# define LM_IRQ_SSI2 (73) /* Vector 73: SSI 2 */
# define LM_IRQ_SSI3 (74) /* Vector 74: SSI 3 */
# define LM_IRQ_UART3 (75) /* Vector 75: UART 3 */
# define LM_IRQ_UART4 (76) /* Vector 76: UART 4 */
# define LM_IRQ_UART5 (77) /* Vector 77: UART 5 */
# define LM_IRQ_UART6 (78) /* Vector 78: UART 6 */
# define LM_IRQ_UART7 (79) /* Vector 79: UART 7 */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define TIVA_RESERVED_71 (71) /* Vector 71: Reserved */
# define TIVA_RESERVED_72 (72) /* Vector 72: Reserved */
# define TIVA_IRQ_SSI2 (73) /* Vector 73: SSI 2 */
# define TIVA_IRQ_SSI3 (74) /* Vector 74: SSI 3 */
# define TIVA_IRQ_UART3 (75) /* Vector 75: UART 3 */
# define TIVA_IRQ_UART4 (76) /* Vector 76: UART 4 */
# define TIVA_IRQ_UART5 (77) /* Vector 77: UART 5 */
# define TIVA_IRQ_UART6 (78) /* Vector 78: UART 6 */
# define TIVA_IRQ_UART7 (79) /* Vector 79: UART 7 */
# define LM_RESERVED_80 (80) /* Vector 80: Reserved */
# define LM_RESERVED_81 (81) /* Vector 81: Reserved */
# define LM_RESERVED_82 (82) /* Vector 82: Reserved */
# define LM_RESERVED_83 (83) /* Vector 83: Reserved */
# define LM_IRQ_I2C2 (84) /* Vector 84: I2C 2 */
# define LM_IRQ_I2C3 (85) /* Vector 85: I2C 3 */
# define LM_IRQ_TIMER4A (86) /* Vector 86: 16/32-Bit Timer 4 A */
# define LM_IRQ_TIMER4B (87) /* Vector 87: 16/32-Bit Timer 4 B */
# define LM_RESERVED_88 (88) /* Vector 88: Reserved */
# define LM_RESERVED_89 (89) /* Vector 89: Reserved */
# define TIVA_RESERVED_80 (80) /* Vector 80: Reserved */
# define TIVA_RESERVED_81 (81) /* Vector 81: Reserved */
# define TIVA_RESERVED_82 (82) /* Vector 82: Reserved */
# define TIVA_RESERVED_83 (83) /* Vector 83: Reserved */
# define TIVA_IRQ_I2C2 (84) /* Vector 84: I2C 2 */
# define TIVA_IRQ_I2C3 (85) /* Vector 85: I2C 3 */
# define TIVA_IRQ_TIMER4A (86) /* Vector 86: 16/32-Bit Timer 4 A */
# define TIVA_IRQ_TIMER4B (87) /* Vector 87: 16/32-Bit Timer 4 B */
# define TIVA_RESERVED_88 (88) /* Vector 88: Reserved */
# define TIVA_RESERVED_89 (89) /* Vector 89: Reserved */
# define LM_RESERVED_90 (90) /* Vector 90: Reserved */
# define LM_RESERVED_91 (91) /* Vector 91: Reserved */
# define LM_RESERVED_92 (92) /* Vector 92: Reserved */
# define LM_RESERVED_93 (93) /* Vector 93: Reserved */
# define LM_RESERVED_94 (94) /* Vector 94: Reserved */
# define LM_RESERVED_95 (95) /* Vector 95: Reserved */
# define LM_RESERVED_96 (96) /* Vector 96: Reserved */
# define LM_RESERVED_97 (97) /* Vector 97: Reserved */
# define LM_RESERVED_98 (98) /* Vector 98: Reserved */
# define LM_RESERVED_99 (99) /* Vector 99: Reserved */
# define TIVA_RESERVED_90 (90) /* Vector 90: Reserved */
# define TIVA_RESERVED_91 (91) /* Vector 91: Reserved */
# define TIVA_RESERVED_92 (92) /* Vector 92: Reserved */
# define TIVA_RESERVED_93 (93) /* Vector 93: Reserved */
# define TIVA_RESERVED_94 (94) /* Vector 94: Reserved */
# define TIVA_RESERVED_95 (95) /* Vector 95: Reserved */
# define TIVA_RESERVED_96 (96) /* Vector 96: Reserved */
# define TIVA_RESERVED_97 (97) /* Vector 97: Reserved */
# define TIVA_RESERVED_98 (98) /* Vector 98: Reserved */
# define TIVA_RESERVED_99 (99) /* Vector 99: Reserved */
# define LM_RESERVED_100 (100) /* Vector 100: Reserved */
# define LM_RESERVED_101 (101) /* Vector 101: Reserved */
# define LM_RESERVED_102 (102) /* Vector 102: Reserved */
# define LM_RESERVED_103 (103) /* Vector 103: Reserved */
# define LM_RESERVED_104 (104) /* Vector 104: Reserved */
# define LM_RESERVED_105 (105) /* Vector 105: Reserved */
# define LM_RESERVED_106 (106) /* Vector 106: Reserved */
# define LM_RESERVED_107 (107) /* Vector 107: Reserved */
# define LM_IRQ_TIMER5A (108) /* Vector 108: 16/32-Bit Timer 5 A */
# define LM_IRQ_TIMER5B (109) /* Vector 109: 16/32-Bit Timer 5 B */
# define TIVA_RESERVED_100 (100) /* Vector 100: Reserved */
# define TIVA_RESERVED_101 (101) /* Vector 101: Reserved */
# define TIVA_RESERVED_102 (102) /* Vector 102: Reserved */
# define TIVA_RESERVED_103 (103) /* Vector 103: Reserved */
# define TIVA_RESERVED_104 (104) /* Vector 104: Reserved */
# define TIVA_RESERVED_105 (105) /* Vector 105: Reserved */
# define TIVA_RESERVED_106 (106) /* Vector 106: Reserved */
# define TIVA_RESERVED_107 (107) /* Vector 107: Reserved */
# define TIVA_IRQ_TIMER5A (108) /* Vector 108: 16/32-Bit Timer 5 A */
# define TIVA_IRQ_TIMER5B (109) /* Vector 109: 16/32-Bit Timer 5 B */
# define LM_IRQ_WTIMER0A (110) /* Vector 110: 32/64-Bit Timer 0 A */
# define LM_IRQ_WTIMER0B (111) /* Vector 111: 32/64-Bit Timer 0 B */
# define LM_IRQ_WTIMER1A (112) /* Vector 112: 32/64-Bit Timer 1 A */
# define LM_IRQ_WTIMER1B (113) /* Vector 113: 32/64-Bit Timer 1 B */
# define LM_IRQ_WTIMER2A (114) /* Vector 114: 32/64-Bit Timer 2 A */
# define LM_IRQ_WTIMER2B (115) /* Vector 115: 32/64-Bit Timer 2 B */
# define LM_IRQ_WTIMER3A (116) /* Vector 116: 32/64-Bit Timer 3 A */
# define LM_IRQ_WTIMER3B (117) /* Vector 117: 32/64-Bit Timer 3 B */
# define LM_IRQ_WTIMER4A (118) /* Vector 118: 32/64-Bit Timer 4 A */
# define LM_IRQ_WTIMER4B (119) /* Vector 119: 32/64-Bit Timer 4 B */
# define TIVA_IRQ_WTIMER0A (110) /* Vector 110: 32/64-Bit Timer 0 A */
# define TIVA_IRQ_WTIMER0B (111) /* Vector 111: 32/64-Bit Timer 0 B */
# define TIVA_IRQ_WTIMER1A (112) /* Vector 112: 32/64-Bit Timer 1 A */
# define TIVA_IRQ_WTIMER1B (113) /* Vector 113: 32/64-Bit Timer 1 B */
# define TIVA_IRQ_WTIMER2A (114) /* Vector 114: 32/64-Bit Timer 2 A */
# define TIVA_IRQ_WTIMER2B (115) /* Vector 115: 32/64-Bit Timer 2 B */
# define TIVA_IRQ_WTIMER3A (116) /* Vector 116: 32/64-Bit Timer 3 A */
# define TIVA_IRQ_WTIMER3B (117) /* Vector 117: 32/64-Bit Timer 3 B */
# define TIVA_IRQ_WTIMER4A (118) /* Vector 118: 32/64-Bit Timer 4 A */
# define TIVA_IRQ_WTIMER4B (119) /* Vector 119: 32/64-Bit Timer 4 B */
# define LM_IRQ_WTIMER5A (120) /* Vector 120: 32/64-Bit Timer 5 A */
# define LM_IRQ_WTIMER5B (121) /* Vector 121: 32/64-Bit Timer 5 B */
# define LM_IRQ_SYSTEM (122) /* Vector 122: System Exception (imprecise) */
# define LM_RESERVED_123 (123) /* Vector 123: Reserved */
# define LM_RESERVED_124 (124) /* Vector 124: Reserved */
# define LM_RESERVED_125 (125) /* Vector 125: Reserved */
# define LM_RESERVED_126 (126) /* Vector 126: Reserved */
# define LM_RESERVED_127 (127) /* Vector 127: Reserved */
# define LM_RESERVED_128 (128) /* Vector 128: Reserved */
# define LM_RESERVED_129 (129) /* Vector 129: Reserved */
# define TIVA_IRQ_WTIMER5A (120) /* Vector 120: 32/64-Bit Timer 5 A */
# define TIVA_IRQ_WTIMER5B (121) /* Vector 121: 32/64-Bit Timer 5 B */
# define TIVA_IRQ_SYSTEM (122) /* Vector 122: System Exception (imprecise) */
# define TIVA_RESERVED_123 (123) /* Vector 123: Reserved */
# define TIVA_RESERVED_124 (124) /* Vector 124: Reserved */
# define TIVA_RESERVED_125 (125) /* Vector 125: Reserved */
# define TIVA_RESERVED_126 (126) /* Vector 126: Reserved */
# define TIVA_RESERVED_127 (127) /* Vector 127: Reserved */
# define TIVA_RESERVED_128 (128) /* Vector 128: Reserved */
# define TIVA_RESERVED_129 (129) /* Vector 129: Reserved */
# define LM_RESERVED_130 (130) /* Vector 130: Reserved */
# define LM_RESERVED_131 (131) /* Vector 131: Reserved */
# define LM_RESERVED_132 (132) /* Vector 132: Reserved */
# define LM_RESERVED_133 (133) /* Vector 133: Reserved */
# define LM_RESERVED_134 (134) /* Vector 134: Reserved */
# define LM_RESERVED_135 (135) /* Vector 135: Reserved */
# define LM_RESERVED_136 (136) /* Vector 136: Reserved */
# define LM_RESERVED_137 (137) /* Vector 137: Reserved */
# define LM_RESERVED_138 (138) /* Vector 138: Reserved */
# define LM_RESERVED_139 (139) /* Vector 139: Reserved */
# define TIVA_RESERVED_130 (130) /* Vector 130: Reserved */
# define TIVA_RESERVED_131 (131) /* Vector 131: Reserved */
# define TIVA_RESERVED_132 (132) /* Vector 132: Reserved */
# define TIVA_RESERVED_133 (133) /* Vector 133: Reserved */
# define TIVA_RESERVED_134 (134) /* Vector 134: Reserved */
# define TIVA_RESERVED_135 (135) /* Vector 135: Reserved */
# define TIVA_RESERVED_136 (136) /* Vector 136: Reserved */
# define TIVA_RESERVED_137 (137) /* Vector 137: Reserved */
# define TIVA_RESERVED_138 (138) /* Vector 138: Reserved */
# define TIVA_RESERVED_139 (139) /* Vector 139: Reserved */
# define LM_RESERVED_140 (140) /* Vector 140: Reserved */
# define LM_RESERVED_141 (141) /* Vector 141: Reserved */
# define LM_RESERVED_142 (142) /* Vector 142: Reserved */
# define LM_RESERVED_143 (143) /* Vector 143: Reserved */
# define LM_RESERVED_144 (144) /* Vector 144: Reserved */
# define LM_RESERVED_145 (145) /* Vector 145: Reserved */
# define LM_RESERVED_146 (146) /* Vector 146: Reserved */
# define LM_RESERVED_147 (147) /* Vector 147: Reserved */
# define LM_RESERVED_148 (148) /* Vector 148: Reserved */
# define LM_RESERVED_149 (149) /* Vector 149: Reserved */
# define TIVA_RESERVED_140 (140) /* Vector 140: Reserved */
# define TIVA_RESERVED_141 (141) /* Vector 141: Reserved */
# define TIVA_RESERVED_142 (142) /* Vector 142: Reserved */
# define TIVA_RESERVED_143 (143) /* Vector 143: Reserved */
# define TIVA_RESERVED_144 (144) /* Vector 144: Reserved */
# define TIVA_RESERVED_145 (145) /* Vector 145: Reserved */
# define TIVA_RESERVED_146 (146) /* Vector 146: Reserved */
# define TIVA_RESERVED_147 (147) /* Vector 147: Reserved */
# define TIVA_RESERVED_148 (148) /* Vector 148: Reserved */
# define TIVA_RESERVED_149 (149) /* Vector 149: Reserved */
# define LM_RESERVED_150 (150) /* Vector 150: Reserved */
# define LM_RESERVED_151 (151) /* Vector 151: Reserved */
# define LM_RESERVED_152 (152) /* Vector 152: Reserved */
# define LM_RESERVED_153 (153) /* Vector 153: Reserved */
# define LM_RESERVED_154 (154) /* Vector 154: Reserved */
# define TIVA_RESERVED_150 (150) /* Vector 150: Reserved */
# define TIVA_RESERVED_151 (151) /* Vector 151: Reserved */
# define TIVA_RESERVED_152 (152) /* Vector 152: Reserved */
# define TIVA_RESERVED_153 (153) /* Vector 153: Reserved */
# define TIVA_RESERVED_154 (154) /* Vector 154: Reserved */
# define NR_VECTORS (155)
# define NR_IRQS (123) /* (Really fewer because of reserved vectors) */
# define NR_VECTORS (155)
# define NR_IRQS (123) /* (Really fewer because of reserved vectors) */
#else
# error "IRQ Numbers not known for this Stellaris chip"
@ -241,5 +241,5 @@ extern "C"
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_LM_LM4F_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_TIVA_LM4F_IRQ_H */

67
arch/arm/src/tiva/Kconfig
View file

@ -15,7 +15,7 @@ config ARCH_CHIP_LM3S6918
depends on ARCH_CHIP_LM
select ARCH_CORTEXM3
select ARCH_CHIP_LM3S
select LM_HAVE_SSI1
select TIVA_HAVE_SSI1
config ARCH_CHIP_LM3S9B96
bool "LM3S9B96"
@ -61,58 +61,59 @@ config ARCH_CHIP_LM4F
config ARCH_CHIP_TM4C
bool
config LM_HAVE_SSI1
config TIVA_HAVE_SSI1
bool
config LM_REVA2
bool "Rev A2"
default n
depends on ARCH_CHIP_LM
---help---
Some early silicon returned an increase LDO voltage or 2.75V to work
around a PLL bug
menu "Tiva/Stellaris Peripheral Support"
config LM_UART0
config TIVA_UART0
bool "UART0"
select ARCH_HAVE_UART0
default n
config LM_UART1
config TIVA_UART1
bool "UART1"
select ARCH_HAVE_UART1
default n
config LM_UART2
config TIVA_UART2
bool "UART2"
select ARCH_HAVE_UART2
default n
config LM_UART3
config TIVA_UART3
bool "UART3"
default n
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
select ARCH_HAVE_UART3
config LM_UART4
config TIVA_UART4
bool "UART4"
default n
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
select ARCH_HAVE_UART4
config LM_UART5
config TIVA_UART5
bool "UART5"
default n
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
select ARCH_HAVE_UART5
config LM_UART6
config TIVA_UART6
bool "UART6"
default n
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
select ARCH_HAVE_UART6
config LM_UART7
config TIVA_UART7
bool "UART7"
default n
depends on ARCH_CHIP_LM4F || ARCH_CHIP_TM4C
@ -126,14 +127,14 @@ config SSI1_DISABLE
bool "Disable SSI1"
default y
config LM_ETHERNET
config TIVA_ETHERNET
bool "Ethernet"
default n
select NETDEVICES
---help---
This must be set (along with NET) to build the Stellaris Ethernet driver.
config LM_FLASH
config TIVA_FLASH
bool "Internal FLASH driver"
default n
---help---
@ -143,95 +144,95 @@ endmenu
menu "Disable GPIO Interrupts"
config LM_DISABLE_GPIOA_IRQS
config TIVA_DISABLE_GPIOA_IRQS
bool "Disable GPIOA IRQs"
default n
config LM_DISABLE_GPIOB_IRQS
config TIVA_DISABLE_GPIOB_IRQS
bool "Disable GPIOB IRQs"
default n
config LM_DISABLE_GPIOC_IRQS
config TIVA_DISABLE_GPIOC_IRQS
bool "Disable GPIOC IRQs"
default n
config LM_DISABLE_GPIOD_IRQS
config TIVA_DISABLE_GPIOD_IRQS
bool "Disable GPIOD IRQs"
default n
config LM_DISABLE_GPIOE_IRQS
config TIVA_DISABLE_GPIOE_IRQS
bool "Disable GPIOE IRQs"
default n
config LM_DISABLE_GPIOF_IRQS
config TIVA_DISABLE_GPIOF_IRQS
bool "Disable GPIOF IRQs"
default n
config LM_DISABLE_GPIOG_IRQS
config TIVA_DISABLE_GPIOG_IRQS
bool "Disable GPIOG IRQs"
default n
config LM_DISABLE_GPIOH_IRQS
config TIVA_DISABLE_GPIOH_IRQS
bool "Disable GPIOH IRQs"
default n
config LM_DISABLE_GPIOJ_IRQS
config TIVA_DISABLE_GPIOJ_IRQS
bool "Disable GPIOJ IRQs"
default n
endmenu
if LM_ETHERNET
if TIVA_ETHERNET
menu "Tiva/Stellaris Ethernet Configuration"
config LM_ETHLEDS
config TIVA_ETHLEDS
bool "Ethernet LEDs"
default n
---help---
Enable to use Ethernet LEDs on the board.
config LM_BOARDMAC
config TIVA_BOARDMAC
bool "Board MAC"
default n
---help---
If the board-specific logic can provide a MAC address (via
tiva_ethernetmac()), then this should be selected.
config LM_ETHHDUPLEX
config TIVA_ETHHDUPLEX
bool "Force Half Duplex"
default n
---help---
Set to force half duplex operation
config LM_ETHNOAUTOCRC
config TIVA_ETHNOAUTOCRC
bool "Disable auto-CRC"
default n
---help---
Set to suppress auto-CRC generation
config LM_ETHNOPAD
config TIVA_ETHNOPAD
bool "Disable Tx Padding"
default n
---help---
Set to suppress Tx padding
config LM_MULTICAST
config TIVA_MULTICAST
bool "Enable Multicast"
default n
---help---
Set to enable multicast frames
config LM_PROMISCUOUS
config TIVA_PROMISCUOUS
bool "Enable Promiscuous Mode"
default n
---help---
Set to enable promiscuous mode
config LM_TIMESTAMP
config TIVA_TIMESTAMP
bool "Enable Timestamping"
default n
config LM_BADCRC
config TIVA_BADCRC
bool "Enable Bad CRC Rejection"
default n
---help---
@ -262,10 +263,10 @@ config SSI_TXLIMIT
endmenu
endif
if LM_FLASH
if TIVA_FLASH
menu "Tiva/Stellaris Internal Flash Driver Configuration"
config LM_FLASH_STARTPAGE
config TIVA_FLASH_STARTPAGE
int "First page accessible by the MTD driver"
default 250
---help---

2
arch/arm/src/tiva/Make.defs
View file

@ -81,6 +81,6 @@ ifdef CONFIG_NET
CHIP_CSRCS += tiva_ethernet.c
endif
ifdef CONFIG_LM_FLASH
ifdef CONFIG_TIVA_FLASH
CHIP_CSRCS += tiva_flash.c
endif

504
arch/arm/src/tiva/chip/lm3s_memorymap.h
View file

@ -50,44 +50,44 @@
#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \
defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
/* -0x1fffffff: Reserved */
# define LM_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
/* -0x21ffffff: Reserved */
# define LM_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
/* -0x3fffffff: Reserved */
# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
/* -0x41ffffff: Peripherals */
# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000- */
/* -0xdfffffff: Reserved */
# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
/* -0xe000dfff: Reserved */
# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
/* -0xe003ffff: Reserved */
# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
/* -0xffffffff: Reserved */
# define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
/* -0x1fffffff: Reserved */
# define TIVA_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
/* -0x21ffffff: Reserved */
# define TIVA_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
/* -0x3fffffff: Reserved */
# define TIVA_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
/* -0x41ffffff: Peripherals */
# define TIVA_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000- */
/* -0xdfffffff: Reserved */
# define TIVA_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
# define TIVA_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
# define TIVA_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
/* -0xe000dfff: Reserved */
# define TIVA_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
/* -0xe003ffff: Reserved */
# define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
/* -0xffffffff: Reserved */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
/* -0x1fffffff: Reserved */
# define LM_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
/* -0x21ffffff: Reserved */
# define LM_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
/* -0x3fffffff: Reserved */
# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
/* -0x41ffffff: Peripherals */
# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
/* -0x5fffffff: Reserved */
# define LM_EPI0RAM_BASE 0x60000000 /* -0xdfffffff: EPI0 mapped peripheral and RAM */
# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
/* -0xe000dfff: Reserved */
# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
/* -0xe003ffff: Reserved */
# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
/* -0xffffffff: Reserved */
# define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
/* -0x1fffffff: Reserved */
# define TIVA_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
/* -0x21ffffff: Reserved */
# define TIVA_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
/* -0x3fffffff: Reserved */
# define TIVA_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
/* -0x41ffffff: Peripherals */
# define TIVA_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
/* -0x5fffffff: Reserved */
# define TIVA_EPI0RAM_BASE 0x60000000 /* -0xdfffffff: EPI0 mapped peripheral and RAM */
# define TIVA_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
# define TIVA_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
# define TIVA_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
/* -0xe000dfff: Reserved */
# define TIVA_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
/* -0xe003ffff: Reserved */
# define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
/* -0xffffffff: Reserved */
#else
# error "Memory map not specified for this LM3S chip"
#endif
@ -102,245 +102,245 @@
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
/* FiRM Peripheral Base Addresses */
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
/* -0x0bfff: Reserved */
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
/* -0x1ffff: Reserved */
# define TIVA_WDOG_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
# define TIVA_SSI1_BASE (TIVA_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
/* -0x0bfff: Reserved */
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
/* -0x23fff: Reserved */
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
# define LM_GPIOH_BASE (LM_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
/* -0x2ffff: Reserved */
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
/* -0x37fff: Reserved */
# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
/* -0x3bfff: Reserved */
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x47fff: Reserved */
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0xfcfff: Reserved */
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */
# define TIVA_I2CM0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define TIVA_I2CS0_BASE (TIVA_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
# define TIVA_I2CM1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
# define TIVA_I2CS1_BASE (TIVA_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
/* -0x23fff: Reserved */
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define TIVA_GPIOG_BASE (TIVA_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
# define TIVA_GPIOH_BASE (TIVA_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
/* -0x37fff: Reserved */
# define TIVA_ADC_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
/* -0x3bfff: Reserved */
# define TIVA_COMPARE_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x47fff: Reserved */
# define TIVA_ETHCON_BASE (TIVA_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0xfcfff: Reserved */
# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
/* FiRM Peripheral Base Addresses */
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
/* -0x0bfff: Reserved */
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
/* -0x1ffff: Reserved */
# define TIVA_WDOG_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
/* -0x0bfff: Reserved */
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
/* -0x23fff: Reserved */
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
/* -0x27fff: Reserved */
# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
/* -0x2ffff: Reserved */
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
/* -0x37fff: Reserved */
# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
/* -0x3bfff: Reserved */
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x47fff: Reserved */
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0xfcfff: Reserved */
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */
# define TIVA_I2CM0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define TIVA_I2CS0_BASE (TIVA_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
/* -0x23fff: Reserved */
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define TIVA_GPIOG_BASE (TIVA_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
/* -0x27fff: Reserved */
# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
/* -0x37fff: Reserved */
# define TIVA_ADC_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
/* -0x3bfff: Reserved */
# define TIVA_COMPARE_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x47fff: Reserved */
# define TIVA_ETHCON_BASE (TIVA_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0xfcfff: Reserved */
# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
/* FiRM Peripheral Base Addresses */
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
/* -0x0bfff: Reserved */
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
/* -0x1ffff: Reserved */
# define TIVA_WDOG_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
/* -0x0bfff: Reserved */
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
/* -0x23fff: Reserved */
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
/* -0x27fff: Reserved */
# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
/* -0x2bfff: Reserved */
# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
/* -0x2ffff: Reserved */
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
/* -0x37fff: Reserved */
# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
/* -0x3bfff: Reserved */
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x47fff: Reserved */
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0xfcfff: Reserved */
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */
# define TIVA_I2CM0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define TIVA_I2CS0_BASE (TIVA_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
# define TIVA_I2CM1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
# define TIVA_I2CS1_BASE (TIVA_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
/* -0x23fff: Reserved */
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define TIVA_GPIOG_BASE (TIVA_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
/* -0x27fff: Reserved */
# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
/* -0x2bfff: Reserved */
# define TIVA_QEI0_BASE (TIVA_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
# define TIVA_QEI1_BASE (TIVA_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
/* -0x37fff: Reserved */
# define TIVA_ADC_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
/* -0x3bfff: Reserved */
# define TIVA_COMPARE_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x47fff: Reserved */
# define TIVA_ETHCON_BASE (TIVA_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0xfcfff: Reserved */
# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
/* FiRM Peripheral Base Addresses */
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
/* -0x0bfff: Reserved */
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
/* -0x1ffff: Reserved */
# define TIVA_WDOG_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
/* -0x0bfff: Reserved */
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
/* -0x23fff: Reserved */
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
/* -0x27fff: Reserved */
# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
/* -0x2bfff: Reserved */
# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
/* -0x2ffff: Reserved */
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
/* -0x37fff: Reserved */
# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
/* -0x3bfff: Reserved */
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x3fffff: Reserved */
# define LM_CANCON_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */
/* -0x47fff: Reserved */
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0xfcfff: Reserved */
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */
# define TIVA_I2CM0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define TIVA_I2CS0_BASE (TIVA_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
/* -0x23fff: Reserved */
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define TIVA_GPIOG_BASE (TIVA_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
/* -0x27fff: Reserved */
# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
/* -0x2bfff: Reserved */
# define TIVA_QEI0_BASE (TIVA_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
# define TIVA_QEI1_BASE (TIVA_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
/* -0x37fff: Reserved */
# define TIVA_ADC_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
/* -0x3bfff: Reserved */
# define TIVA_COMPARE_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x3fffff: Reserved */
# define TIVA_CANCON_BASE (TIVA_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */
/* -0x47fff: Reserved */
# define TIVA_ETHCON_BASE (TIVA_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0xfcfff: Reserved */
# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
/* FiRM Peripheral Base Addresses */
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
/* -0x0bfff: Reserved */
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
/* -0x1ffff: Reserved */
# define TIVA_WDOG_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
/* -0x03fff: Reserved */
# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
# define TIVA_SSI1_BASE (TIVA_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
/* -0x0bfff: Reserved */
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
/* -0x23fff: Reserved */
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
# define LM_GPIOH_BASE (LM_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
# define TIVA_I2CM0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define TIVA_I2CS0_BASE (TIVA_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
# define TIVA_I2CM1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
# define TIVA_I2CS1_BASE (TIVA_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
/* -0x23fff: Reserved */
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define TIVA_GPIOG_BASE (TIVA_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
# define TIVA_GPIOH_BASE (TIVA_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
/* -0x2bfff: Reserved */
# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
/* -0x2ffff: Reserved */
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
/* -0x37fff: Reserved */
# define LM_ADC0_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
# define LM_ADC1_BASE (LM_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
/* -0x3bfff: Reserved */
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
# define LM_GPIOJ_BASE (LM_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */
/* -0x3ffff: Reserved */
# define LM_CAN0_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */
# define LM_CAN1_BASE (LM_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */
/* -0x47fff: Reserved */
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0x49fff: Reserved */
# define LM_USB_BASE (LM_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
/* -0x53fff: Reserved */
# define LM_I2S0_BASE (LM_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */
/* -0x57fff: Reserved */
# define LM_GPIOAAHB_BASE (LM_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
# define LM_GPIOBAHB_BASE (LM_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
# define LM_GPIOCAHB_BASE (LM_PERIPH_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */
# define LM_GPIODAHB_BASE (LM_PERIPH_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */
# define LM_GPIOEAHB_BASE (LM_PERIPH_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */
# define LM_GPIOFAHB_BASE (LM_PERIPH_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */
# define LM_GPIOGAHB_BASE (LM_PERIPH_BASE + 0x5e000) /* -0x5efff: GPIO Port G (AHB aperture) */
# define LM_GPIOHAHB_BASE (LM_PERIPH_BASE + 0x5f000) /* -0x5ffff: GPIO Port H (AHB aperture) */
# define LM_GPIOJAHB_BASE (LM_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */
/* -0xcffff: Reserved */
# define LM_EPI0_BASE (LM_PERIPH_BASE + 0xd0000) /* -0xd0fff: EPI 0 */
/* -0xfcfff: Reserved */
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
# define LM_UDMA_BASE (LM_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
/* -0x1ffffff: Reserved */
# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
/* -0x2bfff: Reserved */
# define TIVA_QEI0_BASE (TIVA_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
# define TIVA_QEI1_BASE (TIVA_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
/* -0x37fff: Reserved */
# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
# define TIVA_ADC1_BASE (TIVA_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
/* -0x3bfff: Reserved */
# define TIVA_COMPARE_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
# define TIVA_GPIOJ_BASE (TIVA_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */
/* -0x3ffff: Reserved */
# define TIVA_CAN0_BASE (TIVA_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */
# define TIVA_CAN1_BASE (TIVA_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */
/* -0x47fff: Reserved */
# define TIVA_ETHCON_BASE (TIVA_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
/* -0x49fff: Reserved */
# define TIVA_USB_BASE (TIVA_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
/* -0x53fff: Reserved */
# define TIVA_I2S0_BASE (TIVA_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */
/* -0x57fff: Reserved */
# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */
# define TIVA_GPIODAHB_BASE (TIVA_PERIPH_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */
# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */
# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */
# define TIVA_GPIOGAHB_BASE (TIVA_PERIPH_BASE + 0x5e000) /* -0x5efff: GPIO Port G (AHB aperture) */
# define TIVA_GPIOHAHB_BASE (TIVA_PERIPH_BASE + 0x5f000) /* -0x5ffff: GPIO Port H (AHB aperture) */
# define TIVA_GPIOJAHB_BASE (TIVA_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */
/* -0xcffff: Reserved */
# define TIVA_EPI0_BASE (TIVA_PERIPH_BASE + 0xd0000) /* -0xd0fff: EPI 0 */
/* -0xfcfff: Reserved */
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
/* -0x1ffffff: Reserved */
#else
# error "Peripheral base addresses not specified for this Stellaris chip"
#endif

116
arch/arm/src/tiva/chip/lm3s_syscontrol.h
View file

@ -48,67 +48,67 @@
/* System Control Register Offsets **************************************************/
#define LM_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
#define LM_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
#define LM_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
#define LM_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
#define LM_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
#define LM_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
#define LM_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
#define LM_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
#define LM_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */
#define LM_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
#define LM_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
#define LM_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/
#define LM_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
#define LM_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
#define LM_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
#define LM_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
#define LM_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
#define LM_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */
#define LM_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
#define LM_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
#define LM_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
#define LM_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
#define LM_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
#define LM_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
#define LM_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
#define LM_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
#define LM_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define LM_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define LM_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
#define TIVA_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
#define TIVA_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
#define TIVA_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
#define TIVA_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
#define TIVA_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
#define TIVA_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
#define TIVA_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
#define TIVA_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
#define TIVA_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */
#define TIVA_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
#define TIVA_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
#define TIVA_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/
#define TIVA_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
#define TIVA_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
#define TIVA_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
#define TIVA_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
#define TIVA_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
#define TIVA_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */
#define TIVA_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
#define TIVA_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
/* System Control Register Addresses ************************************************/
#define LM_SYSCON_DID0 (LM_SYSCON_BASE + LM_SYSCON_DID0_OFFSET)
#define LM_SYSCON_DID1 (LM_SYSCON_BASE + LM_SYSCON_DID1_OFFSET)
#define LM_SYSCON_DC0 (LM_SYSCON_BASE + LM_SYSCON_DC0_OFFSET)
#define LM_SYSCON_DC1 (LM_SYSCON_BASE + LM_SYSCON_DC1_OFFSET)
#define LM_SYSCON_DC2 (LM_SYSCON_BASE + LM_SYSCON_DC2_OFFSET)
#define LM_SYSCON_DC3 (LM_SYSCON_BASE + LM_SYSCON_DC3_OFFSET)
#define LM_SYSCON_DC4 (LM_SYSCON_BASE + LM_SYSCON_DC4_OFFSET)
#define LM_SYSCON_PBORCTL (LM_SYSCON_BASE + LM_SYSCON_PBORCTL_OFFSET)
#define LM_SYSCON_LDOPCTL (LM_SYSCON_BASE + LM_SYSCON_LDOPCTL_OFFSET)
#define LM_SYSCON_SRCR0 (LM_SYSCON_BASE + LM_SYSCON_SRCR0_OFFSET)
#define LM_SYSCON_SRCR1 (LM_SYSCON_BASE + LM_SYSCON_SRCR1_OFFSET)
#define LM_SYSCON_SRCR2 (LM_SYSCON_BASE + LM_SYSCON_SRCR2_OFFSET)
#define LM_SYSCON_RIS (LM_SYSCON_BASE + LM_SYSCON_RIS_OFFSET)
#define LM_SYSCON_IMC (LM_SYSCON_BASE + LM_SYSCON_IMC_OFFSET)
#define LM_SYSCON_MISC (LM_SYSCON_BASE + LM_SYSCON_MISC_OFFSET)
#define LM_SYSCON_RESC (LM_SYSCON_BASE + LM_SYSCON_RESC_OFFSET)
#define LM_SYSCON_RCC (LM_SYSCON_BASE + LM_SYSCON_RCC_OFFSET)
#define LM_SYSCON_PLLCFG (LM_SYSCON_BASE + LM_SYSCON_PLLCFG_OFFSET)
#define LM_SYSCON_RCC2 (LM_SYSCON_BASE + LM_SYSCON_RCC2_OFFSET)
#define LM_SYSCON_RCGC0 (LM_SYSCON_BASE + LM_SYSCON_RCGC0_OFFSET)
#define LM_SYSCON_RCGC1 (LM_SYSCON_BASE + LM_SYSCON_RCGC1_OFFSET)
#define LM_SYSCON_RCGC2 (LM_SYSCON_BASE + LM_SYSCON_RCGC2_OFFSET)
#define LM_SYSCON_SCGC0 (LM_SYSCON_BASE + LM_SYSCON_SCGC0_OFFSET)
#define LM_SYSCON_SCGC1 (LM_SYSCON_BASE + LM_SYSCON_SCGC1_OFFSET)
#define LM_SYSCON_SCGC2 (LM_SYSCON_BASE + LM_SYSCON_SCGC2_OFFSET)
#define LM_SYSCON_DCGC0 (LM_SYSCON_BASE + LM_SYSCON_DCGC0_OFFSET)
#define LM_SYSCON_DCGC1 (LM_SYSCON_BASE + LM_SYSCON_DCGC1_OFFSET)
#define LM_SYSCON_DCGC2 (LM_SYSCON_BASE + LM_SYSCON_DCGC2_OFFSET)
#define LM_SYSCON_DSLPCLKCFG (LM_SYSCON_BASE + LM_SYSCON_DSLPCLKCFG_OFFSET)
#define TIVA_SYSCON_DID0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID0_OFFSET)
#define TIVA_SYSCON_DID1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID1_OFFSET)
#define TIVA_SYSCON_DC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC0_OFFSET)
#define TIVA_SYSCON_DC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC1_OFFSET)
#define TIVA_SYSCON_DC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC2_OFFSET)
#define TIVA_SYSCON_DC3 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC3_OFFSET)
#define TIVA_SYSCON_DC4 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC4_OFFSET)
#define TIVA_SYSCON_PBORCTL (TIVA_SYSCON_BASE + TIVA_SYSCON_PBORCTL_OFFSET)
#define TIVA_SYSCON_LDOPCTL (TIVA_SYSCON_BASE + TIVA_SYSCON_LDOPCTL_OFFSET)
#define TIVA_SYSCON_SRCR0 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR0_OFFSET)
#define TIVA_SYSCON_SRCR1 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR1_OFFSET)
#define TIVA_SYSCON_SRCR2 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR2_OFFSET)
#define TIVA_SYSCON_RIS (TIVA_SYSCON_BASE + TIVA_SYSCON_RIS_OFFSET)
#define TIVA_SYSCON_IMC (TIVA_SYSCON_BASE + TIVA_SYSCON_IMC_OFFSET)
#define TIVA_SYSCON_MISC (TIVA_SYSCON_BASE + TIVA_SYSCON_MISC_OFFSET)
#define TIVA_SYSCON_RESC (TIVA_SYSCON_BASE + TIVA_SYSCON_RESC_OFFSET)
#define TIVA_SYSCON_RCC (TIVA_SYSCON_BASE + TIVA_SYSCON_RCC_OFFSET)
#define TIVA_SYSCON_PLLCFG (TIVA_SYSCON_BASE + TIVA_SYSCON_PLLCFG_OFFSET)
#define TIVA_SYSCON_RCC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCC2_OFFSET)
#define TIVA_SYSCON_RCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC0_OFFSET)
#define TIVA_SYSCON_RCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC1_OFFSET)
#define TIVA_SYSCON_RCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC2_OFFSET)
#define TIVA_SYSCON_SCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC0_OFFSET)
#define TIVA_SYSCON_SCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC1_OFFSET)
#define TIVA_SYSCON_SCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC2_OFFSET)
#define TIVA_SYSCON_DCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC0_OFFSET)
#define TIVA_SYSCON_DCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC1_OFFSET)
#define TIVA_SYSCON_DCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC2_OFFSET)
#define TIVA_SYSCON_DSLPCLKCFG (TIVA_SYSCON_BASE + TIVA_SYSCON_DSLPCLKCFG_OFFSET)
/* System Control Register Bit Definitions ******************************************/

552
arch/arm/src/tiva/chip/lm3s_vectors.h
View file

@ -62,67 +62,67 @@
#else
VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(tiva_gpioa, TIVA_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(tiva_gpiob, TIVA_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(tiva_gpioc, TIVA_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(tiva_gpiod, TIVA_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */
UNUSED(LM_RESERVED_26) /* Vector 26: Reserved */
UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */
UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */
UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */
VECTOR(tiva_gpioe, TIVA_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
UNUSED(TIVA_RESERVED_25) /* Vector 25: Reserved */
UNUSED(TIVA_RESERVED_26) /* Vector 26: Reserved */
UNUSED(TIVA_RESERVED_27) /* Vector 27: Reserved */
UNUSED(TIVA_RESERVED_28) /* Vector 28: Reserved */
UNUSED(TIVA_RESERVED_29) /* Vector 29: Reserved */
VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(tiva_adc0, TIVA_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(tiva_adc1, TIVA_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(tiva_adc2, TIVA_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(tiva_adc3, TIVA_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(tiva_wdog, TIVA_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(tiva_tmr0a, TIVA_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(tiva_tmr0b, TIVA_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(tiva_tmr1a, TIVA_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(tiva_tmr1b, TIVA_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(tiva_tmr2a, TIVA_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
VECTOR(lm_gpioh, LM_IRQ_GPIOH) /* Vector 48: GPIO Port H */
UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */
VECTOR(tiva_tmr2b, TIVA_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(tiva_cmp0, TIVA_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(tiva_cmp1, TIVA_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
UNUSED(TIVA_RESERVED_43) /* Vector 43: Reserved */
VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(tiva_gpiog, TIVA_IRQ_GPIOG) /* Vector 47: GPIO Port G */
VECTOR(tiva_gpioh, TIVA_IRQ_GPIOH) /* Vector 48: GPIO Port H */
UNUSED(TIVA_RESERVED_49) /* Vector 49: Reserved */
VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: SSI 1 */
VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */
UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */
UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
VECTOR(tiva_ssi1, TIVA_IRQ_SSI1) /* Vector 50: SSI 1 */
VECTOR(tiva_tmr3a, TIVA_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
VECTOR(tiva_tmr3b, TIVA_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
VECTOR(tiva_i2c1, TIVA_IRQ_I2C1) /* Vector 53: I2C 1 */
UNUSED(TIVA_RESERVED_54) /* Vector 54: Reserved */
UNUSED(TIVA_RESERVED_55) /* Vector 55: Reserved */
UNUSED(TIVA_RESERVED_56) /* Vector 56: Reserved */
UNUSED(TIVA_RESERVED_57) /* Vector 57: Reserved */
VECTOR(tiva_eth, TIVA_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
VECTOR(tiva_hib, TIVA_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */
UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */
UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */
UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */
UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */
UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */
UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */
UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
UNUSED(TIVA_RESERVED_60) /* Vector 60: Reserved */
UNUSED(TIVA_RESERVED_61) /* Vector 61: Reserved */
UNUSED(TIVA_RESERVED_62) /* Vector 62: Reserved */
UNUSED(TIVA_RESERVED_63) /* Vector 63: Reserved */
UNUSED(TIVA_RESERVED_64) /* Vector 64: Reserved */
UNUSED(TIVA_RESERVED_65) /* Vector 65: Reserved */
UNUSED(TIVA_RESERVED_66) /* Vector 66: Reserved */
UNUSED(TIVA_RESERVED_67) /* Vector 67: Reserved */
UNUSED(TIVA_RESERVED_68) /* Vector 68: Reserved */
UNUSED(TIVA_RESERVED_69) /* Vector 69: Reserved */
UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
UNUSED(TIVA_RESERVED_70) /* Vector 70: Reserved */
#endif
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
@ -139,67 +139,67 @@ UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
#else
VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(tiva_gpioa, TIVA_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(tiva_gpiob, TIVA_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(tiva_gpioc, TIVA_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(tiva_gpiod, TIVA_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */
VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */
UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */
UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */
VECTOR(tiva_gpioe, TIVA_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
UNUSED(TIVA_RESERVED_25) /* Vector 25: Reserved */
VECTOR(tiva_pwm0, TIVA_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
UNUSED(TIVA_RESERVED_27) /* Vector 27: Reserved */
UNUSED(TIVA_RESERVED_28) /* Vector 28: Reserved */
UNUSED(TIVA_RESERVED_29) /* Vector 29: Reserved */
VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(tiva_adc0, TIVA_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(tiva_adc1, TIVA_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(tiva_adc2, TIVA_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(tiva_adc3, TIVA_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(tiva_wdog, TIVA_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(tiva_tmr0a, TIVA_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(tiva_tmr0b, TIVA_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(tiva_tmr1a, TIVA_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(tiva_tmr1b, TIVA_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(tiva_tmr2a, TIVA_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */
UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */
VECTOR(tiva_tmr2b, TIVA_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(tiva_cmp0, TIVA_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(tiva_cmp1, TIVA_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
UNUSED(TIVA_RESERVED_43) /* Vector 43: Reserved */
VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(tiva_gpiog, TIVA_IRQ_GPIOG) /* Vector 47: GPIO Port G */
UNUSED(TIVA_RESERVED_48) /* Vector 48: Reserved */
UNUSED(TIVA_RESERVED_49) /* Vector 49: Reserved */
UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */
UNUSED(LM_RESERVED_51) /* Vector 51: Reserved */
UNUSED(LM_RESERVED_52) /* Vector 52: Reserved */
UNUSED(LM_RESERVED_53) /* Vector 53: Reserved */
UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */
UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */
UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
UNUSED(LM_RESERVED_59) /* Vector 59: Reserved */
UNUSED(TIVA_RESERVED_50) /* Vector 50: Reserved */
UNUSED(TIVA_RESERVED_51) /* Vector 51: Reserved */
UNUSED(TIVA_RESERVED_52) /* Vector 52: Reserved */
UNUSED(TIVA_RESERVED_53) /* Vector 53: Reserved */
UNUSED(TIVA_RESERVED_54) /* Vector 54: Reserved */
UNUSED(TIVA_RESERVED_55) /* Vector 55: Reserved */
UNUSED(TIVA_RESERVED_56) /* Vector 56: Reserved */
UNUSED(TIVA_RESERVED_57) /* Vector 57: Reserved */
VECTOR(tiva_eth, TIVA_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
UNUSED(TIVA_RESERVED_59) /* Vector 59: Reserved */
UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */
UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */
UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */
UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */
UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */
UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */
UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */
UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
UNUSED(TIVA_RESERVED_60) /* Vector 60: Reserved */
UNUSED(TIVA_RESERVED_61) /* Vector 61: Reserved */
UNUSED(TIVA_RESERVED_62) /* Vector 62: Reserved */
UNUSED(TIVA_RESERVED_63) /* Vector 63: Reserved */
UNUSED(TIVA_RESERVED_64) /* Vector 64: Reserved */
UNUSED(TIVA_RESERVED_65) /* Vector 65: Reserved */
UNUSED(TIVA_RESERVED_66) /* Vector 66: Reserved */
UNUSED(TIVA_RESERVED_67) /* Vector 67: Reserved */
UNUSED(TIVA_RESERVED_68) /* Vector 68: Reserved */
UNUSED(TIVA_RESERVED_69) /* Vector 69: Reserved */
UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
UNUSED(TIVA_RESERVED_70) /* Vector 70: Reserved */
#endif
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
@ -216,67 +216,67 @@ UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
#else
VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(tiva_gpioa, TIVA_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(tiva_gpiob, TIVA_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(tiva_gpioc, TIVA_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(tiva_gpiod, TIVA_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */
VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */
VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */
VECTOR(tiva_gpioe, TIVA_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
VECTOR(tiva_pwmfault, TIVA_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
VECTOR(tiva_pwm0, TIVA_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
VECTOR(tiva_pwm1, TIVA_IRQ_PWM1) /* Vector 27: PWM Generator 1 */
VECTOR(tiva_pwm2, TIVA_IRQ_PWM2) /* Vector 28: PWM Generator 2 */
VECTOR(tiva_qei0, TIVA_IRQ_QEI0) /* Vector 29: QEI 0 */
VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(tiva_adc0, TIVA_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(tiva_adc1, TIVA_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(tiva_adc2, TIVA_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(tiva_adc3, TIVA_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(tiva_wdog, TIVA_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(tiva_tmr0a, TIVA_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(tiva_tmr0b, TIVA_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(tiva_tmr1a, TIVA_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(tiva_tmr1b, TIVA_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(tiva_tmr2a, TIVA_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */
VECTOR(lm_uart2, LM_IRQ_UART1) /* Vector 49: UART 1 */
VECTOR(tiva_tmr2b, TIVA_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(tiva_cmp0, TIVA_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(tiva_cmp1, TIVA_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
UNUSED(TIVA_RESERVED_43) /* Vector 43: Reserved */
VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(tiva_gpiog, TIVA_IRQ_GPIOG) /* Vector 47: GPIO Port G */
UNUSED(TIVA_RESERVED_48) /* Vector 48: Reserved */
VECTOR(tiva_uart2, TIVA_IRQ_UART1) /* Vector 49: UART 1 */
UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */
VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */
UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */
UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
UNUSED(TIVA_RESERVED_50) /* Vector 50: Reserved */
VECTOR(tiva_tmr3a, TIVA_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
VECTOR(tiva_tmr3b, TIVA_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
VECTOR(tiva_i2c1, TIVA_IRQ_I2C1) /* Vector 53: I2C 1 */
VECTOR(tiva_qei1, TIVA_IRQ_QEI1) /* Vector 54: QEI 1 */
UNUSED(TIVA_RESERVED_55) /* Vector 55: Reserved */
UNUSED(TIVA_RESERVED_56) /* Vector 56: Reserved */
UNUSED(TIVA_RESERVED_57) /* Vector 57: Reserved */
VECTOR(tiva_eth, TIVA_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
VECTOR(tiva_hib, TIVA_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */
UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */
UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */
UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */
UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */
UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */
UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */
UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
UNUSED(TIVA_RESERVED_60) /* Vector 60: Reserved */
UNUSED(TIVA_RESERVED_61) /* Vector 61: Reserved */
UNUSED(TIVA_RESERVED_62) /* Vector 62: Reserved */
UNUSED(TIVA_RESERVED_63) /* Vector 63: Reserved */
UNUSED(TIVA_RESERVED_64) /* Vector 64: Reserved */
UNUSED(TIVA_RESERVED_65) /* Vector 65: Reserved */
UNUSED(TIVA_RESERVED_66) /* Vector 66: Reserved */
UNUSED(TIVA_RESERVED_67) /* Vector 67: Reserved */
UNUSED(TIVA_RESERVED_68) /* Vector 68: Reserved */
UNUSED(TIVA_RESERVED_69) /* Vector 69: Reserved */
UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
UNUSED(TIVA_RESERVED_70) /* Vector 70: Reserved */
#endif
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
@ -293,67 +293,67 @@ UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
#else
VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(tiva_gpioa, TIVA_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(tiva_gpiob, TIVA_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(tiva_gpioc, TIVA_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(tiva_gpiod, TIVA_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */
VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */
VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */
VECTOR(tiva_gpioe, TIVA_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
VECTOR(tiva_pwmfault, TIVA_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
VECTOR(tiva_pwm0, TIVA_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
VECTOR(tiva_pwm1, TIVA_IRQ_PWM1) /* Vector 27: PWM Generator 1 */
VECTOR(tiva_pwm2, TIVA_IRQ_PWM2) /* Vector 28: PWM Generator 2 */
VECTOR(tiva_qei0, TIVA_IRQ_QEI0) /* Vector 29: QEI 0 */
VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(tiva_adc0, TIVA_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(tiva_adc1, TIVA_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(tiva_adc2, TIVA_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(tiva_adc3, TIVA_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(tiva_wdog, TIVA_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(tiva_tmr0a, TIVA_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(tiva_tmr0b, TIVA_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(tiva_tmr1a, TIVA_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(tiva_tmr1b, TIVA_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(tiva_tmr2a, TIVA_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
UNUSED(LM_RESERVED_42) /* Vector 42: Reserved */
UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */
UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */
VECTOR(tiva_tmr2b, TIVA_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(tiva_cmp0, TIVA_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
UNUSED(TIVA_RESERVED_42) /* Vector 42: Reserved */
UNUSED(TIVA_RESERVED_43) /* Vector 43: Reserved */
VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(tiva_gpiog, TIVA_IRQ_GPIOG) /* Vector 47: GPIO Port G */
UNUSED(TIVA_RESERVED_48) /* Vector 48: Reserved */
UNUSED(TIVA_RESERVED_49) /* Vector 49: Reserved */
UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */
VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */
VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */
UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
UNUSED(TIVA_RESERVED_50) /* Vector 50: Reserved */
VECTOR(tiva_tmr3a, TIVA_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
VECTOR(tiva_tmr3b, TIVA_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
VECTOR(tiva_i2c1, TIVA_IRQ_I2C1) /* Vector 53: I2C 1 */
VECTOR(tiva_qei1, TIVA_IRQ_QEI1) /* Vector 54: QEI 1 */
VECTOR(tiva_can0, TIVA_IRQ_CAN0) /* Vector 55: CAN 0 */
UNUSED(TIVA_RESERVED_56) /* Vector 56: Reserved */
UNUSED(TIVA_RESERVED_57) /* Vector 57: Reserved */
VECTOR(tiva_eth, TIVA_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
VECTOR(tiva_hib, TIVA_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */
UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */
UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */
UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */
UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */
UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */
UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */
UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
UNUSED(TIVA_RESERVED_60) /* Vector 60: Reserved */
UNUSED(TIVA_RESERVED_61) /* Vector 61: Reserved */
UNUSED(TIVA_RESERVED_62) /* Vector 62: Reserved */
UNUSED(TIVA_RESERVED_63) /* Vector 63: Reserved */
UNUSED(TIVA_RESERVED_64) /* Vector 64: Reserved */
UNUSED(TIVA_RESERVED_65) /* Vector 65: Reserved */
UNUSED(TIVA_RESERVED_66) /* Vector 66: Reserved */
UNUSED(TIVA_RESERVED_67) /* Vector 67: Reserved */
UNUSED(TIVA_RESERVED_68) /* Vector 68: Reserved */
UNUSED(TIVA_RESERVED_69) /* Vector 69: Reserved */
UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
UNUSED(TIVA_RESERVED_70) /* Vector 70: Reserved */
#endif
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
@ -370,68 +370,68 @@ UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
#else
VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(tiva_gpioa, TIVA_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(tiva_gpiob, TIVA_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(tiva_gpioc, TIVA_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(tiva_gpiod, TIVA_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(tiva_gpioe, TIVA_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */
VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */
VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */
VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
VECTOR(tiva_pwmfault, TIVA_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
VECTOR(tiva_pwm0, TIVA_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
VECTOR(tiva_pwm1, TIVA_IRQ_PWM1) /* Vector 27: PWM Generator 1 */
VECTOR(tiva_pwm2, TIVA_IRQ_PWM2) /* Vector 28: PWM Generator 2 */
VECTOR(tiva_qei0, TIVA_IRQ_QEI0) /* Vector 29: QEI 0 */
VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(tiva_adc0, TIVA_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(tiva_adc1, TIVA_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(tiva_adc2, TIVA_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(tiva_adc3, TIVA_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(tiva_wdog, TIVA_IRQ_WDOG) /* Vector 34: Watchdog Timer */
VECTOR(tiva_tmr0a, TIVA_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
VECTOR(tiva_tmr0b, TIVA_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
VECTOR(tiva_tmr1a, TIVA_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
VECTOR(tiva_tmr1b, TIVA_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
VECTOR(tiva_tmr2a, TIVA_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
VECTOR(lm_cmp2, LM_IRQ_COMPARE2) /* Vector 43: Analog Comparator 2 */
VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
VECTOR(lm_gpioh, LM_IRQ_GPIOH) /* Vector 48: GPIO Port H */
VECTOR(lm_uart2, LM_IRQ_UART2) /* Vector 49: UART 2 */
VECTOR(tiva_tmr2b, TIVA_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
VECTOR(tiva_cmp0, TIVA_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(tiva_cmp1, TIVA_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
VECTOR(tiva_cmp2, TIVA_IRQ_COMPARE2) /* Vector 43: Analog Comparator 2 */
VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH Control */
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(tiva_gpiog, TIVA_IRQ_GPIOG) /* Vector 47: GPIO Port G */
VECTOR(tiva_gpioh, TIVA_IRQ_GPIOH) /* Vector 48: GPIO Port H */
VECTOR(tiva_uart2, TIVA_IRQ_UART2) /* Vector 49: UART 2 */
VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: GPIO Port H */
VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */
VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */
VECTOR(lm_can1, LM_IRQ_CAN1) /* Vector 56: CAN 1 */
UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
UNUSED(LM_RESERVED_59) /* Vector 59: Reserved */
VECTOR(tiva_ssi1, TIVA_IRQ_SSI1) /* Vector 50: GPIO Port H */
VECTOR(tiva_tmr3a, TIVA_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
VECTOR(tiva_tmr3b, TIVA_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
VECTOR(tiva_i2c1, TIVA_IRQ_I2C1) /* Vector 53: I2C 1 */
VECTOR(tiva_qei1, TIVA_IRQ_QEI1) /* Vector 54: QEI 1 */
VECTOR(tiva_can0, TIVA_IRQ_CAN0) /* Vector 55: CAN 0 */
VECTOR(tiva_can1, TIVA_IRQ_CAN1) /* Vector 56: CAN 1 */
UNUSED(TIVA_RESERVED_57) /* Vector 57: Reserved */
VECTOR(tiva_eth, TIVA_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
UNUSED(TIVA_RESERVED_59) /* Vector 59: Reserved */
VECTOR(lm_usb, LM_IRQ_USB) /* Vector 60: USB */
VECTOR(lm_pwm3, LM_IRQ_PWM3) /* Vector 61: PWM 3 */
VECTOR(lm_udmasoft, LM_IRQ_UDMASOFT) /* Vector 62: uDMA Software */
VECTOR(lm_udmaerror, LM_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
VECTOR(lm_adc1_0, LM_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */
VECTOR(lm_adc1_1, LM_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */
VECTOR(lm_adc1_2, LM_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */
VECTOR(lm_adc1_3, LM_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */
VECTOR(lm_i2s0, LM_IRQ_I2S0) /* Vector 68: I2S 0 */
VECTOR(lm_epi, LM_IRQ_EPI) /* Vector 69: EPI */
VECTOR(tiva_usb, TIVA_IRQ_USB) /* Vector 60: USB */
VECTOR(tiva_pwm3, TIVA_IRQ_PWM3) /* Vector 61: PWM 3 */
VECTOR(tiva_udmasoft, TIVA_IRQ_UDMASOFT) /* Vector 62: uDMA Software */
VECTOR(tiva_udmaerror, TIVA_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
VECTOR(tiva_adc1_0, TIVA_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */
VECTOR(tiva_adc1_1, TIVA_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */
VECTOR(tiva_adc1_2, TIVA_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */
VECTOR(tiva_adc1_3, TIVA_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */
VECTOR(tiva_i2s0, TIVA_IRQ_I2S0) /* Vector 68: I2S 0 */
VECTOR(tiva_epi, TIVA_IRQ_EPI) /* Vector 69: EPI */
VECTOR(lm_gpioj, LM_IRQ_GPIOJ) /* Vector 70: GPIO Port J */
UNUSED(LM_RESERVED_71) /* Vector 71: Reserved */
VECTOR(tiva_gpioj, TIVA_IRQ_GPIOJ) /* Vector 70: GPIO Port J */
UNUSED(TIVA_RESERVED_71) /* Vector 71: Reserved */
#endif
#else

182
arch/arm/src/tiva/chip/lm4f_memorymap.h
View file

@ -50,26 +50,26 @@
/* Memory map ***********************************************************************/
#if defined(CONFIG_ARCH_CHIP_LM4F120)
# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
/* -0x00ffffff: Reserved */
# define LM_ROM_BASE 0x01000000 /* -0x1fffffff: Reserved for ROM */
# define LM_SRAM_BASE 0x20000000 /* -0x20007fff: Bit-banded on-chip SRAM */
/* -0x21ffffff: Reserved */
# define LM_ASRAM_BASE 0x22000000 /* -0x220fffff: Bit-band alias of 20000000- */
/* -0x3fffffff: Reserved */
# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
/* -0x41ffffff: Peripherals */
# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000- */
/* -0xdfffffff: Reserved */
# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
/* -0xe000dfff: Reserved */
# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
/* -0xe003ffff: Reserved */
# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
# define LM_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */
/* -0xffffffff: Reserved */
# define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
/* -0x00ffffff: Reserved */
# define TIVA_ROM_BASE 0x01000000 /* -0x1fffffff: Reserved for ROM */
# define TIVA_SRAM_BASE 0x20000000 /* -0x20007fff: Bit-banded on-chip SRAM */
/* -0x21ffffff: Reserved */
# define TIVA_ASRAM_BASE 0x22000000 /* -0x220fffff: Bit-band alias of 20000000- */
/* -0x3fffffff: Reserved */
# define TIVA_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
/* -0x41ffffff: Peripherals */
# define TIVA_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000- */
/* -0xdfffffff: Reserved */
# define TIVA_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
# define TIVA_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
# define TIVA_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
/* -0xe000dfff: Reserved */
# define TIVA_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
/* -0xe003ffff: Reserved */
# define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
# define TIVA_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */
/* -0xffffffff: Reserved */
#else
# error "Memory map not specified for this LM4F chip"
#endif
@ -79,79 +79,79 @@
#if defined(CONFIG_ARCH_CHIP_LM4F120)
/* FiRM Peripheral Base Addresses */
# define LM_WDOG0_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
# define LM_WDOG1_BASE (LM_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
/* -0x03fff: Reserved */
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
# define LM_SSI2_BASE (LM_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */
# define LM_SSI3_BASE (LM_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */
# define LM_UART3_BASE (LM_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */
# define LM_UART4_BASE (LM_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */
# define LM_UART5_BASE (LM_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */
# define LM_UART6_BASE (LM_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
# define LM_UART7_BASE (LM_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
/* -0x1ffff: Reserved */
# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
/* -0x03fff: Reserved */
# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
# define TIVA_SSI1_BASE (TIVA_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
# define TIVA_SSI2_BASE (TIVA_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */
# define TIVA_SSI3_BASE (TIVA_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */
# define TIVA_UART3_BASE (TIVA_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */
# define TIVA_UART4_BASE (TIVA_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */
# define TIVA_UART5_BASE (TIVA_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */
# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fbf: I2C Slave 0 */
# define LM_I2CSC0_BASE (LM_PERIPH_BASE + 0x20fc0) /* -0x20fff: I2C Status and Control 0 */
# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fbf: I2C Slave 1 */
# define LM_I2CSC1_BASE (LM_PERIPH_BASE + 0x21fc0) /* -0x21fff: I2C Status and Control 1 */
# define LM_I2CM2_BASE (LM_PERIPH_BASE + 0x22000) /* -0x227ff: I2C Master 2 */
# define LM_I2CS2_BASE (LM_PERIPH_BASE + 0x22800) /* -0x22fbf: I2C Slave 2 */
# define LM_I2CSC2_BASE (LM_PERIPH_BASE + 0x22fc0) /* -0x22fff: I2C Status and Control 2 */
# define LM_I2CM3_BASE (LM_PERIPH_BASE + 0x23000) /* -0x237ff: I2C Master 3 */
# define LM_I2CS3_BASE (LM_PERIPH_BASE + 0x23800) /* -0x23fbf: I2C Slave 3 */
# define LM_I2CSC3_BASE (LM_PERIPH_BASE + 0x23fc0) /* -0x23fff: I2C Status and Control 3 */
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
/* -0x2ffff: Reserved */
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
# define LM_TIMER4_BASE (LM_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
# define LM_TIMER5_BASE (LM_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
# define LM_WTIMER0_BASE (LM_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */
# define LM_WTIMER1_BASE (LM_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */
# define LM_ADC0_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
# define LM_ADC1_BASE (LM_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
/* -0x3bfff: Reserved */
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x43fff: Reserved */
# define LM_CANCON_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */
/* -0x4bfff: Reserved */
# define LM_WTIMER2_BASE (LM_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */
# define LM_WTIMER3_BASE (LM_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */
# define LM_WTIMER4_BASE (LM_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */
# define LM_WTIMER5_BASE (LM_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */
# define LM_USB_BASE (LM_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
/* -0x57fff: Reserved */
# define LM_GPIOAAHB_BASE (LM_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
# define LM_GPIOBAHB_BASE (LM_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
# define LM_GPIOCAHB_BASE (LM_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */
# define LM_GPIODAHB_BASE (LM_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */
# define LM_GPIOEAHB_BASE (LM_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */
# define LM_GPIOFAHB_BASE (LM_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */
/* -0xaefff: Reserved */
# define LM_EEPROM_BASE (LM_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
/* -0xf8fff: Reserved */
# define LM_SYSEXC_BASE (LM_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
/* -0xfbfff: Reserved */
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
# define LM_UDMA_BASE (LM_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
# define TIVA_I2CM0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
# define TIVA_I2CS0_BASE (TIVA_PERIPH_BASE + 0x20800) /* -0x20fbf: I2C Slave 0 */
# define TIVA_I2CSC0_BASE (TIVA_PERIPH_BASE + 0x20fc0) /* -0x20fff: I2C Status and Control 0 */
# define TIVA_I2CM1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
# define TIVA_I2CS1_BASE (TIVA_PERIPH_BASE + 0x21800) /* -0x21fbf: I2C Slave 1 */
# define TIVA_I2CSC1_BASE (TIVA_PERIPH_BASE + 0x21fc0) /* -0x21fff: I2C Status and Control 1 */
# define TIVA_I2CM2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x227ff: I2C Master 2 */
# define TIVA_I2CS2_BASE (TIVA_PERIPH_BASE + 0x22800) /* -0x22fbf: I2C Slave 2 */
# define TIVA_I2CSC2_BASE (TIVA_PERIPH_BASE + 0x22fc0) /* -0x22fff: I2C Status and Control 2 */
# define TIVA_I2CM3_BASE (TIVA_PERIPH_BASE + 0x23000) /* -0x237ff: I2C Master 3 */
# define TIVA_I2CS3_BASE (TIVA_PERIPH_BASE + 0x23800) /* -0x23fbf: I2C Slave 3 */
# define TIVA_I2CSC3_BASE (TIVA_PERIPH_BASE + 0x23fc0) /* -0x23fff: I2C Status and Control 3 */
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
# define TIVA_TIMER4_BASE (TIVA_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
# define TIVA_TIMER5_BASE (TIVA_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
# define TIVA_WTIMER0_BASE (TIVA_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */
# define TIVA_WTIMER1_BASE (TIVA_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */
# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
# define TIVA_ADC1_BASE (TIVA_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
/* -0x3bfff: Reserved */
# define TIVA_COMPARE_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
/* -0x43fff: Reserved */
# define TIVA_CANCON_BASE (TIVA_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */
/* -0x4bfff: Reserved */
# define TIVA_WTIMER2_BASE (TIVA_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */
# define TIVA_WTIMER3_BASE (TIVA_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */
# define TIVA_WTIMER4_BASE (TIVA_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */
# define TIVA_WTIMER5_BASE (TIVA_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */
# define TIVA_USB_BASE (TIVA_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
/* -0x57fff: Reserved */
# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */
# define TIVA_GPIODAHB_BASE (TIVA_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */
# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */
# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */
/* -0xaefff: Reserved */
# define TIVA_EEPROM_BASE (TIVA_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
/* -0xf8fff: Reserved */
# define TIVA_SYSEXC_BASE (TIVA_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
/* -0xfbfff: Reserved */
# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
#else
# error "Peripheral base addresses not specified for this Stellaris chip"
#endif

710
arch/arm/src/tiva/chip/lm4f_syscontrol.h
View file

@ -48,291 +48,291 @@
/* System Control Register Offsets **********************************************************/
#define LM_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
#define LM_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
#define LM_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
#define LM_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
#define LM_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
#define LM_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
#define LM_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
#define LM_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
#define LM_SYSCON_GPIOHBCTL_OFFSET 0x06c /* GPIO High-Performance Bus Control */
#define LM_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
#define LM_SYSCON_MOSCCTL_OFFSET 0x07c /* Main Oscillator Control */
#define LM_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration */
#define LM_SYSCON_SYSPROP_OFFSET 0x14c /* System Properties */
#define LM_SYSCON_PIOSCCAL_OFFSET 0x150 /* Precision Internal Oscillator Calibration */
#define LM_SYSCON_PIOSCSTAT_OFFSET 0x154 /* Precision Internal Oscillator Statistics */
#define LM_SYSCON_PLLFREQ0_OFFSET 0x160 /* PLL 0 Frequency */
#define LM_SYSCON_PLLFREQ1_OFFSET 0x164 /* PLL 1 Frequency */
#define LM_SYSCON_PLLSTAT_OFFSET 0x168 /* PLL Status */
#define TIVA_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
#define TIVA_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
#define TIVA_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
#define TIVA_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
#define TIVA_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
#define TIVA_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
#define TIVA_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
#define TIVA_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
#define TIVA_SYSCON_GPIOHBCTL_OFFSET 0x06c /* GPIO High-Performance Bus Control */
#define TIVA_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
#define TIVA_SYSCON_MOSCCTL_OFFSET 0x07c /* Main Oscillator Control */
#define TIVA_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration */
#define TIVA_SYSCON_SYSPROP_OFFSET 0x14c /* System Properties */
#define TIVA_SYSCON_PIOSCCAL_OFFSET 0x150 /* Precision Internal Oscillator Calibration */
#define TIVA_SYSCON_PIOSCSTAT_OFFSET 0x154 /* Precision Internal Oscillator Statistics */
#define TIVA_SYSCON_PLLFREQ0_OFFSET 0x160 /* PLL 0 Frequency */
#define TIVA_SYSCON_PLLFREQ1_OFFSET 0x164 /* PLL 1 Frequency */
#define TIVA_SYSCON_PLLSTAT_OFFSET 0x168 /* PLL Status */
#define LM_SYSCON_PPWD_OFFSET 0x300 /* Watchdog Timer Peripheral Present */
#define LM_SYSCON_PPTIMER_OFFSET 0x304 /* 16/32-Bit Timer Peripheral Present */
#define LM_SYSCON_PPGPIO_OFFSET 0x308 /* GPIO Peripheral Present */
#define LM_SYSCON_PPDMA_OFFSET 0x30c /* uDMA Peripheral Present */
#define LM_SYSCON_PPHIB_OFFSET 0x314 /* Hibernation Peripheral Present */
#define LM_SYSCON_PPUART_OFFSET 0x318 /* UART Present */
#define LM_SYSCON_PPSSI_OFFSET 0x31c /* SSI Peripheral Present */
#define LM_SYSCON_PPI2C_OFFSET 0x320 /* I2C Peripheral Present */
#define LM_SYSCON_PPUSB_OFFSET 0x328 /* USB Peripheral Present */
#define LM_SYSCON_PPCAN_OFFSET 0x334 /* CAN Peripheral Present */
#define LM_SYSCON_PPADC_OFFSET 0x338 /* ADC Peripheral Present */
#define LM_SYSCON_PPACMP_OFFSET 0x33c /* Analog Comparator Peripheral Present */
#define LM_SYSCON_PPPWM_OFFSET 0x340 /* Pulse Width Modulator Peripheral Present */
#define LM_SYSCON_PPQEI_OFFSET 0x344 /* Quadrature Encoder Peripheral Present */
#define LM_SYSCON_PPEEPROM_OFFSET 0x358 /* EEPROM Peripheral Present */
#define LM_SYSCON_PPWTIMER_OFFSET 0x35c /* 32/64-Bit Wide Timer Peripheral Present */
#define TIVA_SYSCON_PPWD_OFFSET 0x300 /* Watchdog Timer Peripheral Present */
#define TIVA_SYSCON_PPTIMER_OFFSET 0x304 /* 16/32-Bit Timer Peripheral Present */
#define TIVA_SYSCON_PPGPIO_OFFSET 0x308 /* GPIO Peripheral Present */
#define TIVA_SYSCON_PPDMA_OFFSET 0x30c /* uDMA Peripheral Present */
#define TIVA_SYSCON_PPHIB_OFFSET 0x314 /* Hibernation Peripheral Present */
#define TIVA_SYSCON_PPUART_OFFSET 0x318 /* UART Present */
#define TIVA_SYSCON_PPSSI_OFFSET 0x31c /* SSI Peripheral Present */
#define TIVA_SYSCON_PPI2C_OFFSET 0x320 /* I2C Peripheral Present */
#define TIVA_SYSCON_PPUSB_OFFSET 0x328 /* USB Peripheral Present */
#define TIVA_SYSCON_PPCAN_OFFSET 0x334 /* CAN Peripheral Present */
#define TIVA_SYSCON_PPADC_OFFSET 0x338 /* ADC Peripheral Present */
#define TIVA_SYSCON_PPACMP_OFFSET 0x33c /* Analog Comparator Peripheral Present */
#define TIVA_SYSCON_PPPWM_OFFSET 0x340 /* Pulse Width Modulator Peripheral Present */
#define TIVA_SYSCON_PPQEI_OFFSET 0x344 /* Quadrature Encoder Peripheral Present */
#define TIVA_SYSCON_PPEEPROM_OFFSET 0x358 /* EEPROM Peripheral Present */
#define TIVA_SYSCON_PPWTIMER_OFFSET 0x35c /* 32/64-Bit Wide Timer Peripheral Present */
#define LM_SYSCON_SRWD_OFFSET 0x500 /* Watchdog Timer Software Reset */
#define LM_SYSCON_SRTIMER_OFFSET 0x504 /* 16/32-Bit Timer Software Reset */
#define LM_SYSCON_SRGPIO_OFFSET 0x508 /* GPIO Software Reset */
#define LM_SYSCON_SRDMA_OFFSET 0x50c /* uDMA Software Reset */
#define LM_SYSCON_SRHIB_OFFSET 0x514 /* Hibernation Software Reset */
#define LM_SYSCON_SRUART_OFFSET 0x518 /* UART Software Reset*/
#define LM_SYSCON_SRSSI_OFFSET 0x51c /* SSI Software Reset */
#define LM_SYSCON_SRI2C_OFFSET 0x520 /* I2C Software Reset */
#define LM_SYSCON_SRUSB_OFFSET 0x528 /* USB Software Reset */
#define LM_SYSCON_SRCAN_OFFSET 0x534 /* CAN Software Reset */
#define LM_SYSCON_SRADC_OFFSET 0x538 /* ADC Software Reset */
#define LM_SYSCON_SRACMP_OFFSET 0x53c /* Analog Comparator Software Reset */
#define LM_SYSCON_SREEPROM_OFFSET 0x558 /* EEPROM Software Reset */
#define LM_SYSCON_SRWTIMER_OFFSET 0x55c /* 32/64-Bit Wide Timer Software Reset */
#define TIVA_SYSCON_SRWD_OFFSET 0x500 /* Watchdog Timer Software Reset */
#define TIVA_SYSCON_SRTIMER_OFFSET 0x504 /* 16/32-Bit Timer Software Reset */
#define TIVA_SYSCON_SRGPIO_OFFSET 0x508 /* GPIO Software Reset */
#define TIVA_SYSCON_SRDMA_OFFSET 0x50c /* uDMA Software Reset */
#define TIVA_SYSCON_SRHIB_OFFSET 0x514 /* Hibernation Software Reset */
#define TIVA_SYSCON_SRUART_OFFSET 0x518 /* UART Software Reset*/
#define TIVA_SYSCON_SRSSI_OFFSET 0x51c /* SSI Software Reset */
#define TIVA_SYSCON_SRI2C_OFFSET 0x520 /* I2C Software Reset */
#define TIVA_SYSCON_SRUSB_OFFSET 0x528 /* USB Software Reset */
#define TIVA_SYSCON_SRCAN_OFFSET 0x534 /* CAN Software Reset */
#define TIVA_SYSCON_SRADC_OFFSET 0x538 /* ADC Software Reset */
#define TIVA_SYSCON_SRACMP_OFFSET 0x53c /* Analog Comparator Software Reset */
#define TIVA_SYSCON_SREEPROM_OFFSET 0x558 /* EEPROM Software Reset */
#define TIVA_SYSCON_SRWTIMER_OFFSET 0x55c /* 32/64-Bit Wide Timer Software Reset */
#define LM_SYSCON_RCGCWD_OFFSET 0x600 /* Watchdog Timer Run Mode Clock Gating Control */
#define LM_SYSCON_RCGCTIMER_OFFSET 0x604 /* 16/32-Bit Timer Run Mode Clock Gating Control */
#define LM_SYSCON_RCGCGPIO_OFFSET 0x608 /* GPIO Run Mode Clock Gating Control*/
#define LM_SYSCON_RCGCDMA_OFFSET 0x60c /* uDMA Run Mode Clock Gating Control*/
#define LM_SYSCON_RCGCHIB_OFFSET 0x614 /* Hibernation Run Mode Clock Gating Control */
#define LM_SYSCON_RCGCUART_OFFSET 0x618 /* UART Run Mode Clock Gating Control*/
#define LM_SYSCON_RCGCSSI_OFFSET 0x61c /* SSI Run Mode Clock Gating Control*/
#define LM_SYSCON_RCGCI2C_OFFSET 0x620 /* I2C Run Mode Clock Gating Control */
#define LM_SYSCON_RCGCUSB_OFFSET 0x628 /* USB Run Mode Clock Gating Control */
#define LM_SYSCON_RCGCCAN_OFFSET 0x634 /* CAN Run Mode Clock Gating Control */
#define LM_SYSCON_RCGCADC_OFFSET 0x638 /* ADC Run Mode Clock Gating Control */
#define LM_SYSCON_RCGCACMP_OFFSET 0x63c /* Analog Comparator Run Mode Clock Gating Control */
#define LM_SYSCON_RCGCEEPROM_OFFSET 0x658 /* EEPROM Run Mode Clock Gating Control */
#define LM_SYSCON_RCGCWTIMER_OFFSET 0x65c /* 32/64-BitWide Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCWD_OFFSET 0x600 /* Watchdog Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCTIMER_OFFSET 0x604 /* 16/32-Bit Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCGPIO_OFFSET 0x608 /* GPIO Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCDMA_OFFSET 0x60c /* uDMA Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCHIB_OFFSET 0x614 /* Hibernation Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCUART_OFFSET 0x618 /* UART Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCSSI_OFFSET 0x61c /* SSI Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCI2C_OFFSET 0x620 /* I2C Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCUSB_OFFSET 0x628 /* USB Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCCAN_OFFSET 0x634 /* CAN Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCADC_OFFSET 0x638 /* ADC Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCACMP_OFFSET 0x63c /* Analog Comparator Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCEEPROM_OFFSET 0x658 /* EEPROM Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCWTIMER_OFFSET 0x65c /* 32/64-BitWide Timer Run Mode Clock Gating Control */
#define LM_SYSCON_SCGCWD_OFFSET 0x700 /* Watchdog Timer Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCTIMER_OFFSET 0x704 /* 16/32-Bit Timer Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCGPIO_OFFSET 0x708 /* GPIO Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCDMA_OFFSET 0x70c /* uDMA Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCHIB_OFFSET 0x714 /* Hibernation Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCUART_OFFSET 0x718 /* UART Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCSSI_OFFSET 0x71c /* SSI Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCI2C_OFFSET 0x720 /* I2C Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCUSB_OFFSET 0x728 /* USB Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCCAN_OFFSET 0x734 /* CAN Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCADC_OFFSET 0x738 /* ADC Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCACMP_OFFSET 0x73c /* Analog Comparator Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCEEPROM_OFFSET 0x758 /* EEPROM Sleep Mode Clock Gating Control */
#define LM_SYSCON_SCGCWTIMER_OFFSET 0x75c /* 32/64-BitWide Timer Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCWD_OFFSET 0x700 /* Watchdog Timer Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCTIMER_OFFSET 0x704 /* 16/32-Bit Timer Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCGPIO_OFFSET 0x708 /* GPIO Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCDMA_OFFSET 0x70c /* uDMA Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCHIB_OFFSET 0x714 /* Hibernation Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCUART_OFFSET 0x718 /* UART Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCSSI_OFFSET 0x71c /* SSI Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCI2C_OFFSET 0x720 /* I2C Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCUSB_OFFSET 0x728 /* USB Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCCAN_OFFSET 0x734 /* CAN Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCADC_OFFSET 0x738 /* ADC Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCACMP_OFFSET 0x73c /* Analog Comparator Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCEEPROM_OFFSET 0x758 /* EEPROM Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCWTIMER_OFFSET 0x75c /* 32/64-BitWide Timer Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCWD_OFFSET 0x800 /* Watchdog Timer Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCTIMER_OFFSET 0x804 /* Clock Gating Control */
#define LM_SYSCON_DCGCGPIO_OFFSET 0x808 /* GPIO Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCDMA_OFFSET 0x80c /* uDMA Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCHIB_OFFSET 0x814 /* Hibernation Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCUART_OFFSET 0x818 /* UART Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCSSI_OFFSET 0x81c /* SSI Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCI2C_OFFSET 0x820 /* I2C Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCUSB_OFFSET 0x828 /* USB Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCCAN_OFFSET 0x834 /* CAN Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCADC_OFFSET 0x838 /* ADC Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCACMP_OFFSET 0x83c /* Analog Comparator Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCEEPROM_OFFSET 0x858 /* EEPROM Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_DCGCWTIMER_OFFSET 0x85c /* 32/64-BitWide Timer Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCWD_OFFSET 0x800 /* Watchdog Timer Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCTIMER_OFFSET 0x804 /* Clock Gating Control */
#define TIVA_SYSCON_DCGCGPIO_OFFSET 0x808 /* GPIO Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCDMA_OFFSET 0x80c /* uDMA Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCHIB_OFFSET 0x814 /* Hibernation Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCUART_OFFSET 0x818 /* UART Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCSSI_OFFSET 0x81c /* SSI Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCI2C_OFFSET 0x820 /* I2C Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCUSB_OFFSET 0x828 /* USB Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCCAN_OFFSET 0x834 /* CAN Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCADC_OFFSET 0x838 /* ADC Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCACMP_OFFSET 0x83c /* Analog Comparator Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCEEPROM_OFFSET 0x858 /* EEPROM Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCWTIMER_OFFSET 0x85c /* 32/64-BitWide Timer Deep-Sleep Mode Clock Gating Control */
#define LM_SYSCON_PRWD_OFFSET 0xa00 /* Watchdog Timer Peripheral Ready */
#define LM_SYSCON_PRTIMER_OFFSET 0xa04 /* 16/32-Bit Timer Peripheral Ready */
#define LM_SYSCON_PRGPIO_OFFSET 0xa08 /* GPIO Peripheral Ready */
#define LM_SYSCON_PRDMA_OFFSET 0xa0c /* uDMA Peripheral Ready */
#define LM_SYSCON_PRHIB_OFFSET 0xa14 /* Hibernation Peripheral Ready */
#define LM_SYSCON_PRUART_OFFSET 0xa18 /* UART Peripheral Ready */
#define LM_SYSCON_PRSSI_OFFSET 0xa1c /* SSI Peripheral Ready */
#define LM_SYSCON_PRI2C_OFFSET 0xa20 /* I2C Peripheral Ready */
#define LM_SYSCON_PRUSB_OFFSET 0xa28 /* USB Peripheral Ready */
#define LM_SYSCON_PRCAN_OFFSET 0xa34 /* CAN Peripheral Ready */
#define LM_SYSCON_PRADC_OFFSET 0xa38 /* ADC Peripheral Ready */
#define LM_SYSCON_PRACMP_OFFSET 0xa3c /* Analog Comparator Peripheral Ready */
#define LM_SYSCON_PREEPROM_OFFSET 0xa58 /* EEPROM Peripheral Ready */
#define LM_SYSCON_PRWTIMER_OFFSET 0xa5c /* 2/64-BitWide Timer Peripheral Ready */
#define TIVA_SYSCON_PRWD_OFFSET 0xa00 /* Watchdog Timer Peripheral Ready */
#define TIVA_SYSCON_PRTIMER_OFFSET 0xa04 /* 16/32-Bit Timer Peripheral Ready */
#define TIVA_SYSCON_PRGPIO_OFFSET 0xa08 /* GPIO Peripheral Ready */
#define TIVA_SYSCON_PRDMA_OFFSET 0xa0c /* uDMA Peripheral Ready */
#define TIVA_SYSCON_PRHIB_OFFSET 0xa14 /* Hibernation Peripheral Ready */
#define TIVA_SYSCON_PRUART_OFFSET 0xa18 /* UART Peripheral Ready */
#define TIVA_SYSCON_PRSSI_OFFSET 0xa1c /* SSI Peripheral Ready */
#define TIVA_SYSCON_PRI2C_OFFSET 0xa20 /* I2C Peripheral Ready */
#define TIVA_SYSCON_PRUSB_OFFSET 0xa28 /* USB Peripheral Ready */
#define TIVA_SYSCON_PRCAN_OFFSET 0xa34 /* CAN Peripheral Ready */
#define TIVA_SYSCON_PRADC_OFFSET 0xa38 /* ADC Peripheral Ready */
#define TIVA_SYSCON_PRACMP_OFFSET 0xa3c /* Analog Comparator Peripheral Ready */
#define TIVA_SYSCON_PREEPROM_OFFSET 0xa58 /* EEPROM Peripheral Ready */
#define TIVA_SYSCON_PRWTIMER_OFFSET 0xa5c /* 2/64-BitWide Timer Peripheral Ready */
/* System Control Legacy Register Offsets ***************************************************/
#define LM_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
#define LM_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
#define LM_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
#define LM_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
#define LM_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
#define LM_SYSCON_DC5_OFFSET 0x020 /* Device Capabilities 5 */
#define LM_SYSCON_DC6_OFFSET 0x024 /* Device Capabilities 6 */
#define LM_SYSCON_DC7_OFFSET 0x028 /* Device Capabilities 7 */
#define LM_SYSCON_DC8_OFFSET 0x02c /* Device Capabilities 8 */
#define TIVA_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
#define TIVA_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
#define TIVA_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
#define TIVA_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
#define TIVA_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
#define TIVA_SYSCON_DC5_OFFSET 0x020 /* Device Capabilities 5 */
#define TIVA_SYSCON_DC6_OFFSET 0x024 /* Device Capabilities 6 */
#define TIVA_SYSCON_DC7_OFFSET 0x028 /* Device Capabilities 7 */
#define TIVA_SYSCON_DC8_OFFSET 0x02c /* Device Capabilities 8 */
#define LM_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
#define LM_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
#define LM_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2 */
#define TIVA_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
#define TIVA_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
#define TIVA_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2 */
#define LM_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
#define LM_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
#define LM_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
#define LM_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
#define LM_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
#define LM_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
#define LM_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
#define LM_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define LM_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define LM_SYSCON_DC9_OFFSET 0x190 /* Device Capabilities */
#define LM_SYSCON_NVMSTAT_OFFSET 0x1a0 /* Non-Volatile Memory Information */
#define TIVA_SYSCON_DC9_OFFSET 0x190 /* Device Capabilities */
#define TIVA_SYSCON_NVMSTAT_OFFSET 0x1a0 /* Non-Volatile Memory Information */
/* System Control Register Addresses ********************************************************/
#define LM_SYSCON_DID0 (LM_SYSCON_BASE + LM_SYSCON_DID0_OFFSET)
#define LM_SYSCON_DID1 (LM_SYSCON_BASE + LM_SYSCON_DID1_OFFSET)
#define LM_SYSCON_PBORCTL (LM_SYSCON_BASE + LM_SYSCON_PBORCTL_OFFSET)
#define LM_SYSCON_RIS (LM_SYSCON_BASE + LM_SYSCON_RIS_OFFSET)
#define LM_SYSCON_IMC (LM_SYSCON_BASE + LM_SYSCON_IMC_OFFSET)
#define LM_SYSCON_MISC (LM_SYSCON_BASE + LM_SYSCON_MISC_OFFSET)
#define LM_SYSCON_RESC (LM_SYSCON_BASE + LM_SYSCON_RESC_OFFSET)
#define LM_SYSCON_RCC (LM_SYSCON_BASE + LM_SYSCON_RCC_OFFSET)
#define LM_SYSCON_GPIOHBCTL (LM_SYSCON_BASE + LM_SYSCON_GPIOHBCTL_OFFSET)
#define LM_SYSCON_RCC2 (LM_SYSCON_BASE + LM_SYSCON_RCC2_OFFSET)
#define LM_SYSCON_MOSCCTL (LM_SYSCON_BASE + LM_SYSCON_MOSCCTL_OFFSET)
#define LM_SYSCON_DSLPCLKCFG (LM_SYSCON_BASE + LM_SYSCON_DSLPCLKCFG_OFFSET)
#define LM_SYSCON_SYSPROP (LM_SYSCON_BASE + LM_SYSCON_SYSPROP_OFFSET)
#define LM_SYSCON_PIOSCCAL (LM_SYSCON_BASE + LM_SYSCON_PIOSCCAL_OFFSET)
#define LM_SYSCON_PIOSCSTAT (LM_SYSCON_BASE + LM_SYSCON_PIOSCSTAT_OFFSET)
#define LM_SYSCON_PLLFREQ0 (LM_SYSCON_BASE + LM_SYSCON_PLLFREQ0_OFFSET)
#define LM_SYSCON_PLLFREQ1 (LM_SYSCON_BASE + LM_SYSCON_PLLFREQ1_OFFSET)
#define LM_SYSCON_PLLSTAT (LM_SYSCON_BASE + LM_SYSCON_PLLSTAT_OFFSET)
#define TIVA_SYSCON_DID0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID0_OFFSET)
#define TIVA_SYSCON_DID1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID1_OFFSET)
#define TIVA_SYSCON_PBORCTL (TIVA_SYSCON_BASE + TIVA_SYSCON_PBORCTL_OFFSET)
#define TIVA_SYSCON_RIS (TIVA_SYSCON_BASE + TIVA_SYSCON_RIS_OFFSET)
#define TIVA_SYSCON_IMC (TIVA_SYSCON_BASE + TIVA_SYSCON_IMC_OFFSET)
#define TIVA_SYSCON_MISC (TIVA_SYSCON_BASE + TIVA_SYSCON_MISC_OFFSET)
#define TIVA_SYSCON_RESC (TIVA_SYSCON_BASE + TIVA_SYSCON_RESC_OFFSET)
#define TIVA_SYSCON_RCC (TIVA_SYSCON_BASE + TIVA_SYSCON_RCC_OFFSET)
#define TIVA_SYSCON_GPIOHBCTL (TIVA_SYSCON_BASE + TIVA_SYSCON_GPIOHBCTL_OFFSET)
#define TIVA_SYSCON_RCC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCC2_OFFSET)
#define TIVA_SYSCON_MOSCCTL (TIVA_SYSCON_BASE + TIVA_SYSCON_MOSCCTL_OFFSET)
#define TIVA_SYSCON_DSLPCLKCFG (TIVA_SYSCON_BASE + TIVA_SYSCON_DSLPCLKCFG_OFFSET)
#define TIVA_SYSCON_SYSPROP (TIVA_SYSCON_BASE + TIVA_SYSCON_SYSPROP_OFFSET)
#define TIVA_SYSCON_PIOSCCAL (TIVA_SYSCON_BASE + TIVA_SYSCON_PIOSCCAL_OFFSET)
#define TIVA_SYSCON_PIOSCSTAT (TIVA_SYSCON_BASE + TIVA_SYSCON_PIOSCSTAT_OFFSET)
#define TIVA_SYSCON_PLLFREQ0 (TIVA_SYSCON_BASE + TIVA_SYSCON_PLLFREQ0_OFFSET)
#define TIVA_SYSCON_PLLFREQ1 (TIVA_SYSCON_BASE + TIVA_SYSCON_PLLFREQ1_OFFSET)
#define TIVA_SYSCON_PLLSTAT (TIVA_SYSCON_BASE + TIVA_SYSCON_PLLSTAT_OFFSET)
#define LM_SYSCON_PPWD (LM_SYSCON_BASE + LM_SYSCON_PPWD_OFFSET)
#define LM_SYSCON_PPTIMER (LM_SYSCON_BASE + LM_SYSCON_PPTIMER_OFFSET)
#define LM_SYSCON_PPGPIO (LM_SYSCON_BASE + LM_SYSCON_PPGPIO_OFFSET)
#define LM_SYSCON_PPDMA (LM_SYSCON_BASE + LM_SYSCON_PPDMA_OFFSET)
#define LM_SYSCON_PPHIB (LM_SYSCON_BASE + LM_SYSCON_PPHIB_OFFSET)
#define LM_SYSCON_PPUART (LM_SYSCON_BASE + LM_SYSCON_PPUART_OFFSET)
#define LM_SYSCON_PPSSI (LM_SYSCON_BASE + LM_SYSCON_PPSSI_OFFSET)
#define LM_SYSCON_PPI2C (LM_SYSCON_BASE + LM_SYSCON_PPI2C_OFFSET)
#define LM_SYSCON_PPUSB (LM_SYSCON_BASE + LM_SYSCON_PPUSB_OFFSET)
#define LM_SYSCON_PPCAN (LM_SYSCON_BASE + LM_SYSCON_PPCAN_OFFSET)
#define LM_SYSCON_PPADC (LM_SYSCON_BASE + LM_SYSCON_PPADC_OFFSET)
#define LM_SYSCON_PPACMP (LM_SYSCON_BASE + LM_SYSCON_PPACMP_OFFSET)
#define LM_SYSCON_PPPWM (LM_SYSCON_BASE + LM_SYSCON_PPPWM_OFFSET)
#define LM_SYSCON_PPQEI (LM_SYSCON_BASE + LM_SYSCON_PPQEI_OFFSET)
#define LM_SYSCON_PPEEPROM (LM_SYSCON_BASE + LM_SYSCON_PPEEPROM_OFFSET)
#define LM_SYSCON_PPWTIMER (LM_SYSCON_BASE + LM_SYSCON_PPWTIMER_OFFSET)
#define TIVA_SYSCON_PPWD (TIVA_SYSCON_BASE + TIVA_SYSCON_PPWD_OFFSET)
#define TIVA_SYSCON_PPTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_PPTIMER_OFFSET)
#define TIVA_SYSCON_PPGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_PPGPIO_OFFSET)
#define TIVA_SYSCON_PPDMA (TIVA_SYSCON_BASE + TIVA_SYSCON_PPDMA_OFFSET)
#define TIVA_SYSCON_PPHIB (TIVA_SYSCON_BASE + TIVA_SYSCON_PPHIB_OFFSET)
#define TIVA_SYSCON_PPUART (TIVA_SYSCON_BASE + TIVA_SYSCON_PPUART_OFFSET)
#define TIVA_SYSCON_PPSSI (TIVA_SYSCON_BASE + TIVA_SYSCON_PPSSI_OFFSET)
#define TIVA_SYSCON_PPI2C (TIVA_SYSCON_BASE + TIVA_SYSCON_PPI2C_OFFSET)
#define TIVA_SYSCON_PPUSB (TIVA_SYSCON_BASE + TIVA_SYSCON_PPUSB_OFFSET)
#define TIVA_SYSCON_PPCAN (TIVA_SYSCON_BASE + TIVA_SYSCON_PPCAN_OFFSET)
#define TIVA_SYSCON_PPADC (TIVA_SYSCON_BASE + TIVA_SYSCON_PPADC_OFFSET)
#define TIVA_SYSCON_PPACMP (TIVA_SYSCON_BASE + TIVA_SYSCON_PPACMP_OFFSET)
#define TIVA_SYSCON_PPPWM (TIVA_SYSCON_BASE + TIVA_SYSCON_PPPWM_OFFSET)
#define TIVA_SYSCON_PPQEI (TIVA_SYSCON_BASE + TIVA_SYSCON_PPQEI_OFFSET)
#define TIVA_SYSCON_PPEEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_PPEEPROM_OFFSET)
#define TIVA_SYSCON_PPWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_PPWTIMER_OFFSET)
#define LM_SYSCON_SRWD (LM_SYSCON_BASE + LM_SYSCON_SRWD_OFFSET)
#define LM_SYSCON_SRTIMER (LM_SYSCON_BASE + LM_SYSCON_SRTIMER_OFFSET)
#define LM_SYSCON_SRGPIO (LM_SYSCON_BASE + LM_SYSCON_SRGPIO_OFFSET)
#define LM_SYSCON_SRDMA (LM_SYSCON_BASE + LM_SYSCON_SRDMA_OFFSET)
#define LM_SYSCON_SRHIB (LM_SYSCON_BASE + LM_SYSCON_SRHIB_OFFSET)
#define LM_SYSCON_SRUART (LM_SYSCON_BASE + LM_SYSCON_SRUART_OFFSET)
#define LM_SYSCON_SRSSI (LM_SYSCON_BASE + LM_SYSCON_SRSSI_OFFSET)
#define LM_SYSCON_SRI2C (LM_SYSCON_BASE + LM_SYSCON_SRI2C_OFFSET)
#define LM_SYSCON_SRUSB (LM_SYSCON_BASE + LM_SYSCON_SRUSB_OFFSET)
#define LM_SYSCON_SRCAN (LM_SYSCON_BASE + LM_SYSCON_SRCAN_OFFSET)
#define LM_SYSCON_SRADC (LM_SYSCON_BASE + LM_SYSCON_SRADC_OFFSET)
#define LM_SYSCON_SRACMP (LM_SYSCON_BASE + LM_SYSCON_SRACMP_OFFSET)
#define LM_SYSCON_SREEPROM (LM_SYSCON_BASE + LM_SYSCON_SREEPROM_OFFSET)
#define LM_SYSCON_SRWTIMER (LM_SYSCON_BASE + LM_SYSCON_SRWTIMER_OFFSET)
#define TIVA_SYSCON_SRWD (TIVA_SYSCON_BASE + TIVA_SYSCON_SRWD_OFFSET)
#define TIVA_SYSCON_SRTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_SRTIMER_OFFSET)
#define TIVA_SYSCON_SRGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_SRGPIO_OFFSET)
#define TIVA_SYSCON_SRDMA (TIVA_SYSCON_BASE + TIVA_SYSCON_SRDMA_OFFSET)
#define TIVA_SYSCON_SRHIB (TIVA_SYSCON_BASE + TIVA_SYSCON_SRHIB_OFFSET)
#define TIVA_SYSCON_SRUART (TIVA_SYSCON_BASE + TIVA_SYSCON_SRUART_OFFSET)
#define TIVA_SYSCON_SRSSI (TIVA_SYSCON_BASE + TIVA_SYSCON_SRSSI_OFFSET)
#define TIVA_SYSCON_SRI2C (TIVA_SYSCON_BASE + TIVA_SYSCON_SRI2C_OFFSET)
#define TIVA_SYSCON_SRUSB (TIVA_SYSCON_BASE + TIVA_SYSCON_SRUSB_OFFSET)
#define TIVA_SYSCON_SRCAN (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCAN_OFFSET)
#define TIVA_SYSCON_SRADC (TIVA_SYSCON_BASE + TIVA_SYSCON_SRADC_OFFSET)
#define TIVA_SYSCON_SRACMP (TIVA_SYSCON_BASE + TIVA_SYSCON_SRACMP_OFFSET)
#define TIVA_SYSCON_SREEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_SREEPROM_OFFSET)
#define TIVA_SYSCON_SRWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_SRWTIMER_OFFSET)
#define LM_SYSCON_RCGCWD (LM_SYSCON_BASE + LM_SYSCON_RCGCWD_OFFSET)
#define LM_SYSCON_RCGCTIMER (LM_SYSCON_BASE + LM_SYSCON_RCGCTIMER_OFFSET)
#define LM_SYSCON_RCGCGPIO (LM_SYSCON_BASE + LM_SYSCON_RCGCGPIO_OFFSET)
#define LM_SYSCON_RCGCDMA (LM_SYSCON_BASE + LM_SYSCON_RCGCDMA_OFFSET)
#define LM_SYSCON_RCGCHIB (LM_SYSCON_BASE + LM_SYSCON_RCGCHIB_OFFSET)
#define LM_SYSCON_RCGCUART (LM_SYSCON_BASE + LM_SYSCON_RCGCUART_OFFSET)
#define LM_SYSCON_RCGCSSI (LM_SYSCON_BASE + LM_SYSCON_RCGCSSI_OFFSET)
#define LM_SYSCON_RCGCI2C (LM_SYSCON_BASE + LM_SYSCON_RCGCI2C_OFFSET)
#define LM_SYSCON_RCGCUSB (LM_SYSCON_BASE + LM_SYSCON_RCGCUSB_OFFSET)
#define LM_SYSCON_RCGCCAN (LM_SYSCON_BASE + LM_SYSCON_RCGCCAN_OFFSET)
#define LM_SYSCON_RCGCADC (LM_SYSCON_BASE + LM_SYSCON_RCGCADC_OFFSET)
#define LM_SYSCON_RCGCACMP (LM_SYSCON_BASE + LM_SYSCON_RCGCACMP_OFFSET)
#define LM_SYSCON_RCGCEEPROM (LM_SYSCON_BASE + LM_SYSCON_RCGCEEPROM_OFFSET)
#define LM_SYSCON_RCGCWTIMER (LM_SYSCON_BASE + LM_SYSCON_RCGCWTIMER_OFFSET)
#define TIVA_SYSCON_RCGCWD (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCWD_OFFSET)
#define TIVA_SYSCON_RCGCTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCTIMER_OFFSET)
#define TIVA_SYSCON_RCGCGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCGPIO_OFFSET)
#define TIVA_SYSCON_RCGCDMA (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCDMA_OFFSET)
#define TIVA_SYSCON_RCGCHIB (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCHIB_OFFSET)
#define TIVA_SYSCON_RCGCUART (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCUART_OFFSET)
#define TIVA_SYSCON_RCGCSSI (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCSSI_OFFSET)
#define TIVA_SYSCON_RCGCI2C (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCI2C_OFFSET)
#define TIVA_SYSCON_RCGCUSB (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCUSB_OFFSET)
#define TIVA_SYSCON_RCGCCAN (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCCAN_OFFSET)
#define TIVA_SYSCON_RCGCADC (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCADC_OFFSET)
#define TIVA_SYSCON_RCGCACMP (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCACMP_OFFSET)
#define TIVA_SYSCON_RCGCEEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCEEPROM_OFFSET)
#define TIVA_SYSCON_RCGCWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCWTIMER_OFFSET)
#define LM_SYSCON_SCGCWD (LM_SYSCON_BASE + LM_SYSCON_SCGCWD_OFFSET)
#define LM_SYSCON_SCGCTIMER (LM_SYSCON_BASE + LM_SYSCON_SCGCTIMER_OFFSET)
#define LM_SYSCON_SCGCGPIO (LM_SYSCON_BASE + LM_SYSCON_SCGCGPIO_OFFSET)
#define LM_SYSCON_SCGCDMA (LM_SYSCON_BASE + LM_SYSCON_SCGCDMA_OFFSET)
#define LM_SYSCON_SCGCHIB (LM_SYSCON_BASE + LM_SYSCON_SCGCHIB_OFFSET)
#define LM_SYSCON_SCGCUART (LM_SYSCON_BASE + LM_SYSCON_SCGCUART_OFFSET)
#define LM_SYSCON_SCGCSSI (LM_SYSCON_BASE + LM_SYSCON_SCGCSSI_OFFSET)
#define LM_SYSCON_SCGCI2C (LM_SYSCON_BASE + LM_SYSCON_SCGCI2C_OFFSET)
#define LM_SYSCON_SCGCUSB (LM_SYSCON_BASE + LM_SYSCON_SCGCUSB_OFFSET)
#define LM_SYSCON_SCGCCAN (LM_SYSCON_BASE + LM_SYSCON_SCGCCAN_OFFSET)
#define LM_SYSCON_SCGCADC (LM_SYSCON_BASE + LM_SYSCON_SCGCADC_OFFSET)
#define LM_SYSCON_SCGCACMP (LM_SYSCON_BASE + LM_SYSCON_SCGCACMP_OFFSET)
#define LM_SYSCON_SCGCEEPROM (LM_SYSCON_BASE + LM_SYSCON_SCGCEEPROM_OFFSET)
#define LM_SYSCON_SCGCWTIMER (LM_SYSCON_BASE + LM_SYSCON_SCGCWTIMER_OFFSET)
#define TIVA_SYSCON_SCGCWD (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCWD_OFFSET)
#define TIVA_SYSCON_SCGCTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCTIMER_OFFSET)
#define TIVA_SYSCON_SCGCGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCGPIO_OFFSET)
#define TIVA_SYSCON_SCGCDMA (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCDMA_OFFSET)
#define TIVA_SYSCON_SCGCHIB (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCHIB_OFFSET)
#define TIVA_SYSCON_SCGCUART (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCUART_OFFSET)
#define TIVA_SYSCON_SCGCSSI (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCSSI_OFFSET)
#define TIVA_SYSCON_SCGCI2C (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCI2C_OFFSET)
#define TIVA_SYSCON_SCGCUSB (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCUSB_OFFSET)
#define TIVA_SYSCON_SCGCCAN (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCCAN_OFFSET)
#define TIVA_SYSCON_SCGCADC (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCADC_OFFSET)
#define TIVA_SYSCON_SCGCACMP (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCACMP_OFFSET)
#define TIVA_SYSCON_SCGCEEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCEEPROM_OFFSET)
#define TIVA_SYSCON_SCGCWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGCWTIMER_OFFSET)
#define LM_SYSCON_DCGCWD (LM_SYSCON_BASE + LM_SYSCON_DCGCWD_OFFSET)
#define LM_SYSCON_DCGCTIMER (LM_SYSCON_BASE + LM_SYSCON_DCGCTIMER_OFFSET)
#define LM_SYSCON_DCGCGPIO (LM_SYSCON_BASE + LM_SYSCON_DCGCGPIO_OFFSET)
#define LM_SYSCON_DCGCDMA (LM_SYSCON_BASE + LM_SYSCON_DCGCDMA_OFFSET)
#define LM_SYSCON_DCGCHIB (LM_SYSCON_BASE + LM_SYSCON_DCGCHIB_OFFSET)
#define LM_SYSCON_DCGCUART (LM_SYSCON_BASE + LM_SYSCON_DCGCUART_OFFSET)
#define LM_SYSCON_DCGCSSI (LM_SYSCON_BASE + LM_SYSCON_DCGCSSI_OFFSET)
#define LM_SYSCON_DCGCI2C (LM_SYSCON_BASE + LM_SYSCON_DCGCI2C_OFFSET)
#define LM_SYSCON_DCGCUSB (LM_SYSCON_BASE + LM_SYSCON_DCGCUSB_OFFSET)
#define LM_SYSCON_DCGCCAN (LM_SYSCON_BASE + LM_SYSCON_DCGCCAN_OFFSET)
#define LM_SYSCON_DCGCADC (LM_SYSCON_BASE + LM_SYSCON_DCGCADC_OFFSET)
#define LM_SYSCON_DCGCACMP (LM_SYSCON_BASE + LM_SYSCON_DCGCACMP_OFFSET)
#define LM_SYSCON_DCGCEEPROM (LM_SYSCON_BASE + LM_SYSCON_DCGCEEPROM_OFFSET)
#define LM_SYSCON_DCGCWTIMER (LM_SYSCON_BASE + LM_SYSCON_DCGCWTIMER_OFFSET)
#define TIVA_SYSCON_DCGCWD (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCWD_OFFSET)
#define TIVA_SYSCON_DCGCTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCTIMER_OFFSET)
#define TIVA_SYSCON_DCGCGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCGPIO_OFFSET)
#define TIVA_SYSCON_DCGCDMA (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCDMA_OFFSET)
#define TIVA_SYSCON_DCGCHIB (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCHIB_OFFSET)
#define TIVA_SYSCON_DCGCUART (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCUART_OFFSET)
#define TIVA_SYSCON_DCGCSSI (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCSSI_OFFSET)
#define TIVA_SYSCON_DCGCI2C (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCI2C_OFFSET)
#define TIVA_SYSCON_DCGCUSB (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCUSB_OFFSET)
#define TIVA_SYSCON_DCGCCAN (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCCAN_OFFSET)
#define TIVA_SYSCON_DCGCADC (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCADC_OFFSET)
#define TIVA_SYSCON_DCGCACMP (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCACMP_OFFSET)
#define TIVA_SYSCON_DCGCEEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCEEPROM_OFFSET)
#define TIVA_SYSCON_DCGCWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGCWTIMER_OFFSET)
#define LM_SYSCON_PRWD (LM_SYSCON_BASE + LM_SYSCON_PRWD_OFFSET)
#define LM_SYSCON_PRTIMER (LM_SYSCON_BASE + LM_SYSCON_PRTIMER_OFFSET)
#define LM_SYSCON_PRGPIO (LM_SYSCON_BASE + LM_SYSCON_PRGPIO_OFFSET)
#define LM_SYSCON_PRDMA (LM_SYSCON_BASE + LM_SYSCON_PRDMA_OFFSET)
#define LM_SYSCON_PRHIB (LM_SYSCON_BASE + LM_SYSCON_PRHIB_OFFSET)
#define LM_SYSCON_PRUART (LM_SYSCON_BASE + LM_SYSCON_PRUART_OFFSET)
#define LM_SYSCON_PRSSI (LM_SYSCON_BASE + LM_SYSCON_PRSSI_OFFSET)
#define LM_SYSCON_PRI2C (LM_SYSCON_BASE + LM_SYSCON_PRI2C_OFFSET)
#define LM_SYSCON_PRUSB (LM_SYSCON_BASE + LM_SYSCON_PRUSB_OFFSET)
#define LM_SYSCON_PRCAN (LM_SYSCON_BASE + LM_SYSCON_PRCAN_OFFSET)
#define LM_SYSCON_PRADC (LM_SYSCON_BASE + LM_SYSCON_PRADC_OFFSET)
#define LM_SYSCON_PRACMP (LM_SYSCON_BASE + LM_SYSCON_PRACMP_OFFSET)
#define LM_SYSCON_PREEPROM (LM_SYSCON_BASE + LM_SYSCON_PREEPROM_OFFSET)
#define LM_SYSCON_PRWTIMER (LM_SYSCON_BASE + LM_SYSCON_PRWTIMER_OFFSET)
#define TIVA_SYSCON_PRWD (TIVA_SYSCON_BASE + TIVA_SYSCON_PRWD_OFFSET)
#define TIVA_SYSCON_PRTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_PRTIMER_OFFSET)
#define TIVA_SYSCON_PRGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_PRGPIO_OFFSET)
#define TIVA_SYSCON_PRDMA (TIVA_SYSCON_BASE + TIVA_SYSCON_PRDMA_OFFSET)
#define TIVA_SYSCON_PRHIB (TIVA_SYSCON_BASE + TIVA_SYSCON_PRHIB_OFFSET)
#define TIVA_SYSCON_PRUART (TIVA_SYSCON_BASE + TIVA_SYSCON_PRUART_OFFSET)
#define TIVA_SYSCON_PRSSI (TIVA_SYSCON_BASE + TIVA_SYSCON_PRSSI_OFFSET)
#define TIVA_SYSCON_PRI2C (TIVA_SYSCON_BASE + TIVA_SYSCON_PRI2C_OFFSET)
#define TIVA_SYSCON_PRUSB (TIVA_SYSCON_BASE + TIVA_SYSCON_PRUSB_OFFSET)
#define TIVA_SYSCON_PRCAN (TIVA_SYSCON_BASE + TIVA_SYSCON_PRCAN_OFFSET)
#define TIVA_SYSCON_PRADC (TIVA_SYSCON_BASE + TIVA_SYSCON_PRADC_OFFSET)
#define TIVA_SYSCON_PRACMP (TIVA_SYSCON_BASE + TIVA_SYSCON_PRACMP_OFFSET)
#define TIVA_SYSCON_PREEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_PREEPROM_OFFSET)
#define TIVA_SYSCON_PRWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_PRWTIMER_OFFSET)
/* System Control Legacy Register Addresses *************************************************/
#define LM_SYSCON_DC0 (LM_SYSCON_BASE + LM_SYSCON_DC0_OFFSET)
#define LM_SYSCON_DC1 (LM_SYSCON_BASE + LM_SYSCON_DC1_OFFSET)
#define LM_SYSCON_DC2 (LM_SYSCON_BASE + LM_SYSCON_DC2_OFFSET)
#define LM_SYSCON_DC3 (LM_SYSCON_BASE + LM_SYSCON_DC3_OFFSET)
#define LM_SYSCON_DC4 (LM_SYSCON_BASE + LM_SYSCON_DC4_OFFSET)
#define LM_SYSCON_DC5 (LM_SYSCON_BASE + LM_SYSCON_DC5_OFFSET)
#define LM_SYSCON_DC6 (LM_SYSCON_BASE + LM_SYSCON_DC6_OFFSET)
#define LM_SYSCON_DC7 (LM_SYSCON_BASE + LM_SYSCON_DC7_OFFSET)
#define LM_SYSCON_DC8 (LM_SYSCON_BASE + LM_SYSCON_DC8_OFFSET)
#define TIVA_SYSCON_DC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC0_OFFSET)
#define TIVA_SYSCON_DC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC1_OFFSET)
#define TIVA_SYSCON_DC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC2_OFFSET)
#define TIVA_SYSCON_DC3 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC3_OFFSET)
#define TIVA_SYSCON_DC4 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC4_OFFSET)
#define TIVA_SYSCON_DC5 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC5_OFFSET)
#define TIVA_SYSCON_DC6 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC6_OFFSET)
#define TIVA_SYSCON_DC7 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC7_OFFSET)
#define TIVA_SYSCON_DC8 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC8_OFFSET)
#define LM_SYSCON_SRCR0 (LM_SYSCON_BASE + LM_SYSCON_SRCR0_OFFSET)
#define LM_SYSCON_SRCR1 (LM_SYSCON_BASE + LM_SYSCON_SRCR1_OFFSET)
#define LM_SYSCON_SRCR2 (LM_SYSCON_BASE + LM_SYSCON_SRCR2_OFFSET)
#define TIVA_SYSCON_SRCR0 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR0_OFFSET)
#define TIVA_SYSCON_SRCR1 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR1_OFFSET)
#define TIVA_SYSCON_SRCR2 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR2_OFFSET)
#define LM_SYSCON_RCGC0 (LM_SYSCON_BASE + LM_SYSCON_RCGC0_OFFSET)
#define LM_SYSCON_RCGC1 (LM_SYSCON_BASE + LM_SYSCON_RCGC1_OFFSET)
#define LM_SYSCON_RCGC2 (LM_SYSCON_BASE + LM_SYSCON_RCGC2_OFFSET)
#define TIVA_SYSCON_RCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC0_OFFSET)
#define TIVA_SYSCON_RCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC1_OFFSET)
#define TIVA_SYSCON_RCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC2_OFFSET)
#define LM_SYSCON_SCGC0 (LM_SYSCON_BASE + LM_SYSCON_SCGC0_OFFSET)
#define LM_SYSCON_SCGC1 (LM_SYSCON_BASE + LM_SYSCON_SCGC1_OFFSET)
#define LM_SYSCON_SCGC2 (LM_SYSCON_BASE + LM_SYSCON_SCGC2_OFFSET)
#define TIVA_SYSCON_SCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC0_OFFSET)
#define TIVA_SYSCON_SCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC1_OFFSET)
#define TIVA_SYSCON_SCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC2_OFFSET)
#define LM_SYSCON_DCGC0 (LM_SYSCON_BASE + LM_SYSCON_DCGC0_OFFSET)
#define LM_SYSCON_DCGC1 (LM_SYSCON_BASE + LM_SYSCON_DCGC1_OFFSET)
#define LM_SYSCON_DCGC2 (LM_SYSCON_BASE + LM_SYSCON_DCGC2_OFFSET)
#define TIVA_SYSCON_DCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC0_OFFSET)
#define TIVA_SYSCON_DCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC1_OFFSET)
#define TIVA_SYSCON_DCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC2_OFFSET)
#define LM_SYSCON_DC9 (LM_SYSCON_BASE + LM_SYSCON_DC9_OFFSET)
#define LM_SYSCON_NVMSTAT (LM_SYSCON_BASE + LM_SYSCON_NVMSTAT_OFFSET)
#define TIVA_SYSCON_DC9 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC9_OFFSET)
#define TIVA_SYSCON_NVMSTAT (TIVA_SYSCON_BASE + TIVA_SYSCON_NVMSTAT_OFFSET)
/* System Control Register Bit Definitions **************************************************/
@ -1241,99 +1241,99 @@
/* Device Capabilities 5 */
#define LM_SYSCON_DC5_PWM0 (1 << 0) /* Bit 0: PWM0 Pin Present */
#define LM_SYSCON_DC5_PWM1 (1 << 1) /* Bit 1: PWM1 Pin Present */
#define LM_SYSCON_DC5_PWM2 (1 << 2) /* Bit 2: PWM2 Pin Present */
#define LM_SYSCON_DC5_PWM3 (1 << 3) /* Bit 3: PWM3 Pin Present */
#define LM_SYSCON_DC5_PWM4 (1 << 4) /* Bit 4: PWM4 Pin Present */
#define LM_SYSCON_DC5_PWM5 (1 << 5) /* Bit 5: PWM5 Pin Present */
#define LM_SYSCON_DC5_PWM6 (1 << 6) /* Bit 6: PWM6 Pin Present */
#define LM_SYSCON_DC5_PWM7 (1 << 7) /* Bit 7: PWM7 Pin Present */
#define LM_SYSCON_DC5_PWMESYNC (1 << 20) /* Bit 20: PWM Extended SYNC Active */
#define LM_SYSCON_DC5_PWMEFLT (1 << 21) /* Bit 21: PWM Extended Fault Active */
#define LM_SYSCON_DC5_PWMFAULT0 (1 << 24) /* Bit 24: PWM Fault 0 Pin Present */
#define LM_SYSCON_DC5_PWMFAULT1 (1 << 25) /* Bit 25: PWM Fault 1 Pin Present */
#define LM_SYSCON_DC5_PWMFAULT2 (1 << 26) /* Bit 26: PWM Fault 2 Pin Present */
#define LM_SYSCON_DC5_PWMFAULT3 (1 << 27) /* Bit 27: PWM Fault 3 Pin Present */
#define TIVA_SYSCON_DC5_PWM0 (1 << 0) /* Bit 0: PWM0 Pin Present */
#define TIVA_SYSCON_DC5_PWM1 (1 << 1) /* Bit 1: PWM1 Pin Present */
#define TIVA_SYSCON_DC5_PWM2 (1 << 2) /* Bit 2: PWM2 Pin Present */
#define TIVA_SYSCON_DC5_PWM3 (1 << 3) /* Bit 3: PWM3 Pin Present */
#define TIVA_SYSCON_DC5_PWM4 (1 << 4) /* Bit 4: PWM4 Pin Present */
#define TIVA_SYSCON_DC5_PWM5 (1 << 5) /* Bit 5: PWM5 Pin Present */
#define TIVA_SYSCON_DC5_PWM6 (1 << 6) /* Bit 6: PWM6 Pin Present */
#define TIVA_SYSCON_DC5_PWM7 (1 << 7) /* Bit 7: PWM7 Pin Present */
#define TIVA_SYSCON_DC5_PWMESYNC (1 << 20) /* Bit 20: PWM Extended SYNC Active */
#define TIVA_SYSCON_DC5_PWMEFLT (1 << 21) /* Bit 21: PWM Extended Fault Active */
#define TIVA_SYSCON_DC5_PWMFAULT0 (1 << 24) /* Bit 24: PWM Fault 0 Pin Present */
#define TIVA_SYSCON_DC5_PWMFAULT1 (1 << 25) /* Bit 25: PWM Fault 1 Pin Present */
#define TIVA_SYSCON_DC5_PWMFAULT2 (1 << 26) /* Bit 26: PWM Fault 2 Pin Present */
#define TIVA_SYSCON_DC5_PWMFAULT3 (1 << 27) /* Bit 27: PWM Fault 3 Pin Present */
/* Device Capabilities 6 */
#define LM_SYSCON_DC6_USB0_SHIFT (0) /* Bits 0-1: USB Module 0 Present */
#define LM_SYSCON_DC6_USB0_MASK (3 << LM_SYSCON_DC6_USB0_SHIFT)
# define LM_SYSCON_DC6_USB0_NONE (1 << LM_SYSCON_DC6_USB0_SHIFT)
# define LM_SYSCON_DC6_USB0_DEVICE (2 << LM_SYSCON_DC6_USB0_SHIFT)
# define LM_SYSCON_DC6_USB0_HOST (3 << LM_SYSCON_DC6_USB0_SHIFT)
# define LM_SYSCON_DC6_USB0_OTG (3 << LM_SYSCON_DC6_USB0_SHIFT)
#define LM_SYSCON_DC6_USB0PHY (1 << 4) /* Bit 4: USB Module 0 PHY Present */
#define TIVA_SYSCON_DC6_USB0_SHIFT (0) /* Bits 0-1: USB Module 0 Present */
#define TIVA_SYSCON_DC6_USB0_MASK (3 << TIVA_SYSCON_DC6_USB0_SHIFT)
# define TIVA_SYSCON_DC6_USB0_NONE (1 << TIVA_SYSCON_DC6_USB0_SHIFT)
# define TIVA_SYSCON_DC6_USB0_DEVICE (2 << TIVA_SYSCON_DC6_USB0_SHIFT)
# define TIVA_SYSCON_DC6_USB0_HOST (3 << TIVA_SYSCON_DC6_USB0_SHIFT)
# define TIVA_SYSCON_DC6_USB0_OTG (3 << TIVA_SYSCON_DC6_USB0_SHIFT)
#define TIVA_SYSCON_DC6_USB0PHY (1 << 4) /* Bit 4: USB Module 0 PHY Present */
/* Device Capabilities 7 */
#define LM_SYSCON_DC7_DMACH0 (1 << 0) /* Bit 0: DMA Channel 0 */
#define LM_SYSCON_DC7_DMACH1 (1 << 1) /* Bit 1: DMA Channel 1 */
#define LM_SYSCON_DC7_DMACH2 (1 << 2) /* Bit 2: DMA Channel 2 */
#define LM_SYSCON_DC7_DMACH3 (1 << 3) /* Bit 3: DMA Channel 3 */
#define LM_SYSCON_DC7_DMACH4 (1 << 4) /* Bit 4: DMA Channel 4 */
#define LM_SYSCON_DC7_DMACH5 (1 << 5) /* Bit 5: DMA Channel 5 */
#define LM_SYSCON_DC7_DMACH6 (1 << 6) /* Bit 6: DMA Channel 6 */
#define LM_SYSCON_DC7_DMACH7 (1 << 7) /* Bit 7: DMA Channel 7 */
#define LM_SYSCON_DC7_DMACH8 (1 << 8) /* Bit 8: DMA Channel 8 */
#define LM_SYSCON_DC7_DMACH9 (1 << 9) /* Bit 9: DMA Channel 9 */
#define LM_SYSCON_DC7_DMACH10 (1 << 10) /* Bit 10: DMA Channel 10 */
#define LM_SYSCON_DC7_DMACH11 (1 << 11) /* Bit 11: DMA Channel 11 */
#define LM_SYSCON_DC7_DMACH12 (1 << 12) /* Bit 12: DMA Channel 12 */
#define LM_SYSCON_DC7_DMACH13 (1 << 13) /* Bit 13: DMA Channel 13 */
#define LM_SYSCON_DC7_DMACH14 (1 << 14) /* Bit 14: DMA Channel 14 */
#define LM_SYSCON_DC7_DMACH15 (1 << 15) /* Bit 15: DMA Channel 15 */
#define LM_SYSCON_DC7_DMACH16 (1 << 16) /* Bit 16: DMA Channel 16 */
#define LM_SYSCON_DC7_DMACH17 (1 << 17) /* Bit 17: DMA Channel 17 */
#define LM_SYSCON_DC7_DMACH18 (1 << 18) /* Bit 18: DMA Channel 18 */
#define LM_SYSCON_DC7_DMACH19 (1 << 19) /* Bit 19: DMA Channel 19 */
#define LM_SYSCON_DC7_DMACH20 (1 << 20) /* Bit 20: DMA Channel 20 */
#define LM_SYSCON_DC7_DMACH21 (1 << 21) /* Bit 21: DMA Channel 21 */
#define LM_SYSCON_DC7_DMACH22 (1 << 22) /* Bit 22: DMA Channel 22 */
#define LM_SYSCON_DC7_DMACH23 (1 << 23) /* Bit 23: DMA Channel 23 */
#define LM_SYSCON_DC7_DMACH24 (1 << 24) /* Bit 24: DMA Channel 24 */
#define LM_SYSCON_DC7_DMACH25 (1 << 25) /* Bit 25: DMA Channel 25 */
#define LM_SYSCON_DC7_DMACH26 (1 << 26) /* Bit 26: DMA Channel 26 */
#define LM_SYSCON_DC7_DMACH27 (1 << 27) /* Bit 27: DMA Channel 27 */
#define LM_SYSCON_DC7_DMACH28 (1 << 28) /* Bit 28: DMA Channel 28 */
#define LM_SYSCON_DC7_DMACH29 (1 << 29) /* Bit 29: DMA Channel 29 */
#define LM_SYSCON_DC7_DMACH30 (1 << 30) /* Bit 30: DMA Channel 30 */
#define TIVA_SYSCON_DC7_DMACH0 (1 << 0) /* Bit 0: DMA Channel 0 */
#define TIVA_SYSCON_DC7_DMACH1 (1 << 1) /* Bit 1: DMA Channel 1 */
#define TIVA_SYSCON_DC7_DMACH2 (1 << 2) /* Bit 2: DMA Channel 2 */
#define TIVA_SYSCON_DC7_DMACH3 (1 << 3) /* Bit 3: DMA Channel 3 */
#define TIVA_SYSCON_DC7_DMACH4 (1 << 4) /* Bit 4: DMA Channel 4 */
#define TIVA_SYSCON_DC7_DMACH5 (1 << 5) /* Bit 5: DMA Channel 5 */
#define TIVA_SYSCON_DC7_DMACH6 (1 << 6) /* Bit 6: DMA Channel 6 */
#define TIVA_SYSCON_DC7_DMACH7 (1 << 7) /* Bit 7: DMA Channel 7 */
#define TIVA_SYSCON_DC7_DMACH8 (1 << 8) /* Bit 8: DMA Channel 8 */
#define TIVA_SYSCON_DC7_DMACH9 (1 << 9) /* Bit 9: DMA Channel 9 */
#define TIVA_SYSCON_DC7_DMACH10 (1 << 10) /* Bit 10: DMA Channel 10 */
#define TIVA_SYSCON_DC7_DMACH11 (1 << 11) /* Bit 11: DMA Channel 11 */
#define TIVA_SYSCON_DC7_DMACH12 (1 << 12) /* Bit 12: DMA Channel 12 */
#define TIVA_SYSCON_DC7_DMACH13 (1 << 13) /* Bit 13: DMA Channel 13 */
#define TIVA_SYSCON_DC7_DMACH14 (1 << 14) /* Bit 14: DMA Channel 14 */
#define TIVA_SYSCON_DC7_DMACH15 (1 << 15) /* Bit 15: DMA Channel 15 */
#define TIVA_SYSCON_DC7_DMACH16 (1 << 16) /* Bit 16: DMA Channel 16 */
#define TIVA_SYSCON_DC7_DMACH17 (1 << 17) /* Bit 17: DMA Channel 17 */
#define TIVA_SYSCON_DC7_DMACH18 (1 << 18) /* Bit 18: DMA Channel 18 */
#define TIVA_SYSCON_DC7_DMACH19 (1 << 19) /* Bit 19: DMA Channel 19 */
#define TIVA_SYSCON_DC7_DMACH20 (1 << 20) /* Bit 20: DMA Channel 20 */
#define TIVA_SYSCON_DC7_DMACH21 (1 << 21) /* Bit 21: DMA Channel 21 */
#define TIVA_SYSCON_DC7_DMACH22 (1 << 22) /* Bit 22: DMA Channel 22 */
#define TIVA_SYSCON_DC7_DMACH23 (1 << 23) /* Bit 23: DMA Channel 23 */
#define TIVA_SYSCON_DC7_DMACH24 (1 << 24) /* Bit 24: DMA Channel 24 */
#define TIVA_SYSCON_DC7_DMACH25 (1 << 25) /* Bit 25: DMA Channel 25 */
#define TIVA_SYSCON_DC7_DMACH26 (1 << 26) /* Bit 26: DMA Channel 26 */
#define TIVA_SYSCON_DC7_DMACH27 (1 << 27) /* Bit 27: DMA Channel 27 */
#define TIVA_SYSCON_DC7_DMACH28 (1 << 28) /* Bit 28: DMA Channel 28 */
#define TIVA_SYSCON_DC7_DMACH29 (1 << 29) /* Bit 29: DMA Channel 29 */
#define TIVA_SYSCON_DC7_DMACH30 (1 << 30) /* Bit 30: DMA Channel 30 */
/* Device Capabilities 8 */
#define LM_SYSCON_DC8_ADC0AIN0 (1 << 0) /* Bit 0: ADC Module 0 AIN0 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN1 (1 << 1) /* Bit 1: ADC Module 0 AIN1 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN2 (1 << 2) /* Bit 2: ADC Module 0 AIN2 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN3 (1 << 3) /* Bit 3: ADC Module 0 AIN3 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN4 (1 << 4) /* Bit 4: ADC Module 0 AIN4 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN5 (1 << 5) /* Bit 5: ADC Module 0 AIN5 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN6 (1 << 6) /* Bit 6: ADC Module 0 AIN6 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN7 (1 << 7) /* Bit 7: ADC Module 0 AIN7 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN8 (1 << 8) /* Bit 8: ADC Module 0 AIN8 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN9 (1 << 9) /* Bit 9: ADC Module 0 AIN9 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN10 (1 << 10) /* Bit 10: ADC Module 0 AIN10 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN11 (1 << 11) /* Bit 11: ADC Module 0 AIN11 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN12 (1 << 12) /* Bit 12: ADC Module 0 AIN12 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN13 (1 << 13) /* Bit 13: ADC Module 0 AIN13 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN14 (1 << 14) /* Bit 14: ADC Module 0 AIN14 Pin Present */
#define LM_SYSCON_DC8_ADC0AIN15 (1 << 15) /* Bit 15: ADC Module 0 AIN15 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN0 (1 << 16) /* Bit 16: ADC Module 1 AIN0 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN1 (1 << 17) /* Bit 17: ADC Module 1 AIN1 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN2 (1 << 18) /* Bit 18: ADC Module 1 AIN2 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN3 (1 << 19) /* Bit 19: ADC Module 1 AIN3 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN4 (1 << 20) /* Bit 20: ADC Module 1 AIN4 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN5 (1 << 21) /* Bit 21: ADC Module 1 AIN5 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN6 (1 << 22) /* Bit 22: ADC Module 1 AIN6 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN7 (1 << 23) /* Bit 23: ADC Module 1 AIN7 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN8 (1 << 24) /* Bit 24: ADC Module 1 AIN8 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN9 (1 << 25) /* Bit 25: ADC Module 1 AIN9 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN10 (1 << 26) /* Bit 26: ADC Module 1 AIN10 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN11 (1 << 27) /* Bit 27: ADC Module 1 AIN11 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN12 (1 << 28) /* Bit 28: ADC Module 1 AIN12 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN13 (1 << 29) /* Bit 29: ADC Module 1 AIN13 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN14 (1 << 30) /* Bit 30: ADC Module 1 AIN14 Pin Present */
#define LM_SYSCON_DC8_ADC1AIN15 (1 << 31) /* Bit 31: ADC Module 1 AIN15 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN0 (1 << 0) /* Bit 0: ADC Module 0 AIN0 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN1 (1 << 1) /* Bit 1: ADC Module 0 AIN1 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN2 (1 << 2) /* Bit 2: ADC Module 0 AIN2 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN3 (1 << 3) /* Bit 3: ADC Module 0 AIN3 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN4 (1 << 4) /* Bit 4: ADC Module 0 AIN4 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN5 (1 << 5) /* Bit 5: ADC Module 0 AIN5 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN6 (1 << 6) /* Bit 6: ADC Module 0 AIN6 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN7 (1 << 7) /* Bit 7: ADC Module 0 AIN7 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN8 (1 << 8) /* Bit 8: ADC Module 0 AIN8 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN9 (1 << 9) /* Bit 9: ADC Module 0 AIN9 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN10 (1 << 10) /* Bit 10: ADC Module 0 AIN10 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN11 (1 << 11) /* Bit 11: ADC Module 0 AIN11 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN12 (1 << 12) /* Bit 12: ADC Module 0 AIN12 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN13 (1 << 13) /* Bit 13: ADC Module 0 AIN13 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN14 (1 << 14) /* Bit 14: ADC Module 0 AIN14 Pin Present */
#define TIVA_SYSCON_DC8_ADC0AIN15 (1 << 15) /* Bit 15: ADC Module 0 AIN15 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN0 (1 << 16) /* Bit 16: ADC Module 1 AIN0 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN1 (1 << 17) /* Bit 17: ADC Module 1 AIN1 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN2 (1 << 18) /* Bit 18: ADC Module 1 AIN2 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN3 (1 << 19) /* Bit 19: ADC Module 1 AIN3 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN4 (1 << 20) /* Bit 20: ADC Module 1 AIN4 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN5 (1 << 21) /* Bit 21: ADC Module 1 AIN5 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN6 (1 << 22) /* Bit 22: ADC Module 1 AIN6 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN7 (1 << 23) /* Bit 23: ADC Module 1 AIN7 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN8 (1 << 24) /* Bit 24: ADC Module 1 AIN8 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN9 (1 << 25) /* Bit 25: ADC Module 1 AIN9 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN10 (1 << 26) /* Bit 26: ADC Module 1 AIN10 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN11 (1 << 27) /* Bit 27: ADC Module 1 AIN11 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN12 (1 << 28) /* Bit 28: ADC Module 1 AIN12 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN13 (1 << 29) /* Bit 29: ADC Module 1 AIN13 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN14 (1 << 30) /* Bit 30: ADC Module 1 AIN14 Pin Present */
#define TIVA_SYSCON_DC8_ADC1AIN15 (1 << 31) /* Bit 31: ADC Module 1 AIN15 Pin Present */
/* Software Reset Control 0 */
@ -1496,26 +1496,26 @@
/* Device Capabilities */
#define LM_SYSCON_DC9_ADC0DC0 (1 << 0) /* Bit 0: ADC0 DC0 Present */
#define LM_SYSCON_DC9_ADC0DC1 (1 << 1) /* Bit 1: ADC0 DC1 Present */
#define LM_SYSCON_DC9_ADC0DC2 (1 << 2) /* Bit 2: ADC0 DC2 Present */
#define LM_SYSCON_DC9_ADC0DC3 (1 << 3) /* Bit 3: ADC0 DC3 Present */
#define LM_SYSCON_DC9_ADC0DC4 (1 << 4) /* Bit 4: ADC0 DC4 Present */
#define LM_SYSCON_DC9_ADC0DC5 (1 << 5) /* Bit 5: ADC0 DC5 Present */
#define LM_SYSCON_DC9_ADC0DC6 (1 << 6) /* Bit 6: ADC0 DC6 Present */
#define LM_SYSCON_DC9_ADC0DC7 (1 << 7) /* Bit 7: ADC0 DC7 Present */
#define LM_SYSCON_DC9_ADC1DC0 (1 << 16) /* Bit 16: ADC1 DC0 Present */
#define LM_SYSCON_DC9_ADC1DC1 (1 << 17) /* Bit 17: ADC1 DC1 Present */
#define LM_SYSCON_DC9_ADC1DC2 (1 << 18) /* Bit 18: ADC1 DC2 Present */
#define LM_SYSCON_DC9_ADC1DC3 (1 << 19) /* Bit 19: ADC1 DC3 Present */
#define LM_SYSCON_DC9_ADC1DC4 (1 << 20) /* Bit 20: ADC1 DC4 Present */
#define LM_SYSCON_DC9_ADC1DC5 (1 << 21) /* Bit 21: ADC1 DC5 Present */
#define LM_SYSCON_DC9_ADC1DC6 (1 << 22) /* Bit 22: ADC1 DC6 Present */
#define LM_SYSCON_DC9_ADC1DC7 (1 << 23) /* Bit 23: ADC1 DC7 Present */
#define TIVA_SYSCON_DC9_ADC0DC0 (1 << 0) /* Bit 0: ADC0 DC0 Present */
#define TIVA_SYSCON_DC9_ADC0DC1 (1 << 1) /* Bit 1: ADC0 DC1 Present */
#define TIVA_SYSCON_DC9_ADC0DC2 (1 << 2) /* Bit 2: ADC0 DC2 Present */
#define TIVA_SYSCON_DC9_ADC0DC3 (1 << 3) /* Bit 3: ADC0 DC3 Present */
#define TIVA_SYSCON_DC9_ADC0DC4 (1 << 4) /* Bit 4: ADC0 DC4 Present */
#define TIVA_SYSCON_DC9_ADC0DC5 (1 << 5) /* Bit 5: ADC0 DC5 Present */
#define TIVA_SYSCON_DC9_ADC0DC6 (1 << 6) /* Bit 6: ADC0 DC6 Present */
#define TIVA_SYSCON_DC9_ADC0DC7 (1 << 7) /* Bit 7: ADC0 DC7 Present */
#define TIVA_SYSCON_DC9_ADC1DC0 (1 << 16) /* Bit 16: ADC1 DC0 Present */
#define TIVA_SYSCON_DC9_ADC1DC1 (1 << 17) /* Bit 17: ADC1 DC1 Present */
#define TIVA_SYSCON_DC9_ADC1DC2 (1 << 18) /* Bit 18: ADC1 DC2 Present */
#define TIVA_SYSCON_DC9_ADC1DC3 (1 << 19) /* Bit 19: ADC1 DC3 Present */
#define TIVA_SYSCON_DC9_ADC1DC4 (1 << 20) /* Bit 20: ADC1 DC4 Present */
#define TIVA_SYSCON_DC9_ADC1DC5 (1 << 21) /* Bit 21: ADC1 DC5 Present */
#define TIVA_SYSCON_DC9_ADC1DC6 (1 << 22) /* Bit 22: ADC1 DC6 Present */
#define TIVA_SYSCON_DC9_ADC1DC7 (1 << 23) /* Bit 23: ADC1 DC7 Present */
/* Non-Volatile Memory Information */
#define LM_SYSCON_NVMSTAT_FWB (1 << 0) /* Bit 0: 32 Word Flash Write Buffer Available */
#define TIVA_SYSCON_NVMSTAT_FWB (1 << 0) /* Bit 0: 32 Word Flash Write Buffer Available */
/********************************************************************************************
* Public Types

282
arch/arm/src/tiva/chip/lm4f_vectors.h
View file

@ -41,10 +41,10 @@
* Vectors
************************************************************************************/
/* This file is included by lm_vectors.S. It provides the macro VECTOR that
/* This file is included by tiva_vectors.S. It provides the macro VECTOR that
* supplies ach Stellaris vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/lm/lm4f_irq.h.
* lm_vectors.S will define the VECTOR in different ways in order to generate
* tiva_vectors.S will define the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
@ -62,159 +62,159 @@ ARMV7M_PERIPHERAL_INTERRUPTS 155
# else
VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(tiva_gpioa, TIVA_IRQ_GPIOA) /* Vector 16: GPIO Port A */
VECTOR(tiva_gpiob, TIVA_IRQ_GPIOB) /* Vector 17: GPIO Port B */
VECTOR(tiva_gpioc, TIVA_IRQ_GPIOC) /* Vector 18: GPIO Port C */
VECTOR(tiva_gpiod, TIVA_IRQ_GPIOD) /* Vector 19: GPIO Port D */
VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */
UNUSED(LM_RESERVED_26) /* Vector 26: Reserved */
UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */
UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */
UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */
VECTOR(tiva_gpioe, TIVA_IRQ_GPIOE) /* Vector 20: GPIO Port E */
VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
UNUSED(TIVA_RESERVED_25) /* Vector 25: Reserved */
UNUSED(TIVA_RESERVED_26) /* Vector 26: Reserved */
UNUSED(TIVA_RESERVED_27) /* Vector 27: Reserved */
UNUSED(TIVA_RESERVED_28) /* Vector 28: Reserved */
UNUSED(TIVA_RESERVED_29) /* Vector 29: Reserved */
VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timers 0 and 1 */
VECTOR(lm_timer0a, LM_IRQ_TIMER0A) /* Vector 35: 16/32-Bit Timer 0 A */
VECTOR(lm_timer0b, LM_IRQ_TIMER0B) /* Vector 36: 16/32-Bit Timer 0 B */
VECTOR(lm_timer1a, LM_IRQ_TIMER1A) /* Vector 37: 16/32-Bit Timer 1 A */
VECTOR(lm_timer1b, LM_IRQ_TIMER1B) /* Vector 38: 16/32-Bit Timer 1 B */
VECTOR(lm_timer2a, LM_IRQ_TIMER2A) /* Vector 39: 16/32-Bit Timer 2 A */
VECTOR(tiva_adc0, TIVA_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
VECTOR(tiva_adc1, TIVA_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
VECTOR(tiva_adc2, TIVA_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
VECTOR(tiva_adc3, TIVA_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
VECTOR(tiva_wdog, TIVA_IRQ_WDOG) /* Vector 34: Watchdog Timers 0 and 1 */
VECTOR(tiva_timer0a, TIVA_IRQ_TIMER0A) /* Vector 35: 16/32-Bit Timer 0 A */
VECTOR(tiva_timer0b, TIVA_IRQ_TIMER0B) /* Vector 36: 16/32-Bit Timer 0 B */
VECTOR(tiva_timer1a, TIVA_IRQ_TIMER1A) /* Vector 37: 16/32-Bit Timer 1 A */
VECTOR(tiva_timer1b, TIVA_IRQ_TIMER1B) /* Vector 38: 16/32-Bit Timer 1 B */
VECTOR(tiva_timer2a, TIVA_IRQ_TIMER2A) /* Vector 39: 16/32-Bit Timer 2 A */
VECTOR(lm_timer2b, LM_IRQ_TIMER2B) /* Vector 40: 16/32-Bit Timer 2 B */
VECTOR(lm_compare0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(lm_compare1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH and EEPROM Control */
VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
UNUSED(LM_RESERVED_47) /* Vector 47: Reserved */
UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */
VECTOR(lm_uart2, LM_IRQ_UART2) /* Vector 22: UART 2 */
VECTOR(tiva_timer2b, TIVA_IRQ_TIMER2B) /* Vector 40: 16/32-Bit Timer 2 B */
VECTOR(tiva_compare0, TIVA_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
VECTOR(tiva_compare1, TIVA_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
UNUSED(TIVA_RESERVED_43) /* Vector 43: Reserved */
VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH and EEPROM Control */
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
UNUSED(TIVA_RESERVED_47) /* Vector 47: Reserved */
UNUSED(TIVA_RESERVED_48) /* Vector 48: Reserved */
VECTOR(tiva_uart2, TIVA_IRQ_UART2) /* Vector 22: UART 2 */
VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: SSI 1 */
VECTOR(lm_timer3a, LM_IRQ_TIMER3A) /* Vector 51: 16/32-Bit Timer 3 A */
VECTOR(lm_timer3b, LM_IRQ_TIMER3B) /* Vector 52: 16/32-Bit Timer 3 B */
VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */
VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */
UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
UNUSED(LM_RESERVED_58) /* Vector 58: Reserved */
VECTOR(lm_hibernate, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
VECTOR(tiva_ssi1, TIVA_IRQ_SSI1) /* Vector 50: SSI 1 */
VECTOR(tiva_timer3a, TIVA_IRQ_TIMER3A) /* Vector 51: 16/32-Bit Timer 3 A */
VECTOR(tiva_timer3b, TIVA_IRQ_TIMER3B) /* Vector 52: 16/32-Bit Timer 3 B */
VECTOR(tiva_i2c1, TIVA_IRQ_I2C1) /* Vector 53: I2C 1 */
UNUSED(TIVA_RESERVED_54) /* Vector 54: Reserved */
VECTOR(tiva_can0, TIVA_IRQ_CAN0) /* Vector 55: CAN 0 */
UNUSED(TIVA_RESERVED_56) /* Vector 56: Reserved */
UNUSED(TIVA_RESERVED_57) /* Vector 57: Reserved */
UNUSED(TIVA_RESERVED_58) /* Vector 58: Reserved */
VECTOR(tiva_hibernate, TIVA_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
VECTOR(lm_usb, LM_IRQ_USB) /* Vector 60: USB */
UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
VECTOR(lm_udmasoft, LM_IRQ_UDMASOFT) /* Vector 62: uDMA Software */
VECTOR(lm_udmaerro, LM_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
VECTOR(lm_adc1_0, LM_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */
VECTOR(lm_adc1_1, LM_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */
VECTOR(lm_adc1_2, LM_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */
VECTOR(lm_adc1_3, LM_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */
UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
VECTOR(tiva_usb, TIVA_IRQ_USB) /* Vector 60: USB */
UNUSED(TIVA_RESERVED_61) /* Vector 61: Reserved */
VECTOR(tiva_udmasoft, TIVA_IRQ_UDMASOFT) /* Vector 62: uDMA Software */
VECTOR(tiva_udmaerro, TIVA_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
VECTOR(tiva_adc1_0, TIVA_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */
VECTOR(tiva_adc1_1, TIVA_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */
VECTOR(tiva_adc1_2, TIVA_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */
VECTOR(tiva_adc1_3, TIVA_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */
UNUSED(TIVA_RESERVED_68) /* Vector 68: Reserved */
UNUSED(TIVA_RESERVED_69) /* Vector 69: Reserved */
UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
UNUSED(LM_RESERVED_71) /* Vector 71: Reserved */
UNUSED(LM_RESERVED_72) /* Vector 72: Reserved */
VECTOR(lm_ssi2, LM_IRQ_SSI2) /* Vector 73: SSI 2 */
VECTOR(lm_ssi3, LM_IRQ_SSI3) /* Vector 74: SSI 3 */
VECTOR(lm_uart3, LM_IRQ_UART3) /* Vector 75: UART 3 */
VECTOR(lm_uart4, LM_IRQ_UART4) /* Vector 76: UART 4 */
VECTOR(lm_uart5, LM_IRQ_UART5) /* Vector 77: UART 5 */
VECTOR(lm_uart6, LM_IRQ_UART6) /* Vector 78: UART 6 */
VECTOR(lm_uart7, LM_IRQ_UART7) /* Vector 79: UART 7 */
UNUSED(TIVA_RESERVED_70) /* Vector 70: Reserved */
UNUSED(TIVA_RESERVED_71) /* Vector 71: Reserved */
UNUSED(TIVA_RESERVED_72) /* Vector 72: Reserved */
VECTOR(tiva_ssi2, TIVA_IRQ_SSI2) /* Vector 73: SSI 2 */
VECTOR(tiva_ssi3, TIVA_IRQ_SSI3) /* Vector 74: SSI 3 */
VECTOR(tiva_uart3, TIVA_IRQ_UART3) /* Vector 75: UART 3 */
VECTOR(tiva_uart4, TIVA_IRQ_UART4) /* Vector 76: UART 4 */
VECTOR(tiva_uart5, TIVA_IRQ_UART5) /* Vector 77: UART 5 */
VECTOR(tiva_uart6, TIVA_IRQ_UART6) /* Vector 78: UART 6 */
VECTOR(tiva_uart7, TIVA_IRQ_UART7) /* Vector 79: UART 7 */
UNUSED(LM_RESERVED_80) /* Vector 80: Reserved */
UNUSED(LM_RESERVED_81) /* Vector 81: Reserved */
UNUSED(LM_RESERVED_82) /* Vector 82: Reserved */
UNUSED(LM_RESERVED_83) /* Vector 83: Reserved */
VECTOR(lm_i2c2, LM_IRQ_I2C2) /* Vector 84: I2C 2 */
VECTOR(lm_i2c3, LM_IRQ_I2C3) /* Vector 85: I2C 3 */
VECTOR(lm_timer4a, LM_IRQ_TIMER4A) /* Vector 86: 16/32-Bit Timer 4 A */
VECTOR(lm_timer4b, LM_IRQ_TIMER4B) /* Vector 87: 16/32-Bit Timer 4 B */
UNUSED(LM_RESERVED_88) /* Vector 88: Reserved */
UNUSED(LM_RESERVED_89) /* Vector 89: Reserved */
UNUSED(TIVA_RESERVED_80) /* Vector 80: Reserved */
UNUSED(TIVA_RESERVED_81) /* Vector 81: Reserved */
UNUSED(TIVA_RESERVED_82) /* Vector 82: Reserved */
UNUSED(TIVA_RESERVED_83) /* Vector 83: Reserved */
VECTOR(tiva_i2c2, TIVA_IRQ_I2C2) /* Vector 84: I2C 2 */
VECTOR(tiva_i2c3, TIVA_IRQ_I2C3) /* Vector 85: I2C 3 */
VECTOR(tiva_timer4a, TIVA_IRQ_TIMER4A) /* Vector 86: 16/32-Bit Timer 4 A */
VECTOR(tiva_timer4b, TIVA_IRQ_TIMER4B) /* Vector 87: 16/32-Bit Timer 4 B */
UNUSED(TIVA_RESERVED_88) /* Vector 88: Reserved */
UNUSED(TIVA_RESERVED_89) /* Vector 89: Reserved */
UNUSED(LM_RESERVED_90) /* Vector 90: Reserved */
UNUSED(LM_RESERVED_91) /* Vector 91: Reserved */
UNUSED(LM_RESERVED_92) /* Vector 92: Reserved */
UNUSED(LM_RESERVED_93) /* Vector 93: Reserved */
UNUSED(LM_RESERVED_94) /* Vector 94: Reserved */
UNUSED(LM_RESERVED_95) /* Vector 95: Reserved */
UNUSED(LM_RESERVED_96) /* Vector 96: Reserved */
UNUSED(LM_RESERVED_97) /* Vector 97: Reserved */
UNUSED(LM_RESERVED_98) /* Vector 98: Reserved */
UNUSED(LM_RESERVED_99) /* Vector 99: Reserved */
UNUSED(TIVA_RESERVED_90) /* Vector 90: Reserved */
UNUSED(TIVA_RESERVED_91) /* Vector 91: Reserved */
UNUSED(TIVA_RESERVED_92) /* Vector 92: Reserved */
UNUSED(TIVA_RESERVED_93) /* Vector 93: Reserved */
UNUSED(TIVA_RESERVED_94) /* Vector 94: Reserved */
UNUSED(TIVA_RESERVED_95) /* Vector 95: Reserved */
UNUSED(TIVA_RESERVED_96) /* Vector 96: Reserved */
UNUSED(TIVA_RESERVED_97) /* Vector 97: Reserved */
UNUSED(TIVA_RESERVED_98) /* Vector 98: Reserved */
UNUSED(TIVA_RESERVED_99) /* Vector 99: Reserved */
UNUSED(LM_RESERVED_100) /* Vector 100: Reserved */
UNUSED(LM_RESERVED_101) /* Vector 101: Reserved */
UNUSED(LM_RESERVED_102) /* Vector 102: Reserved */
UNUSED(LM_RESERVED_103) /* Vector 103: Reserved */
UNUSED(LM_RESERVED_104) /* Vector 104: Reserved */
UNUSED(LM_RESERVED_105) /* Vector 105: Reserved */
UNUSED(LM_RESERVED_106) /* Vector 106: Reserved */
UNUSED(LM_RESERVED_107) /* Vector 107: Reserved */
VECTOR(lm_timer5a, LM_IRQ_TIMER5A) /* Vector 108: 16/32-Bit Timer 5 A */
VECTOR(lm_timer5b, LM_IRQ_TIMER5B) /* Vector 109: 16/32-Bit Timer 5 B */
UNUSED(TIVA_RESERVED_100) /* Vector 100: Reserved */
UNUSED(TIVA_RESERVED_101) /* Vector 101: Reserved */
UNUSED(TIVA_RESERVED_102) /* Vector 102: Reserved */
UNUSED(TIVA_RESERVED_103) /* Vector 103: Reserved */
UNUSED(TIVA_RESERVED_104) /* Vector 104: Reserved */
UNUSED(TIVA_RESERVED_105) /* Vector 105: Reserved */
UNUSED(TIVA_RESERVED_106) /* Vector 106: Reserved */
UNUSED(TIVA_RESERVED_107) /* Vector 107: Reserved */
VECTOR(tiva_timer5a, TIVA_IRQ_TIMER5A) /* Vector 108: 16/32-Bit Timer 5 A */
VECTOR(tiva_timer5b, TIVA_IRQ_TIMER5B) /* Vector 109: 16/32-Bit Timer 5 B */
VECTOR(lm_wtimer0a, LM_IRQ_WTIMER0A) /* Vector 110: 32/64-Bit Timer 0 A */
VECTOR(lm_wtimer0b, LM_IRQ_WTIMER0B) /* Vector 111: 32/64-Bit Timer 0 B */
VECTOR(lm_wtimer1a, LM_IRQ_WTIMER1A) /* Vector 112: 32/64-Bit Timer 1 A */
VECTOR(lm_wtimer1b, LM_IRQ_WTIMER1B) /* Vector 113: 32/64-Bit Timer 1 B */
VECTOR(lm_wtimer2a, LM_IRQ_WTIMER2A) /* Vector 114: 32/64-Bit Timer 2 A */
VECTOR(lm_wtimer2b, LM_IRQ_WTIMER2B) /* Vector 115: 32/64-Bit Timer 2 B */
VECTOR(lm_wtimer3a, LM_IRQ_WTIMER3A) /* Vector 116: 32/64-Bit Timer 3 A */
VECTOR(lm_wtimer3b, LM_IRQ_WTIMER3B) /* Vector 117: 32/64-Bit Timer 3 B */
VECTOR(lm_wtimer4a, LM_IRQ_WTIMER4A) /* Vector 118: 32/64-Bit Timer 4 A */
VECTOR(lm_WTIMER4B, LM_IRQ_WTIMER4B) /* Vector 119: 32/64-Bit Timer 4 B */
VECTOR(tiva_wtimer0a, TIVA_IRQ_WTIMER0A) /* Vector 110: 32/64-Bit Timer 0 A */
VECTOR(tiva_wtimer0b, TIVA_IRQ_WTIMER0B) /* Vector 111: 32/64-Bit Timer 0 B */
VECTOR(tiva_wtimer1a, TIVA_IRQ_WTIMER1A) /* Vector 112: 32/64-Bit Timer 1 A */
VECTOR(tiva_wtimer1b, TIVA_IRQ_WTIMER1B) /* Vector 113: 32/64-Bit Timer 1 B */
VECTOR(tiva_wtimer2a, TIVA_IRQ_WTIMER2A) /* Vector 114: 32/64-Bit Timer 2 A */
VECTOR(tiva_wtimer2b, TIVA_IRQ_WTIMER2B) /* Vector 115: 32/64-Bit Timer 2 B */
VECTOR(tiva_wtimer3a, TIVA_IRQ_WTIMER3A) /* Vector 116: 32/64-Bit Timer 3 A */
VECTOR(tiva_wtimer3b, TIVA_IRQ_WTIMER3B) /* Vector 117: 32/64-Bit Timer 3 B */
VECTOR(tiva_wtimer4a, TIVA_IRQ_WTIMER4A) /* Vector 118: 32/64-Bit Timer 4 A */
VECTOR(tiva_WTIMER4B, TIVA_IRQ_WTIMER4B) /* Vector 119: 32/64-Bit Timer 4 B */
VECTOR(lm_wtimer5a, LM_IRQ_WTIMER5A) /* Vector 120: 32/64-Bit Timer 5 A */
VECTOR(lm_wtimer5b, LM_IRQ_WTIMER5B) /* Vector 121: 32/64-Bit Timer 5 B */
VECTOR(lm_system, LM_IRQ_SYSTEM) /* Vector 122: System Exception (imprecise) */
UNUSED(LM_RESERVED_123) /* Vector 123: Reserved */
UNUSED(LM_RESERVED_124) /* Vector 124: Reserved */
UNUSED(LM_RESERVED_125) /* Vector 125: Reserved */
UNUSED(LM_RESERVED_126) /* Vector 126: Reserved */
UNUSED(LM_RESERVED_127) /* Vector 127: Reserved */
UNUSED(LM_RESERVED_128) /* Vector 128: Reserved */
UNUSED(LM_RESERVED_129) /* Vector 129: Reserved */
VECTOR(tiva_wtimer5a, TIVA_IRQ_WTIMER5A) /* Vector 120: 32/64-Bit Timer 5 A */
VECTOR(tiva_wtimer5b, TIVA_IRQ_WTIMER5B) /* Vector 121: 32/64-Bit Timer 5 B */
VECTOR(tiva_system, TIVA_IRQ_SYSTEM) /* Vector 122: System Exception (imprecise) */
UNUSED(TIVA_RESERVED_123) /* Vector 123: Reserved */
UNUSED(TIVA_RESERVED_124) /* Vector 124: Reserved */
UNUSED(TIVA_RESERVED_125) /* Vector 125: Reserved */
UNUSED(TIVA_RESERVED_126) /* Vector 126: Reserved */
UNUSED(TIVA_RESERVED_127) /* Vector 127: Reserved */
UNUSED(TIVA_RESERVED_128) /* Vector 128: Reserved */
UNUSED(TIVA_RESERVED_129) /* Vector 129: Reserved */
UNUSED(LM_RESERVED_130) /* Vector 130: Reserved */
UNUSED(LM_RESERVED_131) /* Vector 131: Reserved */
UNUSED(LM_RESERVED_132) /* Vector 132: Reserved */
UNUSED(LM_RESERVED_133) /* Vector 133: Reserved */
UNUSED(LM_RESERVED_134) /* Vector 134: Reserved */
UNUSED(LM_RESERVED_135) /* Vector 135: Reserved */
UNUSED(LM_RESERVED_136) /* Vector 136: Reserved */
UNUSED(LM_RESERVED_137) /* Vector 137: Reserved */
UNUSED(LM_RESERVED_138) /* Vector 138: Reserved */
UNUSED(LM_RESERVED_139) /* Vector 139: Reserved */
UNUSED(TIVA_RESERVED_130) /* Vector 130: Reserved */
UNUSED(TIVA_RESERVED_131) /* Vector 131: Reserved */
UNUSED(TIVA_RESERVED_132) /* Vector 132: Reserved */
UNUSED(TIVA_RESERVED_133) /* Vector 133: Reserved */
UNUSED(TIVA_RESERVED_134) /* Vector 134: Reserved */
UNUSED(TIVA_RESERVED_135) /* Vector 135: Reserved */
UNUSED(TIVA_RESERVED_136) /* Vector 136: Reserved */
UNUSED(TIVA_RESERVED_137) /* Vector 137: Reserved */
UNUSED(TIVA_RESERVED_138) /* Vector 138: Reserved */
UNUSED(TIVA_RESERVED_139) /* Vector 139: Reserved */
UNUSED(LM_RESERVED_140) /* Vector 140: Reserved */
UNUSED(LM_RESERVED_141) /* Vector 141: Reserved */
UNUSED(LM_RESERVED_142) /* Vector 142: Reserved */
UNUSED(LM_RESERVED_143) /* Vector 143: Reserved */
UNUSED(LM_RESERVED_144) /* Vector 144: Reserved */
UNUSED(LM_RESERVED_145) /* Vector 145: Reserved */
UNUSED(LM_RESERVED_146) /* Vector 146: Reserved */
UNUSED(LM_RESERVED_147) /* Vector 147: Reserved */
UNUSED(LM_RESERVED_148) /* Vector 148: Reserved */
UNUSED(LM_RESERVED_149) /* Vector 149: Reserved */
UNUSED(TIVA_RESERVED_140) /* Vector 140: Reserved */
UNUSED(TIVA_RESERVED_141) /* Vector 141: Reserved */
UNUSED(TIVA_RESERVED_142) /* Vector 142: Reserved */
UNUSED(TIVA_RESERVED_143) /* Vector 143: Reserved */
UNUSED(TIVA_RESERVED_144) /* Vector 144: Reserved */
UNUSED(TIVA_RESERVED_145) /* Vector 145: Reserved */
UNUSED(TIVA_RESERVED_146) /* Vector 146: Reserved */
UNUSED(TIVA_RESERVED_147) /* Vector 147: Reserved */
UNUSED(TIVA_RESERVED_148) /* Vector 148: Reserved */
UNUSED(TIVA_RESERVED_149) /* Vector 149: Reserved */
UNUSED(LM_RESERVED_150) /* Vector 150: Reserved */
UNUSED(LM_RESERVED_151) /* Vector 151: Reserved */
UNUSED(LM_RESERVED_152) /* Vector 152: Reserved */
UNUSED(LM_RESERVED_153) /* Vector 153: Reserved */
UNUSED(LM_RESERVED_154) /* Vector 154: Reserved */
UNUSED(TIVA_RESERVED_150) /* Vector 150: Reserved */
UNUSED(TIVA_RESERVED_151) /* Vector 151: Reserved */
UNUSED(TIVA_RESERVED_152) /* Vector 152: Reserved */
UNUSED(TIVA_RESERVED_153) /* Vector 153: Reserved */
UNUSED(TIVA_RESERVED_154) /* Vector 154: Reserved */
# endif /* CONFIG_ARMV7M_CMNVECTOR */

94
arch/arm/src/tiva/chip/tiva_ethernet.h
View file

@ -53,63 +53,63 @@
/* Ethernet MAC Register Offsets */
#define LM_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
#define LM_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
#define LM_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
#define LM_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
#define LM_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
#define LM_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
#define LM_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
#define LM_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
#define LM_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
#define LM_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
#define LM_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
#define LM_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
#define LM_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
#define LM_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
#define LM_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
#ifdef LM_ETHTS
# define LM_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
#define TIVA_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
#define TIVA_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
#define TIVA_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
#define TIVA_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
#define TIVA_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
#define TIVA_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
#define TIVA_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
#define TIVA_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
#define TIVA_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
#define TIVA_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
#define TIVA_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
#define TIVA_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
#define TIVA_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
#define TIVA_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
#define TIVA_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
#ifdef TIVA_ETHTS
# define TIVA_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
#endif
/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
/* Ethernet Controller Register Addresses *******************************************/
#define LM_MAC_RIS (LM_ETHCON_BASE + LM_MAC_RIS_OFFSET)
#define LM_MAC_IACK (LM_ETHCON_BASE + LM_MAC_IACK_OFFSET)
#define LM_MAC_IM (LM_ETHCON_BASE + LM_MAC_IM_OFFSET)
#define LM_MAC_RCTL (LM_ETHCON_BASE + LM_MAC_RCTL_OFFSET)
#define LM_MAC_TCTL (LM_ETHCON_BASE + LM_MAC_TCTL_OFFSET)
#define LM_MAC_DATA (LM_ETHCON_BASE + LM_MAC_DATA_OFFSET)
#define LM_MAC_IA0 (LM_ETHCON_BASE + LM_MAC_IA0_OFFSET)
#define LM_MAC_IA1 (LM_ETHCON_BASE + LM_MAC_IA1_OFFSET)
#define LM_MAC_THR (LM_ETHCON_BASE + LM_MAC_THR_OFFSET)
#define LM_MAC_MCTL (LM_ETHCON_BASE + LM_MAC_MCTL_OFFSET)
#define LM_MAC_MDV (LM_ETHCON_BASE + LM_MAC_MDV_OFFSET)
#define LM_MAC_MTXD (LM_ETHCON_BASE + LM_MAC_MTXD_OFFSET)
#define LM_MAC_MRXD (LM_ETHCON_BASE + LM_MAC_MRXD_OFFSET)
#define LM_MAC_NP (LM_ETHCON_BASE + LM_MAC_NP_OFFSET)
#define LM_MAC_TR (LM_ETHCON_BASE + LM_MAC_TR_OFFSET)
#ifdef LM_ETHTS
# define LM_MAC_TS (LM_ETHCON_BASE + LM_MAC_TS_OFFSET)
#define TIVA_MAC_RIS (TIVA_ETHCON_BASE + TIVA_MAC_RIS_OFFSET)
#define TIVA_MAC_IACK (TIVA_ETHCON_BASE + TIVA_MAC_IACK_OFFSET)
#define TIVA_MAC_IM (TIVA_ETHCON_BASE + TIVA_MAC_IM_OFFSET)
#define TIVA_MAC_RCTL (TIVA_ETHCON_BASE + TIVA_MAC_RCTL_OFFSET)
#define TIVA_MAC_TCTL (TIVA_ETHCON_BASE + TIVA_MAC_TCTL_OFFSET)
#define TIVA_MAC_DATA (TIVA_ETHCON_BASE + TIVA_MAC_DATA_OFFSET)
#define TIVA_MAC_IA0 (TIVA_ETHCON_BASE + TIVA_MAC_IA0_OFFSET)
#define TIVA_MAC_IA1 (TIVA_ETHCON_BASE + TIVA_MAC_IA1_OFFSET)
#define TIVA_MAC_THR (TIVA_ETHCON_BASE + TIVA_MAC_THR_OFFSET)
#define TIVA_MAC_MCTL (TIVA_ETHCON_BASE + TIVA_MAC_MCTL_OFFSET)
#define TIVA_MAC_MDV (TIVA_ETHCON_BASE + TIVA_MAC_MDV_OFFSET)
#define TIVA_MAC_MTXD (TIVA_ETHCON_BASE + TIVA_MAC_MTXD_OFFSET)
#define TIVA_MAC_MRXD (TIVA_ETHCON_BASE + TIVA_MAC_MRXD_OFFSET)
#define TIVA_MAC_NP (TIVA_ETHCON_BASE + TIVA_MAC_NP_OFFSET)
#define TIVA_MAC_TR (TIVA_ETHCON_BASE + TIVA_MAC_TR_OFFSET)
#ifdef TIVA_ETHTS
# define TIVA_MAC_TS (TIVA_ETHCON_BASE + TIVA_MAC_TS_OFFSET)
#endif
/* Memory Mapped MII Management Registers */
#define MAC_MII_MCR (LM_ETHCON_BASE + MII_MCR)
#define MAC_MII_MSR (LM_ETHCON_BASE + MII_MSR)
#define MAC_MII_PHYID1 (LM_ETHCON_BASE + MII_PHYID1)
#define MAC_MII_PHYID2 (LM_ETHCON_BASE + MII_PHYID2)
#define MAC_MII_ADVERTISE (LM_ETHCON_BASE + MII_ADVERTISE)
#define MAC_MII_LPA (LM_ETHCON_BASE + MII_LPA)
#define MAC_MII_EXPANSION (LM_ETHCON_BASE + MII_EXPANSION)
#define MAC_MII_VSPECIFIC (LM_ETHCON_BASE + MII_LM_VSPECIFIC)
#define MAC_MII_INTCS (LM_ETHCON_BASE + MII_LM_INTCS)
#define MAC_MII_DIAGNOSTIC (LM_ETHCON_BASE + MII_LM_DIAGNOSTIC)
#define MAC_MII_XCVRCONTROL (LM_ETHCON_BASE + MII_LM_XCVRCONTROL)
#define MAC_MII_LEDCONFIG (LM_ETHCON_BASE + MII_LM_LEDCONFIG)
#define MAC_MII_MDICONTROL (LM_ETHCON_BASE + MII_LM_MDICONTROL)
#define MAC_MII_MCR (TIVA_ETHCON_BASE + MII_MCR)
#define MAC_MII_MSR (TIVA_ETHCON_BASE + MII_MSR)
#define MAC_MII_PHYID1 (TIVA_ETHCON_BASE + MII_PHYID1)
#define MAC_MII_PHYID2 (TIVA_ETHCON_BASE + MII_PHYID2)
#define MAC_MII_ADVERTISE (TIVA_ETHCON_BASE + MII_ADVERTISE)
#define MAC_MII_LPA (TIVA_ETHCON_BASE + MII_LPA)
#define MAC_MII_EXPANSION (TIVA_ETHCON_BASE + MII_EXPANSION)
#define MAC_MII_VSPECIFIC (TIVA_ETHCON_BASE + MII_TIVA_VSPECIFIC)
#define MAC_MII_INTCS (TIVA_ETHCON_BASE + MII_TIVA_INTCS)
#define MAC_MII_DIAGNOSTIC (TIVA_ETHCON_BASE + MII_TIVA_DIAGNOSTIC)
#define MAC_MII_XCVRCONTROL (TIVA_ETHCON_BASE + MII_TIVA_XCVRCONTROL)
#define MAC_MII_LEDCONFIG (TIVA_ETHCON_BASE + MII_TIVA_LEDCONFIG)
#define MAC_MII_MDICONTROL (TIVA_ETHCON_BASE + MII_TIVA_MDICONTROL)
/* Ethernet Controller Register Bit Definitions *************************************/

103
arch/arm/src/tiva/chip/tiva_flash.h
View file

@ -48,81 +48,81 @@
/* FLASH dimensions ****************************************************************/
#if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120)
# define LM_FLASH_NPAGES 256
# define LM_FLASH_PAGESIZE 1024
#if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120) || \
defined(CONFIG_ARCH_CHIP_LM3S8962) || defined(CONFIG_ARCH_CHIP_LM3S9B96)
# define TIVA_FLASH_NPAGES 256
# define TIVA_FLASH_PAGESIZE 1024
#else
# error "No flash dimensions defined for selected chip."
# warning "No flash dimensions defined for selected chip."
#endif
#define LM_FLASH_SIZE (LM_FLASH_NPAGES * LM_FLASH_PAGESIZE)
#define TIVA_FLASH_SIZE (TIVA_FLASH_NPAGES * TIVA_FLASH_PAGESIZE)
/* FLASH register offsets ***********************************************************/
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
* control base address of LM_FLASHCON_BASE.
* control base address of TIVA_FLASHCON_BASE.
*/
#define LM_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
#define LM_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
#define LM_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
#define LM_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
#define LM_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
#define LM_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */
#define TIVA_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
#define TIVA_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
#define TIVA_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
#define TIVA_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
#define TIVA_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
#define TIVA_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
* System Control base address of LM_SYSCON_BASE
* System Control base address of TIVA_SYSCON_BASE
*/
#define LM_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
#define LM_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
#define LM_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
#define LM_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
#define LM_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
#define LM_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
#define LM_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
#define LM_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
#define LM_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
#define LM_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
#define LM_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
#define LM_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
#define LM_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
#define LM_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
#define TIVA_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
#define TIVA_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
#define TIVA_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
#define TIVA_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
#define TIVA_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
#define TIVA_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
#define TIVA_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
#define TIVA_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
#define TIVA_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
#define TIVA_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
#define TIVA_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
#define TIVA_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
#define TIVA_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
#define TIVA_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
/* FLASH register addresses *********************************************************/
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
* control base address of LM_FLASHCON_BASE.
* control base address of TIVA_FLASHCON_BASE.
*/
#define LM_FLASH_FMA (LM_FLASHCON_BASE + LM_FLASH_FMA_OFFSET)
#define LM_FLASH_FMD (LM_FLASHCON_BASE + LM_FLASH_FMD_OFFSET)
#define LM_FLASH_FMC (LM_FLASHCON_BASE + LM_FLASH_FMC_OFFSET)
#define LM_FLASH_FCRIS (LM_FLASHCON_BASE + LM_FLASH_FCRIS_OFFSET)
#define LM_FLASH_FCIM (LM_FLASHCON_BASE + LM_FLASH_FCIM_OFFSET)
#define LM_FLASH_FCMISC (LM_FLASHCON_BASE + LM_FLASH_FCMISC_OFFSET)
#define TIVA_FLASH_FMA (TIVA_FLASHCON_BASE + TIVA_FLASH_FMA_OFFSET)
#define TIVA_FLASH_FMD (TIVA_FLASHCON_BASE + TIVA_FLASH_FMD_OFFSET)
#define TIVA_FLASH_FMC (TIVA_FLASHCON_BASE + TIVA_FLASH_FMC_OFFSET)
#define TIVA_FLASH_FCRIS (TIVA_FLASHCON_BASE + TIVA_FLASH_FCRIS_OFFSET)
#define TIVA_FLASH_FCIM (TIVA_FLASHCON_BASE + TIVA_FLASH_FCIM_OFFSET)
#define TIVA_FLASH_FCMISC (TIVA_FLASHCON_BASE + TIVA_FLASH_FCMISC_OFFSET)
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
* System Control base address of LM_SYSCON_BASE
* System Control base address of TIVA_SYSCON_BASE
*/
#define LM_FLASH_FMPRE (LM_SYSCON_BASE + LM_FLASH_FMPRE_OFFSET)
#define LM_FLASH_FMPPE (LM_SYSCON_BASE + LM_FLASH_FMPPE_OFFSET)
#define LM_FLASH_USECRL (LM_SYSCON_BASE + LM_FLASH_USECRL_OFFSET)
#define LM_FLASH_USERDBG (LM_SYSCON_BASE + LM_FLASH_USERDBG_OFFSET)
#define LM_FLASH_USERREG0 (LM_SYSCON_BASE + LM_FLASH_USERREG0_OFFSET)
#define LM_FLASH_USERREG1 (LM_SYSCON_BASE + LM_FLASH_USERREG1_OFFSET)
#define LM_FLASH_FMPRE0 (LM_SYSCON_BASE + LM_FLASH_FMPRE0_OFFSET)
#define LM_FLASH_FMPRE1 (LM_SYSCON_BASE + LM_FLASH_FMPRE1_OFFSET)
#define LM_FLASH_FMPRE2 (LM_SYSCON_BASE + LM_FLASH_FMPRE2_OFFSET)
#define LM_FLASH_FMPRE3 (LM_SYSCON_BASE + LM_FLASH_FMPRE3_OFFSET)
#define LM_FLASH_FMPPE0 (LM_SYSCON_BASE + LM_FLASH_FMPPE0_OFFSET)
#define LM_FLASH_FMPPE1 (LM_SYSCON_BASE + LM_FLASH_FMPPE1_OFFSET)
#define LM_FLASH_FMPPE2 (LM_SYSCON_BASE + LM_FLASH_FMPPE2_OFFSET)
#define LM_FLASH_FMPPE3 (LM_SYSCON_BASE + LM_FLASH_FMPPE3_OFFSET)
#define TIVA_FLASH_FMPRE (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE_OFFSET)
#define TIVA_FLASH_FMPPE (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE_OFFSET)
#define TIVA_FLASH_USECRL (TIVA_SYSCON_BASE + TIVA_FLASH_USECRL_OFFSET)
#define TIVA_FLASH_USERDBG (TIVA_SYSCON_BASE + TIVA_FLASH_USERDBG_OFFSET)
#define TIVA_FLASH_USERREG0 (TIVA_SYSCON_BASE + TIVA_FLASH_USERREG0_OFFSET)
#define TIVA_FLASH_USERREG1 (TIVA_SYSCON_BASE + TIVA_FLASH_USERREG1_OFFSET)
#define TIVA_FLASH_FMPRE0 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE0_OFFSET)
#define TIVA_FLASH_FMPRE1 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE1_OFFSET)
#define TIVA_FLASH_FMPRE2 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE2_OFFSET)
#define TIVA_FLASH_FMPRE3 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE3_OFFSET)
#define TIVA_FLASH_FMPPE0 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE0_OFFSET)
#define TIVA_FLASH_FMPPE1 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE1_OFFSET)
#define TIVA_FLASH_FMPPE2 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE2_OFFSET)
#define TIVA_FLASH_FMPPE3 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE3_OFFSET)
/* FLASH register bit defitiions ****************************************************/
/* FLASH register bit definitions ***************************************************/
#define FLASH_FMA_OFFSET_SHIFT 0 /* Bits 17-0: Address Offset */
#define FLASH_FMA_OFFSET_MASK (0x0003ffff << FLASH_FMA_OFFSET_SHIFT)
@ -141,7 +141,6 @@
#define FLASH_FMC_WRKEY_MASK (0xffff << FLASH_FMC_WRKEY_SHIFT)
#define FLASH_FMC_WRKEY (0xa442 << FLASH_FMC_WRKEY_SHIFT) /* Magic write key */
/************************************************************************************
* Public Types
************************************************************************************/

740
arch/arm/src/tiva/chip/tiva_gpio.h
View file

@ -49,437 +49,437 @@
/* GPIO Register Offsets ************************************************************/
#define LM_GPIO_DATA_OFFSET 0x000 /* GPIO Data */
#define LM_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */
#define LM_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */
#define LM_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */
#define LM_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */
#define LM_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */
#define LM_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */
#define LM_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */
#define LM_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */
#define LM_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */
#define LM_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */
#define LM_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */
#define LM_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */
#define LM_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */
#define LM_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */
#define LM_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */
#define LM_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */
#define LM_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */
#define LM_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */
#define LM_GPIO_CR_OFFSET 0x524 /* GPIO Commit */
#define TIVA_GPIO_DATA_OFFSET 0x000 /* GPIO Data */
#define TIVA_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */
#define TIVA_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */
#define TIVA_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */
#define TIVA_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */
#define TIVA_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */
#define TIVA_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */
#define TIVA_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */
#define TIVA_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */
#define TIVA_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */
#define TIVA_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */
#define TIVA_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */
#define TIVA_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */
#define TIVA_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */
#define TIVA_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */
#define TIVA_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */
#define TIVA_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */
#define TIVA_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */
#define TIVA_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */
#define TIVA_GPIO_CR_OFFSET 0x524 /* GPIO Commit */
#ifdef LM4F
# define LM_GPIO_AMSEL_OFFSET 0x528 /* GPIO Analog Mode Select */
# define LM_GPIO_PCTL_OFFSET 0x52c /* GPIO Port Control */
# define LM_GPIO_ADCCTL_OFFSET 0x530 /* GPIO ADC Control */
# define LM_GPIO_DMACTL_OFFSET 0x534 /* GPIO DMA Control */
# define TIVA_GPIO_AMSEL_OFFSET 0x528 /* GPIO Analog Mode Select */
# define TIVA_GPIO_PCTL_OFFSET 0x52c /* GPIO Port Control */
# define TIVA_GPIO_ADCCTL_OFFSET 0x530 /* GPIO ADC Control */
# define TIVA_GPIO_DMACTL_OFFSET 0x534 /* GPIO DMA Control */
#endif
#define LM_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */
#define LM_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */
#define LM_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */
#define LM_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */
#define LM_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */
#define LM_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */
#define LM_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */
#define LM_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */
#define LM_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */
#define LM_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */
#define LM_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */
#define LM_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/
#define TIVA_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */
#define TIVA_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */
#define TIVA_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */
#define TIVA_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */
#define TIVA_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */
#define TIVA_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */
#define TIVA_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */
#define TIVA_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */
#define TIVA_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */
#define TIVA_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */
#define TIVA_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */
#define TIVA_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/
/* GPIO Register Addresses **********************************************************/
#if LM_NPORTS > 0
#if TIVA_NPORTS > 0
# define LM_GPIOA_DATA (LM_GPIOA_BASE + LM_GPIO_DATA_OFFSET)
# define LM_GPIOA_DIR (LM_GPIOA_BASE + LM_GPIO_DIR_OFFSET)
# define LM_GPIOA_IS (LM_GPIOA_BASE + LM_GPIO_IS_OFFSET)
# define LM_GPIOA_IBE (LM_GPIOA_BASE + LM_GPIO_IBE_OFFSET)
# define LM_GPIOA_IEV (LM_GPIOA_BASE + LM_GPIO_IEV_OFFSET)
# define LM_GPIOA_IM (LM_GPIOA_BASE + LM_GPIO_IM_OFFSET)
# define LM_GPIOA_RIS (LM_GPIOA_BASE + LM_GPIO_RIS_OFFSET)
# define LM_GPIOA_MIS (LM_GPIOA_BASE + LM_GPIO_MIS_OFFSET)
# define LM_GPIOA_ICR (LM_GPIOA_BASE + LM_GPIO_ICR_OFFSET)
# define LM_GPIOA_AFSEL (LM_GPIOA_BASE + LM_GPIO_AFSEL_OFFSET)
# define LM_GPIOA_DR2R (LM_GPIOA_BASE + LM_GPIO_DR2R_OFFSET)
# define LM_GPIOA_DR4R (LM_GPIOA_BASE + LM_GPIO_DR4R_OFFSET)
# define LM_GPIOA_DR8R (LM_GPIOA_BASE + LM_GPIO_DR8R_OFFSET)
# define LM_GPIOA_ODR (LM_GPIOA_BASE + LM_GPIO_ODR_OFFSET)
# define LM_GPIOA_PUR (LM_GPIOA_BASE + LM_GPIO_PUR_OFFSET)
# define LM_GPIOA_PDR (LM_GPIOA_BASE + LM_GPIO_PDR_OFFSET)
# define LM_GPIOA_SLR (LM_GPIOA_BASE + LM_GPIO_SLR_OFFSET)
# define LM_GPIOA_DEN (LM_GPIOA_BASE + LM_GPIO_DEN_OFFSET)
# define LM_GPIOA_LOCK (LM_GPIOA_BASE + LM_GPIO_LOCK_OFFSET)
# define LM_GPIOA_CR (LM_GPIOA_BASE + LM_GPIO_CR_OFFSET)
# define TIVA_GPIOA_DATA (TIVA_GPIOA_BASE + TIVA_GPIO_DATA_OFFSET)
# define TIVA_GPIOA_DIR (TIVA_GPIOA_BASE + TIVA_GPIO_DIR_OFFSET)
# define TIVA_GPIOA_IS (TIVA_GPIOA_BASE + TIVA_GPIO_IS_OFFSET)
# define TIVA_GPIOA_IBE (TIVA_GPIOA_BASE + TIVA_GPIO_IBE_OFFSET)
# define TIVA_GPIOA_IEV (TIVA_GPIOA_BASE + TIVA_GPIO_IEV_OFFSET)
# define TIVA_GPIOA_IM (TIVA_GPIOA_BASE + TIVA_GPIO_IM_OFFSET)
# define TIVA_GPIOA_RIS (TIVA_GPIOA_BASE + TIVA_GPIO_RIS_OFFSET)
# define TIVA_GPIOA_MIS (TIVA_GPIOA_BASE + TIVA_GPIO_MIS_OFFSET)
# define TIVA_GPIOA_ICR (TIVA_GPIOA_BASE + TIVA_GPIO_ICR_OFFSET)
# define TIVA_GPIOA_AFSEL (TIVA_GPIOA_BASE + TIVA_GPIO_AFSEL_OFFSET)
# define TIVA_GPIOA_DR2R (TIVA_GPIOA_BASE + TIVA_GPIO_DR2R_OFFSET)
# define TIVA_GPIOA_DR4R (TIVA_GPIOA_BASE + TIVA_GPIO_DR4R_OFFSET)
# define TIVA_GPIOA_DR8R (TIVA_GPIOA_BASE + TIVA_GPIO_DR8R_OFFSET)
# define TIVA_GPIOA_ODR (TIVA_GPIOA_BASE + TIVA_GPIO_ODR_OFFSET)
# define TIVA_GPIOA_PUR (TIVA_GPIOA_BASE + TIVA_GPIO_PUR_OFFSET)
# define TIVA_GPIOA_PDR (TIVA_GPIOA_BASE + TIVA_GPIO_PDR_OFFSET)
# define TIVA_GPIOA_SLR (TIVA_GPIOA_BASE + TIVA_GPIO_SLR_OFFSET)
# define TIVA_GPIOA_DEN (TIVA_GPIOA_BASE + TIVA_GPIO_DEN_OFFSET)
# define TIVA_GPIOA_LOCK (TIVA_GPIOA_BASE + TIVA_GPIO_LOCK_OFFSET)
# define TIVA_GPIOA_CR (TIVA_GPIOA_BASE + TIVA_GPIO_CR_OFFSET)
# ifdef LM4F
# define LM_GPIOA_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
# define LM_GPIOA_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
# define LM_GPIOA_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
# define LM_GPIOA_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
# define TIVA_GPIOA_AMSEL (TIVA_GPIOA_BASE + TIVA_GPIO_AMSEL_OFFSET)
# define TIVA_GPIOA_PCTL (TIVA_GPIOA_BASE + TIVA_GPIO_PCTL_OFFSET)
# define TIVA_GPIOA_ADCCTL (TIVA_GPIOA_BASE + TIVA_GPIO_ADCCTL_OFFSET)
# define TIVA_GPIOA_DMACTL (TIVA_GPIOA_BASE + TIVA_GPIO_DMACTL_OFFSET)
# endif
# define LM_GPIOA_PERIPHID4 (LM_GPIOA_BASE + LM_GPIO_PERIPHID4_OFFSET)
# define LM_GPIOA_PERIPHID5 (LM_GPIOA_BASE + LM_GPIO_PERIPHID5_OFFSET)
# define LM_GPIOA_PERIPHID6 (LM_GPIOA_BASE + LM_GPIO_PERIPHID6_OFFSET)
# define LM_GPIOA_PERIPHID7 (LM_GPIOA_BASE + LM_GPIO_PERIPHID7_OFFSET)
# define LM_GPIOA_PERIPHID0 (LM_GPIOA_BASE + LM_GPIO_PERIPHID0_OFFSET)
# define LM_GPIOA_PERIPHID1 (LM_GPIOA_BASE + LM_GPIO_PERIPHID1_OFFSET)
# define LM_GPIOA_PERIPHID2 (LM_GPIOA_BASE + LM_GPIO_PERIPHID2_OFFSET)
# define LM_GPIOA_PERIPHID3 (LM_GPIOA_BASE + LM_GPIO_PERIPHID3_OFFSET)
# define LM_GPIOA_PCELLID0 (LM_GPIOA_BASE + LM_GPIO_PCELLID0_OFFSET)
# define LM_GPIOA_PCELLID1 (LM_GPIOA_BASE + LM_GPIO_PCELLID1_OFFSET)
# define LM_GPIOA_PCELLID2 (LM_GPIOA_BASE + LM_GPIO_PCELLID2_OFFSET)
# define LM_GPIOA_PCELLID3 (LM_GPIOA_BASE + LM_GPIO_PCELLID3_OFFSET)
# define TIVA_GPIOA_PERIPHID4 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID4_OFFSET)
# define TIVA_GPIOA_PERIPHID5 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID5_OFFSET)
# define TIVA_GPIOA_PERIPHID6 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID6_OFFSET)
# define TIVA_GPIOA_PERIPHID7 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID7_OFFSET)
# define TIVA_GPIOA_PERIPHID0 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID0_OFFSET)
# define TIVA_GPIOA_PERIPHID1 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID1_OFFSET)
# define TIVA_GPIOA_PERIPHID2 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID2_OFFSET)
# define TIVA_GPIOA_PERIPHID3 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID3_OFFSET)
# define TIVA_GPIOA_PCELLID0 (TIVA_GPIOA_BASE + TIVA_GPIO_PCELLID0_OFFSET)
# define TIVA_GPIOA_PCELLID1 (TIVA_GPIOA_BASE + TIVA_GPIO_PCELLID1_OFFSET)
# define TIVA_GPIOA_PCELLID2 (TIVA_GPIOA_BASE + TIVA_GPIO_PCELLID2_OFFSET)
# define TIVA_GPIOA_PCELLID3 (TIVA_GPIOA_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#elif LM_NPORTS > 1
#elif TIVA_NPORTS > 1
# define LM_GPIOB_DATA (LM_GPIOB_BASE + LM_GPIO_DATA_OFFSET)
# define LM_GPIOB_DIR (LM_GPIOB_BASE + LM_GPIO_DIR_OFFSET)
# define LM_GPIOB_IS (LM_GPIOB_BASE + LM_GPIO_IS_OFFSET)
# define LM_GPIOB_IBE (LM_GPIOB_BASE + LM_GPIO_IBE_OFFSET)
# define LM_GPIOB_IEV (LM_GPIOB_BASE + LM_GPIO_IEV_OFFSET)
# define LM_GPIOB_IM (LM_GPIOB_BASE + LM_GPIO_IM_OFFSET)
# define LM_GPIOB_RIS (LM_GPIOB_BASE + LM_GPIO_RIS_OFFSET)
# define LM_GPIOB_MIS (LM_GPIOB_BASE + LM_GPIO_MIS_OFFSET)
# define LM_GPIOB_ICR (LM_GPIOB_BASE + LM_GPIO_ICR_OFFSET)
# define LM_GPIOB_AFSEL (LM_GPIOB_BASE + LM_GPIO_AFSEL_OFFSET)
# define LM_GPIOB_DR2R (LM_GPIOB_BASE + LM_GPIO_DR2R_OFFSET)
# define LM_GPIOB_DR4R (LM_GPIOB_BASE + LM_GPIO_DR4R_OFFSET)
# define LM_GPIOB_DR8R (LM_GPIOB_BASE + LM_GPIO_DR8R_OFFSET)
# define LM_GPIOB_ODR (LM_GPIOB_BASE + LM_GPIO_ODR_OFFSET)
# define LM_GPIOB_PUR (LM_GPIOB_BASE + LM_GPIO_PUR_OFFSET)
# define LM_GPIOB_PDR (LM_GPIOB_BASE + LM_GPIO_PDR_OFFSET)
# define LM_GPIOB_SLR (LM_GPIOB_BASE + LM_GPIO_SLR_OFFSET)
# define LM_GPIOB_DEN (LM_GPIOB_BASE + LM_GPIO_DEN_OFFSET)
# define LM_GPIOB_LOCK (LM_GPIOB_BASE + LM_GPIO_LOCK_OFFSET)
# define LM_GPIOB_CR (LM_GPIOB_BASE + LM_GPIO_CR_OFFSET)
# define TIVA_GPIOB_DATA (TIVA_GPIOB_BASE + TIVA_GPIO_DATA_OFFSET)
# define TIVA_GPIOB_DIR (TIVA_GPIOB_BASE + TIVA_GPIO_DIR_OFFSET)
# define TIVA_GPIOB_IS (TIVA_GPIOB_BASE + TIVA_GPIO_IS_OFFSET)
# define TIVA_GPIOB_IBE (TIVA_GPIOB_BASE + TIVA_GPIO_IBE_OFFSET)
# define TIVA_GPIOB_IEV (TIVA_GPIOB_BASE + TIVA_GPIO_IEV_OFFSET)
# define TIVA_GPIOB_IM (TIVA_GPIOB_BASE + TIVA_GPIO_IM_OFFSET)
# define TIVA_GPIOB_RIS (TIVA_GPIOB_BASE + TIVA_GPIO_RIS_OFFSET)
# define TIVA_GPIOB_MIS (TIVA_GPIOB_BASE + TIVA_GPIO_MIS_OFFSET)
# define TIVA_GPIOB_ICR (TIVA_GPIOB_BASE + TIVA_GPIO_ICR_OFFSET)
# define TIVA_GPIOB_AFSEL (TIVA_GPIOB_BASE + TIVA_GPIO_AFSEL_OFFSET)
# define TIVA_GPIOB_DR2R (TIVA_GPIOB_BASE + TIVA_GPIO_DR2R_OFFSET)
# define TIVA_GPIOB_DR4R (TIVA_GPIOB_BASE + TIVA_GPIO_DR4R_OFFSET)
# define TIVA_GPIOB_DR8R (TIVA_GPIOB_BASE + TIVA_GPIO_DR8R_OFFSET)
# define TIVA_GPIOB_ODR (TIVA_GPIOB_BASE + TIVA_GPIO_ODR_OFFSET)
# define TIVA_GPIOB_PUR (TIVA_GPIOB_BASE + TIVA_GPIO_PUR_OFFSET)
# define TIVA_GPIOB_PDR (TIVA_GPIOB_BASE + TIVA_GPIO_PDR_OFFSET)
# define TIVA_GPIOB_SLR (TIVA_GPIOB_BASE + TIVA_GPIO_SLR_OFFSET)
# define TIVA_GPIOB_DEN (TIVA_GPIOB_BASE + TIVA_GPIO_DEN_OFFSET)
# define TIVA_GPIOB_LOCK (TIVA_GPIOB_BASE + TIVA_GPIO_LOCK_OFFSET)
# define TIVA_GPIOB_CR (TIVA_GPIOB_BASE + TIVA_GPIO_CR_OFFSET)
# ifdef LM4F
# define LM_GPIOB_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
# define LM_GPIOB_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
# define LM_GPIOB_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
# define LM_GPIOB_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
# define TIVA_GPIOB_AMSEL (TIVA_GPIOB_BASE + TIVA_GPIO_AMSEL_OFFSET)
# define TIVA_GPIOB_PCTL (TIVA_GPIOB_BASE + TIVA_GPIO_PCTL_OFFSET)
# define TIVA_GPIOB_ADCCTL (TIVA_GPIOB_BASE + TIVA_GPIO_ADCCTL_OFFSET)
# define TIVA_GPIOB_DMACTL (TIVA_GPIOB_BASE + TIVA_GPIO_DMACTL_OFFSET)
# endif
# define LM_GPIOB_PERIPHID4 (LM_GPIOB_BASE + LM_GPIO_PERIPHID4_OFFSET)
# define LM_GPIOB_PERIPHID5 (LM_GPIOB_BASE + LM_GPIO_PERIPHID5_OFFSET)
# define LM_GPIOB_PERIPHID6 (LM_GPIOB_BASE + LM_GPIO_PERIPHID6_OFFSET)
# define LM_GPIOB_PERIPHID7 (LM_GPIOB_BASE + LM_GPIO_PERIPHID7_OFFSET)
# define LM_GPIOB_PERIPHID0 (LM_GPIOB_BASE + LM_GPIO_PERIPHID0_OFFSET)
# define LM_GPIOB_PERIPHID1 (LM_GPIOB_BASE + LM_GPIO_PERIPHID1_OFFSET)
# define LM_GPIOB_PERIPHID2 (LM_GPIOB_BASE + LM_GPIO_PERIPHID2_OFFSET)
# define LM_GPIOB_PERIPHID3 (LM_GPIOB_BASE + LM_GPIO_PERIPHID3_OFFSET)
# define LM_GPIOB_PCELLID0 (LM_GPIOB_BASE + LM_GPIO_PCELLID0_OFFSET)
# define LM_GPIOB_PCELLID1 (LM_GPIOB_BASE + LM_GPIO_PCELLID1_OFFSET)
# define LM_GPIOB_PCELLID2 (LM_GPIOB_BASE + LM_GPIO_PCELLID2_OFFSET)
# define LM_GPIOB_PCELLID3 (LM_GPIOB_BASE + LM_GPIO_PCELLID3_OFFSET)
# define TIVA_GPIOB_PERIPHID4 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID4_OFFSET)
# define TIVA_GPIOB_PERIPHID5 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID5_OFFSET)
# define TIVA_GPIOB_PERIPHID6 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID6_OFFSET)
# define TIVA_GPIOB_PERIPHID7 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID7_OFFSET)
# define TIVA_GPIOB_PERIPHID0 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID0_OFFSET)
# define TIVA_GPIOB_PERIPHID1 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID1_OFFSET)
# define TIVA_GPIOB_PERIPHID2 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID2_OFFSET)
# define TIVA_GPIOB_PERIPHID3 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID3_OFFSET)
# define TIVA_GPIOB_PCELLID0 (TIVA_GPIOB_BASE + TIVA_GPIO_PCELLID0_OFFSET)
# define TIVA_GPIOB_PCELLID1 (TIVA_GPIOB_BASE + TIVA_GPIO_PCELLID1_OFFSET)
# define TIVA_GPIOB_PCELLID2 (TIVA_GPIOB_BASE + TIVA_GPIO_PCELLID2_OFFSET)
# define TIVA_GPIOB_PCELLID3 (TIVA_GPIOB_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#elif LM_NPORTS > 2
#elif TIVA_NPORTS > 2
# define LM_GPIOC_DATA (LM_GPIOC_BASE + LM_GPIO_DATA_OFFSET)
# define LM_GPIOC_DIR (LM_GPIOC_BASE + LM_GPIO_DIR_OFFSET)
# define LM_GPIOC_IS (LM_GPIOC_BASE + LM_GPIO_IS_OFFSET)
# define LM_GPIOC_IBE (LM_GPIOC_BASE + LM_GPIO_IBE_OFFSET)
# define LM_GPIOC_IEV (LM_GPIOC_BASE + LM_GPIO_IEV_OFFSET)
# define LM_GPIOC_IM (LM_GPIOC_BASE + LM_GPIO_IM_OFFSET)
# define LM_GPIOC_RIS (LM_GPIOC_BASE + LM_GPIO_RIS_OFFSET)
# define LM_GPIOC_MIS (LM_GPIOC_BASE + LM_GPIO_MIS_OFFSET)
# define LM_GPIOC_ICR (LM_GPIOC_BASE + LM_GPIO_ICR_OFFSET)
# define LM_GPIOC_AFSEL (LM_GPIOC_BASE + LM_GPIO_AFSEL_OFFSET)
# define LM_GPIOC_DR2R (LM_GPIOC_BASE + LM_GPIO_DR2R_OFFSET)
# define LM_GPIOC_DR4R (LM_GPIOC_BASE + LM_GPIO_DR4R_OFFSET)
# define LM_GPIOC_DR8R (LM_GPIOC_BASE + LM_GPIO_DR8R_OFFSET)
# define LM_GPIOC_ODR (LM_GPIOC_BASE + LM_GPIO_ODR_OFFSET)
# define LM_GPIOC_PUR (LM_GPIOC_BASE + LM_GPIO_PUR_OFFSET)
# define LM_GPIOC_PDR (LM_GPIOC_BASE + LM_GPIO_PDR_OFFSET)
# define LM_GPIOC_SLR (LM_GPIOC_BASE + LM_GPIO_SLR_OFFSET)
# define LM_GPIOC_DEN (LM_GPIOC_BASE + LM_GPIO_DEN_OFFSET)
# define LM_GPIOC_LOCK (LM_GPIOC_BASE + LM_GPIO_LOCK_OFFSET)
# define LM_GPIOC_CR (LM_GPIOC_BASE + LM_GPIO_CR_OFFSET)
# define TIVA_GPIOC_DATA (TIVA_GPIOC_BASE + TIVA_GPIO_DATA_OFFSET)
# define TIVA_GPIOC_DIR (TIVA_GPIOC_BASE + TIVA_GPIO_DIR_OFFSET)
# define TIVA_GPIOC_IS (TIVA_GPIOC_BASE + TIVA_GPIO_IS_OFFSET)
# define TIVA_GPIOC_IBE (TIVA_GPIOC_BASE + TIVA_GPIO_IBE_OFFSET)
# define TIVA_GPIOC_IEV (TIVA_GPIOC_BASE + TIVA_GPIO_IEV_OFFSET)
# define TIVA_GPIOC_IM (TIVA_GPIOC_BASE + TIVA_GPIO_IM_OFFSET)
# define TIVA_GPIOC_RIS (TIVA_GPIOC_BASE + TIVA_GPIO_RIS_OFFSET)
# define TIVA_GPIOC_MIS (TIVA_GPIOC_BASE + TIVA_GPIO_MIS_OFFSET)
# define TIVA_GPIOC_ICR (TIVA_GPIOC_BASE + TIVA_GPIO_ICR_OFFSET)
# define TIVA_GPIOC_AFSEL (TIVA_GPIOC_BASE + TIVA_GPIO_AFSEL_OFFSET)
# define TIVA_GPIOC_DR2R (TIVA_GPIOC_BASE + TIVA_GPIO_DR2R_OFFSET)
# define TIVA_GPIOC_DR4R (TIVA_GPIOC_BASE + TIVA_GPIO_DR4R_OFFSET)
# define TIVA_GPIOC_DR8R (TIVA_GPIOC_BASE + TIVA_GPIO_DR8R_OFFSET)
# define TIVA_GPIOC_ODR (TIVA_GPIOC_BASE + TIVA_GPIO_ODR_OFFSET)
# define TIVA_GPIOC_PUR (TIVA_GPIOC_BASE + TIVA_GPIO_PUR_OFFSET)
# define TIVA_GPIOC_PDR (TIVA_GPIOC_BASE + TIVA_GPIO_PDR_OFFSET)
# define TIVA_GPIOC_SLR (TIVA_GPIOC_BASE + TIVA_GPIO_SLR_OFFSET)
# define TIVA_GPIOC_DEN (TIVA_GPIOC_BASE + TIVA_GPIO_DEN_OFFSET)
# define TIVA_GPIOC_LOCK (TIVA_GPIOC_BASE + TIVA_GPIO_LOCK_OFFSET)
# define TIVA_GPIOC_CR (TIVA_GPIOC_BASE + TIVA_GPIO_CR_OFFSET)
# ifdef LM4F
# define LM_GPIOC_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
# define LM_GPIOC_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
# define LM_GPIOC_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
# define LM_GPIOC_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
# define TIVA_GPIOC_AMSEL (TIVA_GPIOC_BASE + TIVA_GPIO_AMSEL_OFFSET)
# define TIVA_GPIOC_PCTL (TIVA_GPIOC_BASE + TIVA_GPIO_PCTL_OFFSET)
# define TIVA_GPIOC_ADCCTL (TIVA_GPIOC_BASE + TIVA_GPIO_ADCCTL_OFFSET)
# define TIVA_GPIOC_DMACTL (TIVA_GPIOC_BASE + TIVA_GPIO_DMACTL_OFFSET)
# endif
# define LM_GPIOC_PERIPHID4 (LM_GPIOC_BASE + LM_GPIO_PERIPHID4_OFFSET)
# define LM_GPIOC_PERIPHID5 (LM_GPIOC_BASE + LM_GPIO_PERIPHID5_OFFSET)
# define LM_GPIOC_PERIPHID6 (LM_GPIOC_BASE + LM_GPIO_PERIPHID6_OFFSET)
# define LM_GPIOC_PERIPHID7 (LM_GPIOC_BASE + LM_GPIO_PERIPHID7_OFFSET)
# define LM_GPIOC_PERIPHID0 (LM_GPIOC_BASE + LM_GPIO_PERIPHID0_OFFSET)
# define LM_GPIOC_PERIPHID1 (LM_GPIOC_BASE + LM_GPIO_PERIPHID1_OFFSET)
# define LM_GPIOC_PERIPHID2 (LM_GPIOC_BASE + LM_GPIO_PERIPHID2_OFFSET)
# define LM_GPIOC_PERIPHID3 (LM_GPIOC_BASE + LM_GPIO_PERIPHID3_OFFSET)
# define LM_GPIOC_PCELLID0 (LM_GPIOC_BASE + LM_GPIO_PCELLID0_OFFSET)
# define LM_GPIOC_PCELLID1 (LM_GPIOC_BASE + LM_GPIO_PCELLID1_OFFSET)
# define LM_GPIOC_PCELLID2 (LM_GPIOC_BASE + LM_GPIO_PCELLID2_OFFSET)
# define LM_GPIOC_PCELLID3 (LM_GPIOC_BASE + LM_GPIO_PCELLID3_OFFSET)
# define TIVA_GPIOC_PERIPHID4 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID4_OFFSET)
# define TIVA_GPIOC_PERIPHID5 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID5_OFFSET)
# define TIVA_GPIOC_PERIPHID6 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID6_OFFSET)
# define TIVA_GPIOC_PERIPHID7 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID7_OFFSET)
# define TIVA_GPIOC_PERIPHID0 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID0_OFFSET)
# define TIVA_GPIOC_PERIPHID1 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID1_OFFSET)
# define TIVA_GPIOC_PERIPHID2 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID2_OFFSET)
# define TIVA_GPIOC_PERIPHID3 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID3_OFFSET)
# define TIVA_GPIOC_PCELLID0 (TIVA_GPIOC_BASE + TIVA_GPIO_PCELLID0_OFFSET)
# define TIVA_GPIOC_PCELLID1 (TIVA_GPIOC_BASE + TIVA_GPIO_PCELLID1_OFFSET)
# define TIVA_GPIOC_PCELLID2 (TIVA_GPIOC_BASE + TIVA_GPIO_PCELLID2_OFFSET)
# define TIVA_GPIOC_PCELLID3 (TIVA_GPIOC_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#elif LM_NPORTS > 3
#elif TIVA_NPORTS > 3
# define LM_GPIOD_DATA (LM_GPIOD_BASE + LM_GPIO_DATA_OFFSET)
# define LM_GPIOD_DIR (LM_GPIOD_BASE + LM_GPIO_DIR_OFFSET)
# define LM_GPIOD_IS (LM_GPIOD_BASE + LM_GPIO_IS_OFFSET)
# define LM_GPIOD_IBE (LM_GPIOD_BASE + LM_GPIO_IBE_OFFSET)
# define LM_GPIOD_IEV (LM_GPIOD_BASE + LM_GPIO_IEV_OFFSET)
# define LM_GPIOD_IM (LM_GPIOD_BASE + LM_GPIO_IM_OFFSET)
# define LM_GPIOD_RIS (LM_GPIOD_BASE + LM_GPIO_RIS_OFFSET)
# define LM_GPIOD_MIS (LM_GPIOD_BASE + LM_GPIO_MIS_OFFSET)
# define LM_GPIOD_ICR (LM_GPIOD_BASE + LM_GPIO_ICR_OFFSET)
# define LM_GPIOD_AFSEL (LM_GPIOD_BASE + LM_GPIO_AFSEL_OFFSET)
# define LM_GPIOD_DR2R (LM_GPIOD_BASE + LM_GPIO_DR2R_OFFSET)
# define LM_GPIOD_DR4R (LM_GPIOD_BASE + LM_GPIO_DR4R_OFFSET)
# define LM_GPIOD_DR8R (LM_GPIOD_BASE + LM_GPIO_DR8R_OFFSET)
# define LM_GPIOD_ODR (LM_GPIOD_BASE + LM_GPIO_ODR_OFFSET)
# define LM_GPIOD_PUR (LM_GPIOD_BASE + LM_GPIO_PUR_OFFSET)
# define LM_GPIOD_PDR (LM_GPIOD_BASE + LM_GPIO_PDR_OFFSET)
# define LM_GPIOD_SLR (LM_GPIOD_BASE + LM_GPIO_SLR_OFFSET)
# define LM_GPIOD_DEN (LM_GPIOD_BASE + LM_GPIO_DEN_OFFSET)
# define LM_GPIOD_LOCK (LM_GPIOD_BASE + LM_GPIO_LOCK_OFFSET)
# define LM_GPIOD_CR (LM_GPIOD_BASE + LM_GPIO_CR_OFFSET)
# define TIVA_GPIOD_DATA (TIVA_GPIOD_BASE + TIVA_GPIO_DATA_OFFSET)
# define TIVA_GPIOD_DIR (TIVA_GPIOD_BASE + TIVA_GPIO_DIR_OFFSET)
# define TIVA_GPIOD_IS (TIVA_GPIOD_BASE + TIVA_GPIO_IS_OFFSET)
# define TIVA_GPIOD_IBE (TIVA_GPIOD_BASE + TIVA_GPIO_IBE_OFFSET)
# define TIVA_GPIOD_IEV (TIVA_GPIOD_BASE + TIVA_GPIO_IEV_OFFSET)
# define TIVA_GPIOD_IM (TIVA_GPIOD_BASE + TIVA_GPIO_IM_OFFSET)
# define TIVA_GPIOD_RIS (TIVA_GPIOD_BASE + TIVA_GPIO_RIS_OFFSET)
# define TIVA_GPIOD_MIS (TIVA_GPIOD_BASE + TIVA_GPIO_MIS_OFFSET)
# define TIVA_GPIOD_ICR (TIVA_GPIOD_BASE + TIVA_GPIO_ICR_OFFSET)
# define TIVA_GPIOD_AFSEL (TIVA_GPIOD_BASE + TIVA_GPIO_AFSEL_OFFSET)
# define TIVA_GPIOD_DR2R (TIVA_GPIOD_BASE + TIVA_GPIO_DR2R_OFFSET)
# define TIVA_GPIOD_DR4R (TIVA_GPIOD_BASE + TIVA_GPIO_DR4R_OFFSET)
# define TIVA_GPIOD_DR8R (TIVA_GPIOD_BASE + TIVA_GPIO_DR8R_OFFSET)
# define TIVA_GPIOD_ODR (TIVA_GPIOD_BASE + TIVA_GPIO_ODR_OFFSET)
# define TIVA_GPIOD_PUR (TIVA_GPIOD_BASE + TIVA_GPIO_PUR_OFFSET)
# define TIVA_GPIOD_PDR (TIVA_GPIOD_BASE + TIVA_GPIO_PDR_OFFSET)
# define TIVA_GPIOD_SLR (TIVA_GPIOD_BASE + TIVA_GPIO_SLR_OFFSET)
# define TIVA_GPIOD_DEN (TIVA_GPIOD_BASE + TIVA_GPIO_DEN_OFFSET)
# define TIVA_GPIOD_LOCK (TIVA_GPIOD_BASE + TIVA_GPIO_LOCK_OFFSET)
# define TIVA_GPIOD_CR (TIVA_GPIOD_BASE + TIVA_GPIO_CR_OFFSET)
# ifdef LM4F
# define LM_GPIOD_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
# define LM_GPIOD_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
# define LM_GPIOD_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
# define LM_GPIOD_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
# define TIVA_GPIOD_AMSEL (TIVA_GPIOD_BASE + TIVA_GPIO_AMSEL_OFFSET)
# define TIVA_GPIOD_PCTL (TIVA_GPIOD_BASE + TIVA_GPIO_PCTL_OFFSET)
# define TIVA_GPIOD_ADCCTL (TIVA_GPIOD_BASE + TIVA_GPIO_ADCCTL_OFFSET)
# define TIVA_GPIOD_DMACTL (TIVA_GPIOD_BASE + TIVA_GPIO_DMACTL_OFFSET)
# endif
# define LM_GPIOD_PERIPHID4 (LM_GPIOD_BASE + LM_GPIO_PERIPHID4_OFFSET)
# define LM_GPIOD_PERIPHID5 (LM_GPIOD_BASE + LM_GPIO_PERIPHID5_OFFSET)
# define LM_GPIOD_PERIPHID6 (LM_GPIOD_BASE + LM_GPIO_PERIPHID6_OFFSET)
# define LM_GPIOD_PERIPHID7 (LM_GPIOD_BASE + LM_GPIO_PERIPHID7_OFFSET)
# define LM_GPIOD_PERIPHID0 (LM_GPIOD_BASE + LM_GPIO_PERIPHID0_OFFSET)
# define LM_GPIOD_PERIPHID1 (LM_GPIOD_BASE + LM_GPIO_PERIPHID1_OFFSET)
# define LM_GPIOD_PERIPHID2 (LM_GPIOD_BASE + LM_GPIO_PERIPHID2_OFFSET)
# define LM_GPIOD_PERIPHID3 (LM_GPIOD_BASE + LM_GPIO_PERIPHID3_OFFSET)
# define LM_GPIOD_PCELLID0 (LM_GPIOD_BASE + LM_GPIO_PCELLID0_OFFSET)
# define LM_GPIOD_PCELLID1 (LM_GPIOD_BASE + LM_GPIO_PCELLID1_OFFSET)
# define LM_GPIOD_PCELLID2 (LM_GPIOD_BASE + LM_GPIO_PCELLID2_OFFSET)
# define LM_GPIOD_PCELLID3 (LM_GPIOD_BASE + LM_GPIO_PCELLID3_OFFSET)
# define TIVA_GPIOD_PERIPHID4 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID4_OFFSET)
# define TIVA_GPIOD_PERIPHID5 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID5_OFFSET)
# define TIVA_GPIOD_PERIPHID6 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID6_OFFSET)
# define TIVA_GPIOD_PERIPHID7 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID7_OFFSET)
# define TIVA_GPIOD_PERIPHID0 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID0_OFFSET)
# define TIVA_GPIOD_PERIPHID1 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID1_OFFSET)
# define TIVA_GPIOD_PERIPHID2 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID2_OFFSET)
# define TIVA_GPIOD_PERIPHID3 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID3_OFFSET)
# define TIVA_GPIOD_PCELLID0 (TIVA_GPIOD_BASE + TIVA_GPIO_PCELLID0_OFFSET)
# define TIVA_GPIOD_PCELLID1 (TIVA_GPIOD_BASE + TIVA_GPIO_PCELLID1_OFFSET)
# define TIVA_GPIOD_PCELLID2 (TIVA_GPIOD_BASE + TIVA_GPIO_PCELLID2_OFFSET)
# define TIVA_GPIOD_PCELLID3 (TIVA_GPIOD_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#elif LM_NPORTS > 4
#elif TIVA_NPORTS > 4
# define LM_GPIOE_DATA (LM_GPIOE_BASE + LM_GPIO_DATA_OFFSET)
# define LM_GPIOE_DIR (LM_GPIOE_BASE + LM_GPIO_DIR_OFFSET)
# define LM_GPIOE_IS (LM_GPIOE_BASE + LM_GPIO_IS_OFFSET)
# define LM_GPIOE_IBE (LM_GPIOE_BASE + LM_GPIO_IBE_OFFSET)
# define LM_GPIOE_IEV (LM_GPIOE_BASE + LM_GPIO_IEV_OFFSET)
# define LM_GPIOE_IM (LM_GPIOE_BASE + LM_GPIO_IM_OFFSET)
# define LM_GPIOE_RIS (LM_GPIOE_BASE + LM_GPIO_RIS_OFFSET)
# define LM_GPIOE_MIS (LM_GPIOE_BASE + LM_GPIO_MIS_OFFSET)
# define LM_GPIOE_ICR (LM_GPIOE_BASE + LM_GPIO_ICR_OFFSET)
# define LM_GPIOE_AFSEL (LM_GPIOE_BASE + LM_GPIO_AFSEL_OFFSET)
# define LM_GPIOE_DR2R (LM_GPIOE_BASE + LM_GPIO_DR2R_OFFSET)
# define LM_GPIOE_DR4R (LM_GPIOE_BASE + LM_GPIO_DR4R_OFFSET)
# define LM_GPIOE_DR8R (LM_GPIOE_BASE + LM_GPIO_DR8R_OFFSET)
# define LM_GPIOE_ODR (LM_GPIOE_BASE + LM_GPIO_ODR_OFFSET)
# define LM_GPIOE_PUR (LM_GPIOE_BASE + LM_GPIO_PUR_OFFSET)
# define LM_GPIOE_PDR (LM_GPIOE_BASE + LM_GPIO_PDR_OFFSET)
# define LM_GPIOE_SLR (LM_GPIOE_BASE + LM_GPIO_SLR_OFFSET)
# define LM_GPIOE_DEN (LM_GPIOE_BASE + LM_GPIO_DEN_OFFSET)
# define LM_GPIOE_LOCK (LM_GPIOE_BASE + LM_GPIO_LOCK_OFFSET)
# define LM_GPIOE_CR (LM_GPIOE_BASE + LM_GPIO_CR_OFFSET)
# define TIVA_GPIOE_DATA (TIVA_GPIOE_BASE + TIVA_GPIO_DATA_OFFSET)
# define TIVA_GPIOE_DIR (TIVA_GPIOE_BASE + TIVA_GPIO_DIR_OFFSET)
# define TIVA_GPIOE_IS (TIVA_GPIOE_BASE + TIVA_GPIO_IS_OFFSET)
# define TIVA_GPIOE_IBE (TIVA_GPIOE_BASE + TIVA_GPIO_IBE_OFFSET)
# define TIVA_GPIOE_IEV (TIVA_GPIOE_BASE + TIVA_GPIO_IEV_OFFSET)
# define TIVA_GPIOE_IM (TIVA_GPIOE_BASE + TIVA_GPIO_IM_OFFSET)
# define TIVA_GPIOE_RIS (TIVA_GPIOE_BASE + TIVA_GPIO_RIS_OFFSET)
# define TIVA_GPIOE_MIS (TIVA_GPIOE_BASE + TIVA_GPIO_MIS_OFFSET)
# define TIVA_GPIOE_ICR (TIVA_GPIOE_BASE + TIVA_GPIO_ICR_OFFSET)
# define TIVA_GPIOE_AFSEL (TIVA_GPIOE_BASE + TIVA_GPIO_AFSEL_OFFSET)
# define TIVA_GPIOE_DR2R (TIVA_GPIOE_BASE + TIVA_GPIO_DR2R_OFFSET)
# define TIVA_GPIOE_DR4R (TIVA_GPIOE_BASE + TIVA_GPIO_DR4R_OFFSET)
# define TIVA_GPIOE_DR8R (TIVA_GPIOE_BASE + TIVA_GPIO_DR8R_OFFSET)
# define TIVA_GPIOE_ODR (TIVA_GPIOE_BASE + TIVA_GPIO_ODR_OFFSET)
# define TIVA_GPIOE_PUR (TIVA_GPIOE_BASE + TIVA_GPIO_PUR_OFFSET)
# define TIVA_GPIOE_PDR (TIVA_GPIOE_BASE + TIVA_GPIO_PDR_OFFSET)
# define TIVA_GPIOE_SLR (TIVA_GPIOE_BASE + TIVA_GPIO_SLR_OFFSET)
# define TIVA_GPIOE_DEN (TIVA_GPIOE_BASE + TIVA_GPIO_DEN_OFFSET)
# define TIVA_GPIOE_LOCK (TIVA_GPIOE_BASE + TIVA_GPIO_LOCK_OFFSET)
# define TIVA_GPIOE_CR (TIVA_GPIOE_BASE + TIVA_GPIO_CR_OFFSET)
# ifdef LM4F
# define LM_GPIOE_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
# define LM_GPIOE_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
# define LM_GPIOE_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
# define LM_GPIOE_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
# define TIVA_GPIOE_AMSEL (TIVA_GPIOE_BASE + TIVA_GPIO_AMSEL_OFFSET)
# define TIVA_GPIOE_PCTL (TIVA_GPIOE_BASE + TIVA_GPIO_PCTL_OFFSET)
# define TIVA_GPIOE_ADCCTL (TIVA_GPIOE_BASE + TIVA_GPIO_ADCCTL_OFFSET)
# define TIVA_GPIOE_DMACTL (TIVA_GPIOE_BASE + TIVA_GPIO_DMACTL_OFFSET)
# endif
# define LM_GPIOE_PERIPHID4 (LM_GPIOE_BASE + LM_GPIO_PERIPHID4_OFFSET)
# define LM_GPIOE_PERIPHID5 (LM_GPIOE_BASE + LM_GPIO_PERIPHID5_OFFSET)
# define LM_GPIOE_PERIPHID6 (LM_GPIOE_BASE + LM_GPIO_PERIPHID6_OFFSET)
# define LM_GPIOE_PERIPHID7 (LM_GPIOE_BASE + LM_GPIO_PERIPHID7_OFFSET)
# define LM_GPIOE_PERIPHID0 (LM_GPIOE_BASE + LM_GPIO_PERIPHID0_OFFSET)
# define LM_GPIOE_PERIPHID1 (LM_GPIOE_BASE + LM_GPIO_PERIPHID1_OFFSET)
# define LM_GPIOE_PERIPHID2 (LM_GPIOE_BASE + LM_GPIO_PERIPHID2_OFFSET)
# define LM_GPIOE_PERIPHID3 (LM_GPIOE_BASE + LM_GPIO_PERIPHID3_OFFSET)
# define LM_GPIOE_PCELLID0 (LM_GPIOE_BASE + LM_GPIO_PCELLID0_OFFSET)
# define LM_GPIOE_PCELLID1 (LM_GPIOE_BASE + LM_GPIO_PCELLID1_OFFSET)
# define LM_GPIOE_PCELLID2 (LM_GPIOE_BASE + LM_GPIO_PCELLID2_OFFSET)
# define LM_GPIOE_PCELLID3 (LM_GPIOE_BASE + LM_GPIO_PCELLID3_OFFSET)
# define TIVA_GPIOE_PERIPHID4 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID4_OFFSET)
# define TIVA_GPIOE_PERIPHID5 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID5_OFFSET)
# define TIVA_GPIOE_PERIPHID6 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID6_OFFSET)
# define TIVA_GPIOE_PERIPHID7 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID7_OFFSET)
# define TIVA_GPIOE_PERIPHID0 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID0_OFFSET)
# define TIVA_GPIOE_PERIPHID1 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID1_OFFSET)
# define TIVA_GPIOE_PERIPHID2 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID2_OFFSET)
# define TIVA_GPIOE_PERIPHID3 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID3_OFFSET)
# define TIVA_GPIOE_PCELLID0 (TIVA_GPIOE_BASE + TIVA_GPIO_PCELLID0_OFFSET)
# define TIVA_GPIOE_PCELLID1 (TIVA_GPIOE_BASE + TIVA_GPIO_PCELLID1_OFFSET)
# define TIVA_GPIOE_PCELLID2 (TIVA_GPIOE_BASE + TIVA_GPIO_PCELLID2_OFFSET)
# define TIVA_GPIOE_PCELLID3 (TIVA_GPIOE_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#elif LM_NPORTS > 5
#elif TIVA_NPORTS > 5
# define LM_GPIOF_DATA (LM_GPIOF_BASE + LM_GPIO_DATA_OFFSET)
# define LM_GPIOF_DIR (LM_GPIOF_BASE + LM_GPIO_DIR_OFFSET)
# define LM_GPIOF_IS (LM_GPIOF_BASE + LM_GPIO_IS_OFFSET)
# define LM_GPIOF_IBE (LM_GPIOF_BASE + LM_GPIO_IBE_OFFSET)
# define LM_GPIOF_IEV (LM_GPIOF_BASE + LM_GPIO_IEV_OFFSET)
# define LM_GPIOF_IM (LM_GPIOF_BASE + LM_GPIO_IM_OFFSET)
# define LM_GPIOF_RIS (LM_GPIOF_BASE + LM_GPIO_RIS_OFFSET)
# define LM_GPIOF_MIS (LM_GPIOF_BASE + LM_GPIO_MIS_OFFSET)
# define LM_GPIOF_ICR (LM_GPIOF_BASE + LM_GPIO_ICR_OFFSET)
# define LM_GPIOF_AFSEL (LM_GPIOF_BASE + LM_GPIO_AFSEL_OFFSET)
# define LM_GPIOF_DR2R (LM_GPIOF_BASE + LM_GPIO_DR2R_OFFSET)
# define LM_GPIOF_DR4R (LM_GPIOF_BASE + LM_GPIO_DR4R_OFFSET)
# define LM_GPIOF_DR8R (LM_GPIOF_BASE + LM_GPIO_DR8R_OFFSET)
# define LM_GPIOF_ODR (LM_GPIOF_BASE + LM_GPIO_ODR_OFFSET)
# define LM_GPIOF_PUR (LM_GPIOF_BASE + LM_GPIO_PUR_OFFSET)
# define LM_GPIOF_PDR (LM_GPIOF_BASE + LM_GPIO_PDR_OFFSET)
# define LM_GPIOF_SLR (LM_GPIOF_BASE + LM_GPIO_SLR_OFFSET)
# define LM_GPIOF_DEN (LM_GPIOF_BASE + LM_GPIO_DEN_OFFSET)
# define LM_GPIOF_LOCK (LM_GPIOF_BASE + LM_GPIO_LOCK_OFFSET)
# define LM_GPIOF_CR (LM_GPIOF_BASE + LM_GPIO_CR_OFFSET)
# define TIVA_GPIOF_DATA (TIVA_GPIOF_BASE + TIVA_GPIO_DATA_OFFSET)
# define TIVA_GPIOF_DIR (TIVA_GPIOF_BASE + TIVA_GPIO_DIR_OFFSET)
# define TIVA_GPIOF_IS (TIVA_GPIOF_BASE + TIVA_GPIO_IS_OFFSET)
# define TIVA_GPIOF_IBE (TIVA_GPIOF_BASE + TIVA_GPIO_IBE_OFFSET)
# define TIVA_GPIOF_IEV (TIVA_GPIOF_BASE + TIVA_GPIO_IEV_OFFSET)
# define TIVA_GPIOF_IM (TIVA_GPIOF_BASE + TIVA_GPIO_IM_OFFSET)
# define TIVA_GPIOF_RIS (TIVA_GPIOF_BASE + TIVA_GPIO_RIS_OFFSET)
# define TIVA_GPIOF_MIS (TIVA_GPIOF_BASE + TIVA_GPIO_MIS_OFFSET)
# define TIVA_GPIOF_ICR (TIVA_GPIOF_BASE + TIVA_GPIO_ICR_OFFSET)
# define TIVA_GPIOF_AFSEL (TIVA_GPIOF_BASE + TIVA_GPIO_AFSEL_OFFSET)
# define TIVA_GPIOF_DR2R (TIVA_GPIOF_BASE + TIVA_GPIO_DR2R_OFFSET)
# define TIVA_GPIOF_DR4R (TIVA_GPIOF_BASE + TIVA_GPIO_DR4R_OFFSET)
# define TIVA_GPIOF_DR8R (TIVA_GPIOF_BASE + TIVA_GPIO_DR8R_OFFSET)
# define TIVA_GPIOF_ODR (TIVA_GPIOF_BASE + TIVA_GPIO_ODR_OFFSET)
# define TIVA_GPIOF_PUR (TIVA_GPIOF_BASE + TIVA_GPIO_PUR_OFFSET)
# define TIVA_GPIOF_PDR (TIVA_GPIOF_BASE + TIVA_GPIO_PDR_OFFSET)
# define TIVA_GPIOF_SLR (TIVA_GPIOF_BASE + TIVA_GPIO_SLR_OFFSET)
# define TIVA_GPIOF_DEN (TIVA_GPIOF_BASE + TIVA_GPIO_DEN_OFFSET)
# define TIVA_GPIOF_LOCK (TIVA_GPIOF_BASE + TIVA_GPIO_LOCK_OFFSET)
# define TIVA_GPIOF_CR (TIVA_GPIOF_BASE + TIVA_GPIO_CR_OFFSET)
# ifdef LM4F
# define LM_GPIOF_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
# define LM_GPIOF_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
# define LM_GPIOF_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
# define LM_GPIOF_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
# define TIVA_GPIOF_AMSEL (TIVA_GPIOF_BASE + TIVA_GPIO_AMSEL_OFFSET)
# define TIVA_GPIOF_PCTL (TIVA_GPIOF_BASE + TIVA_GPIO_PCTL_OFFSET)
# define TIVA_GPIOF_ADCCTL (TIVA_GPIOF_BASE + TIVA_GPIO_ADCCTL_OFFSET)
# define TIVA_GPIOF_DMACTL (TIVA_GPIOF_BASE + TIVA_GPIO_DMACTL_OFFSET)
# endif
# define LM_GPIOF_PERIPHID4 (LM_GPIOF_BASE + LM_GPIO_PERIPHID4_OFFSET)
# define LM_GPIOF_PERIPHID5 (LM_GPIOF_BASE + LM_GPIO_PERIPHID5_OFFSET)
# define LM_GPIOF_PERIPHID6 (LM_GPIOF_BASE + LM_GPIO_PERIPHID6_OFFSET)
# define LM_GPIOF_PERIPHID7 (LM_GPIOF_BASE + LM_GPIO_PERIPHID7_OFFSET)
# define LM_GPIOF_PERIPHID0 (LM_GPIOF_BASE + LM_GPIO_PERIPHID0_OFFSET)
# define LM_GPIOF_PERIPHID1 (LM_GPIOF_BASE + LM_GPIO_PERIPHID1_OFFSET)
# define LM_GPIOF_PERIPHID2 (LM_GPIOF_BASE + LM_GPIO_PERIPHID2_OFFSET)
# define LM_GPIOF_PERIPHID3 (LM_GPIOF_BASE + LM_GPIO_PERIPHID3_OFFSET)
# define LM_GPIOF_PCELLID0 (LM_GPIOF_BASE + LM_GPIO_PCELLID0_OFFSET)
# define LM_GPIOF_PCELLID1 (LM_GPIOF_BASE + LM_GPIO_PCELLID1_OFFSET)
# define LM_GPIOF_PCELLID2 (LM_GPIOF_BASE + LM_GPIO_PCELLID2_OFFSET)
# define LM_GPIOF_PCELLID3 (LM_GPIOF_BASE + LM_GPIO_PCELLID3_OFFSET)
# define TIVA_GPIOF_PERIPHID4 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID4_OFFSET)
# define TIVA_GPIOF_PERIPHID5 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID5_OFFSET)
# define TIVA_GPIOF_PERIPHID6 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID6_OFFSET)
# define TIVA_GPIOF_PERIPHID7 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID7_OFFSET)
# define TIVA_GPIOF_PERIPHID0 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID0_OFFSET)
# define TIVA_GPIOF_PERIPHID1 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID1_OFFSET)
# define TIVA_GPIOF_PERIPHID2 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID2_OFFSET)
# define TIVA_GPIOF_PERIPHID3 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID3_OFFSET)
# define TIVA_GPIOF_PCELLID0 (TIVA_GPIOF_BASE + TIVA_GPIO_PCELLID0_OFFSET)
# define TIVA_GPIOF_PCELLID1 (TIVA_GPIOF_BASE + TIVA_GPIO_PCELLID1_OFFSET)
# define TIVA_GPIOF_PCELLID2 (TIVA_GPIOF_BASE + TIVA_GPIO_PCELLID2_OFFSET)
# define TIVA_GPIOF_PCELLID3 (TIVA_GPIOF_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#elif LM_NPORTS > 6
#elif TIVA_NPORTS > 6
# define LM_GPIOG_DATA (LM_GPIOG_BASE + LM_GPIO_DATA_OFFSET)
# define LM_GPIOG_DIR (LM_GPIOG_BASE + LM_GPIO_DIR_OFFSET)
# define LM_GPIOG_IS (LM_GPIOG_BASE + LM_GPIO_IS_OFFSET)
# define LM_GPIOG_IBE (LM_GPIOG_BASE + LM_GPIO_IBE_OFFSET)
# define LM_GPIOG_IEV (LM_GPIOG_BASE + LM_GPIO_IEV_OFFSET)
# define LM_GPIOG_IM (LM_GPIOG_BASE + LM_GPIO_IM_OFFSET)
# define LM_GPIOG_RIS (LM_GPIOG_BASE + LM_GPIO_RIS_OFFSET)
# define LM_GPIOG_MIS (LM_GPIOG_BASE + LM_GPIO_MIS_OFFSET)
# define LM_GPIOG_ICR (LM_GPIOG_BASE + LM_GPIO_ICR_OFFSET)
# define LM_GPIOG_AFSEL (LM_GPIOG_BASE + LM_GPIO_AFSEL_OFFSET)
# define LM_GPIOG_DR2R (LM_GPIOG_BASE + LM_GPIO_DR2R_OFFSET)
# define LM_GPIOG_DR4R (LM_GPIOG_BASE + LM_GPIO_DR4R_OFFSET)
# define LM_GPIOG_DR8R (LM_GPIOG_BASE + LM_GPIO_DR8R_OFFSET)
# define LM_GPIOG_ODR (LM_GPIOG_BASE + LM_GPIO_ODR_OFFSET)
# define LM_GPIOG_PUR (LM_GPIOG_BASE + LM_GPIO_PUR_OFFSET)
# define LM_GPIOG_PDR (LM_GPIOG_BASE + LM_GPIO_PDR_OFFSET)
# define LM_GPIOG_SLR (LM_GPIOG_BASE + LM_GPIO_SLR_OFFSET)
# define LM_GPIOG_DEN (LM_GPIOG_BASE + LM_GPIO_DEN_OFFSET)
# define LM_GPIOG_LOCK (LM_GPIOG_BASE + LM_GPIO_LOCK_OFFSET)
# define LM_GPIOG_CR (LM_GPIOG_BASE + LM_GPIO_CR_OFFSET)
# define TIVA_GPIOG_DATA (TIVA_GPIOG_BASE + TIVA_GPIO_DATA_OFFSET)
# define TIVA_GPIOG_DIR (TIVA_GPIOG_BASE + TIVA_GPIO_DIR_OFFSET)
# define TIVA_GPIOG_IS (TIVA_GPIOG_BASE + TIVA_GPIO_IS_OFFSET)
# define TIVA_GPIOG_IBE (TIVA_GPIOG_BASE + TIVA_GPIO_IBE_OFFSET)
# define TIVA_GPIOG_IEV (TIVA_GPIOG_BASE + TIVA_GPIO_IEV_OFFSET)
# define TIVA_GPIOG_IM (TIVA_GPIOG_BASE + TIVA_GPIO_IM_OFFSET)
# define TIVA_GPIOG_RIS (TIVA_GPIOG_BASE + TIVA_GPIO_RIS_OFFSET)
# define TIVA_GPIOG_MIS (TIVA_GPIOG_BASE + TIVA_GPIO_MIS_OFFSET)
# define TIVA_GPIOG_ICR (TIVA_GPIOG_BASE + TIVA_GPIO_ICR_OFFSET)
# define TIVA_GPIOG_AFSEL (TIVA_GPIOG_BASE + TIVA_GPIO_AFSEL_OFFSET)
# define TIVA_GPIOG_DR2R (TIVA_GPIOG_BASE + TIVA_GPIO_DR2R_OFFSET)
# define TIVA_GPIOG_DR4R (TIVA_GPIOG_BASE + TIVA_GPIO_DR4R_OFFSET)
# define TIVA_GPIOG_DR8R (TIVA_GPIOG_BASE + TIVA_GPIO_DR8R_OFFSET)
# define TIVA_GPIOG_ODR (TIVA_GPIOG_BASE + TIVA_GPIO_ODR_OFFSET)
# define TIVA_GPIOG_PUR (TIVA_GPIOG_BASE + TIVA_GPIO_PUR_OFFSET)
# define TIVA_GPIOG_PDR (TIVA_GPIOG_BASE + TIVA_GPIO_PDR_OFFSET)
# define TIVA_GPIOG_SLR (TIVA_GPIOG_BASE + TIVA_GPIO_SLR_OFFSET)
# define TIVA_GPIOG_DEN (TIVA_GPIOG_BASE + TIVA_GPIO_DEN_OFFSET)
# define TIVA_GPIOG_LOCK (TIVA_GPIOG_BASE + TIVA_GPIO_LOCK_OFFSET)
# define TIVA_GPIOG_CR (TIVA_GPIOG_BASE + TIVA_GPIO_CR_OFFSET)
# ifdef LM4F
# define LM_GPIOG_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
# define LM_GPIOG_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
# define LM_GPIOG_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
# define LM_GPIOG_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
# define TIVA_GPIOG_AMSEL (TIVA_GPIOG_BASE + TIVA_GPIO_AMSEL_OFFSET)
# define TIVA_GPIOG_PCTL (TIVA_GPIOG_BASE + TIVA_GPIO_PCTL_OFFSET)
# define TIVA_GPIOG_ADCCTL (TIVA_GPIOG_BASE + TIVA_GPIO_ADCCTL_OFFSET)
# define TIVA_GPIOG_DMACTL (TIVA_GPIOG_BASE + TIVA_GPIO_DMACTL_OFFSET)
# endif
# define LM_GPIOG_PERIPHID4 (LM_GPIOG_BASE + LM_GPIO_PERIPHID4_OFFSET)
# define LM_GPIOG_PERIPHID5 (LM_GPIOG_BASE + LM_GPIO_PERIPHID5_OFFSET)
# define LM_GPIOG_PERIPHID6 (LM_GPIOG_BASE + LM_GPIO_PERIPHID6_OFFSET)
# define LM_GPIOG_PERIPHID7 (LM_GPIOG_BASE + LM_GPIO_PERIPHID7_OFFSET)
# define LM_GPIOG_PERIPHID0 (LM_GPIOG_BASE + LM_GPIO_PERIPHID0_OFFSET)
# define LM_GPIOG_PERIPHID1 (LM_GPIOG_BASE + LM_GPIO_PERIPHID1_OFFSET)
# define LM_GPIOG_PERIPHID2 (LM_GPIOG_BASE + LM_GPIO_PERIPHID2_OFFSET)
# define LM_GPIOG_PERIPHID3 (LM_GPIOG_BASE + LM_GPIO_PERIPHID3_OFFSET)
# define LM_GPIOG_PCELLID0 (LM_GPIOG_BASE + LM_GPIO_PCELLID0_OFFSET)
# define LM_GPIOG_PCELLID1 (LM_GPIOG_BASE + LM_GPIO_PCELLID1_OFFSET)
# define LM_GPIOG_PCELLID2 (LM_GPIOG_BASE + LM_GPIO_PCELLID2_OFFSET)
# define LM_GPIOG_PCELLID3 (LM_GPIOG_BASE + LM_GPIO_PCELLID3_OFFSET)
# define TIVA_GPIOG_PERIPHID4 (TIVA_GPIOG_BASE + TIVA_GPIO_PERIPHID4_OFFSET)
# define TIVA_GPIOG_PERIPHID5 (TIVA_GPIOG_BASE + TIVA_GPIO_PERIPHID5_OFFSET)
# define TIVA_GPIOG_PERIPHID6 (TIVA_GPIOG_BASE + TIVA_GPIO_PERIPHID6_OFFSET)
# define TIVA_GPIOG_PERIPHID7 (TIVA_GPIOG_BASE + TIVA_GPIO_PERIPHID7_OFFSET)
# define TIVA_GPIOG_PERIPHID0 (TIVA_GPIOG_BASE + TIVA_GPIO_PERIPHID0_OFFSET)
# define TIVA_GPIOG_PERIPHID1 (TIVA_GPIOG_BASE + TIVA_GPIO_PERIPHID1_OFFSET)
# define TIVA_GPIOG_PERIPHID2 (TIVA_GPIOG_BASE + TIVA_GPIO_PERIPHID2_OFFSET)
# define TIVA_GPIOG_PERIPHID3 (TIVA_GPIOG_BASE + TIVA_GPIO_PERIPHID3_OFFSET)
# define TIVA_GPIOG_PCELLID0 (TIVA_GPIOG_BASE + TIVA_GPIO_PCELLID0_OFFSET)
# define TIVA_GPIOG_PCELLID1 (TIVA_GPIOG_BASE + TIVA_GPIO_PCELLID1_OFFSET)
# define TIVA_GPIOG_PCELLID2 (TIVA_GPIOG_BASE + TIVA_GPIO_PCELLID2_OFFSET)
# define TIVA_GPIOG_PCELLID3 (TIVA_GPIOG_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#elif LM_NPORTS > 7
#elif TIVA_NPORTS > 7
# define LM_GPIOH_DATA (LM_GPIOH_BASE + LM_GPIO_DATA_OFFSET)
# define LM_GPIOH_DIR (LM_GPIOH_BASE + LM_GPIO_DIR_OFFSET)
# define LM_GPIOH_IS (LM_GPIOH_BASE + LM_GPIO_IS_OFFSET)
# define LM_GPIOH_IBE (LM_GPIOH_BASE + LM_GPIO_IBE_OFFSET)
# define LM_GPIOH_IEV (LM_GPIOH_BASE + LM_GPIO_IEV_OFFSET)
# define LM_GPIOH_IM (LM_GPIOH_BASE + LM_GPIO_IM_OFFSET)
# define LM_GPIOH_RIS (LM_GPIOH_BASE + LM_GPIO_RIS_OFFSET)
# define LM_GPIOH_MIS (LM_GPIOH_BASE + LM_GPIO_MIS_OFFSET)
# define LM_GPIOH_ICR (LM_GPIOH_BASE + LM_GPIO_ICR_OFFSET)
# define LM_GPIOH_AFSEL (LM_GPIOH_BASE + LM_GPIO_AFSEL_OFFSET)
# define LM_GPIOH_DR2R (LM_GPIOH_BASE + LM_GPIO_DR2R_OFFSET)
# define LM_GPIOH_DR4R (LM_GPIOH_BASE + LM_GPIO_DR4R_OFFSET)
# define LM_GPIOH_DR8R (LM_GPIOH_BASE + LM_GPIO_DR8R_OFFSET)
# define LM_GPIOH_ODR (LM_GPIOH_BASE + LM_GPIO_ODR_OFFSET)
# define LM_GPIOH_PUR (LM_GPIOH_BASE + LM_GPIO_PUR_OFFSET)
# define LM_GPIOH_PDR (LM_GPIOH_BASE + LM_GPIO_PDR_OFFSET)
# define LM_GPIOH_SLR (LM_GPIOH_BASE + LM_GPIO_SLR_OFFSET)
# define LM_GPIOH_DEN (LM_GPIOH_BASE + LM_GPIO_DEN_OFFSET)
# define LM_GPIOH_LOCK (LM_GPIOH_BASE + LM_GPIO_LOCK_OFFSET)
# define LM_GPIOH_CR (LM_GPIOH_BASE + LM_GPIO_CR_OFFSET)
# define TIVA_GPIOH_DATA (TIVA_GPIOH_BASE + TIVA_GPIO_DATA_OFFSET)
# define TIVA_GPIOH_DIR (TIVA_GPIOH_BASE + TIVA_GPIO_DIR_OFFSET)
# define TIVA_GPIOH_IS (TIVA_GPIOH_BASE + TIVA_GPIO_IS_OFFSET)
# define TIVA_GPIOH_IBE (TIVA_GPIOH_BASE + TIVA_GPIO_IBE_OFFSET)
# define TIVA_GPIOH_IEV (TIVA_GPIOH_BASE + TIVA_GPIO_IEV_OFFSET)
# define TIVA_GPIOH_IM (TIVA_GPIOH_BASE + TIVA_GPIO_IM_OFFSET)
# define TIVA_GPIOH_RIS (TIVA_GPIOH_BASE + TIVA_GPIO_RIS_OFFSET)
# define TIVA_GPIOH_MIS (TIVA_GPIOH_BASE + TIVA_GPIO_MIS_OFFSET)
# define TIVA_GPIOH_ICR (TIVA_GPIOH_BASE + TIVA_GPIO_ICR_OFFSET)
# define TIVA_GPIOH_AFSEL (TIVA_GPIOH_BASE + TIVA_GPIO_AFSEL_OFFSET)
# define TIVA_GPIOH_DR2R (TIVA_GPIOH_BASE + TIVA_GPIO_DR2R_OFFSET)
# define TIVA_GPIOH_DR4R (TIVA_GPIOH_BASE + TIVA_GPIO_DR4R_OFFSET)
# define TIVA_GPIOH_DR8R (TIVA_GPIOH_BASE + TIVA_GPIO_DR8R_OFFSET)
# define TIVA_GPIOH_ODR (TIVA_GPIOH_BASE + TIVA_GPIO_ODR_OFFSET)
# define TIVA_GPIOH_PUR (TIVA_GPIOH_BASE + TIVA_GPIO_PUR_OFFSET)
# define TIVA_GPIOH_PDR (TIVA_GPIOH_BASE + TIVA_GPIO_PDR_OFFSET)
# define TIVA_GPIOH_SLR (TIVA_GPIOH_BASE + TIVA_GPIO_SLR_OFFSET)
# define TIVA_GPIOH_DEN (TIVA_GPIOH_BASE + TIVA_GPIO_DEN_OFFSET)
# define TIVA_GPIOH_LOCK (TIVA_GPIOH_BASE + TIVA_GPIO_LOCK_OFFSET)
# define TIVA_GPIOH_CR (TIVA_GPIOH_BASE + TIVA_GPIO_CR_OFFSET)
# ifdef LM4F
# define LM_GPIOH_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
# define LM_GPIOH_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
# define LM_GPIOH_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
# define LM_GPIOH_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
# define TIVA_GPIOH_AMSEL (TIVA_GPIOH_BASE + TIVA_GPIO_AMSEL_OFFSET)
# define TIVA_GPIOH_PCTL (TIVA_GPIOH_BASE + TIVA_GPIO_PCTL_OFFSET)
# define TIVA_GPIOH_ADCCTL (TIVA_GPIOH_BASE + TIVA_GPIO_ADCCTL_OFFSET)
# define TIVA_GPIOH_DMACTL (TIVA_GPIOH_BASE + TIVA_GPIO_DMACTL_OFFSET)
# endif
# define LM_GPIOH_PERIPHID4 (LM_GPIOH_BASE + LM_GPIO_PERIPHID4_OFFSET)
# define LM_GPIOH_PERIPHID5 (LM_GPIOH_BASE + LM_GPIO_PERIPHID5_OFFSET)
# define LM_GPIOH_PERIPHID6 (LM_GPIOH_BASE + LM_GPIO_PERIPHID6_OFFSET)
# define LM_GPIOH_PERIPHID7 (LM_GPIOH_BASE + LM_GPIO_PERIPHID7_OFFSET)
# define LM_GPIOH_PERIPHID0 (LM_GPIOH_BASE + LM_GPIO_PERIPHID0_OFFSET)
# define LM_GPIOH_PERIPHID1 (LM_GPIOH_BASE + LM_GPIO_PERIPHID1_OFFSET)
# define LM_GPIOH_PERIPHID2 (LM_GPIOH_BASE + LM_GPIO_PERIPHID2_OFFSET)
# define LM_GPIOH_PERIPHID3 (LM_GPIOH_BASE + LM_GPIO_PERIPHID3_OFFSET)
# define LM_GPIOH_PCELLID0 (LM_GPIOH_BASE + LM_GPIO_PCELLID0_OFFSET)
# define LM_GPIOH_PCELLID1 (LM_GPIOH_BASE + LM_GPIO_PCELLID1_OFFSET)
# define LM_GPIOH_PCELLID2 (LM_GPIOH_BASE + LM_GPIO_PCELLID2_OFFSET)
# define LM_GPIOH_PCELLID3 (LM_GPIOH_BASE + LM_GPIO_PCELLID3_OFFSET)
# define TIVA_GPIOH_PERIPHID4 (TIVA_GPIOH_BASE + TIVA_GPIO_PERIPHID4_OFFSET)
# define TIVA_GPIOH_PERIPHID5 (TIVA_GPIOH_BASE + TIVA_GPIO_PERIPHID5_OFFSET)
# define TIVA_GPIOH_PERIPHID6 (TIVA_GPIOH_BASE + TIVA_GPIO_PERIPHID6_OFFSET)
# define TIVA_GPIOH_PERIPHID7 (TIVA_GPIOH_BASE + TIVA_GPIO_PERIPHID7_OFFSET)
# define TIVA_GPIOH_PERIPHID0 (TIVA_GPIOH_BASE + TIVA_GPIO_PERIPHID0_OFFSET)
# define TIVA_GPIOH_PERIPHID1 (TIVA_GPIOH_BASE + TIVA_GPIO_PERIPHID1_OFFSET)
# define TIVA_GPIOH_PERIPHID2 (TIVA_GPIOH_BASE + TIVA_GPIO_PERIPHID2_OFFSET)
# define TIVA_GPIOH_PERIPHID3 (TIVA_GPIOH_BASE + TIVA_GPIO_PERIPHID3_OFFSET)
# define TIVA_GPIOH_PCELLID0 (TIVA_GPIOH_BASE + TIVA_GPIO_PCELLID0_OFFSET)
# define TIVA_GPIOH_PCELLID1 (TIVA_GPIOH_BASE + TIVA_GPIO_PCELLID1_OFFSET)
# define TIVA_GPIOH_PCELLID2 (TIVA_GPIOH_BASE + TIVA_GPIO_PCELLID2_OFFSET)
# define TIVA_GPIOH_PCELLID3 (TIVA_GPIOH_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#elif LM_NPORTS > 8
#elif TIVA_NPORTS > 8
# define LM_GPIOJ_DATA (LM_GPIOJ_BASE + LM_GPIO_DATA_OFFSET)
# define LM_GPIOJ_DIR (LM_GPIOJ_BASE + LM_GPIO_DIR_OFFSET)
# define LM_GPIOJ_IS (LM_GPIOJ_BASE + LM_GPIO_IS_OFFSET)
# define LM_GPIOJ_IBE (LM_GPIOJ_BASE + LM_GPIO_IBE_OFFSET)
# define LM_GPIOJ_IEV (LM_GPIOJ_BASE + LM_GPIO_IEV_OFFSET)
# define LM_GPIOJ_IM (LM_GPIOJ_BASE + LM_GPIO_IM_OFFSET)
# define LM_GPIOJ_RIS (LM_GPIOJ_BASE + LM_GPIO_RIS_OFFSET)
# define LM_GPIOJ_MIS (LM_GPIOJ_BASE + LM_GPIO_MIS_OFFSET)
# define LM_GPIOJ_ICR (LM_GPIOJ_BASE + LM_GPIO_ICR_OFFSET)
# define LM_GPIOJ_AFSEL (LM_GPIOJ_BASE + LM_GPIO_AFSEL_OFFSET)
# define LM_GPIOJ_DR2R (LM_GPIOJ_BASE + LM_GPIO_DR2R_OFFSET)
# define LM_GPIOJ_DR4R (LM_GPIOJ_BASE + LM_GPIO_DR4R_OFFSET)
# define LM_GPIOJ_DR8R (LM_GPIOJ_BASE + LM_GPIO_DR8R_OFFSET)
# define LM_GPIOJ_ODR (LM_GPIOJ_BASE + LM_GPIO_ODR_OFFSET)
# define LM_GPIOJ_PUR (LM_GPIOJ_BASE + LM_GPIO_PUR_OFFSET)
# define LM_GPIOJ_PDR (LM_GPIOJ_BASE + LM_GPIO_PDR_OFFSET)
# define LM_GPIOJ_SLR (LM_GPIOJ_BASE + LM_GPIO_SLR_OFFSET)
# define LM_GPIOJ_DEN (LM_GPIOJ_BASE + LM_GPIO_DEN_OFFSET)
# define LM_GPIOJ_LOCK (LM_GPIOJ_BASE + LM_GPIO_LOCK_OFFSET)
# define LM_GPIOJ_CR (LM_GPIOJ_BASE + LM_GPIO_CR_OFFSET)
# define TIVA_GPIOJ_DATA (TIVA_GPIOJ_BASE + TIVA_GPIO_DATA_OFFSET)
# define TIVA_GPIOJ_DIR (TIVA_GPIOJ_BASE + TIVA_GPIO_DIR_OFFSET)
# define TIVA_GPIOJ_IS (TIVA_GPIOJ_BASE + TIVA_GPIO_IS_OFFSET)
# define TIVA_GPIOJ_IBE (TIVA_GPIOJ_BASE + TIVA_GPIO_IBE_OFFSET)
# define TIVA_GPIOJ_IEV (TIVA_GPIOJ_BASE + TIVA_GPIO_IEV_OFFSET)
# define TIVA_GPIOJ_IM (TIVA_GPIOJ_BASE + TIVA_GPIO_IM_OFFSET)
# define TIVA_GPIOJ_RIS (TIVA_GPIOJ_BASE + TIVA_GPIO_RIS_OFFSET)
# define TIVA_GPIOJ_MIS (TIVA_GPIOJ_BASE + TIVA_GPIO_MIS_OFFSET)
# define TIVA_GPIOJ_ICR (TIVA_GPIOJ_BASE + TIVA_GPIO_ICR_OFFSET)
# define TIVA_GPIOJ_AFSEL (TIVA_GPIOJ_BASE + TIVA_GPIO_AFSEL_OFFSET)
# define TIVA_GPIOJ_DR2R (TIVA_GPIOJ_BASE + TIVA_GPIO_DR2R_OFFSET)
# define TIVA_GPIOJ_DR4R (TIVA_GPIOJ_BASE + TIVA_GPIO_DR4R_OFFSET)
# define TIVA_GPIOJ_DR8R (TIVA_GPIOJ_BASE + TIVA_GPIO_DR8R_OFFSET)
# define TIVA_GPIOJ_ODR (TIVA_GPIOJ_BASE + TIVA_GPIO_ODR_OFFSET)
# define TIVA_GPIOJ_PUR (TIVA_GPIOJ_BASE + TIVA_GPIO_PUR_OFFSET)
# define TIVA_GPIOJ_PDR (TIVA_GPIOJ_BASE + TIVA_GPIO_PDR_OFFSET)
# define TIVA_GPIOJ_SLR (TIVA_GPIOJ_BASE + TIVA_GPIO_SLR_OFFSET)
# define TIVA_GPIOJ_DEN (TIVA_GPIOJ_BASE + TIVA_GPIO_DEN_OFFSET)
# define TIVA_GPIOJ_LOCK (TIVA_GPIOJ_BASE + TIVA_GPIO_LOCK_OFFSET)
# define TIVA_GPIOJ_CR (TIVA_GPIOJ_BASE + TIVA_GPIO_CR_OFFSET)
# ifdef LM4F
# define LM_GPIOJ_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
# define LM_GPIOJ_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
# define LM_GPIOJ_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
# define LM_GPIOJ_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
# define TIVA_GPIOJ_AMSEL (TIVA_GPIOJ_BASE + TIVA_GPIO_AMSEL_OFFSET)
# define TIVA_GPIOJ_PCTL (TIVA_GPIOJ_BASE + TIVA_GPIO_PCTL_OFFSET)
# define TIVA_GPIOJ_ADCCTL (TIVA_GPIOJ_BASE + TIVA_GPIO_ADCCTL_OFFSET)
# define TIVA_GPIOJ_DMACTL (TIVA_GPIOJ_BASE + TIVA_GPIO_DMACTL_OFFSET)
# endif
# define LM_GPIOJ_PERIPHID4 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID4_OFFSET)
# define LM_GPIOJ_PERIPHID5 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID5_OFFSET)
# define LM_GPIOJ_PERIPHID6 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID6_OFFSET)
# define LM_GPIOJ_PERIPHID7 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID7_OFFSET)
# define LM_GPIOJ_PERIPHID0 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID0_OFFSET)
# define LM_GPIOJ_PERIPHID1 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID1_OFFSET)
# define LM_GPIOJ_PERIPHID2 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID2_OFFSET)
# define LM_GPIOJ_PERIPHID3 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID3_OFFSET)
# define LM_GPIOJ_PCELLID0 (LM_GPIOJ_BASE + LM_GPIO_PCELLID0_OFFSET)
# define LM_GPIOJ_PCELLID1 (LM_GPIOJ_BASE + LM_GPIO_PCELLID1_OFFSET)
# define LM_GPIOJ_PCELLID2 (LM_GPIOJ_BASE + LM_GPIO_PCELLID2_OFFSET)
# define LM_GPIOJ_PCELLID3 (LM_GPIOJ_BASE + LM_GPIO_PCELLID3_OFFSET)
# define TIVA_GPIOJ_PERIPHID4 (TIVA_GPIOJ_BASE + TIVA_GPIO_PERIPHID4_OFFSET)
# define TIVA_GPIOJ_PERIPHID5 (TIVA_GPIOJ_BASE + TIVA_GPIO_PERIPHID5_OFFSET)
# define TIVA_GPIOJ_PERIPHID6 (TIVA_GPIOJ_BASE + TIVA_GPIO_PERIPHID6_OFFSET)
# define TIVA_GPIOJ_PERIPHID7 (TIVA_GPIOJ_BASE + TIVA_GPIO_PERIPHID7_OFFSET)
# define TIVA_GPIOJ_PERIPHID0 (TIVA_GPIOJ_BASE + TIVA_GPIO_PERIPHID0_OFFSET)
# define TIVA_GPIOJ_PERIPHID1 (TIVA_GPIOJ_BASE + TIVA_GPIO_PERIPHID1_OFFSET)
# define TIVA_GPIOJ_PERIPHID2 (TIVA_GPIOJ_BASE + TIVA_GPIO_PERIPHID2_OFFSET)
# define TIVA_GPIOJ_PERIPHID3 (TIVA_GPIOJ_BASE + TIVA_GPIO_PERIPHID3_OFFSET)
# define TIVA_GPIOJ_PCELLID0 (TIVA_GPIOJ_BASE + TIVA_GPIO_PCELLID0_OFFSET)
# define TIVA_GPIOJ_PCELLID1 (TIVA_GPIOJ_BASE + TIVA_GPIO_PCELLID1_OFFSET)
# define TIVA_GPIOJ_PCELLID2 (TIVA_GPIOJ_BASE + TIVA_GPIO_PCELLID2_OFFSET)
# define TIVA_GPIOJ_PCELLID3 (TIVA_GPIOJ_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#endif /* LM_NPORTS */
#endif /* TIVA_NPORTS */
/* GPIO Register Bitfield Definitions ***********************************************/

136
arch/arm/src/tiva/chip/tiva_i2c.h
View file

@ -50,99 +50,99 @@
/* I2C Master */
#define LM_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */
#define LM_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */
#define LM_I2CM_DR_OFFSET 0x008 /* I2C Master Data */
#define LM_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
#define LM_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
#define LM_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
#define LM_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
#define LM_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
#define LM_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */
#define TIVA_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */
#define TIVA_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */
#define TIVA_I2CM_DR_OFFSET 0x008 /* I2C Master Data */
#define TIVA_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
#define TIVA_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
#define TIVA_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
#define TIVA_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
#define TIVA_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
#define TIVA_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */
/* I2C Slave */
#define LM_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
#define LM_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
#define LM_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */
#define LM_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
#define LM_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
#define LM_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
#define LM_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
#define TIVA_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
#define TIVA_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
#define TIVA_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */
#define TIVA_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
#define TIVA_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
#define TIVA_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
#define TIVA_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
/* I2C Register Addresses ***********************************************************/
#if LM_NI2C > 0
#if TIVA_NI2C > 0
/* I2C Master */
#define LM_I2CM_BASE(n) (LM_I2CM0_BASE + (n)*0x1000)
#define LM_I2CM_SA(n) (LM_I2CM_BASE(n) + LM_I2CM_SA_OFFSET)
#define LM_I2CM_CS(n) (LM_I2CM_BASE(n) + LM_I2CM_CS_OFFSET)
#define LM_I2CM_DR(n) (LM_I2CM_BASE(n) + LM_I2CM_DR_OFFSET)
#define LM_I2CM_TPR(n) (LM_I2CM_BASE(n) + LM_I2CM_TPR_OFFSET)
#define LM_I2CM_IMR(n) (LM_I2CM_BASE(n) + LM_I2CM_IMR_OFFSET)
#define LM_I2CM_RIS(n) (LM_I2CM_BASE(n) + LM_I2CM_RIS_OFFSET)
#define LM_I2CM_MIS(n) (LM_I2CM_BASE(n) + LM_I2CM_MIS_OFFSET)
#define LM_I2CM_ICR(n) (LM_I2CM_BASE(n) + LM_I2CM_ICR_OFFSET)
#define LM_I2CM_CR(n) (LM_I2CM_BASE(n) + LM_I2CM_CR_OFFSET)
#define TIVA_I2CM_BASE(n) (TIVA_I2CM0_BASE + (n)*0x1000)
#define TIVA_I2CM_SA(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM_CS(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM_DR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM_TPR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM_IMR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM_RIS(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM_MIS(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM_ICR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM_CR(n) (TIVA_I2CM_BASE(n) + TIVA_I2CM_CR_OFFSET)
/* I2C Slave */
#define LM_I2CS_BASE(n) (LM_I2CS0_BASE + (n)*0x1000)
#define LM_I2CS_OAR(n) (LM_I2CS_BASE(n) + LM_I2CS_OAR_OFFSET)
#define LM_I2CS_CSR(n) (LM_I2CS_BASE(n) + LM_I2CS_CSR_OFFSET)
#define LM_I2CS_DR(n) (LM_I2CS_BASE(n) + LM_I2CS_DR_OFFSET)
#define LM_I2CS_IMR(n) (LM_I2CS_BASE(n) + LM_I2CS_IMR_OFFSET)
#define LM_I2CS_RIS(n) (LM_I2CS_BASE(n) + LM_I2CS_RIS_OFFSET)
#define LM_I2CS_MIS(n) (LM_I2CS_BASE(n) + LM_I2CS_MIS_OFFSET)
#define LM_I2CS_ICR(n) (LM_I2CS_BASE(n) + LM_I2CS_ICR_OFFSET)
#define TIVA_I2CS_BASE(n) (TIVA_I2CS0_BASE + (n)*0x1000)
#define TIVA_I2CS_OAR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS_CSR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS_DR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS_IMR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS_RIS(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS_MIS(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS_ICR(n) (TIVA_I2CS_BASE(n) + TIVA_I2CS_ICR_OFFSET)
/* I2C0 Master */
#define LM_I2CM0_SA (LM_I2CM0_BASE + LM_I2CM_SA_OFFSET)
#define LM_I2CM0_CS (LM_I2CM0_BASE + LM_I2CM_CS_OFFSET)
#define LM_I2CM0_DR (LM_I2CM0_BASE + LM_I2CM_DR_OFFSET)
#define LM_I2CM0_TPR (LM_I2CM0_BASE + LM_I2CM_TPR_OFFSET)
#define LM_I2CM0_IMR (LM_I2CM0_BASE + LM_I2CM_IMR_OFFSET)
#define LM_I2CM0_RIS (LM_I2CM0_BASE + LM_I2CM_RIS_OFFSET)
#define LM_I2CM0_MIS (LM_I2CM0_BASE + LM_I2CM_MIS_OFFSET)
#define LM_I2CM0_ICR (LM_I2CM0_BASE + LM_I2CM_ICR_OFFSET)
#define LM_I2CM0_CR (LM_I2CM0_BASE + LM_I2CM_CR_OFFSET)
#define TIVA_I2CM0_SA (TIVA_I2CM0_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM0_CS (TIVA_I2CM0_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM0_DR (TIVA_I2CM0_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM0_TPR (TIVA_I2CM0_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM0_IMR (TIVA_I2CM0_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM0_RIS (TIVA_I2CM0_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM0_MIS (TIVA_I2CM0_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM0_ICR (TIVA_I2CM0_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM0_CR (TIVA_I2CM0_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C0 Slave */
#define LM_I2CS0_OAR (LM_I2CS0_BASE + LM_I2CS_OAR_OFFSET)
#define LM_I2CS0_CSR (LM_I2CS0_BASE + LM_I2CS_CSR_OFFSET)
#define LM_I2CS0_DR (LM_I2CS0_BASE + LM_I2CS_DR_OFFSET)
#define LM_I2CS0_IMR (LM_I2CS0_BASE + LM_I2CS_IMR_OFFSET)
#define LM_I2CS0_RIS (LM_I2CS0_BASE + LM_I2CS_RIS_OFFSET)
#define LM_I2CS0_MIS (LM_I2CS0_BASE + LM_I2CS_MIS_OFFSET)
#define LM_I2CS0_ICR (LM_I2CS0_BASE + LM_I2CS_ICR_OFFSET)
#define TIVA_I2CS0_OAR (TIVA_I2CS0_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS0_CSR (TIVA_I2CS0_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS0_DR (TIVA_I2CS0_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS0_IMR (TIVA_I2CS0_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS0_RIS (TIVA_I2CS0_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS0_MIS (TIVA_I2CS0_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS0_ICR (TIVA_I2CS0_BASE + TIVA_I2CS_ICR_OFFSET)
#if LM_NI2C > 1
#if TIVA_NI2C > 1
/* I2C1 Master */
#define LM_I2CM1_SA (LM_I2CM1_BASE + LM_I2CM_SA_OFFSET)
#define LM_I2CM1_CS (LM_I2CM1_BASE + LM_I2CM_CS_OFFSET)
#define LM_I2CM1_DR (LM_I2CM1_BASE + LM_I2CM_DR_OFFSET)
#define LM_I2CM1_TPR (LM_I2CM1_BASE + LM_I2CM_TPR_OFFSET)
#define LM_I2CM1_IMR (LM_I2CM1_BASE + LM_I2CM_IMR_OFFSET)
#define LM_I2CM1_RIS (LM_I2CM1_BASE + LM_I2CM_RIS_OFFSET)
#define LM_I2CM1_MIS (LM_I2CM1_BASE + LM_I2CM_MIS_OFFSET)
#define LM_I2CM1_ICR (LM_I2CM1_BASE + LM_I2CM_ICR_OFFSET)
#define LM_I2CM1_CR (LM_I2CM1_BASE + LM_I2CM_CR_OFFSET)
#define TIVA_I2CM1_SA (TIVA_I2CM1_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM1_CS (TIVA_I2CM1_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM1_DR (TIVA_I2CM1_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM1_TPR (TIVA_I2CM1_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM1_IMR (TIVA_I2CM1_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM1_RIS (TIVA_I2CM1_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM1_MIS (TIVA_I2CM1_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM1_ICR (TIVA_I2CM1_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM1_CR (TIVA_I2CM1_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C1 Slave */
#define LM_I2CS1_OAR (LM_I2CS1_BASE + LM_I2CS_OAR_OFFSET)
#define LM_I2CS1_CSR (LM_I2CS1_BASE + LM_I2CS_CSR_OFFSET)
#define LM_I2CS1_DR (LM_I2CS1_BASE + LM_I2CS_DR_OFFSET)
#define LM_I2CS1_IMR (LM_I2CS1_BASE + LM_I2CS_IMR_OFFSET)
#define LM_I2CS1_RIS (LM_I2CS1_BASE + LM_I2CS_RIS_OFFSET)
#define LM_I2CS1_MIS (LM_I2CS1_BASE + LM_I2CS_MIS_OFFSET)
#define LM_I2CS1_ICR (LM_I2CS1_BASE + LM_I2CS_ICR_OFFSET)
#define TIVA_I2CS1_OAR (TIVA_I2CS1_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS1_CSR (TIVA_I2CS1_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS1_DR (TIVA_I2CS1_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS1_IMR (TIVA_I2CS1_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS1_RIS (TIVA_I2CS1_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS1_MIS (TIVA_I2CS1_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS1_ICR (TIVA_I2CS1_BASE + TIVA_I2CS_ICR_OFFSET)
#endif
#endif

256
arch/arm/src/tiva/chip/tiva_ssi.h
View file

@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <sys/types.h>
#if LM_NSSI > 0
#if TIVA_NSSI > 0
/************************************************************************************
* Definitions
@ -51,173 +51,173 @@
/* SSI register offsets *************************************************************/
#define LM_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */
#define LM_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */
#define LM_SSI_DR_OFFSET 0x008 /* SSI Data */
#define LM_SSI_SR_OFFSET 0x00c /* SSI Status */
#define LM_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */
#define LM_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */
#define LM_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */
#define LM_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */
#define LM_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */
#define LM_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
#define LM_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
#define LM_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
#define LM_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
#define LM_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
#define LM_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
#define LM_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
#define LM_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
#define LM_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */
#define LM_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */
#define LM_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */
#define LM_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */
#define TIVA_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */
#define TIVA_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */
#define TIVA_SSI_DR_OFFSET 0x008 /* SSI Data */
#define TIVA_SSI_SR_OFFSET 0x00c /* SSI Status */
#define TIVA_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */
#define TIVA_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */
#define TIVA_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */
#define TIVA_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */
#define TIVA_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */
#define TIVA_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
#define TIVA_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
#define TIVA_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
#define TIVA_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
#define TIVA_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
#define TIVA_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
#define TIVA_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
#define TIVA_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
#define TIVA_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */
#define TIVA_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */
#define TIVA_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */
#define TIVA_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */
/* SSI register addresses ***********************************************************/
#define LM_SSI0_CR0 (LM_SSI0_BASE + LM_SSI_CR0_OFFSET)
#define LM_SSI0_CR1 (LM_SSI0_BASE + LM_SSI_CR1_OFFSET)
#define LM_SSI0_DR (LM_SSI0_BASE + LM_SSI_DR_OFFSET)
#define LM_SSI0_SR (LM_SSI0_BASE + LM_SSI_SR_OFFSET)
#define LM_SSI0_CPSR (LM_SSI0_BASE + LM_SSI_CPSR_OFFSET)
#define LM_SSI0_IM (LM_SSI0_BASE + LM_SSI_IM_OFFSET)
#define LM_SSI0_RIS (LM_SSI0_BASE + LM_SSI_RIS_OFFSET)
#define LM_SSI0_MIS (LM_SSI0_BASE + LM_SSI_MIS_OFFSET)
#define LM_SSI0_ICR (LM_SSI0_BASE + LM_SSI_ICR_OFFSET)
#define LM_SSI0_PERIPHID4 (LM_SSI0_BASE + LM_SSI_PERIPHID4_OFFSET)
#define LM_SSI0_PERIPHID5 (LM_SSI0_BASE + LM_SSI_PERIPHID5_OFFSET)
#define LM_SSI0_PERIPHID6 (LM_SSI0_BASE + LM_SSI_PERIPHID6_OFFSET)
#define LM_SSI0_PERIPHID7 (LM_SSI0_BASE + LM_SSI_PERIPHID7_OFFSET)
#define LM_SSI0_PERIPHID0 (LM_SSI0_BASE + LM_SSI_PERIPHID0_OFFSET)
#define LM_SSI0_PERIPHID1 (LM_SSI0_BASE + LM_SSI_PERIPHID1_OFFSET)
#define LM_SSI0_PERIPHID2 (LM_SSI0_BASE + LM_SSI_PERIPHID2_OFFSET)
#define LM_SSI0_PERIPHID3 (LM_SSI0_BASE + LM_SSI_PERIPHID3_OFFSET)
#define LM_SSI0_PCELLID0 (LM_SSI0_BASE + LM_SSI_PCELLID0_OFFSET)
#define LM_SSI0_PCELLID1 (LM_SSI0_BASE + LM_SSI_PCELLID1_OFFSET)
#define LM_SSI0_PCELLID2 (LM_SSI0_BASE + LM_SSI_PCELLID2_OFFSET)
#define LM_SSI0_PCELLID3 (LM_SSI0_BASE + LM_SSI_PCELLID3_OFFSET)
#define TIVA_SSI0_CR0 (TIVA_SSI0_BASE + TIVA_SSI_CR0_OFFSET)
#define TIVA_SSI0_CR1 (TIVA_SSI0_BASE + TIVA_SSI_CR1_OFFSET)
#define TIVA_SSI0_DR (TIVA_SSI0_BASE + TIVA_SSI_DR_OFFSET)
#define TIVA_SSI0_SR (TIVA_SSI0_BASE + TIVA_SSI_SR_OFFSET)
#define TIVA_SSI0_CPSR (TIVA_SSI0_BASE + TIVA_SSI_CPSR_OFFSET)
#define TIVA_SSI0_IM (TIVA_SSI0_BASE + TIVA_SSI_IM_OFFSET)
#define TIVA_SSI0_RIS (TIVA_SSI0_BASE + TIVA_SSI_RIS_OFFSET)
#define TIVA_SSI0_MIS (TIVA_SSI0_BASE + TIVA_SSI_MIS_OFFSET)
#define TIVA_SSI0_ICR (TIVA_SSI0_BASE + TIVA_SSI_ICR_OFFSET)
#define TIVA_SSI0_PERIPHID4 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID4_OFFSET)
#define TIVA_SSI0_PERIPHID5 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID5_OFFSET)
#define TIVA_SSI0_PERIPHID6 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID6_OFFSET)
#define TIVA_SSI0_PERIPHID7 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID7_OFFSET)
#define TIVA_SSI0_PERIPHID0 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID0_OFFSET)
#define TIVA_SSI0_PERIPHID1 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID1_OFFSET)
#define TIVA_SSI0_PERIPHID2 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID2_OFFSET)
#define TIVA_SSI0_PERIPHID3 (TIVA_SSI0_BASE + TIVA_SSI_PERIPHID3_OFFSET)
#define TIVA_SSI0_PCELLID0 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID0_OFFSET)
#define TIVA_SSI0_PCELLID1 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID1_OFFSET)
#define TIVA_SSI0_PCELLID2 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID2_OFFSET)
#define TIVA_SSI0_PCELLID3 (TIVA_SSI0_BASE + TIVA_SSI_PCELLID3_OFFSET)
#if LM_NSSI > 1
#define LM_SSI1_CR0 (LM_SSI1_BASE + LM_SSI_CR0_OFFSET)
#define LM_SSI1_CR1 (LM_SSI1_BASE + LM_SSI_CR1_OFFSET)
#define LM_SSI1_DR (LM_SSI1_BASE + LM_SSI_DR_OFFSET)
#define LM_SSI1_SR (LM_SSI1_BASE + LM_SSI_SR_OFFSET)
#define LM_SSI1_CPSR (LM_SSI1_BASE + LM_SSI_CPSR_OFFSET)
#define LM_SSI1_IM (LM_SSI1_BASE + LM_SSI_IM_OFFSET)
#define LM_SSI1_RIS (LM_SSI1_BASE + LM_SSI_RIS_OFFSET)
#define LM_SSI1_MIS (LM_SSI1_BASE + LM_SSI_MIS_OFFSET)
#define LM_SSI1_ICR (LM_SSI1_BASE + LM_SSI_ICR_OFFSET)
#define LM_SSI1_PERIPHID4 (LM_SSI1_BASE + LM_SSI_PERIPHID4_OFFSET)
#define LM_SSI1_PERIPHID5 (LM_SSI1_BASE + LM_SSI_PERIPHID5_OFFSET)
#define LM_SSI1_PERIPHID6 (LM_SSI1_BASE + LM_SSI_PERIPHID6_OFFSET)
#define LM_SSI1_PERIPHID7 (LM_SSI1_BASE + LM_SSI_PERIPHID7_OFFSET)
#define LM_SSI1_PERIPHID0 (LM_SSI1_BASE + LM_SSI_PERIPHID0_OFFSET)
#define LM_SSI1_PERIPHID1 (LM_SSI1_BASE + LM_SSI_PERIPHID1_OFFSET)
#define LM_SSI1_PERIPHID2 (LM_SSI1_BASE + LM_SSI_PERIPHID2_OFFSET)
#define LM_SSI1_PERIPHID3 (LM_SSI1_BASE + LM_SSI_PERIPHID3_OFFSET)
#define LM_SSI1_PCELLID0 (LM_SSI1_BASE + LM_SSI_PCELLID0_OFFSET)
#define LM_SSI1_PCELLID1 (LM_SSI1_BASE + LM_SSI_PCELLID1_OFFSET)
#define LM_SSI1_PCELLID2 (LM_SSI1_BASE + LM_SSI_PCELLID2_OFFSET)
#define LM_SSI1_PCELLID3 (LM_SSI1_BASE + LM_SSI_PCELLID3_OFFSET)
#if TIVA_NSSI > 1
#define TIVA_SSI1_CR0 (TIVA_SSI1_BASE + TIVA_SSI_CR0_OFFSET)
#define TIVA_SSI1_CR1 (TIVA_SSI1_BASE + TIVA_SSI_CR1_OFFSET)
#define TIVA_SSI1_DR (TIVA_SSI1_BASE + TIVA_SSI_DR_OFFSET)
#define TIVA_SSI1_SR (TIVA_SSI1_BASE + TIVA_SSI_SR_OFFSET)
#define TIVA_SSI1_CPSR (TIVA_SSI1_BASE + TIVA_SSI_CPSR_OFFSET)
#define TIVA_SSI1_IM (TIVA_SSI1_BASE + TIVA_SSI_IM_OFFSET)
#define TIVA_SSI1_RIS (TIVA_SSI1_BASE + TIVA_SSI_RIS_OFFSET)
#define TIVA_SSI1_MIS (TIVA_SSI1_BASE + TIVA_SSI_MIS_OFFSET)
#define TIVA_SSI1_ICR (TIVA_SSI1_BASE + TIVA_SSI_ICR_OFFSET)
#define TIVA_SSI1_PERIPHID4 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID4_OFFSET)
#define TIVA_SSI1_PERIPHID5 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID5_OFFSET)
#define TIVA_SSI1_PERIPHID6 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID6_OFFSET)
#define TIVA_SSI1_PERIPHID7 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID7_OFFSET)
#define TIVA_SSI1_PERIPHID0 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID0_OFFSET)
#define TIVA_SSI1_PERIPHID1 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID1_OFFSET)
#define TIVA_SSI1_PERIPHID2 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID2_OFFSET)
#define TIVA_SSI1_PERIPHID3 (TIVA_SSI1_BASE + TIVA_SSI_PERIPHID3_OFFSET)
#define TIVA_SSI1_PCELLID0 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID0_OFFSET)
#define TIVA_SSI1_PCELLID1 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID1_OFFSET)
#define TIVA_SSI1_PCELLID2 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID2_OFFSET)
#define TIVA_SSI1_PCELLID3 (TIVA_SSI1_BASE + TIVA_SSI_PCELLID3_OFFSET)
#define LM_SSI_BASE(n) (LM_SSI0_BASE + (n)*0x01000)
#define TIVA_SSI_BASE(n) (TIVA_SSI0_BASE + (n)*0x01000)
#define LM_SSI_CR0(n) (LM_SSI_BASE(n) + LM_SSI_CR0_OFFSET)
#define LM_SSI_CR1(n) (LM_SSI_BASE(n) + LM_SSI_CR1_OFFSET)
#define LM_SSI_DR(n) (LM_SSI_BASE(n) + LM_SSI_DR_OFFSET)
#define LM_SSI_SR(n) (LM_SSI_BASE(n) + LM_SSI_SR_OFFSET)
#define LM_SSI_CPSR(n) (LM_SSI_BASE(n) + LM_SSI_CPSR_OFFSET)
#define LM_SSI_IM(n) (LM_SSI_BASE(n) + LM_SSI_IM_OFFSET)
#define LM_SSI_RIS(n) (LM_SSI_BASE(n) + LM_SSI_RIS_OFFSET)
#define LM_SSI_MIS(n) (LM_SSI_BASE(n) + LM_SSI_MIS_OFFSET)
#define LM_SSI_ICR(n) (LM_SSI_BASE(n) + LM_SSI_ICR_OFFSET)
#define LM_SSI_PERIPHID4(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID4_OFFSET)
#define LM_SSI_PERIPHID5(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID5_OFFSET)
#define LM_SSI_PERIPHID6(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID6_OFFSET)
#define LM_SSI_PERIPHID7(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID7_OFFSET)
#define LM_SSI_PERIPHID0(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID0_OFFSET)
#define LM_SSI_PERIPHID1(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID1_OFFSET)
#define LM_SSI_PERIPHID2(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID2_OFFSET)
#define LM_SSI_PERIPHID3(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID3_OFFSET)
#define LM_SSI_PCELLID0(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID0_OFFSET)
#define LM_SSI_PCELLID1(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID1_OFFSET)
#define LM_SSI_PCELLID2(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID2_OFFSET)
#define LM_SSI_PCELLID3(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID3_OFFSET)
#endif /* LM_NSSI > 1 */
#define TIVA_SSI_CR0(n) (TIVA_SSI_BASE(n) + TIVA_SSI_CR0_OFFSET)
#define TIVA_SSI_CR1(n) (TIVA_SSI_BASE(n) + TIVA_SSI_CR1_OFFSET)
#define TIVA_SSI_DR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_DR_OFFSET)
#define TIVA_SSI_SR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_SR_OFFSET)
#define TIVA_SSI_CPSR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_CPSR_OFFSET)
#define TIVA_SSI_IM(n) (TIVA_SSI_BASE(n) + TIVA_SSI_IM_OFFSET)
#define TIVA_SSI_RIS(n) (TIVA_SSI_BASE(n) + TIVA_SSI_RIS_OFFSET)
#define TIVA_SSI_MIS(n) (TIVA_SSI_BASE(n) + TIVA_SSI_MIS_OFFSET)
#define TIVA_SSI_ICR(n) (TIVA_SSI_BASE(n) + TIVA_SSI_ICR_OFFSET)
#define TIVA_SSI_PERIPHID4(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID4_OFFSET)
#define TIVA_SSI_PERIPHID5(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID5_OFFSET)
#define TIVA_SSI_PERIPHID6(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID6_OFFSET)
#define TIVA_SSI_PERIPHID7(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID7_OFFSET)
#define TIVA_SSI_PERIPHID0(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID0_OFFSET)
#define TIVA_SSI_PERIPHID1(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID1_OFFSET)
#define TIVA_SSI_PERIPHID2(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID2_OFFSET)
#define TIVA_SSI_PERIPHID3(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PERIPHID3_OFFSET)
#define TIVA_SSI_PCELLID0(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID0_OFFSET)
#define TIVA_SSI_PCELLID1(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID1_OFFSET)
#define TIVA_SSI_PCELLID2(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID2_OFFSET)
#define TIVA_SSI_PCELLID3(n) (TIVA_SSI_BASE(n) + TIVA_SSI_PCELLID3_OFFSET)
#endif /* TIVA_NSSI > 1 */
/* SSI register bit defitiions ******************************************************/
/* SSI Control 0 (SSICR0), offset 0x000 */
#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */
#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT)
#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */
#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT)
#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */
#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */
#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */
#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */
#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */
#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */
#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT)
#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */
#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT)
#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */
#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT)
#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */
#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */
#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */
#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */
#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */
#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */
#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT)
/* SSI Control 1 (SSICR1), offset 0x004 */
#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */
#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */
#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */
#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */
#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */
#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */
#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */
#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */
/* SSI Data (SSIDR), offset 0x008 */
#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */
#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */
/* SSI Status (SSISR), offset 0x00c */
#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */
#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */
#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */
#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */
#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */
#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */
#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */
#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */
#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */
#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */
/* SSI Clock Prescale (SSICPSR), offset 0x010 */
#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */
#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */
/* SSI Interrupt Mask (SSIIM), offset 0x014 */
#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */
#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */
#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */
#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */
#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */
#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */
#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */
#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */
/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */
#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */
#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */
#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */
#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */
#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */
#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */
#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */
/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */
#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */
#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */
#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */
#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */
#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */
#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */
#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */
/* SSI Interrupt Clear (SSIICR), offset 0x020 */
#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */
#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */
#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */
#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */
/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */
#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */
/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */
#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */
/************************************************************************************
* Public Types
@ -231,5 +231,5 @@
* Public Function Prototypes
************************************************************************************/
#endif /* LM_NSSI > 0 */
#endif /* TIVA_NSSI > 0 */
#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TIVA_SSI_H */

36
arch/arm/src/tiva/chip/tiva_timer.h
View file

@ -46,29 +46,29 @@
/* Timer register offsets ***********************************************************/
#define LM_TIMER_GPTMCFG_OFFSET 0x000
#define LM_TIMER_GPTMTAMR_OFFSET 0x004
#define LM_TIMER_GPTMCTL_OFFSET 0x00c
#define LM_TIMER_GPTMIMR_OFFSET 0x018
#define LM_TIMER_GPTMRIS_OFFSET 0x01c
#define LM_TIMER_GPTMICR_OFFSET 0x024
#define LM_TIMER_GPTMTAILR_OFFSET 0x028
#define LM_TIMER_GPTMTAR_OFFSET 0x048
#define TIVA_TIMER_GPTMCFG_OFFSET 0x000
#define TIVA_TIMER_GPTMTAMR_OFFSET 0x004
#define TIVA_TIMER_GPTMCTL_OFFSET 0x00c
#define TIVA_TIMER_GPTMIMR_OFFSET 0x018
#define TIVA_TIMER_GPTMRIS_OFFSET 0x01c
#define TIVA_TIMER_GPTMICR_OFFSET 0x024
#define TIVA_TIMER_GPTMTAILR_OFFSET 0x028
#define TIVA_TIMER_GPTMTAR_OFFSET 0x048
/* SSI register addresses ***********************************************************/
#define LM_TIMER_BASE(n) (LM_TIMER0_BASE + (n)*0x01000)
#define TIVA_TIMER_BASE(n) (TIVA_TIMER0_BASE + (n)*0x01000)
#define LM_TIMER_GPTMCFG(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCFG_OFFSET)
#define LM_TIMER_GPTMTAMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAMR_OFFSET)
#define LM_TIMER_GPTMCTL(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCTL_OFFSET)
#define LM_TIMER_GPTMIMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMIMR_OFFSET)
#define LM_TIMER_GPTMRIS(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMRIS_OFFSET)
#define LM_TIMER_GPTMICR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMICR_OFFSET)
#define LM_TIMER_GPTMTAILR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAILR_OFFSET)
#define LM_TIMER_GPTMTAR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAR_OFFSET)
#define TIVA_TIMER_GPTMCFG(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMCFG_OFFSET)
#define TIVA_TIMER_GPTMTAMR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMTAMR_OFFSET)
#define TIVA_TIMER_GPTMCTL(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMCTL_OFFSET)
#define TIVA_TIMER_GPTMIMR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMIMR_OFFSET)
#define TIVA_TIMER_GPTMRIS(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMRIS_OFFSET)
#define TIVA_TIMER_GPTMICR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMICR_OFFSET)
#define TIVA_TIMER_GPTMTAILR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMTAILR_OFFSET)
#define TIVA_TIMER_GPTMTAR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMTAR_OFFSET)
/* SSI register bit defitiions ******************************************************/
/* SSI register bit definitions *****************************************************/
/* GPTM Configuration (GPTMCFG), offset 0x000 */

210
arch/arm/src/tiva/chip/tiva_uart.h
View file

@ -48,117 +48,117 @@
/* UART register offsets ************************************************************/
#define LM_UART_DR_OFFSET 0x000 /* UART Data */
#define LM_UART_RSR_OFFSET 0x004 /* UART Receive Status */
#define LM_UART_ECR_OFFSET 0x004 /* UART Error Clear */
#define LM_UART_FR_OFFSET 0x018 /* UART Flag */
#define LM_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */
#define LM_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/
#define LM_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */
#define LM_UART_LCRH_OFFSET 0x02c /* UART Line Control */
#define LM_UART_CTL_OFFSET 0x030 /* UART Control */
#define LM_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */
#define LM_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */
#define LM_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */
#define LM_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */
#define LM_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */
#define LM_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
#define LM_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
#define LM_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
#define LM_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
#define LM_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
#define LM_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
#define LM_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
#define LM_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
#define LM_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */
#define LM_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */
#define LM_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */
#define LM_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */
#define TIVA_UART_DR_OFFSET 0x000 /* UART Data */
#define TIVA_UART_RSR_OFFSET 0x004 /* UART Receive Status */
#define TIVA_UART_ECR_OFFSET 0x004 /* UART Error Clear */
#define TIVA_UART_FR_OFFSET 0x018 /* UART Flag */
#define TIVA_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */
#define TIVA_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/
#define TIVA_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */
#define TIVA_UART_LCRH_OFFSET 0x02c /* UART Line Control */
#define TIVA_UART_CTL_OFFSET 0x030 /* UART Control */
#define TIVA_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */
#define TIVA_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */
#define TIVA_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */
#define TIVA_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */
#define TIVA_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */
#define TIVA_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
#define TIVA_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
#define TIVA_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
#define TIVA_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
#define TIVA_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
#define TIVA_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
#define TIVA_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
#define TIVA_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
#define TIVA_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */
#define TIVA_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */
#define TIVA_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */
#define TIVA_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */
/* UART register addresses **********************************************************/
#define LM_UART_BASE(n) (LM_UART0_BASE + (n)*0x01000)
#define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000)
#define LM_UART_DR(n) (LM_UART_BASE(n) + LM_UART_DR_OFFSET)
#define LM_UART_RSR(n) (LM_UART_BASE(n) + LM_UART_RSR_OFFSET)
#define LM_UART_ECR(n) (LM_UART_BASE(n) + LM_UART_ECR_OFFSET)
#define LM_UART_FR(n) (LM_UART_BASE(n) + LM_UART_FR_OFFSET)
#define LM_UART_ILPR(n) (LM_UART_BASE(n) + LM_UART_ILPR_OFFSET)
#define LM_UART_IBRD(n) (LM_UART_BASE(n) + LM_UART_IBRD_OFFSET)
#define LM_UART_FBRD(n) (LM_UART_BASE(n) + LM_UART_FBRD_OFFSET)
#define LM_UART_LCRH(n) (LM_UART_BASE(n) + LM_UART_LCRH_OFFSET)
#define LM_UART_CTL(n) (LM_UART_BASE(n) + LM_UART_CTL_OFFSET)
#define LM_UART_IFLS(n) (LM_UART_BASE(n) + LM_UART_IFLS_OFFSET)
#define LM_UART_IM(n) (LM_UART_BASE(n) + LM_UART_IM_OFFSET)
#define LM_UART_RIS(n) (LM_UART_BASE(n) + LM_UART_RIS_OFFSET)
#define LM_UART_MIS(n) (LM_UART_BASE(n) + LM_UART_MIS_OFFSET)
#define LM_UART_ICR(n) (LM_UART_BASE(n) + LM_UART_ICR_OFFSET)
#define LM_UART_PERIPHID4(n) (LM_UART_BASE(n) + LM_UART_PERIPHID4_OFFSET)
#define LM_UART_PERIPHID5(n) (LM_UART_BASE(n) + LM_UART_PERIPHID5_OFFSET)
#define LM_UART_PERIPHID6(n) (LM_UART_BASE(n) + LM_UART_PERIPHID6_OFFSET)
#define LM_UART_PERIPHID7(n) (LM_UART_BASE(n) + LM_UART_PERIPHID7_OFFSET)
#define LM_UART_PERIPHID0(n) (LM_UART_BASE(n) + LM_UART_PERIPHID0_OFFSET)
#define LM_UART_PERIPHID1(n) (LM_UART_BASE(n) + LM_UART_PERIPHID1_OFFSET)
#define LM_UART_PERIPHID2(n) (LM_UART_BASE(n) + LM_UART_PERIPHID2_OFFSET)
#define LM_UART_PERIPHID3(n) (LM_UART_BASE(n) + LM_UART_PERIPHID3_OFFSET)
#define LM_UART_PCELLID0(n) (LM_UART_BASE(n) + LM_UART_PCELLID0_OFFSET)
#define LM_UART_PCELLID1(n) (LM_UART_BASE(n) + LM_UART_PCELLID1_OFFSET)
#define LM_UART_PCELLID2(n) (LM_UART_BASE(n) + LM_UART_PCELLID2_OFFSET)
#define LM_UART_PCELLID3(n) (LM_UART_BASE(n) + LM_UART_PCELLID3_OFFSET)
#define TIVA_UART_DR(n) (TIVA_UART_BASE(n) + TIVA_UART_DR_OFFSET)
#define TIVA_UART_RSR(n) (TIVA_UART_BASE(n) + TIVA_UART_RSR_OFFSET)
#define TIVA_UART_ECR(n) (TIVA_UART_BASE(n) + TIVA_UART_ECR_OFFSET)
#define TIVA_UART_FR(n) (TIVA_UART_BASE(n) + TIVA_UART_FR_OFFSET)
#define TIVA_UART_ILPR(n) (TIVA_UART_BASE(n) + TIVA_UART_ILPR_OFFSET)
#define TIVA_UART_IBRD(n) (TIVA_UART_BASE(n) + TIVA_UART_IBRD_OFFSET)
#define TIVA_UART_FBRD(n) (TIVA_UART_BASE(n) + TIVA_UART_FBRD_OFFSET)
#define TIVA_UART_LCRH(n) (TIVA_UART_BASE(n) + TIVA_UART_LCRH_OFFSET)
#define TIVA_UART_CTL(n) (TIVA_UART_BASE(n) + TIVA_UART_CTL_OFFSET)
#define TIVA_UART_IFLS(n) (TIVA_UART_BASE(n) + TIVA_UART_IFLS_OFFSET)
#define TIVA_UART_IM(n) (TIVA_UART_BASE(n) + TIVA_UART_IM_OFFSET)
#define TIVA_UART_RIS(n) (TIVA_UART_BASE(n) + TIVA_UART_RIS_OFFSET)
#define TIVA_UART_MIS(n) (TIVA_UART_BASE(n) + TIVA_UART_MIS_OFFSET)
#define TIVA_UART_ICR(n) (TIVA_UART_BASE(n) + TIVA_UART_ICR_OFFSET)
#define TIVA_UART_PERIPHID4(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID4_OFFSET)
#define TIVA_UART_PERIPHID5(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID5_OFFSET)
#define TIVA_UART_PERIPHID6(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID6_OFFSET)
#define TIVA_UART_PERIPHID7(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID7_OFFSET)
#define TIVA_UART_PERIPHID0(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID0_OFFSET)
#define TIVA_UART_PERIPHID1(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID1_OFFSET)
#define TIVA_UART_PERIPHID2(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID2_OFFSET)
#define TIVA_UART_PERIPHID3(n) (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID3_OFFSET)
#define TIVA_UART_PCELLID0(n) (TIVA_UART_BASE(n) + TIVA_UART_PCELLID0_OFFSET)
#define TIVA_UART_PCELLID1(n) (TIVA_UART_BASE(n) + TIVA_UART_PCELLID1_OFFSET)
#define TIVA_UART_PCELLID2(n) (TIVA_UART_BASE(n) + TIVA_UART_PCELLID2_OFFSET)
#define TIVA_UART_PCELLID3(n) (TIVA_UART_BASE(n) + TIVA_UART_PCELLID3_OFFSET)
#define LM_UART0_DR (LM_UART0_BASE + LM_UART_TDR_OFFSET)
#define LM_UART0_RSR (LM_UART0_BASE + LM_UART_RSR_OFFSET)
#define LM_UART0_ECR (LM_UART0_BASE + LM_UART_ECR_OFFSET)
#define LM_UART0_FR (LM_UART0_BASE + LM_UART_FR_OFFSET)
#define LM_UART0_ILPR (LM_UART0_BASE + LM_UART_ILPR_OFFSET)
#define LM_UART0_IBRD (LM_UART0_BASE + LM_UART_IBRD_OFFSET)
#define LM_UART0_FBRD (LM_UART0_BASE + LM_UART_FBRD_OFFSET)
#define LM_UART0_LCRH (LM_UART0_BASE + LM_UART_LCRH_OFFSET)
#define LM_UART0_CTL (LM_UART0_BASE + LM_UART_CTL_OFFSET)
#define LM_UART0_IFLS (LM_UART0_BASE + LM_UART_IFLS_OFFSET)
#define LM_UART0_IM (LM_UART0_BASE + LM_UART_IM_OFFSET)
#define LM_UART0_RIS (LM_UART0_BASE + LM_UART_RIS_OFFSET)
#define LM_UART0_MIS (LM_UART0_BASE + LM_UART_MIS_OFFSET)
#define LM_UART0_ICR (LM_UART0_BASE + LM_UART_ICR_OFFSET)
#define LM_UART0_PERIPHID4 (LM_UART0_BASE + LM_UART_PERIPHID4_OFFSET)
#define LM_UART0_PERIPHID5 (LM_UART0_BASE + LM_UART_PERIPHID5_OFFSET)
#define LM_UART0_PERIPHID6 (LM_UART0_BASE + LM_UART_PERIPHID6_OFFSET)
#define LM_UART0_PERIPHID7 (LM_UART0_BASE + LM_UART_PERIPHID7_OFFSET)
#define LM_UART0_PERIPHID0 (LM_UART0_BASE + LM_UART_PERIPHID0_OFFSET)
#define LM_UART0_PERIPHID1 (LM_UART0_BASE + LM_UART_PERIPHID1_OFFSET)
#define LM_UART0_PERIPHID2 (LM_UART0_BASE + LM_UART_PERIPHID2_OFFSET)
#define LM_UART0_PERIPHID3 (LM_UART0_BASE + LM_UART_PERIPHID3_OFFSET)
#define LM_UART0_PCELLID0 (LM_UART0_BASE + LM_UART_PCELLID0_OFFSET)
#define LM_UART0_PCELLID1 (LM_UART0_BASE + LM_UART_PCELLID1_OFFSET)
#define LM_UART0_PCELLID2 (LM_UART0_BASE + LM_UART_PCELLID2_OFFSET)
#define LM_UART0_PCELLID3 (LM_UART0_BASE + LM_UART_PCELLID3_OFFSET)
#define TIVA_UART0_DR (TIVA_UART0_BASE + TIVA_UART_TDR_OFFSET)
#define TIVA_UART0_RSR (TIVA_UART0_BASE + TIVA_UART_RSR_OFFSET)
#define TIVA_UART0_ECR (TIVA_UART0_BASE + TIVA_UART_ECR_OFFSET)
#define TIVA_UART0_FR (TIVA_UART0_BASE + TIVA_UART_FR_OFFSET)
#define TIVA_UART0_ILPR (TIVA_UART0_BASE + TIVA_UART_ILPR_OFFSET)
#define TIVA_UART0_IBRD (TIVA_UART0_BASE + TIVA_UART_IBRD_OFFSET)
#define TIVA_UART0_FBRD (TIVA_UART0_BASE + TIVA_UART_FBRD_OFFSET)
#define TIVA_UART0_LCRH (TIVA_UART0_BASE + TIVA_UART_LCRH_OFFSET)
#define TIVA_UART0_CTL (TIVA_UART0_BASE + TIVA_UART_CTL_OFFSET)
#define TIVA_UART0_IFLS (TIVA_UART0_BASE + TIVA_UART_IFLS_OFFSET)
#define TIVA_UART0_IM (TIVA_UART0_BASE + TIVA_UART_IM_OFFSET)
#define TIVA_UART0_RIS (TIVA_UART0_BASE + TIVA_UART_RIS_OFFSET)
#define TIVA_UART0_MIS (TIVA_UART0_BASE + TIVA_UART_MIS_OFFSET)
#define TIVA_UART0_ICR (TIVA_UART0_BASE + TIVA_UART_ICR_OFFSET)
#define TIVA_UART0_PERIPHID4 (TIVA_UART0_BASE + TIVA_UART_PERIPHID4_OFFSET)
#define TIVA_UART0_PERIPHID5 (TIVA_UART0_BASE + TIVA_UART_PERIPHID5_OFFSET)
#define TIVA_UART0_PERIPHID6 (TIVA_UART0_BASE + TIVA_UART_PERIPHID6_OFFSET)
#define TIVA_UART0_PERIPHID7 (TIVA_UART0_BASE + TIVA_UART_PERIPHID7_OFFSET)
#define TIVA_UART0_PERIPHID0 (TIVA_UART0_BASE + TIVA_UART_PERIPHID0_OFFSET)
#define TIVA_UART0_PERIPHID1 (TIVA_UART0_BASE + TIVA_UART_PERIPHID1_OFFSET)
#define TIVA_UART0_PERIPHID2 (TIVA_UART0_BASE + TIVA_UART_PERIPHID2_OFFSET)
#define TIVA_UART0_PERIPHID3 (TIVA_UART0_BASE + TIVA_UART_PERIPHID3_OFFSET)
#define TIVA_UART0_PCELLID0 (TIVA_UART0_BASE + TIVA_UART_PCELLID0_OFFSET)
#define TIVA_UART0_PCELLID1 (TIVA_UART0_BASE + TIVA_UART_PCELLID1_OFFSET)
#define TIVA_UART0_PCELLID2 (TIVA_UART0_BASE + TIVA_UART_PCELLID2_OFFSET)
#define TIVA_UART0_PCELLID3 (TIVA_UART0_BASE + TIVA_UART_PCELLID3_OFFSET)
#define LM_UART1_DR (LM_UART1_BASE + LM_UART_DR_OFFSET)
#define LM_UART1_RSR (LM_UART1_BASE + LM_UART_RSR_OFFSET)
#define LM_UART1_ECR (LM_UART1_BASE + LM_UART_ECR_OFFSET)
#define LM_UART1_FR (LM_UART1_BASE + LM_UART_FR_OFFSET)
#define LM_UART1_ILPR (LM_UART1_BASE + LM_UART_ILPR_OFFSET)
#define LM_UART1_IBRD (LM_UART1_BASE + LM_UART_IBRD_OFFSET)
#define LM_UART1_FBRD (LM_UART1_BASE + LM_UART_FBRD_OFFSET)
#define LM_UART1_LCRH (LM_UART1_BASE + LM_UART_LCRH_OFFSET)
#define LM_UART1_CTL (LM_UART1_BASE + LM_UART_CTL_OFFSET)
#define LM_UART1_IFLS (LM_UART1_BASE + LM_UART_IFLS_OFFSET)
#define LM_UART1_IM (LM_UART1_BASE + LM_UART_IM_OFFSET)
#define LM_UART1_RIS (LM_UART1_BASE + LM_UART_RIS_OFFSET)
#define LM_UART1_MIS (LM_UART1_BASE + LM_UART_MIS_OFFSET)
#define LM_UART1_ICR (LM_UART1_BASE + LM_UART_ICR_OFFSET)
#define LM_UART1_PERIPHID4 (LM_UART1_BASE + LM_UART_PERIPHID4_OFFSET)
#define LM_UART1_PERIPHID5 (LM_UART1_BASE + LM_UART_PERIPHID5_OFFSET)
#define LM_UART1_PERIPHID6 (LM_UART1_BASE + LM_UART_PERIPHID6_OFFSET)
#define LM_UART1_PERIPHID7 (LM_UART1_BASE + LM_UART_PERIPHID7_OFFSET)
#define LM_UART1_PERIPHID0 (LM_UART1_BASE + LM_UART_PERIPHID0_OFFSET)
#define LM_UART1_PERIPHID1 (LM_UART1_BASE + LM_UART_PERIPHID1_OFFSET)
#define LM_UART1_PERIPHID2 (LM_UART1_BASE + LM_UART_PERIPHID2_OFFSET)
#define LM_UART1_PERIPHID3 (LM_UART1_BASE + LM_UART_PERIPHID3_OFFSET)
#define LM_UART1_PCELLID0 (LM_UART1_BASE + LM_UART_PCELLID0_OFFSET)
#define LM_UART1_PCELLID1 (LM_UART1_BASE + LM_UART_PCELLID1_OFFSET)
#define LM_UART1_PCELLID2 (LM_UART1_BASE + LM_UART_PCELLID2_OFFSET)
#define LM_UART1_PCELLID3 (LM_UART1_BASE + LM_UART_PCELLID3_OFFSET)
#define TIVA_UART1_DR (TIVA_UART1_BASE + TIVA_UART_DR_OFFSET)
#define TIVA_UART1_RSR (TIVA_UART1_BASE + TIVA_UART_RSR_OFFSET)
#define TIVA_UART1_ECR (TIVA_UART1_BASE + TIVA_UART_ECR_OFFSET)
#define TIVA_UART1_FR (TIVA_UART1_BASE + TIVA_UART_FR_OFFSET)
#define TIVA_UART1_ILPR (TIVA_UART1_BASE + TIVA_UART_ILPR_OFFSET)
#define TIVA_UART1_IBRD (TIVA_UART1_BASE + TIVA_UART_IBRD_OFFSET)
#define TIVA_UART1_FBRD (TIVA_UART1_BASE + TIVA_UART_FBRD_OFFSET)
#define TIVA_UART1_LCRH (TIVA_UART1_BASE + TIVA_UART_LCRH_OFFSET)
#define TIVA_UART1_CTL (TIVA_UART1_BASE + TIVA_UART_CTL_OFFSET)
#define TIVA_UART1_IFLS (TIVA_UART1_BASE + TIVA_UART_IFLS_OFFSET)
#define TIVA_UART1_IM (TIVA_UART1_BASE + TIVA_UART_IM_OFFSET)
#define TIVA_UART1_RIS (TIVA_UART1_BASE + TIVA_UART_RIS_OFFSET)
#define TIVA_UART1_MIS (TIVA_UART1_BASE + TIVA_UART_MIS_OFFSET)
#define TIVA_UART1_ICR (TIVA_UART1_BASE + TIVA_UART_ICR_OFFSET)
#define TIVA_UART1_PERIPHID4 (TIVA_UART1_BASE + TIVA_UART_PERIPHID4_OFFSET)
#define TIVA_UART1_PERIPHID5 (TIVA_UART1_BASE + TIVA_UART_PERIPHID5_OFFSET)
#define TIVA_UART1_PERIPHID6 (TIVA_UART1_BASE + TIVA_UART_PERIPHID6_OFFSET)
#define TIVA_UART1_PERIPHID7 (TIVA_UART1_BASE + TIVA_UART_PERIPHID7_OFFSET)
#define TIVA_UART1_PERIPHID0 (TIVA_UART1_BASE + TIVA_UART_PERIPHID0_OFFSET)
#define TIVA_UART1_PERIPHID1 (TIVA_UART1_BASE + TIVA_UART_PERIPHID1_OFFSET)
#define TIVA_UART1_PERIPHID2 (TIVA_UART1_BASE + TIVA_UART_PERIPHID2_OFFSET)
#define TIVA_UART1_PERIPHID3 (TIVA_UART1_BASE + TIVA_UART_PERIPHID3_OFFSET)
#define TIVA_UART1_PCELLID0 (TIVA_UART1_BASE + TIVA_UART_PCELLID0_OFFSET)
#define TIVA_UART1_PCELLID1 (TIVA_UART1_BASE + TIVA_UART_PCELLID1_OFFSET)
#define TIVA_UART1_PCELLID2 (TIVA_UART1_BASE + TIVA_UART_PCELLID2_OFFSET)
#define TIVA_UART1_PCELLID3 (TIVA_UART1_BASE + TIVA_UART_PCELLID3_OFFSET)
/* UART register bit settings *******************************************************/

80
arch/arm/src/tiva/tiva_dumpgpio.c
View file

@ -60,64 +60,64 @@
/* NOTE: this is duplicated in tiva_gpio.c */
static const uintptr_t g_gpiobase[LM_NPORTS] =
static const uintptr_t g_gpiobase[TIVA_NPORTS] =
{
#if LM_NPORTS > 0
LM_GPIOA_BASE
#if TIVA_NPORTS > 0
TIVA_GPIOA_BASE
#endif
#if LM_NPORTS > 1
, LM_GPIOB_BASE
#if TIVA_NPORTS > 1
, TIVA_GPIOB_BASE
#endif
#if LM_NPORTS > 2
, LM_GPIOC_BASE
#if TIVA_NPORTS > 2
, TIVA_GPIOC_BASE
#endif
#if LM_NPORTS > 3
, LM_GPIOD_BASE
#if TIVA_NPORTS > 3
, TIVA_GPIOD_BASE
#endif
#if LM_NPORTS > 4
, LM_GPIOE_BASE
#if TIVA_NPORTS > 4
, TIVA_GPIOE_BASE
#endif
#if LM_NPORTS > 5
, LM_GPIOF_BASE
#if TIVA_NPORTS > 5
, TIVA_GPIOF_BASE
#endif
#if LM_NPORTS > 6
, LM_GPIOG_BASE
#if TIVA_NPORTS > 6
, TIVA_GPIOG_BASE
#endif
#if LM_NPORTS > 7
, LM_GPIOH_BASE
#if TIVA_NPORTS > 7
, TIVA_GPIOH_BASE
#endif
#if LM_NPORTS > 8
, LM_GPIOJ_BASE
#if TIVA_NPORTS > 8
, TIVA_GPIOJ_BASE
#endif
};
static const char g_portchar[LM_NPORTS] =
static const char g_portchar[TIVA_NPORTS] =
{
#if LM_NPORTS > 0
#if TIVA_NPORTS > 0
'A'
#endif
#if LM_NPORTS > 1
#if TIVA_NPORTS > 1
, 'B'
#endif
#if LM_NPORTS > 2
#if TIVA_NPORTS > 2
, 'C'
#endif
#if LM_NPORTS > 3
#if TIVA_NPORTS > 3
, 'D'
#endif
#if LM_NPORTS > 4
#if TIVA_NPORTS > 4
, 'E'
#endif
#if LM_NPORTS > 5
#if TIVA_NPORTS > 5
, 'F'
#endif
#if LM_NPORTS > 6
#if TIVA_NPORTS > 6
, 'G'
#endif
#if LM_NPORTS > 7
#if TIVA_NPORTS > 7
, 'H'
#endif
#if LM_NPORTS > 8
#if TIVA_NPORTS > 8
, 'J'
#endif
};
@ -137,7 +137,7 @@ static const char g_portchar[LM_NPORTS] =
static inline uintptr_t tiva_gpiobaseaddress(int port)
{
return port < LM_NPORTS ? g_gpiobase[port] : 0;
return port < TIVA_NPORTS ? g_gpiobase[port] : 0;
}
/****************************************************************************
@ -151,7 +151,7 @@ static inline uintptr_t tiva_gpiobaseaddress(int port)
static inline uint8_t tiva_gpioport(int port)
{
return port < LM_NPORTS ? g_portchar[port] : '?';
return port < TIVA_NPORTS ? g_portchar[port] : '?';
}
/****************************************************************************
@ -182,7 +182,7 @@ int tiva_dumpgpio(uint32_t pinset, const char *msg)
/* The following requires exclusive access to the GPIO registers */
flags = irqsave();
rcgc2 = getreg32(LM_SYSCON_RCGC2);
rcgc2 = getreg32(TIVA_SYSCON_RCGC2);
enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
@ -195,16 +195,16 @@ int tiva_dumpgpio(uint32_t pinset, const char *msg)
if (enabled)
{
lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
getreg32(base + LM_GPIO_AFSEL_OFFSET), getreg32(base + LM_GPIO_DEN_OFFSET),
getreg32(base + LM_GPIO_DIR_OFFSET), getreg32(base + LM_GPIO_DATA_OFFSET + 0x3fc));
getreg32(base + TIVA_GPIO_AFSEL_OFFSET), getreg32(base + TIVA_GPIO_DEN_OFFSET),
getreg32(base + TIVA_GPIO_DIR_OFFSET), getreg32(base + TIVA_GPIO_DATA_OFFSET + 0x3fc));
lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n",
getreg32(base + LM_GPIO_IEV_OFFSET), getreg32(base + LM_GPIO_IM_OFFSET),
getreg32(base + LM_GPIO_RIS_OFFSET), getreg32(base + LM_GPIO_MIS_OFFSET));
getreg32(base + TIVA_GPIO_IEV_OFFSET), getreg32(base + TIVA_GPIO_IM_OFFSET),
getreg32(base + TIVA_GPIO_RIS_OFFSET), getreg32(base + TIVA_GPIO_MIS_OFFSET));
lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
getreg32(base + LM_GPIO_DR2R_OFFSET), getreg32(base + LM_GPIO_DR4R_OFFSET),
getreg32(base + LM_GPIO_DR8R_OFFSET), getreg32(base + LM_GPIO_ODR_OFFSET),
getreg32(base + LM_GPIO_PUR_OFFSET), getreg32(base + LM_GPIO_PDR_OFFSET),
getreg32(base + LM_GPIO_SLR_OFFSET));
getreg32(base + TIVA_GPIO_DR2R_OFFSET), getreg32(base + TIVA_GPIO_DR4R_OFFSET),
getreg32(base + TIVA_GPIO_DR8R_OFFSET), getreg32(base + TIVA_GPIO_ODR_OFFSET),
getreg32(base + TIVA_GPIO_PUR_OFFSET), getreg32(base + TIVA_GPIO_PDR_OFFSET),
getreg32(base + TIVA_GPIO_SLR_OFFSET));
}
irqrestore(flags);
return OK;

297
arch/arm/src/tiva/tiva_ethernet.c
View file

@ -38,7 +38,7 @@
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_NET) && defined(CONFIG_LM_ETHERNET)
#if defined(CONFIG_NET) && defined(CONFIG_TIVA_ETHERNET)
#include <stdint.h>
#include <stdbool.h>
@ -66,75 +66,75 @@
* Pre-processor Definitions
****************************************************************************/
/* Half duplex can be forced if CONFIG_LM_ETHHDUPLEX is defined. */
/* Half duplex can be forced if CONFIG_TIVA_ETHHDUPLEX is defined. */
#ifdef CONFIG_LM_ETHHDUPLEX
# define LM_DUPLEX_SETBITS 0
# define LM_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
#ifdef CONFIG_TIVA_ETHHDUPLEX
# define TIVA_DUPLEX_SETBITS 0
# define TIVA_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
#else
# define LM_DUPLEX_SETBITS MAC_TCTL_DUPLEX
# define LM_DUPLEX_CLRBITS 0
# define TIVA_DUPLEX_SETBITS MAC_TCTL_DUPLEX
# define TIVA_DUPLEX_CLRBITS 0
#endif
/* Auto CRC generation can be suppressed if CONFIG_LM_ETHNOAUTOCRC is definde */
/* Auto CRC generation can be suppressed if CONFIG_TIVA_ETHNOAUTOCRC is definde */
#ifdef CONFIG_LM_ETHNOAUTOCRC
# define LM_CRC_SETBITS 0
# define LM_CRC_CLRBITS MAC_TCTL_CRC
#ifdef CONFIG_TIVA_ETHNOAUTOCRC
# define TIVA_CRC_SETBITS 0
# define TIVA_CRC_CLRBITS MAC_TCTL_CRC
#else
# define LM_CRC_SETBITS MAC_TCTL_CRC
# define LM_CRC_CLRBITS 0
# define TIVA_CRC_SETBITS MAC_TCTL_CRC
# define TIVA_CRC_CLRBITS 0
#endif
/* Tx padding can be suppressed if CONFIG_LM_ETHNOPAD is defined */
/* Tx padding can be suppressed if CONFIG_TIVA_ETHNOPAD is defined */
#ifdef CONFIG_LM_ETHNOPAD
# define LM_PADEN_SETBITS 0
# define LM_PADEN_CLRBITS MAC_TCTL_PADEN
#ifdef CONFIG_TIVA_ETHNOPAD
# define TIVA_PADEN_SETBITS 0
# define TIVA_PADEN_CLRBITS MAC_TCTL_PADEN
#else
# define LM_PADEN_SETBITS MAC_TCTL_PADEN
# define LM_PADEN_CLRBITS 0
# define TIVA_PADEN_SETBITS MAC_TCTL_PADEN
# define TIVA_PADEN_CLRBITS 0
#endif
#define LM_TCTCL_SETBITS (LM_DUPLEX_SETBITS|LM_CRC_SETBITS|LM_PADEN_SETBITS)
#define LM_TCTCL_CLRBITS (LM_DUPLEX_CLRBITS|LM_CRC_CLRBITS|LM_PADEN_CLRBITS)
#define TIVA_TCTCL_SETBITS (TIVA_DUPLEX_SETBITS|TIVA_CRC_SETBITS|TIVA_PADEN_SETBITS)
#define TIVA_TCTCL_CLRBITS (TIVA_DUPLEX_CLRBITS|TIVA_CRC_CLRBITS|TIVA_PADEN_CLRBITS)
/* Multicast frames can be enabled by defining CONFIG_LM_MULTICAST */
/* Multicast frames can be enabled by defining CONFIG_TIVA_MULTICAST */
#ifdef CONFIG_LM_MULTICAST
# define LM_AMUL_SETBITS MAC_RCTL_AMUL
# define LM_AMUL_CLRBITS 0
#ifdef CONFIG_TIVA_MULTICAST
# define TIVA_AMUL_SETBITS MAC_RCTL_AMUL
# define TIVA_AMUL_CLRBITS 0
#else
# define LM_AMUL_SETBITS 0
# define LM_AMUL_CLRBITS MAC_RCTL_AMUL
# define TIVA_AMUL_SETBITS 0
# define TIVA_AMUL_CLRBITS MAC_RCTL_AMUL
#endif
/* Promiscuous mode can be enabled by defining CONFIG_LM_PROMISCUOUS */
/* Promiscuous mode can be enabled by defining CONFIG_TIVA_PROMISCUOUS */
#ifdef CONFIG_LM_PROMISCUOUS
# define LM_PRMS_SETBITS MAC_RCTL_PRMS
# define LM_PRMS_CLRBITS 0
#ifdef CONFIG_TIVA_PROMISCUOUS
# define TIVA_PRMS_SETBITS MAC_RCTL_PRMS
# define TIVA_PRMS_CLRBITS 0
#else
# define LM_PRMS_SETBITS 0
# define LM_PRMS_CLRBITS MAC_RCTL_PRMS
# define TIVA_PRMS_SETBITS 0
# define TIVA_PRMS_CLRBITS MAC_RCTL_PRMS
#endif
/* Bad CRC rejection can be enabled by define CONFIG_LM_BADCRC */
/* Bad CRC rejection can be enabled by define CONFIG_TIVA_BADCRC */
#ifdef CONFIG_LM_BADCRC
# define LM_BADCRC_SETBITS MAC_RCTL_BADCRC
# define LM_BADCRC_CLRBITS 0
#ifdef CONFIG_TIVA_BADCRC
# define TIVA_BADCRC_SETBITS MAC_RCTL_BADCRC
# define TIVA_BADCRC_CLRBITS 0
#else
# define LM_BADCRC_SETBITS 0
# define LM_BADCRC_CLRBITS MAC_RCTL_BADCRC
# define TIVA_BADCRC_SETBITS 0
# define TIVA_BADCRC_CLRBITS MAC_RCTL_BADCRC
#endif
#define LM_RCTCL_SETBITS (LM_AMUL_SETBITS|LM_PRMS_SETBITS|LM_BADCRC_SETBITS)
#define LM_RCTCL_CLRBITS (LM_AMUL_CLRBITS|LM_PRMS_CLRBITS|LM_BADCRC_CLRBITS)
#define TIVA_RCTCL_SETBITS (TIVA_AMUL_SETBITS|TIVA_PRMS_SETBITS|TIVA_BADCRC_SETBITS)
#define TIVA_RCTCL_CLRBITS (TIVA_AMUL_CLRBITS|TIVA_PRMS_CLRBITS|TIVA_BADCRC_CLRBITS)
/* CONFIG_LM_DUMPPACKET will dump the contents of each packet to the console. */
/* CONFIG_TIVA_DUMPPACKET will dump the contents of each packet to the console. */
#ifdef CONFIG_LM_DUMPPACKET
#ifdef CONFIG_TIVA_DUMPPACKET
# define tiva_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
#else
# define tiva_dumppacket(m,a,n)
@ -142,18 +142,18 @@
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
#define LM_WDDELAY (1*CLK_TCK)
#define LM_POLLHSEC (1*2)
#define TIVA_WDDELAY (1*CLK_TCK)
#define TIVA_POLLHSEC (1*2)
/* TX timeout = 1 minute */
#define LM_TXTIMEOUT (60*CLK_TCK)
#define TIVA_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf)
#define LM_MAX_MDCCLK 2500000
#define TIVA_MAX_MDCCLK 2500000
/****************************************************************************
* Private Types
@ -192,7 +192,7 @@ struct tiva_driver_s
* multiple Ethernet controllers.
*/
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
uint32_t ld_base; /* Ethernet controller base address */
int ld_irq; /* Ethernet controller IRQ */
#endif
@ -214,7 +214,7 @@ struct tiva_driver_s
* Private Data
****************************************************************************/
static struct tiva_driver_s g_lm3sdev[LM_NETHCONTROLLERS];
static struct tiva_driver_s g_lm3sdev[TIVA_NETHCONTROLLERS];
/****************************************************************************
* Private Function Prototypes
@ -222,7 +222,7 @@ static struct tiva_driver_s g_lm3sdev[LM_NETHCONTROLLERS];
/* Miscellaneous low level helpers */
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
static uint32_t tiva_ethin(struct tiva_driver_s *priv, int offset);
static void tiva_ethout(struct tiva_driver_s *priv, int offset, uint32_t value);
#else
@ -280,7 +280,7 @@ static int tiva_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
*
****************************************************************************/
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
static uint32_t tiva_ethin(struct tiva_driver_s *priv, int offset)
{
return getreg32(priv->ld_base + offset);
@ -288,7 +288,7 @@ static uint32_t tiva_ethin(struct tiva_driver_s *priv, int offset)
#else
static inline uint32_t tiva_ethin(struct tiva_driver_s *priv, int offset)
{
return getreg32(LM_ETHCON_BASE + offset);
return getreg32(TIVA_ETHCON_BASE + offset);
}
#endif
@ -308,7 +308,7 @@ static inline uint32_t tiva_ethin(struct tiva_driver_s *priv, int offset)
*
****************************************************************************/
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
static void tiva_ethout(struct tiva_driver_s *priv, int offset, uint32_t value)
{
putreg32(value, priv->ld_base + offset);
@ -316,7 +316,7 @@ static void tiva_ethout(struct tiva_driver_s *priv, int offset, uint32_t value)
#else
static inline void tiva_ethout(struct tiva_driver_s *priv, int offset, uint32_t value)
{
putreg32(value, LM_ETHCON_BASE + offset);
putreg32(value, TIVA_ETHCON_BASE + offset);
}
#endif
@ -341,23 +341,23 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
irqstate_t flags;
uint32_t regval;
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
# error "If multiple interfaces are supported, this function would have to be redesigned"
#endif
/* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
flags = irqsave();
regval = getreg32(LM_SYSCON_RCGC2);
regval = getreg32(TIVA_SYSCON_RCGC2);
regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0);
putreg32(regval, LM_SYSCON_RCGC2);
putreg32(regval, TIVA_SYSCON_RCGC2);
nllvdbg("RCGC2: %08x\n", regval);
/* Put the Ethernet controller into the reset state */
regval = getreg32(LM_SYSCON_SRCR2);
regval = getreg32(TIVA_SYSCON_SRCR2);
regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
putreg32(regval, LM_SYSCON_SRCR2);
putreg32(regval, TIVA_SYSCON_SRCR2);
/* Wait just a bit. This is a much longer delay than necessary */
@ -366,7 +366,7 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
/* Then take the Ethernet controller out of the reset state */
regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
putreg32(regval, LM_SYSCON_SRCR2);
putreg32(regval, TIVA_SYSCON_SRCR2);
nllvdbg("SRCR2: %08x\n", regval);
/* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */
@ -375,7 +375,7 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
/* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */
#ifdef CONFIG_LM_ETHLEDS
#ifdef CONFIG_TIVA_ETHLEDS
/* Configure the pins for the peripheral function */
tiva_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD);
@ -384,14 +384,14 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
/* Disable all Ethernet controller interrupts */
regval = tiva_ethin(priv, LM_MAC_IM_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_IM_OFFSET);
regval &= ~MAC_IM_ALLINTS;
tiva_ethout(priv, LM_MAC_IM_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_IM_OFFSET, regval);
/* Clear any pending interrupts (shouldn't be any) */
regval = tiva_ethin(priv, LM_MAC_RIS_OFFSET);
tiva_ethout(priv, LM_MAC_IACK_OFFSET, regval);
regval = tiva_ethin(priv, TIVA_MAC_RIS_OFFSET);
tiva_ethout(priv, TIVA_MAC_IACK_OFFSET, regval);
irqrestore(flags);
}
@ -416,22 +416,22 @@ static void tiva_phywrite(struct tiva_driver_s *priv, int regaddr, uint16_t valu
{
/* Wait for any MII transactions in progress to complete */
while ((tiva_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
while ((tiva_ethin(priv, TIVA_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
/* Set up the data to be written */
DEBUGASSERT(value < MAC_MTXD_MASK);
tiva_ethout(priv, LM_MAC_MTXD_OFFSET, value);
tiva_ethout(priv, TIVA_MAC_MTXD_OFFSET, value);
/* Set up the PHY register address and start the write operation */
regaddr <<= MAC_MCTL_REGADR_SHIFT;
DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
tiva_ethout(priv, LM_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
tiva_ethout(priv, TIVA_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
/* Wait for the write transaction to complete */
while ((tiva_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
while ((tiva_ethin(priv, TIVA_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
}
#endif
@ -455,21 +455,21 @@ static uint16_t tiva_phyread(struct tiva_driver_s *priv, int regaddr)
{
/* Wait for any MII transactions in progress to complete */
while ((tiva_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
while ((tiva_ethin(priv, TIVA_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
/* Set up the PHY register address and start the read operation */
regaddr <<= MAC_MCTL_REGADR_SHIFT;
DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
tiva_ethout(priv, LM_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
tiva_ethout(priv, TIVA_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
/* Wait for the write transaction to complete */
while ((tiva_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
while ((tiva_ethin(priv, TIVA_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
/* Read and return the PHY data */
return (uint16_t)(tiva_ethin(priv, LM_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
return (uint16_t)(tiva_ethin(priv, TIVA_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
}
/****************************************************************************
@ -499,7 +499,7 @@ static int tiva_transmit(struct tiva_driver_s *priv)
/* Verify that the hardware is ready to send another packet */
flags = irqsave();
if ((tiva_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
if ((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
{
/* Increment statistics */
@ -520,7 +520,7 @@ static int tiva_transmit(struct tiva_driver_s *priv)
regval = (uint32_t)(pktlen - 14);
regval |= ((uint32_t)(*dbuf++) << 16);
regval |= ((uint32_t)(*dbuf++) << 24);
tiva_ethout(priv, LM_MAC_DATA_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_DATA_OFFSET, regval);
/* Write all of the whole, 32-bit values in the middle of the packet */
@ -530,7 +530,7 @@ static int tiva_transmit(struct tiva_driver_s *priv)
* buffer may be un-aligned.
*/
tiva_ethout(priv, LM_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
tiva_ethout(priv, TIVA_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
}
/* Write the last, partial word in the FIFO */
@ -555,16 +555,16 @@ static int tiva_transmit(struct tiva_driver_s *priv)
break;
}
tiva_ethout(priv, LM_MAC_DATA_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_DATA_OFFSET, regval);
}
/* Activate the transmitter */
tiva_ethout(priv, LM_MAC_TR_OFFSET, MAC_TR_NEWTX);
tiva_ethout(priv, TIVA_MAC_TR_OFFSET, MAC_TR_NEWTX);
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
(void)wd_start(priv->ld_txtimeout, LM_TXTIMEOUT, tiva_txtimeout, 1, (uint32_t)priv);
(void)wd_start(priv->ld_txtimeout, TIVA_TXTIMEOUT, tiva_txtimeout, 1, (uint32_t)priv);
ret = OK;
}
@ -609,7 +609,7 @@ static int tiva_uiptxpoll(struct uip_driver_s *dev)
* packet was successfully handled.
*/
DEBUGASSERT((tiva_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
DEBUGASSERT((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
uip_arp_out(&priv->ld_dev);
ret = tiva_transmit(priv);
}
@ -646,7 +646,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
/* Loop while there are incoming packets to be processed */
while ((tiva_ethin(priv, LM_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
while ((tiva_ethin(priv, TIVA_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
{
/* Update statistics */
@ -666,7 +666,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
* includes the len/type field (size 2) and the FCS (size 4).
*/
regval = tiva_ethin(priv, LM_MAC_DATA_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_DATA_OFFSET);
pktlen = (int)(regval & 0x0000ffff);
nllvdbg("Receiving packet, pktlen: %d\n", pktlen);
@ -695,7 +695,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
while (wordlen--)
{
(void)tiva_ethin(priv, LM_MAC_DATA_OFFSET);
(void)tiva_ethin(priv, TIVA_MAC_DATA_OFFSET);
}
/* Check for another packet */
@ -719,7 +719,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
* buffer may be un-aligned.
*/
*(uint32_t*)dbuf = tiva_ethin(priv, LM_MAC_DATA_OFFSET);
*(uint32_t*)dbuf = tiva_ethin(priv, TIVA_MAC_DATA_OFFSET);
}
/* Handle the last, partial word in the FIFO (0-3 bytes) and discard
@ -732,7 +732,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
* bytes of the FCS into the user buffer.
*/
regval = tiva_ethin(priv, LM_MAC_DATA_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_DATA_OFFSET);
switch (bytesleft)
{
default:
@ -835,7 +835,7 @@ static void tiva_txdone(struct tiva_driver_s *priv)
* at this point.
*/
DEBUGASSERT((tiva_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
DEBUGASSERT((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
/* Then poll uIP for new XMIT data */
@ -864,7 +864,7 @@ static int tiva_interrupt(int irq, FAR void *context)
register struct tiva_driver_s *priv;
uint32_t ris;
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
# error "A mechanism to associate and interface with an IRQ is needed"
#else
priv = &g_lm3sdev[0];
@ -872,11 +872,11 @@ static int tiva_interrupt(int irq, FAR void *context)
/* Read the raw interrupt status register */
ris = tiva_ethin(priv, LM_MAC_RIS_OFFSET);
ris = tiva_ethin(priv, TIVA_MAC_RIS_OFFSET);
/* Clear all pending interrupts */
tiva_ethout(priv, LM_MAC_IACK_OFFSET, ris);
tiva_ethout(priv, TIVA_MAC_IACK_OFFSET, ris);
/* Check for errors */
@ -899,7 +899,7 @@ static int tiva_interrupt(int irq, FAR void *context)
/* Handle (unmasked) interrupts according to status bit settings */
ris &= tiva_ethin(priv, LM_MAC_IM_OFFSET);
ris &= tiva_ethin(priv, TIVA_MAC_IM_OFFSET);
/* Is this an Rx interrupt (meaning that a packet has been received)? */
@ -995,15 +995,15 @@ static void tiva_polltimer(int argc, uint32_t arg, ...)
* inaccuracies.
*/
if ((tiva_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
if ((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
{
/* If so, update TCP timing states and poll uIP for new XMIT data */
(void)uip_timer(&priv->ld_dev, tiva_uiptxpoll, LM_POLLHSEC);
(void)uip_timer(&priv->ld_dev, tiva_uiptxpoll, TIVA_POLLHSEC);
/* Setup the watchdog poll timer again */
(void)wd_start(priv->ld_txpoll, LM_WDDELAY, tiva_polltimer, 1, arg);
(void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_polltimer, 1, arg);
}
}
@ -1048,11 +1048,11 @@ static int tiva_ifup(struct uip_driver_s *dev)
* div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1
*
* Where the maximum value for MDCCLK_FREQUENCY is 2,500,000. We will
* add 1 to assure the max LM_MAX_MDCCLK is not exceeded.
* add 1 to assure the max TIVA_MAX_MDCCLK is not exceeded.
*/
div = SYSCLK_FREQUENCY / 2 / LM_MAX_MDCCLK;
tiva_ethout(priv, LM_MAC_MDV_OFFSET, div);
div = SYSCLK_FREQUENCY / 2 / TIVA_MAX_MDCCLK;
tiva_ethout(priv, TIVA_MAC_MDV_OFFSET, div);
nllvdbg("MDV: %08x\n", div);
/* Then configure the Ethernet Controller for normal operation
@ -1061,32 +1061,32 @@ static int tiva_ifup(struct uip_driver_s *dev)
* TX Padding Enabled).
*/
regval = tiva_ethin(priv, LM_MAC_TCTL_OFFSET);
regval &= ~LM_TCTCL_CLRBITS;
regval |= LM_TCTCL_SETBITS;
tiva_ethout(priv, LM_MAC_TCTL_OFFSET, regval);
regval = tiva_ethin(priv, TIVA_MAC_TCTL_OFFSET);
regval &= ~TIVA_TCTCL_CLRBITS;
regval |= TIVA_TCTCL_SETBITS;
tiva_ethout(priv, TIVA_MAC_TCTL_OFFSET, regval);
nllvdbg("TCTL: %08x\n", regval);
/* Setup the receive control register (Disable multicast frames, disable
* promiscuous mode, disable bad CRC rejection).
*/
regval = tiva_ethin(priv, LM_MAC_RCTL_OFFSET);
regval &= ~LM_RCTCL_CLRBITS;
regval |= LM_RCTCL_SETBITS;
tiva_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
regval = tiva_ethin(priv, TIVA_MAC_RCTL_OFFSET);
regval &= ~TIVA_RCTCL_CLRBITS;
regval |= TIVA_RCTCL_SETBITS;
tiva_ethout(priv, TIVA_MAC_RCTL_OFFSET, regval);
nllvdbg("RCTL: %08x\n", regval);
/* Setup the time stamp configuration register */
#ifdef LM_ETHTS
regval = tiva_ethin(priv, LM_MAC_TS_OFFSET);
#ifdef CONFIG_LM_TIMESTAMP
#ifdef TIVA_ETHTS
regval = tiva_ethin(priv, TIVA_MAC_TS_OFFSET);
#ifdef CONFIG_TIVA_TIMESTAMP
regval |= MAC_TS_EN;
#else
regval &= ~(MAC_TS_EN);
#endif
tiva_ethout(priv, LM_MAC_TS_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_TS_OFFSET, regval);
nllvdbg("TS: %08x\n", regval);
#endif
@ -1106,41 +1106,41 @@ static int tiva_ifup(struct uip_driver_s *dev)
/* Reset the receive FIFO */
regval = tiva_ethin(priv, LM_MAC_RCTL_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_RCTL_OFFSET);
regval |= MAC_RCTL_RSTFIFO;
tiva_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_RCTL_OFFSET, regval);
/* Enable the Ethernet receiver */
regval = tiva_ethin(priv, LM_MAC_RCTL_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_RCTL_OFFSET);
regval |= MAC_RCTL_RXEN;
tiva_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_RCTL_OFFSET, regval);
/* Enable the Ethernet transmitter */
regval = tiva_ethin(priv, LM_MAC_TCTL_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_TCTL_OFFSET);
regval |= MAC_TCTL_TXEN;
tiva_ethout(priv, LM_MAC_TCTL_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_TCTL_OFFSET, regval);
/* Reset the receive FIFO (again) */
regval = tiva_ethin(priv, LM_MAC_RCTL_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_RCTL_OFFSET);
regval |= MAC_RCTL_RSTFIFO;
tiva_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_RCTL_OFFSET, regval);
/* Enable the Ethernet interrupt */
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
up_enable_irq(priv->irq);
#else
up_enable_irq(LM_IRQ_ETHCON);
up_enable_irq(TIVA_IRQ_ETHCON);
#endif
/* Enable the Ethernet RX packet receipt interrupt */
regval = tiva_ethin(priv, LM_MAC_IM_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_IM_OFFSET);
regval |= MAC_IM_RXINTM;
tiva_ethout(priv, LM_MAC_IM_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_IM_OFFSET, regval);
/* Program the hardware with it's MAC address (for filtering) */
@ -1148,15 +1148,15 @@ static int tiva_ifup(struct uip_driver_s *dev)
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 |
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 |
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0];
tiva_ethout(priv, LM_MAC_IA0_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_IA0_OFFSET, regval);
regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 |
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4];
tiva_ethout(priv, LM_MAC_IA1_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_IA1_OFFSET, regval);
/* Set and activate a timer process */
(void)wd_start(priv->ld_txpoll, LM_WDDELAY, tiva_polltimer, 1, (uint32_t)priv);
(void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_polltimer, 1, (uint32_t)priv);
priv->ld_bifup = true;
irqrestore(flags);
@ -1198,46 +1198,46 @@ static int tiva_ifdown(struct uip_driver_s *dev)
/* Disable the Ethernet interrupt */
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
up_disable_irq(priv->irq);
#else
up_disable_irq(LM_IRQ_ETHCON);
up_disable_irq(TIVA_IRQ_ETHCON);
#endif
/* Disable all Ethernet controller interrupt sources */
regval = tiva_ethin(priv, LM_MAC_IM_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_IM_OFFSET);
regval &= ~MAC_IM_ALLINTS;
tiva_ethout(priv, LM_MAC_IM_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_IM_OFFSET, regval);
/* Reset the receive FIFO */
regval = tiva_ethin(priv, LM_MAC_RCTL_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_RCTL_OFFSET);
regval |= MAC_RCTL_RSTFIFO;
tiva_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_RCTL_OFFSET, regval);
/* Disable the Ethernet receiver */
regval = tiva_ethin(priv, LM_MAC_RCTL_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_RCTL_OFFSET);
regval &= ~MAC_RCTL_RXEN;
tiva_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_RCTL_OFFSET, regval);
/* Disable the Ethernet transmitter */
regval = tiva_ethin(priv, LM_MAC_RCTL_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_RCTL_OFFSET);
regval &= ~MAC_TCTL_TXEN;
tiva_ethout(priv, LM_MAC_TCTL_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_TCTL_OFFSET, regval);
/* Reset the receive FIFO (again) */
regval = tiva_ethin(priv, LM_MAC_RCTL_OFFSET);
regval = tiva_ethin(priv, TIVA_MAC_RCTL_OFFSET);
regval |= MAC_RCTL_RSTFIFO;
tiva_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
tiva_ethout(priv, TIVA_MAC_RCTL_OFFSET, regval);
/* Clear any pending interrupts */
regval = tiva_ethin(priv, LM_MAC_RIS_OFFSET);
tiva_ethout(priv, LM_MAC_IACK_OFFSET, regval);
regval = tiva_ethin(priv, TIVA_MAC_RIS_OFFSET);
tiva_ethout(priv, TIVA_MAC_IACK_OFFSET, regval);
/* The interface is now DOWN */
@ -1279,7 +1279,7 @@ static int tiva_txavail(struct uip_driver_s *dev)
*/
flags = irqsave();
if (priv->ld_bifup && (tiva_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
if (priv->ld_bifup && (tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
{
/* If the interface is up and we can use the Tx FIFO, then poll uIP
* for new Tx data
@ -1372,7 +1372,7 @@ static int tiva_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
*
****************************************************************************/
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
int tiva_ethinitialize(int intf)
#else
static inline int tiva_ethinitialize(int intf)
@ -1385,12 +1385,12 @@ static inline int tiva_ethinitialize(int intf)
ndbg("Setting up eth%d\n", intf);
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
# error "This debug check only works with one interface"
#else
DEBUGASSERT((getreg32(LM_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
DEBUGASSERT((getreg32(TIVA_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
#endif
DEBUGASSERT((unsigned)intf < LM_NETHCONTROLLERS);
DEBUGASSERT((unsigned)intf < TIVA_NETHCONTROLLERS);
/* Initialize the driver structure */
@ -1406,7 +1406,7 @@ static inline int tiva_ethinitialize(int intf)
/* Create a watchdog for timing polling for and timing of transmisstions */
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
# error "A mechanism to associate base address an IRQ with an interface is needed"
priv->ld_base = ??; /* Ethernet controller base address */
priv->ld_irq = ??; /* Ethernet controller IRQ number */
@ -1419,7 +1419,7 @@ static inline int tiva_ethinitialize(int intf)
* is caleld (and the MAC can be overwritten with a netdev ioctl call).
*/
#ifdef CONFIG_LM_BOARDMAC
#ifdef CONFIG_TIVA_BOARDMAC
tiva_ethernetmac(&priv->ld_dev.d_mac);
#endif
@ -1433,10 +1433,10 @@ static inline int tiva_ethinitialize(int intf)
/* Attach the IRQ to the driver */
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
ret = irq_attach(priv->irq, tiva_interrupt);
#else
ret = irq_attach(LM_IRQ_ETHCON, tiva_interrupt);
ret = irq_attach(TIVA_IRQ_ETHCON, tiva_interrupt);
#endif
if (ret != 0)
{
@ -1462,12 +1462,11 @@ static inline int tiva_ethinitialize(int intf)
*
************************************************************************************/
#if LM_NETHCONTROLLERS == 1
#if TIVA_NETHCONTROLLERS == 1
void up_netinitialize(void)
{
(void)tiva_ethinitialize(0);
}
#endif
#endif /* CONFIG_NET && CONFIG_LM_ETHERNET */
#endif /* CONFIG_NET && CONFIG_TIVA_ETHERNET */

4
arch/arm/src/tiva/tiva_ethernet.h
View file

@ -44,7 +44,7 @@
#include "chip.h"
#if LM_NETHCONTROLLERS > 1
#if TIVA_NETHCONTROLLERS > 1
/************************************************************************************
* Pre-processor Definitions
@ -99,5 +99,5 @@ int tiva_ethinitialize(int intf);
#endif
#endif /* __ASSEMBLY__ */
#endif /* LM_NETHCONTROLLERS > 1 */
#endif /* TIVA_NETHCONTROLLERS > 1 */
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_ETHERNET_H */

50
arch/arm/src/tiva/tiva_flash.c
View file

@ -62,9 +62,9 @@
* Pre-processor Definitions
****************************************************************************/
#define LM_VIRTUAL_NPAGES (LM_FLASH_NPAGES - CONFIG_LM_FLASH_STARTPAGE)
#define LM_VIRTUAL_BASE (LM_FLASH_BASE \
+ CONFIG_LM_FLASH_STARTPAGE * LM_FLASH_PAGESIZE)
#define TIVA_VIRTUAL_NPAGES (TIVA_FLASH_NPAGES - CONFIG_TIVA_FLASH_STARTPAGE)
#define TIVA_VIRTUAL_BASE (TIVA_FLASH_BASE \
+ CONFIG_TIVA_FLASH_STARTPAGE * TIVA_FLASH_PAGESIZE)
/****************************************************************************
* Private Types
@ -140,26 +140,26 @@ static int tiva_erase(FAR struct mtd_dev_s *dev, off_t startblock,
int curpage;
uint32_t pageaddr;
DEBUGASSERT(nblocks <= LM_VIRTUAL_NPAGES);
DEBUGASSERT(nblocks <= TIVA_VIRTUAL_NPAGES);
for (curpage = startblock; curpage < nblocks; curpage++)
{
pageaddr = LM_VIRTUAL_BASE + curpage * LM_FLASH_PAGESIZE;
pageaddr = TIVA_VIRTUAL_BASE + curpage * TIVA_FLASH_PAGESIZE;
fvdbg("Erase page at %08x\n", pageaddr);
/* set page address */
putreg32((pageaddr << FLASH_FMA_OFFSET_SHIFT) & FLASH_FMA_OFFSET_MASK,
LM_FLASH_FMA);
TIVA_FLASH_FMA);
/* set flash write key and erase bit */
putreg32(FLASH_FMC_WRKEY | FLASH_FMC_ERASE, LM_FLASH_FMC);
putreg32(FLASH_FMC_WRKEY | FLASH_FMC_ERASE, TIVA_FLASH_FMC);
/* wait until erase has finished */
while (getreg32(LM_FLASH_FMC) & FLASH_FMC_ERASE);
while (getreg32(TIVA_FLASH_FMC) & FLASH_FMC_ERASE);
}
return OK;
@ -176,10 +176,10 @@ static int tiva_erase(FAR struct mtd_dev_s *dev, off_t startblock,
static ssize_t tiva_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
FAR uint8_t *buf)
{
DEBUGASSERT(startblock + nblocks <= LM_VIRTUAL_NPAGES);
DEBUGASSERT(startblock + nblocks <= TIVA_VIRTUAL_NPAGES);
memcpy(buf, (void*)(LM_VIRTUAL_BASE + startblock * LM_FLASH_PAGESIZE),
nblocks * LM_FLASH_PAGESIZE);
memcpy(buf, (void*)(TIVA_VIRTUAL_BASE + startblock * TIVA_FLASH_PAGESIZE),
nblocks * TIVA_FLASH_PAGESIZE);
return nblocks;
}
@ -196,28 +196,28 @@ static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
FAR const uint8_t *buf)
{
FAR uint32_t *src = (uint32_t*)buf;
FAR uint32_t *dst = (uint32_t*)(LM_VIRTUAL_BASE + startblock * LM_FLASH_PAGESIZE);
FAR uint32_t *dst = (uint32_t*)(TIVA_VIRTUAL_BASE + startblock * TIVA_FLASH_PAGESIZE);
int i;
DEBUGASSERT(nblocks <= LM_VIRTUAL_NPAGES);
DEBUGASSERT(nblocks <= TIVA_VIRTUAL_NPAGES);
for (i = 0; i < (nblocks * LM_FLASH_PAGESIZE) >> 2; i++)
for (i = 0; i < (nblocks * TIVA_FLASH_PAGESIZE) >> 2; i++)
{
/* set data to write */
putreg32(*src++, LM_FLASH_FMD);
putreg32(*src++, TIVA_FLASH_FMD);
/* set destination address */
putreg32((uint32_t)dst++, LM_FLASH_FMA);
putreg32((uint32_t)dst++, TIVA_FLASH_FMA);
/* start write */
putreg32(FLASH_FMC_WRKEY | FLASH_FMC_WRITE, LM_FLASH_FMC);
putreg32(FLASH_FMC_WRKEY | FLASH_FMC_WRITE, TIVA_FLASH_FMC);
/* wait until write has finished */
while(getreg32(LM_FLASH_FMC) & FLASH_FMC_WRITE);
while(getreg32(TIVA_FLASH_FMC) & FLASH_FMC_WRITE);
}
return nblocks;
@ -234,9 +234,9 @@ static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
static ssize_t tiva_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
FAR uint8_t *buf)
{
DEBUGASSERT(offset + nbytes < LM_VIRTUAL_NPAGES * LM_FLASH_PAGESIZE);
DEBUGASSERT(offset + nbytes < TIVA_VIRTUAL_NPAGES * TIVA_FLASH_PAGESIZE);
memcpy(buf, (void*)(LM_VIRTUAL_BASE + offset), nbytes);
memcpy(buf, (void*)(TIVA_VIRTUAL_BASE + offset), nbytes);
return nbytes;
}
@ -282,9 +282,9 @@ static int tiva_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
* appear so.
*/
geo->blocksize = LM_FLASH_PAGESIZE; /* Size of one read/write block */
geo->erasesize = LM_FLASH_PAGESIZE; /* Size of one erase block */
geo->neraseblocks = LM_VIRTUAL_NPAGES;
geo->blocksize = TIVA_FLASH_PAGESIZE; /* Size of one read/write block */
geo->erasesize = TIVA_FLASH_PAGESIZE; /* Size of one erase block */
geo->neraseblocks = TIVA_VIRTUAL_NPAGES;
ret = OK;
}
}
@ -301,7 +301,7 @@ static int tiva_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
* this case altogether and simply return -ENOTTY.
*/
*ppv = (void*)LM_VIRTUAL_BASE;
*ppv = (void*)TIVA_VIRTUAL_BASE;
ret = OK;
}
}
@ -311,7 +311,7 @@ static int tiva_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
{
/* Erase the entire device */
tiva_erase(dev, 0, LM_VIRTUAL_NPAGES);
tiva_erase(dev, 0, TIVA_VIRTUAL_NPAGES);
ret = OK;
}

127
arch/arm/src/tiva/tiva_gpio.c
View file

@ -146,34 +146,34 @@ static const struct gpio_func_s g_funcbits[] =
/* NOTE: this is duplicated in tiva_dumpgpio.c */
static const uintptr_t g_gpiobase[LM_NPORTS] =
static const uintptr_t g_gpiobase[TIVA_NPORTS] =
{
#if LM_NPORTS > 0
LM_GPIOA_BASE
#if TIVA_NPORTS > 0
TIVA_GPIOA_BASE
#endif
#if LM_NPORTS > 1
, LM_GPIOB_BASE
#if TIVA_NPORTS > 1
, TIVA_GPIOB_BASE
#endif
#if LM_NPORTS > 2
, LM_GPIOC_BASE
#if TIVA_NPORTS > 2
, TIVA_GPIOC_BASE
#endif
#if LM_NPORTS > 3
, LM_GPIOD_BASE
#if TIVA_NPORTS > 3
, TIVA_GPIOD_BASE
#endif
#if LM_NPORTS > 4
, LM_GPIOE_BASE
#if TIVA_NPORTS > 4
, TIVA_GPIOE_BASE
#endif
#if LM_NPORTS > 5
, LM_GPIOF_BASE
#if TIVA_NPORTS > 5
, TIVA_GPIOF_BASE
#endif
#if LM_NPORTS > 6
, LM_GPIOG_BASE
#if TIVA_NPORTS > 6
, TIVA_GPIOG_BASE
#endif
#if LM_NPORTS > 7
, LM_GPIOH_BASE
#if TIVA_NPORTS > 7
, TIVA_GPIOH_BASE
#endif
#if LM_NPORTS > 8
, LM_GPIOJ_BASE
#if TIVA_NPORTS > 8
, TIVA_GPIOJ_BASE
#endif
};
@ -197,7 +197,7 @@ static const uintptr_t g_gpiobase[LM_NPORTS] =
static uintptr_t tiva_gpiobaseaddress(unsigned int port)
{
uintptr_t gpiobase = 0;
if (port < LM_NPORTS)
if (port < TIVA_NPORTS)
{
gpiobase = g_gpiobase[port];
}
@ -234,10 +234,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno;
regval = getreg32(base + LM_GPIO_ODR_OFFSET);
regval = getreg32(base + TIVA_GPIO_ODR_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM_GPIO_ODR_OFFSET);
putreg32(regval, base + TIVA_GPIO_ODR_OFFSET);
/* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
* register. When a bit is set to 1, it enables a weak pull-up resistor on the
@ -250,10 +250,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
if (setbit || clrbit)
{
regval = getreg32(base + LM_GPIO_PUR_OFFSET);
regval = getreg32(base + TIVA_GPIO_PUR_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM_GPIO_PUR_OFFSET);
putreg32(regval, base + TIVA_GPIO_PUR_OFFSET);
}
/* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
@ -267,10 +267,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
if (setbit || clrbit)
{
regval = getreg32(base + LM_GPIO_PDR_OFFSET);
regval = getreg32(base + TIVA_GPIO_PDR_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM_GPIO_PDR_OFFSET);
putreg32(regval, base + TIVA_GPIO_PDR_OFFSET);
}
/* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
@ -285,10 +285,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno;
regval = getreg32(base + LM_GPIO_DEN_OFFSET);
regval = getreg32(base + TIVA_GPIO_DEN_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM_GPIO_DEN_OFFSET);
putreg32(regval, base + TIVA_GPIO_DEN_OFFSET);
/* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data
* direction register. Bits set to 1 in the GPIODIR register configure
@ -300,10 +300,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno;
regval = getreg32(base + LM_GPIO_DIR_OFFSET);
regval = getreg32(base + TIVA_GPIO_DIR_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM_GPIO_DIR_OFFSET);
putreg32(regval, base + TIVA_GPIO_DIR_OFFSET);
/* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode
* control select register. Writing a 1 to any bit in this register selects
@ -317,10 +317,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno;
regval = getreg32(base + LM_GPIO_AFSEL_OFFSET);
regval = getreg32(base + TIVA_GPIO_AFSEL_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM_GPIO_AFSEL_OFFSET);
putreg32(regval, base + TIVA_GPIO_AFSEL_OFFSET);
/* Set/clear/ignore the GPIO AMSEL bit. "The GPIOAMSEL register controls
* isolation circuits to the analog side of a unified I/O pad. Because
@ -334,10 +334,10 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
setbit = (((uint32_t)func->setbits >> AMSEL_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> AMSEL_SHIFT) & 1) << pinno;
regval = getreg32(base + LM_GPIO_AMSEL_OFFSET);
regval = getreg32(base + TIVA_GPIO_AMSEL_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM_GPIO_AMSEL_OFFSET);
putreg32(regval, base + TIVA_GPIO_AMSEL_OFFSET);
#endif
}
@ -374,7 +374,7 @@ static inline void tiva_gpiopadstrength(uint32_t base, uint32_t pin,
* DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
*/
regoffset = LM_GPIO_DR2R_OFFSET;
regoffset = TIVA_GPIO_DR2R_OFFSET;
}
break;
@ -387,7 +387,7 @@ static inline void tiva_gpiopadstrength(uint32_t base, uint32_t pin,
* in the GPIO DR8R register are automatically cleared by hardware."
*/
regoffset = LM_GPIO_DR4R_OFFSET;
regoffset = TIVA_GPIO_DR4R_OFFSET;
}
break;
@ -412,7 +412,7 @@ static inline void tiva_gpiopadstrength(uint32_t base, uint32_t pin,
* DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
*/
regoffset = LM_GPIO_DR8R_OFFSET;
regoffset = TIVA_GPIO_DR8R_OFFSET;
}
break;
}
@ -423,10 +423,10 @@ static inline void tiva_gpiopadstrength(uint32_t base, uint32_t pin,
regval |= pin;
putreg32(regval, base + regoffset);
regval = getreg32(base + LM_GPIO_SLR_OFFSET);
regval = getreg32(base + TIVA_GPIO_SLR_OFFSET);
regval &= slrclr;
regval |= slrset;
putreg32(regval, base + LM_GPIO_SLR_OFFSET);
putreg32(regval, base + TIVA_GPIO_SLR_OFFSET);
}
/****************************************************************************
@ -542,10 +542,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
*/
#if 0 /* always overwritten by tiva_gpiofunc */
regval = getreg32(base + LM_GPIO_ODR_OFFSET);
regval = getreg32(base + TIVA_GPIO_ODR_OFFSET);
regval &= ~odrclr;
regval |= odrset;
putreg32(regval, base + LM_GPIO_ODR_OFFSET);
putreg32(regval, base + TIVA_GPIO_ODR_OFFSET);
#endif
/* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
@ -554,10 +554,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
* corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
*/
regval = getreg32(base + LM_GPIO_PUR_OFFSET);
regval = getreg32(base + TIVA_GPIO_PUR_OFFSET);
regval &= ~purclr;
regval |= purset;
putreg32(regval, base + LM_GPIO_PUR_OFFSET);
putreg32(regval, base + TIVA_GPIO_PUR_OFFSET);
/* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
* register. When a bit is set to 1, it enables a weak pull-down resistor on the
@ -565,10 +565,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
* the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
*/
regval = getreg32(base + LM_GPIO_PDR_OFFSET);
regval = getreg32(base + TIVA_GPIO_PDR_OFFSET);
regval &= ~pdrclr;
regval |= pdrset;
putreg32(regval, base + LM_GPIO_PDR_OFFSET);
putreg32(regval, base + TIVA_GPIO_PDR_OFFSET);
/* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
* register. By default, with the exception of the GPIO signals used for JTAG/SWD
@ -580,10 +580,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
*/
#if 0 /* always overwritten by tiva_gpiofunc */
regval = getreg32(base + LM_GPIO_DEN_OFFSET);
regval = getreg32(base + TIVA_GPIO_DEN_OFFSET);
regval &= ~denclr;
regval |= denset;
putreg32(regval, base + LM_GPIO_DEN_OFFSET);
putreg32(regval, base + TIVA_GPIO_DEN_OFFSET);
#endif
}
@ -628,18 +628,18 @@ static inline void tiva_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
* on that pin. All bits are cleared by a reset."
*/
regval = getreg32(base + LM_GPIO_IM_OFFSET);
regval = getreg32(base + TIVA_GPIO_IM_OFFSET);
regval &= ~pin;
putreg32(regval, base + LM_GPIO_IM_OFFSET);
putreg32(regval, base + TIVA_GPIO_IM_OFFSET);
/* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
* in this register clears the corresponding interrupt edge detection logic
* register. Writing a 0 has no effect."
*/
regval = getreg32(base + LM_GPIO_ICR_OFFSET);
regval = getreg32(base + TIVA_GPIO_ICR_OFFSET);
regval |= pin;
putreg32(regval, base + LM_GPIO_ICR_OFFSET);
putreg32(regval, base + TIVA_GPIO_ICR_OFFSET);
/* Assume rising edge */
@ -695,10 +695,10 @@ static inline void tiva_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
* by a reset.
*/
regval = getreg32(base + LM_GPIO_IS_OFFSET);
regval = getreg32(base + TIVA_GPIO_IS_OFFSET);
regval &= isclr;
regval |= isset;
putreg32(regval, base + LM_GPIO_IS_OFFSET);
putreg32(regval, base + TIVA_GPIO_IS_OFFSET);
/* "The GPIO IBE register is the interrupt both-edges register. When the
* corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
@ -709,10 +709,10 @@ static inline void tiva_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
* are cleared by a reset.
*/
regval = getreg32(base + LM_GPIO_IBE_OFFSET);
regval = getreg32(base + TIVA_GPIO_IBE_OFFSET);
regval &= ibeclr;
regval |= ibeset;
putreg32(regval, base + LM_GPIO_IBE_OFFSET);
putreg32(regval, base + TIVA_GPIO_IBE_OFFSET);
/* "The GPIOIEV register is the interrupt event register. Bits set to
* High in GPIO IEV configure the corresponding pin to detect rising edges
@ -722,10 +722,10 @@ static inline void tiva_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
* value in GPIOIS. All bits are cleared by a reset.
*/
regval = getreg32(base + LM_GPIO_IEV_OFFSET);
regval = getreg32(base + TIVA_GPIO_IEV_OFFSET);
regval &= iveclr;
regval |= iveset;
putreg32(regval, base + LM_GPIO_IEV_OFFSET);
putreg32(regval, base + TIVA_GPIO_IEV_OFFSET);
}
/****************************************************************************
@ -758,11 +758,11 @@ static inline void tiva_portcontrol(uint32_t base, uint32_t pinno,
/* Set the alternate function in the port control register */
regval = getreg32(base + LM_GPIO_PCTL_OFFSET);
regval = getreg32(base + TIVA_GPIO_PCTL_OFFSET);
mask = GPIO_PCTL_PMC_MASK(pinno);
regval &= ~mask;
regval |= (alt << GPIO_PCTL_PMC_SHIFT(pinno)) & mask;
putreg32(regval, base + LM_GPIO_PCTL_OFFSET);
putreg32(regval, base + TIVA_GPIO_PCTL_OFFSET);
}
#else
# define tiva_portcontrol(b,p,c,f)
@ -813,9 +813,9 @@ int tiva_configgpio(uint32_t cfgset)
* in the RCGC2 register."
*/
regval = getreg32(LM_SYSCON_RCGC2);
regval = getreg32(TIVA_SYSCON_RCGC2);
regval |= SYSCON_RCGC2_GPIO(port);
putreg32(regval, LM_SYSCON_RCGC2);
putreg32(regval, TIVA_SYSCON_RCGC2);
/* First, set the port to digital input. This is the safest state in which
* to perform reconfiguration.
@ -890,7 +890,7 @@ void tiva_gpiowrite(uint32_t pinset, bool value)
* "... All bits are cleared by a reset."
*/
putreg32((uint32_t)value << pinno, base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
putreg32((uint32_t)value << pinno, base + TIVA_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
}
/****************************************************************************
@ -929,6 +929,5 @@ bool tiva_gpioread(uint32_t pinset, bool value)
* are cleared by a reset."
*/
return (getreg32(base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
return (getreg32(base + TIVA_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
}

138
arch/arm/src/tiva/tiva_gpioirq.c
View file

@ -71,34 +71,34 @@ static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
static const uintptr_t g_gpiobase[] =
{
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
LM_GPIOA_BASE
#ifndef CONFIG_TIVA_DISABLE_GPIOA_IRQS
TIVA_GPIOA_BASE
#else
0
#endif
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
, LM_GPIOB_BASE
#ifndef CONFIG_TIVA_DISABLE_GPIOB_IRQS
, TIVA_GPIOB_BASE
#endif
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
, LM_GPIOC_BASE
#ifndef CONFIG_TIVA_DISABLE_GPIOC_IRQS
, TIVA_GPIOC_BASE
#endif
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
, LM_GPIOD_BASE
#ifndef CONFIG_TIVA_DISABLE_GPIOD_IRQS
, TIVA_GPIOD_BASE
#endif
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
, LM_GPIOE_BASE
#ifndef CONFIG_TIVA_DISABLE_GPIOE_IRQS
, TIVA_GPIOE_BASE
#endif
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
, LM_GPIOF_BASE
#ifndef CONFIG_TIVA_DISABLE_GPIOF_IRQS
, TIVA_GPIOF_BASE
#endif
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
, LM_GPIOG_BASE
#ifndef CONFIG_TIVA_DISABLE_GPIOG_IRQS
, TIVA_GPIOG_BASE
#endif
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
, LM_GPIOH_BASE
#ifndef CONFIG_TIVA_DISABLE_GPIOH_IRQS
, TIVA_GPIOH_BASE
#endif
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
, LM_GPIOJ_BASE
#ifndef CONFIG_TIVA_DISABLE_GPIOJ_IRQS
, TIVA_GPIOJ_BASE
#endif
};
@ -156,7 +156,7 @@ static int tiva_gpiohandler(uint32_t regbase, int irqbase, void *context)
* either no interrupt has been generated, or the interrupt is masked."
*/
mis = getreg32(regbase + LM_GPIO_MIS_OFFSET) & 0xff;
mis = getreg32(regbase + TIVA_GPIO_MIS_OFFSET) & 0xff;
/* Clear all GPIO interrupts that we are going to process. "The GPIO ICR
* register is the interrupt clear register. Writing a 1 to a bit in this
@ -164,7 +164,7 @@ static int tiva_gpiohandler(uint32_t regbase, int irqbase, void *context)
* Writing a 0 has no effect."
*/
putreg32(mis, regbase + LM_GPIO_ICR_OFFSET);
putreg32(mis, regbase + TIVA_GPIO_ICR_OFFSET);
/* Now process each IRQ pending in the MIS */
@ -179,66 +179,66 @@ static int tiva_gpiohandler(uint32_t regbase, int irqbase, void *context)
return OK;
}
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIOA_IRQS
static int tiva_gpioahandler(int irq, FAR void *context)
{
return tiva_gpiohandler(LM_GPIOA_BASE, LM_IRQ_GPIOA_0, context);
return tiva_gpiohandler(TIVA_GPIOA_BASE, TIVA_IRQ_GPIOA_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIOB_IRQS
static int tiva_gpiobhandler(int irq, FAR void *context)
{
return tiva_gpiohandler(LM_GPIOB_BASE, LM_IRQ_GPIOB_0, context);
return tiva_gpiohandler(TIVA_GPIOB_BASE, TIVA_IRQ_GPIOB_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIOC_IRQS
static int tiva_gpiochandler(int irq, FAR void *context)
{
return tiva_gpiohandler(LM_GPIOC_BASE, LM_IRQ_GPIOC_0, context);
return tiva_gpiohandler(TIVA_GPIOC_BASE, TIVA_IRQ_GPIOC_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIOD_IRQS
static int tiva_gpiodhandler(int irq, FAR void *context)
{
return tiva_gpiohandler(LM_GPIOD_BASE, LM_IRQ_GPIOD_0, context);
return tiva_gpiohandler(TIVA_GPIOD_BASE, TIVA_IRQ_GPIOD_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIOE_IRQS
static int tiva_gpioehandler(int irq, FAR void *context)
{
return tiva_gpiohandler(LM_GPIOE_BASE, LM_IRQ_GPIOE_0, context);
return tiva_gpiohandler(TIVA_GPIOE_BASE, TIVA_IRQ_GPIOE_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIOF_IRQS
static int tiva_gpiofhandler(int irq, FAR void *context)
{
return tiva_gpiohandler(LM_GPIOF_BASE, LM_IRQ_GPIOF_0, context);
return tiva_gpiohandler(TIVA_GPIOF_BASE, TIVA_IRQ_GPIOF_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIOG_IRQS
static int tiva_gpioghandler(int irq, FAR void *context)
{
return tiva_gpiohandler(LM_GPIOG_BASE, LM_IRQ_GPIOG_0, context);
return tiva_gpiohandler(TIVA_GPIOG_BASE, TIVA_IRQ_GPIOG_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIOH_IRQS
static int tiva_gpiohhandler(int irq, FAR void *context)
{
return tiva_gpiohandler(LM_GPIOH_BASE, LM_IRQ_GPIOH_0, context);
return tiva_gpiohandler(TIVA_GPIOH_BASE, TIVA_IRQ_GPIOH_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIOJ_IRQS
static int tiva_gpiojhandler(int irq, FAR void *context)
{
return tiva_gpiohandler(LM_GPIOJ_BASE, LM_IRQ_GPIOJ_0, context);
return tiva_gpiohandler(TIVA_GPIOJ_BASE, TIVA_IRQ_GPIOJ_0, context);
}
#endif
@ -269,41 +269,41 @@ int gpio_irqinitialize(void)
* interrupts
*/
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
irq_attach(LM_IRQ_GPIOA, tiva_gpioahandler);
up_enable_irq(LM_IRQ_GPIOA);
#ifndef CONFIG_TIVA_DISABLE_GPIOA_IRQS
irq_attach(TIVA_IRQ_GPIOA, tiva_gpioahandler);
up_enable_irq(TIVA_IRQ_GPIOA);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
irq_attach(LM_IRQ_GPIOB, tiva_gpiobhandler);
up_enable_irq(LM_IRQ_GPIOB);
#ifndef CONFIG_TIVA_DISABLE_GPIOB_IRQS
irq_attach(TIVA_IRQ_GPIOB, tiva_gpiobhandler);
up_enable_irq(TIVA_IRQ_GPIOB);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
irq_attach(LM_IRQ_GPIOC, tiva_gpiochandler);
up_enable_irq(LM_IRQ_GPIOC);
#ifndef CONFIG_TIVA_DISABLE_GPIOC_IRQS
irq_attach(TIVA_IRQ_GPIOC, tiva_gpiochandler);
up_enable_irq(TIVA_IRQ_GPIOC);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
irq_attach(LM_IRQ_GPIOD, tiva_gpiodhandler);
up_enable_irq(LM_IRQ_GPIOD);
#ifndef CONFIG_TIVA_DISABLE_GPIOD_IRQS
irq_attach(TIVA_IRQ_GPIOD, tiva_gpiodhandler);
up_enable_irq(TIVA_IRQ_GPIOD);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
irq_attach(LM_IRQ_GPIOE, tiva_gpioehandler);
up_enable_irq(LM_IRQ_GPIOE);
#ifndef CONFIG_TIVA_DISABLE_GPIOE_IRQS
irq_attach(TIVA_IRQ_GPIOE, tiva_gpioehandler);
up_enable_irq(TIVA_IRQ_GPIOE);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
irq_attach(LM_IRQ_GPIOF, tiva_gpiofhandler);
up_enable_irq(LM_IRQ_GPIOF);
#ifndef CONFIG_TIVA_DISABLE_GPIOF_IRQS
irq_attach(TIVA_IRQ_GPIOF, tiva_gpiofhandler);
up_enable_irq(TIVA_IRQ_GPIOF);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
irq_attach(LM_IRQ_GPIOG, tiva_gpioghandler);
up_enable_irq(LM_IRQ_GPIOG);
#ifndef CONFIG_TIVA_DISABLE_GPIOG_IRQS
irq_attach(TIVA_IRQ_GPIOG, tiva_gpioghandler);
up_enable_irq(TIVA_IRQ_GPIOG);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
irq_attach(LM_IRQ_GPIOH, tiva_gpiohhandler);
up_enable_irq(LM_IRQ_GPIOH);
#ifndef CONFIG_TIVA_DISABLE_GPIOH_IRQS
irq_attach(TIVA_IRQ_GPIOH, tiva_gpiohhandler);
up_enable_irq(TIVA_IRQ_GPIOH);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
irq_attach(LM_IRQ_GPIOJ, tiva_gpiojhandler);
up_enable_irq(LM_IRQ_GPIOJ);
#ifndef CONFIG_TIVA_DISABLE_GPIOJ_IRQS
irq_attach(TIVA_IRQ_GPIOJ, tiva_gpiojhandler);
up_enable_irq(TIVA_IRQ_GPIOJ);
#endif
return OK;
@ -381,9 +381,9 @@ void gpio_irqenable(int irq)
*/
flags = irqsave();
regval = getreg32(base + LM_GPIO_IM_OFFSET);
regval = getreg32(base + TIVA_GPIO_IM_OFFSET);
regval |= pin;
putreg32(regval, base + LM_GPIO_IM_OFFSET);
putreg32(regval, base + TIVA_GPIO_IM_OFFSET);
irqrestore(flags);
}
}
@ -420,9 +420,9 @@ void gpio_irqdisable(int irq)
*/
flags = irqsave();
regval = getreg32(base + LM_GPIO_IM_OFFSET);
regval = getreg32(base + TIVA_GPIO_IM_OFFSET);
regval &= ~pin;
putreg32(regval, base + LM_GPIO_IM_OFFSET);
putreg32(regval, base + TIVA_GPIO_IM_OFFSET);
irqrestore(flags);
}
}

54
arch/arm/src/tiva/tiva_irq.c
View file

@ -226,21 +226,21 @@ static inline void tiva_prioritize_syscall(int priority)
static int tiva_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
DEBUGASSERT(irq >= LM_IRQ_NMI && irq < NR_IRQS);
DEBUGASSERT(irq >= TIVA_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= LM_IRQ_INTERRUPTS)
if (irq >= TIVA_IRQ_INTERRUPTS)
{
if (irq < LM_IRQ_INTERRUPTS + 32)
if (irq < TIVA_IRQ_INTERRUPTS + 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - LM_IRQ_INTERRUPTS);
*bit = 1 << (irq - TIVA_IRQ_INTERRUPTS);
}
else if (irq < NR_IRQS)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - LM_IRQ_INTERRUPTS - 32);
*bit = 1 << (irq - TIVA_IRQ_INTERRUPTS - 32);
}
else
{
@ -253,19 +253,19 @@ static int tiva_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
else
{
*regaddr = NVIC_SYSHCON;
if (irq == LM_IRQ_MEMFAULT)
if (irq == TIVA_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == LM_IRQ_BUSFAULT)
else if (irq == TIVA_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == LM_IRQ_USAGEFAULT)
else if (irq == TIVA_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == LM_IRQ_SYSTICK)
else if (irq == TIVA_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
@ -327,7 +327,7 @@ void up_irqinitialize(void)
/* Initialize support for GPIO interrupts if included in this build */
#ifndef CONFIG_LM_DISABLE_GPIO_IRQS
#ifndef CONFIG_TIVA_DISABLE_GPIO_IRQS
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
if (gpio_irqinitialize != NULL)
#endif
@ -342,13 +342,13 @@ void up_irqinitialize(void)
* under certain conditions.
*/
irq_attach(LM_IRQ_SVCALL, up_svcall);
irq_attach(LM_IRQ_HARDFAULT, up_hardfault);
irq_attach(TIVA_IRQ_SVCALL, up_svcall);
irq_attach(TIVA_IRQ_HARDFAULT, up_hardfault);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(TIVA_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
tiva_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
@ -359,22 +359,22 @@ void up_irqinitialize(void)
*/
#ifdef CONFIG_ARMV7M_MPU
irq_attach(LM_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LM_IRQ_MEMFAULT);
irq_attach(TIVA_IRQ_MEMFAULT, up_memfault);
up_enable_irq(TIVA_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(LM_IRQ_NMI, tiva_nmi);
irq_attach(TIVA_IRQ_NMI, tiva_nmi);
#ifndef CONFIG_ARMV7M_MPU
irq_attach(LM_IRQ_MEMFAULT, up_memfault);
irq_attach(TIVA_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LM_IRQ_BUSFAULT, tiva_busfault);
irq_attach(LM_IRQ_USAGEFAULT, tiva_usagefault);
irq_attach(LM_IRQ_PENDSV, tiva_pendsv);
irq_attach(LM_IRQ_DBGMONITOR, tiva_dbgmonitor);
irq_attach(LM_IRQ_RESERVED, tiva_reserved);
irq_attach(TIVA_IRQ_BUSFAULT, tiva_busfault);
irq_attach(TIVA_IRQ_USAGEFAULT, tiva_usagefault);
irq_attach(TIVA_IRQ_PENDSV, tiva_pendsv);
irq_attach(TIVA_IRQ_DBGMONITOR, tiva_dbgmonitor);
irq_attach(TIVA_IRQ_RESERVED, tiva_reserved);
#endif
tiva_dumpnvic("initial", NR_IRQS);
@ -409,7 +409,7 @@ void up_disable_irq(int irq)
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= LM_IRQ_INTERRUPTS)
if (irq >= TIVA_IRQ_INTERRUPTS)
{
putreg32(bit, regaddr);
}
@ -446,7 +446,7 @@ void up_enable_irq(int irq)
* set the bit in the System Handler Control and State Register.
*/
if (irq >= LM_IRQ_INTERRUPTS)
if (irq >= TIVA_IRQ_INTERRUPTS)
{
putreg32(bit, regaddr);
}
@ -491,10 +491,10 @@ int up_prioritize_irq(int irq, int priority)
uint32_t regval;
int shift;
DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS &&
DEBUGASSERT(irq >= TIVA_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < LM_IRQ_INTERRUPTS)
if (irq < TIVA_IRQ_INTERRUPTS)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
@ -507,7 +507,7 @@ int up_prioritize_irq(int irq, int priority)
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= LM_IRQ_INTERRUPTS;
irq -= TIVA_IRQ_INTERRUPTS;
regaddr = NVIC_IRQ_PRIORITY(irq);
}

178
arch/arm/src/tiva/tiva_lowputc.c
View file

@ -59,82 +59,82 @@
/* Select UART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define LM_CONSOLE_BASE LM_UART0_BASE
# define LM_CONSOLE_BAUD CONFIG_UART0_BAUD
# define LM_CONSOLE_BITS CONFIG_UART0_BITS
# define LM_CONSOLE_PARITY CONFIG_UART0_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART0_2STOP
# define TIVA_CONSOLE_BASE TIVA_UART0_BASE
# define TIVA_CONSOLE_BAUD CONFIG_UART0_BAUD
# define TIVA_CONSOLE_BITS CONFIG_UART0_BITS
# define TIVA_CONSOLE_PARITY CONFIG_UART0_PARITY
# define TIVA_CONSOLE_2STOP CONFIG_UART0_2STOP
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define LM_CONSOLE_BASE LM_UART1_BASE
# define LM_CONSOLE_BAUD CONFIG_UART1_BAUD
# define LM_CONSOLE_BITS CONFIG_UART1_BITS
# define LM_CONSOLE_PARITY CONFIG_UART1_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART1_2STOP
# define TIVA_CONSOLE_BASE TIVA_UART1_BASE
# define TIVA_CONSOLE_BAUD CONFIG_UART1_BAUD
# define TIVA_CONSOLE_BITS CONFIG_UART1_BITS
# define TIVA_CONSOLE_PARITY CONFIG_UART1_PARITY
# define TIVA_CONSOLE_2STOP CONFIG_UART1_2STOP
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define LM_CONSOLE_BASE LM_UART2_BASE
# define LM_CONSOLE_BAUD CONFIG_UART2_BAUD
# define LM_CONSOLE_BITS CONFIG_UART2_BITS
# define LM_CONSOLE_PARITY CONFIG_UART2_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART2_2STOP
# define TIVA_CONSOLE_BASE TIVA_UART2_BASE
# define TIVA_CONSOLE_BAUD CONFIG_UART2_BAUD
# define TIVA_CONSOLE_BITS CONFIG_UART2_BITS
# define TIVA_CONSOLE_PARITY CONFIG_UART2_PARITY
# define TIVA_CONSOLE_2STOP CONFIG_UART2_2STOP
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
# define LM_CONSOLE_BASE LM_UART3_BASE
# define LM_CONSOLE_BAUD CONFIG_UART3_BAUD
# define LM_CONSOLE_BITS CONFIG_UART3_BITS
# define LM_CONSOLE_PARITY CONFIG_UART3_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART3_2STOP
# define TIVA_CONSOLE_BASE TIVA_UART3_BASE
# define TIVA_CONSOLE_BAUD CONFIG_UART3_BAUD
# define TIVA_CONSOLE_BITS CONFIG_UART3_BITS
# define TIVA_CONSOLE_PARITY CONFIG_UART3_PARITY
# define TIVA_CONSOLE_2STOP CONFIG_UART3_2STOP
#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define LM_CONSOLE_BASE LM_UART4_BASE
# define LM_CONSOLE_BAUD CONFIG_UART4_BAUD
# define LM_CONSOLE_BITS CONFIG_UART4_BITS
# define LM_CONSOLE_PARITY CONFIG_UART4_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART4_2STOP
# define TIVA_CONSOLE_BASE TIVA_UART4_BASE
# define TIVA_CONSOLE_BAUD CONFIG_UART4_BAUD
# define TIVA_CONSOLE_BITS CONFIG_UART4_BITS
# define TIVA_CONSOLE_PARITY CONFIG_UART4_PARITY
# define TIVA_CONSOLE_2STOP CONFIG_UART4_2STOP
#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define LM_CONSOLE_BASE LM_UART5_BASE
# define LM_CONSOLE_BAUD CONFIG_UART5_BAUD
# define LM_CONSOLE_BITS CONFIG_UART5_BITS
# define LM_CONSOLE_PARITY CONFIG_UART5_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART5_2STOP
# define TIVA_CONSOLE_BASE TIVA_UART5_BASE
# define TIVA_CONSOLE_BAUD CONFIG_UART5_BAUD
# define TIVA_CONSOLE_BITS CONFIG_UART5_BITS
# define TIVA_CONSOLE_PARITY CONFIG_UART5_PARITY
# define TIVA_CONSOLE_2STOP CONFIG_UART5_2STOP
#elif defined(CONFIG_UART6_SERIAL_CONSOLE)
# define LM_CONSOLE_BASE LM_UART6_BASE
# define LM_CONSOLE_BAUD CONFIG_UART6_BAUD
# define LM_CONSOLE_BITS CONFIG_UART6_BITS
# define LM_CONSOLE_PARITY CONFIG_UART6_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART6_2STOP
# define TIVA_CONSOLE_BASE TIVA_UART6_BASE
# define TIVA_CONSOLE_BAUD CONFIG_UART6_BAUD
# define TIVA_CONSOLE_BITS CONFIG_UART6_BITS
# define TIVA_CONSOLE_PARITY CONFIG_UART6_PARITY
# define TIVA_CONSOLE_2STOP CONFIG_UART6_2STOP
#elif defined(CONFIG_UART7_SERIAL_CONSOLE)
# define LM_CONSOLE_BASE LM_UART7_BASE
# define LM_CONSOLE_BAUD CONFIG_UART7_BAUD
# define LM_CONSOLE_BITS CONFIG_UART7_BITS
# define LM_CONSOLE_PARITY CONFIG_UART7_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART7_2STOP
# define TIVA_CONSOLE_BASE TIVA_UART7_BASE
# define TIVA_CONSOLE_BAUD CONFIG_UART7_BAUD
# define TIVA_CONSOLE_BITS CONFIG_UART7_BITS
# define TIVA_CONSOLE_PARITY CONFIG_UART7_PARITY
# define TIVA_CONSOLE_2STOP CONFIG_UART7_2STOP
#else
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
#endif
/* Get LCRH settings */
#if LM_CONSOLE_BITS == 5
#if TIVA_CONSOLE_BITS == 5
# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
#elif LM_CONSOLE_BITS == 6
#elif TIVA_CONSOLE_BITS == 6
# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
#elif LM_CONSOLE_BITS == 7
#elif TIVA_CONSOLE_BITS == 7
# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
#elif LM_CONSOLE_BITS == 8
#elif TIVA_CONSOLE_BITS == 8
# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
#else
# error "Number of bits not supported"
#endif
#if LM_CONSOLE_PARITY == 0
#if TIVA_CONSOLE_PARITY == 0
# define UART_LCRH_PARITY (0)
#elif LM_CONSOLE_PARITY == 1
#elif TIVA_CONSOLE_PARITY == 1
# define UART_LCRH_PARITY UART_LCRH_PEN
#elif LM_CONSOLE_PARITY == 2
#elif TIVA_CONSOLE_PARITY == 2
# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
#else
# error "Invalid parity selection"
#endif
#if LM_CONSOLE_2STOP != 0
#if TIVA_CONSOLE_2STOP != 0
# define UART_LCRH_NSTOP UART_LCRH_STP2
#else
# define UART_LCRH_NSTOP (0)
@ -174,17 +174,17 @@
* divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
*/
#define LM_BRDDEN (16 * LM_CONSOLE_BAUD)
#define LM_BRDI (SYSCLK_FREQUENCY / LM_BRDDEN)
#define LM_REMAINDER (SYSCLK_FREQUENCY - LM_BRDDEN * LM_BRDI)
#define LM_DIVFRAC ((LM_REMAINDER * 64 + (LM_BRDDEN/2)) / LM_BRDDEN)
#define TIVA_BRDDEN (16 * TIVA_CONSOLE_BAUD)
#define TIVA_BRDI (SYSCLK_FREQUENCY / TIVA_BRDDEN)
#define TIVA_REMAINDER (SYSCLK_FREQUENCY - TIVA_BRDDEN * TIVA_BRDI)
#define TIVA_DIVFRAC ((TIVA_REMAINDER * 64 + (TIVA_BRDDEN/2)) / TIVA_BRDDEN)
/* For example: LM_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
/* For example: TIVA_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
*
* LM_BRDDEN = (16 * 115,200) = 1,843,200
* LM_BRDI = 50,000,000 / 1,843,200 = 27
* LM_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600
* LM_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8
* TIVA_BRDDEN = (16 * 115,200) = 1,843,200
* TIVA_BRDI = 50,000,000 / 1,843,200 = 27
* TIVA_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600
* TIVA_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8
*
* Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
*/
@ -226,11 +226,11 @@ void up_lowputc(char ch)
#ifdef HAVE_SERIAL_CONSOLE
/* Wait until the TX FIFO is not full */
while ((getreg32(LM_CONSOLE_BASE+LM_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
while ((getreg32(TIVA_CONSOLE_BASE+TIVA_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
/* Then send the character */
putreg32((uint32_t)ch, LM_CONSOLE_BASE+LM_UART_DR_OFFSET);
putreg32((uint32_t)ch, TIVA_CONSOLE_BASE+TIVA_UART_DR_OFFSET);
#endif
}
@ -256,73 +256,73 @@ void up_lowsetup(void)
* this pin configuration -- whether or not a serial console is selected.
*/
#ifdef CONFIG_LM_UART0
regval = getreg32(LM_SYSCON_RCGC1);
#ifdef CONFIG_TIVA_UART0
regval = getreg32(TIVA_SYSCON_RCGC1);
regval |= SYSCON_RCGC1_UART0;
putreg32(regval, LM_SYSCON_RCGC1);
putreg32(regval, TIVA_SYSCON_RCGC1);
tiva_configgpio(GPIO_UART0_RX);
tiva_configgpio(GPIO_UART0_TX);
#endif
#ifdef CONFIG_LM_UART1
regval = getreg32(LM_SYSCON_RCGC1);
#ifdef CONFIG_TIVA_UART1
regval = getreg32(TIVA_SYSCON_RCGC1);
regval |= SYSCON_RCGC1_UART1;
putreg32(regval, LM_SYSCON_RCGC1);
putreg32(regval, TIVA_SYSCON_RCGC1);
tiva_configgpio(GPIO_UART1_RX);
tiva_configgpio(GPIO_UART1_TX);
#endif
#ifdef CONFIG_LM_UART2
regval = getreg32(LM_SYSCON_RCGC1);
#ifdef CONFIG_TIVA_UART2
regval = getreg32(TIVA_SYSCON_RCGC1);
regval |= SYSCON_RCGC1_UART2;
putreg32(regval, LM_SYSCON_RCGC1);
putreg32(regval, TIVA_SYSCON_RCGC1);
tiva_configgpio(GPIO_UART2_RX);
tiva_configgpio(GPIO_UART2_TX);
#endif
#ifdef CONFIG_LM_UART3
regval = getreg32(LM_SYSCON_RCGCUART);
#ifdef CONFIG_TIVA_UART3
regval = getreg32(TIVA_SYSCON_RCGCUART);
regval |= SYSCON_RCGCUART_R3;
putreg32(regval, LM_SYSCON_RCGCUART);
putreg32(regval, TIVA_SYSCON_RCGCUART);
tiva_configgpio(GPIO_UART3_RX);
tiva_configgpio(GPIO_UART3_TX);
#endif
#ifdef CONFIG_LM_UART4
regval = getreg32(LM_SYSCON_RCGCUART);
#ifdef CONFIG_TIVA_UART4
regval = getreg32(TIVA_SYSCON_RCGCUART);
regval |= SYSCON_RCGCUART_R4;
putreg32(regval, LM_SYSCON_RCGCUART);
putreg32(regval, TIVA_SYSCON_RCGCUART);
tiva_configgpio(GPIO_UART4_RX);
tiva_configgpio(GPIO_UART4_TX);
#endif
#ifdef CONFIG_LM_UART5
regval = getreg32(LM_SYSCON_RCGCUART);
#ifdef CONFIG_TIVA_UART5
regval = getreg32(TIVA_SYSCON_RCGCUART);
regval |= SYSCON_RCGCUART_R5;
putreg32(regval, LM_SYSCON_RCGCUART);
putreg32(regval, TIVA_SYSCON_RCGCUART);
tiva_configgpio(GPIO_UART5_RX);
tiva_configgpio(GPIO_UART5_TX);
#endif
#ifdef CONFIG_LM_UART6
regval = getreg32(LM_SYSCON_RCGCUART);
#ifdef CONFIG_TIVA_UART6
regval = getreg32(TIVA_SYSCON_RCGCUART);
regval |= SYSCON_RCGCUART_R6;
putreg32(regval, LM_SYSCON_RCGCUART);
putreg32(regval, TIVA_SYSCON_RCGCUART);
tiva_configgpio(GPIO_UART6_RX);
tiva_configgpio(GPIO_UART6_TX);
#endif
#ifdef CONFIG_LM_UART7
regval = getreg32(LM_SYSCON_RCGCUART);
#ifdef CONFIG_TIVA_UART7
regval = getreg32(TIVA_SYSCON_RCGCUART);
regval |= SYSCON_RCGCUART_R7;
putreg32(regval, LM_SYSCON_RCGCUART);
putreg32(regval, TIVA_SYSCON_RCGCUART);
tiva_configgpio(GPIO_UART7_RX);
tiva_configgpio(GPIO_UART7_TX);
@ -333,25 +333,25 @@ void up_lowsetup(void)
#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
ctl = getreg32(LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
ctl = getreg32(TIVA_CONSOLE_BASE+TIVA_UART_CTL_OFFSET);
ctl &= ~UART_CTL_UARTEN;
putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
putreg32(ctl, TIVA_CONSOLE_BASE+TIVA_UART_CTL_OFFSET);
/* Write the integer portion of the BRD to the UART IBRD register */
putreg32(LM_BRDI, LM_CONSOLE_BASE+LM_UART_IBRD_OFFSET);
putreg32(TIVA_BRDI, TIVA_CONSOLE_BASE+TIVA_UART_IBRD_OFFSET);
/* Write the fractional portion of the BRD to the UART FBRD register */
putreg32(LM_DIVFRAC, LM_CONSOLE_BASE+LM_UART_FBRD_OFFSET);
putreg32(TIVA_DIVFRAC, TIVA_CONSOLE_BASE+TIVA_UART_FBRD_OFFSET);
/* Write the desired serial parameters to the UART LCRH register */
putreg32(UART_LCRH_VALUE, LM_CONSOLE_BASE+LM_UART_LCRH_OFFSET);
putreg32(UART_LCRH_VALUE, TIVA_CONSOLE_BASE+TIVA_UART_LCRH_OFFSET);
/* Enable the UART by setting the UARTEN bit in the UART CTL register */
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
putreg32(ctl, TIVA_CONSOLE_BASE+TIVA_UART_CTL_OFFSET);
#endif
}

44
arch/arm/src/tiva/tiva_lowputc.h
View file

@ -47,26 +47,26 @@
************************************************************************************/
/* Configuration *******************************************************************/
#if LM_NUARTS < 8
# undef CONFIG_LM_UART7
#if TIVA_NUARTS < 8
# undef CONFIG_TIVA_UART7
# undef CONFIG_UART7_SERIAL_CONSOLE
# if LM_NUARTS < 7
# undef CONFIG_LM_UART6
# if TIVA_NUARTS < 7
# undef CONFIG_TIVA_UART6
# undef CONFIG_UART6_SERIAL_CONSOLE
# if LM_NUARTS < 6
# undef CONFIG_LM_UART5
# if TIVA_NUARTS < 6
# undef CONFIG_TIVA_UART5
# undef CONFIG_UART5_SERIAL_CONSOLE
# if LM_NUARTS < 5
# undef CONFIG_LM_UART4
# if TIVA_NUARTS < 5
# undef CONFIG_TIVA_UART4
# undef CONFIG_UART4_SERIAL_CONSOLE
# if LM_NUARTS < 4
# undef CONFIG_LM_UART3
# if TIVA_NUARTS < 4
# undef CONFIG_TIVA_UART3
# undef CONFIG_UART3_SERIAL_CONSOLE
# if LM_NUARTS < 3
# undef CONFIG_LM_UART2
# if TIVA_NUARTS < 3
# undef CONFIG_TIVA_UART2
# undef CONFIG_UART2_SERIAL_CONSOLE
# if LM_NUARTS < 2
# undef CONFIG_LM_UART1
# if TIVA_NUARTS < 2
# undef CONFIG_TIVA_UART1
# undef CONFIG_UART1_SERIAL_CONSOLE
# endif
# endif
@ -78,7 +78,7 @@
/* Is there a serial console? */
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM_UART0)
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART0)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
@ -87,7 +87,7 @@
# undef CONFIG_UART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM_UART1)
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
@ -96,7 +96,7 @@
# undef CONFIG_UART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
@ -105,7 +105,7 @@
# undef CONFIG_UART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
@ -114,7 +114,7 @@
# undef CONFIG_UART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
@ -123,7 +123,7 @@
# undef CONFIG_UART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
@ -132,7 +132,7 @@
# undef CONFIG_UART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART6_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
#elif defined(CONFIG_UART6_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
@ -141,7 +141,7 @@
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_TIVA_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE

226
arch/arm/src/tiva/tiva_serial.c
View file

@ -70,9 +70,9 @@
/* Is there a UART enabled? */
#if !defined(CONFIG_LM_UART0) && !defined(CONFIG_LM_UART1) && !defined(CONFIG_LM_UART2) && \
!defined(CONFIG_LM_UART3) && !defined(CONFIG_LM_UART4) && !defined(CONFIG_LM_UART5) && \
!defined(CONFIG_LM_UART6) && !defined(CONFIG_LM_UART7)
#if !defined(CONFIG_TIVA_UART0) && !defined(CONFIG_TIVA_UART1) && !defined(CONFIG_TIVA_UART2) && \
!defined(CONFIG_TIVA_UART3) && !defined(CONFIG_TIVA_UART4) && !defined(CONFIG_TIVA_UART5) && \
!defined(CONFIG_TIVA_UART6) && !defined(CONFIG_TIVA_UART7)
# error "No UARTs enabled"
#endif
@ -119,28 +119,28 @@
# define TTYS5_DEV g_uart7port /* UART7 is ttyS0 */
#else
# undef CONSOLE_DEV /* No console */
# if defined(CONFIG_LM_UART0)
# if defined(CONFIG_TIVA_UART0)
# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
# define UART0_ASSIGNED 1
# elif defined(CONFIG_LM_UART1)
# elif defined(CONFIG_TIVA_UART1)
# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
# define UART1_ASSIGNED 1
# elif defined(CONFIG_LM_UART2)
# elif defined(CONFIG_TIVA_UART2)
# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */
# define UART2_ASSIGNED 1
# elif defined(CONFIG_LM_UART3)
# elif defined(CONFIG_TIVA_UART3)
# define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */
# define UART3_ASSIGNED 1
# elif defined(CONFIG_LM_UART4)
# elif defined(CONFIG_TIVA_UART4)
# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */
# define UART4_ASSIGNED 1
# elif defined(CONFIG_LM_UART5)
# elif defined(CONFIG_TIVA_UART5)
# define TTYS0_DEV g_uart5port /* UART5 is ttyS0 */
# define UART5_ASSIGNED 1
# elif defined(CONFIG_LM_UART6)
# elif defined(CONFIG_TIVA_UART6)
# define TTYS0_DEV g_uart6port /* UART5 is ttyS0 */
# define UART6_ASSIGNED 1
# elif defined(CONFIG_LM_UART7)
# elif defined(CONFIG_TIVA_UART7)
# define TTYS0_DEV g_uart7port /* UART5 is ttyS0 */
# define UART7_ASSIGNED 1
# endif
@ -148,28 +148,28 @@
/* Pick ttys1. This could be any of UART0-7 excluding the console UART. */
#if defined(CONFIG_LM_UART0) && !defined(UART0_ASSIGNED)
#if defined(CONFIG_TIVA_UART0) && !defined(UART0_ASSIGNED)
# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */
# define UART0_ASSIGNED 1
#elif defined(CONFIG_LM_UART1) && !defined(UART1_ASSIGNED)
#elif defined(CONFIG_TIVA_UART1) && !defined(UART1_ASSIGNED)
# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */
# define UART1_ASSIGNED 1
#elif defined(CONFIG_LM_UART2) && !defined(UART2_ASSIGNED)
#elif defined(CONFIG_TIVA_UART2) && !defined(UART2_ASSIGNED)
# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */
# define UART2_ASSIGNED 1
#elif defined(CONFIG_LM_UART3) && !defined(UART3_ASSIGNED)
#elif defined(CONFIG_TIVA_UART3) && !defined(UART3_ASSIGNED)
# define TTYS1_DEV g_uart3port /* UART3 is ttyS1 */
# define UART3_ASSIGNED 1
#elif defined(CONFIG_LM_UART4) && !defined(UART4_ASSIGNED)
#elif defined(CONFIG_TIVA_UART4) && !defined(UART4_ASSIGNED)
# define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_LM_UART5) && !defined(UART5_ASSIGNED)
#elif defined(CONFIG_TIVA_UART5) && !defined(UART5_ASSIGNED)
# define TTYS1_DEV g_uart5port /* UART5 is ttyS1 */
# define UART5_ASSIGNED 1
#elif defined(CONFIG_LM_UART6) && !defined(UART6_ASSIGNED)
#elif defined(CONFIG_TIVA_UART6) && !defined(UART6_ASSIGNED)
# define TTYS1_DEV g_uart6port /* UART6 is ttyS1 */
# define UART6_ASSIGNED 1
#elif defined(CONFIG_LM_UART7) && !defined(UART7_ASSIGNED)
#elif defined(CONFIG_TIVA_UART7) && !defined(UART7_ASSIGNED)
# define TTYS1_DEV g_uart7port /* UART7 is ttyS1 */
# define UART7_ASSIGNED 1
#endif
@ -179,25 +179,25 @@
* console.
*/
#if defined(CONFIG_LM_UART1) && !defined(UART1_ASSIGNED)
#if defined(CONFIG_TIVA_UART1) && !defined(UART1_ASSIGNED)
# define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */
# define UART1_ASSIGNED 1
#elif defined(CONFIG_LM_UART2) && !defined(UART2_ASSIGNED)
#elif defined(CONFIG_TIVA_UART2) && !defined(UART2_ASSIGNED)
# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */
# define UART2_ASSIGNED 1
#elif defined(CONFIG_LM_UART3) && !defined(UART3_ASSIGNED)
#elif defined(CONFIG_TIVA_UART3) && !defined(UART3_ASSIGNED)
# define TTYS2_DEV g_uart3port /* UART3 is ttyS2 */
# define UART3_ASSIGNED 1
#elif defined(CONFIG_LM_UART4) && !defined(UART4_ASSIGNED)
#elif defined(CONFIG_TIVA_UART4) && !defined(UART4_ASSIGNED)
# define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_LM_UART5) && !defined(UART5_ASSIGNED)
#elif defined(CONFIG_TIVA_UART5) && !defined(UART5_ASSIGNED)
# define TTYS2_DEV g_uart5port /* UART5 is ttyS2 */
# define UART5_ASSIGNED 1
#elif defined(CONFIG_LM_UART6) && !defined(UART6_ASSIGNED)
#elif defined(CONFIG_TIVA_UART6) && !defined(UART6_ASSIGNED)
# define TTYS2_DEV g_uart6port /* UART6 is ttyS2 */
# define UART6_ASSIGNED 1
#elif defined(CONFIG_LM_UART7) && !defined(UART7_ASSIGNED)
#elif defined(CONFIG_TIVA_UART7) && !defined(UART7_ASSIGNED)
# define TTYS2_DEV g_uart7port /* UART7 is ttyS2 */
# define UART7_ASSIGNED 1
#endif
@ -207,22 +207,22 @@
* UART 2-7 could also be the console.
*/
#if defined(CONFIG_LM_UART2) && !defined(UART2_ASSIGNED)
#if defined(CONFIG_TIVA_UART2) && !defined(UART2_ASSIGNED)
# define TTYS3_DEV g_uart2port /* UART2 is ttyS3 */
# define UART2_ASSIGNED 1
#elif defined(CONFIG_LM_UART3) && !defined(UART3_ASSIGNED)
#elif defined(CONFIG_TIVA_UART3) && !defined(UART3_ASSIGNED)
# define TTYS3_DEV g_uart3port /* UART3 is ttyS3 */
# define UART3_ASSIGNED 1
#elif defined(CONFIG_LM_UART4) && !defined(UART4_ASSIGNED)
#elif defined(CONFIG_TIVA_UART4) && !defined(UART4_ASSIGNED)
# define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_LM_UART5) && !defined(UART5_ASSIGNED)
#elif defined(CONFIG_TIVA_UART5) && !defined(UART5_ASSIGNED)
# define TTYS3_DEV g_uart5port /* UART5 is ttyS3 */
# define UART5_ASSIGNED 1
#elif defined(CONFIG_LM_UART6) && !defined(UART6_ASSIGNED)
#elif defined(CONFIG_TIVA_UART6) && !defined(UART6_ASSIGNED)
# define TTYS3_DEV g_uart6port /* UART6 is ttyS3 */
# define UART6_ASSIGNED 1
#elif defined(CONFIG_LM_UART7) && !defined(UART7_ASSIGNED)
#elif defined(CONFIG_TIVA_UART7) && !defined(UART7_ASSIGNED)
# define TTYS3_DEV g_uart7port /* UART7 is ttyS3 */
# define UART7_ASSIGNED 1
#endif
@ -232,19 +232,19 @@
* UART 3-7 could also be the console.
*/
#if defined(CONFIG_LM_UART3) && !defined(UART3_ASSIGNED)
#if defined(CONFIG_TIVA_UART3) && !defined(UART3_ASSIGNED)
# define TTYS4_DEV g_uart3port /* UART3 is ttyS4 */
# define UART3_ASSIGNED 1
#elif defined(CONFIG_LM_UART4) && !defined(UART4_ASSIGNED)
#elif defined(CONFIG_TIVA_UART4) && !defined(UART4_ASSIGNED)
# define TTYS4_DEV g_uart4port /* UART4 is ttyS4 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_LM_UART5) && !defined(UART5_ASSIGNED)
#elif defined(CONFIG_TIVA_UART5) && !defined(UART5_ASSIGNED)
# define TTYS4_DEV g_uart5port /* UART5 is ttyS4 */
# define UART5_ASSIGNED 1
#elif defined(CONFIG_LM_UART6) && !defined(UART6_ASSIGNED)
#elif defined(CONFIG_TIVA_UART6) && !defined(UART6_ASSIGNED)
# define TTYS4_DEV g_uart6port /* UART6 is ttyS4 */
# define UART6_ASSIGNED 1
#elif defined(CONFIG_LM_UART7) && !defined(UART7_ASSIGNED)
#elif defined(CONFIG_TIVA_UART7) && !defined(UART7_ASSIGNED)
# define TTYS4_DEV g_uart7port /* UART7 is ttyS4 */
# define UART7_ASSIGNED 1
#endif
@ -254,16 +254,16 @@
* UART 4-7 could also be the console.
*/
#if defined(CONFIG_LM_UART4) && !defined(UART4_ASSIGNED)
#if defined(CONFIG_TIVA_UART4) && !defined(UART4_ASSIGNED)
# define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_LM_UART5) && !defined(UART5_ASSIGNED)
#elif defined(CONFIG_TIVA_UART5) && !defined(UART5_ASSIGNED)
# define TTYS5_DEV g_uart5port /* UART5 is ttyS5 */
# define UART5_ASSIGNED 1
#elif defined(CONFIG_LM_UART6) && !defined(UART6_ASSIGNED)
#elif defined(CONFIG_TIVA_UART6) && !defined(UART6_ASSIGNED)
# define TTYS5_DEV g_uart6port /* UART6 is ttyS5 */
# define UART6_ASSIGNED 1
#elif defined(CONFIG_LM_UART7) && !defined(UART7_ASSIGNED)
#elif defined(CONFIG_TIVA_UART7) && !defined(UART7_ASSIGNED)
# define TTYS5_DEV g_uart7port /* UART7 is ttyS5 */
# define UART7_ASSIGNED 1
#endif
@ -273,13 +273,13 @@
* UART 5-7 could also be the console.
*/
#if defined(CONFIG_LM_UART5) && !defined(UART5_ASSIGNED)
#if defined(CONFIG_TIVA_UART5) && !defined(UART5_ASSIGNED)
# define TTYS6_DEV g_uart5port /* UART5 is ttyS6 */
# define UART5_ASSIGNED 1
#elif defined(CONFIG_LM_UART6) && !defined(UART6_ASSIGNED)
#elif defined(CONFIG_TIVA_UART6) && !defined(UART6_ASSIGNED)
# define TTYS6_DEV g_uart6port /* UART6 is ttyS6 */
# define UART6_ASSIGNED 1
#elif defined(CONFIG_LM_UART7) && !defined(UART7_ASSIGNED)
#elif defined(CONFIG_TIVA_UART7) && !defined(UART7_ASSIGNED)
# define TTYS6_DEV g_uart7port /* UART7 is ttyS6 */
# define UART7_ASSIGNED 1
#endif
@ -289,10 +289,10 @@
* UART 6-7 could also be the console.
*/
#if defined(CONFIG_LM_UART6) && !defined(UART6_ASSIGNED)
#if defined(CONFIG_TIVA_UART6) && !defined(UART6_ASSIGNED)
# define TTYS7_DEV g_uart6port /* UART6 is ttyS7 */
# define UART6_ASSIGNED 1
#elif defined(CONFIG_LM_UART7) && !defined(UART7_ASSIGNED)
#elif defined(CONFIG_TIVA_UART7) && !defined(UART7_ASSIGNED)
# define TTYS7_DEV g_uart7port /* UART7 is ttyS7 */
# define UART7_ASSIGNED 1
#endif
@ -352,47 +352,47 @@ static const struct uart_ops_s g_uart_ops =
/* I/O buffers */
#ifdef CONFIG_LM_UART0
#ifdef CONFIG_TIVA_UART0
static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
#endif
#ifdef CONFIG_LM_UART1
#ifdef CONFIG_TIVA_UART1
static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
#endif
#ifdef CONFIG_LM_UART2
#ifdef CONFIG_TIVA_UART2
static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
#endif
#ifdef CONFIG_LM_UART3
#ifdef CONFIG_TIVA_UART3
static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE];
static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
#endif
#ifdef CONFIG_LM_UART4
#ifdef CONFIG_TIVA_UART4
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
#endif
#ifdef CONFIG_LM_UART5
#ifdef CONFIG_TIVA_UART5
static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE];
static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE];
#endif
#ifdef CONFIG_LM_UART6
#ifdef CONFIG_TIVA_UART6
static char g_uart6rxbuffer[CONFIG_UART6_RXBUFSIZE];
static char g_uart6txbuffer[CONFIG_UART6_TXBUFSIZE];
#endif
#ifdef CONFIG_LM_UART7
#ifdef CONFIG_TIVA_UART7
static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE];
static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE];
#endif
/* This describes the state of the Stellaris uart0 port. */
#ifdef CONFIG_LM_UART0
#ifdef CONFIG_TIVA_UART0
static struct up_dev_s g_uart0priv =
{
.uartbase = LM_UART0_BASE,
.uartbase = TIVA_UART0_BASE,
.baud = CONFIG_UART0_BAUD,
.irq = LM_IRQ_UART0,
.irq = TIVA_IRQ_UART0,
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
.stopbits2 = CONFIG_UART0_2STOP,
@ -417,12 +417,12 @@ static uart_dev_t g_uart0port =
/* This describes the state of the Stellaris uart1 port. */
#ifdef CONFIG_LM_UART1
#ifdef CONFIG_TIVA_UART1
static struct up_dev_s g_uart1priv =
{
.uartbase = LM_UART1_BASE,
.uartbase = TIVA_UART1_BASE,
.baud = CONFIG_UART1_BAUD,
.irq = LM_IRQ_UART1,
.irq = TIVA_IRQ_UART1,
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
.stopbits2 = CONFIG_UART1_2STOP,
@ -447,12 +447,12 @@ static uart_dev_t g_uart1port =
/* This describes the state of the Stellaris uart2 port. */
#ifdef CONFIG_LM_UART2
#ifdef CONFIG_TIVA_UART2
static struct up_dev_s g_uart2priv =
{
.uartbase = LM_UART2_BASE,
.uartbase = TIVA_UART2_BASE,
.baud = CONFIG_UART2_BAUD,
.irq = LM_IRQ_UART2,
.irq = TIVA_IRQ_UART2,
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
.stopbits2 = CONFIG_UART2_2STOP,
@ -477,12 +477,12 @@ static uart_dev_t g_uart2port =
/* This describes the state of the Stellaris uart3 port. */
#ifdef CONFIG_LM_UART3
#ifdef CONFIG_TIVA_UART3
static struct up_dev_s g_uart3priv =
{
.uartbase = LM_UART3_BASE,
.uartbase = TIVA_UART3_BASE,
.baud = CONFIG_UART3_BAUD,
.irq = LM_IRQ_UART3,
.irq = TIVA_IRQ_UART3,
.parity = CONFIG_UART3_PARITY,
.bits = CONFIG_UART3_BITS,
.stopbits2 = CONFIG_UART3_2STOP,
@ -507,12 +507,12 @@ static uart_dev_t g_uart3port =
/* This describes the state of the Stellaris uart4 port. */
#ifdef CONFIG_LM_UART4
#ifdef CONFIG_TIVA_UART4
static struct up_dev_s g_uart4priv =
{
.uartbase = LM_UART4_BASE,
.uartbase = TIVA_UART4_BASE,
.baud = CONFIG_UART4_BAUD,
.irq = LM_IRQ_UART4,
.irq = TIVA_IRQ_UART4,
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stopbits2 = CONFIG_UART4_2STOP,
@ -537,12 +537,12 @@ static uart_dev_t g_uart4port =
/* This describes the state of the Stellaris uart5 port. */
#ifdef CONFIG_LM_UART5
#ifdef CONFIG_TIVA_UART5
static struct up_dev_s g_uart5priv =
{
.uartbase = LM_UART5_BASE,
.uartbase = TIVA_UART5_BASE,
.baud = CONFIG_UART5_BAUD,
.irq = LM_IRQ_UART5,
.irq = TIVA_IRQ_UART5,
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stopbits2 = CONFIG_UART5_2STOP,
@ -567,12 +567,12 @@ static uart_dev_t g_uart5port =
/* This describes the state of the Stellaris uart6 port. */
#ifdef CONFIG_LM_UART6
#ifdef CONFIG_TIVA_UART6
static struct up_dev_s g_uart6priv =
{
.uartbase = LM_UART6_BASE,
.uartbase = TIVA_UART6_BASE,
.baud = CONFIG_UART6_BAUD,
.irq = LM_IRQ_UART6,
.irq = TIVA_IRQ_UART6,
.parity = CONFIG_UART6_PARITY,
.bits = CONFIG_UART6_BITS,
.stopbits2 = CONFIG_UART6_2STOP,
@ -597,12 +597,12 @@ static uart_dev_t g_uart6port =
/* This describes the state of the Stellaris uart7 port. */
#ifdef CONFIG_LM_UART7
#ifdef CONFIG_TIVA_UART7
static struct up_dev_s g_uart7priv =
{
.uartbase = LM_UART7_BASE,
.uartbase = TIVA_UART7_BASE,
.baud = CONFIG_UART7_BAUD,
.irq = LM_IRQ_UART7,
.irq = TIVA_IRQ_UART7,
.parity = CONFIG_UART7_PARITY,
.bits = CONFIG_UART7_BITS,
.stopbits2 = CONFIG_UART7_2STOP,
@ -663,7 +663,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
/* Disable all interrupts */
priv->im = 0;
up_serialout(priv, LM_UART_IM_OFFSET, 0);
up_serialout(priv, TIVA_UART_IM_OFFSET, 0);
}
/****************************************************************************
@ -673,7 +673,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
{
priv->im = im;
up_serialout(priv, LM_UART_IM_OFFSET, im);
up_serialout(priv, TIVA_UART_IM_OFFSET, im);
}
/****************************************************************************
@ -691,7 +691,7 @@ static inline void up_waittxnotfull(struct up_dev_s *priv)
{
/* Check Tx FIFO is full */
if ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
if ((up_serialin(priv, TIVA_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
{
/* The Tx FIFO is not full... return */
@ -732,9 +732,9 @@ static int up_setup(struct uart_dev_s *dev)
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
ctl = up_serialin(priv, LM_UART_CTL_OFFSET);
ctl = up_serialin(priv, TIVA_UART_CTL_OFFSET);
ctl &= ~UART_CTL_UARTEN;
up_serialout(priv, LM_UART_CTL_OFFSET, ctl);
up_serialout(priv, TIVA_UART_CTL_OFFSET, ctl);
/* Calculate BAUD rate from the SYS clock:
*
@ -778,8 +778,8 @@ static int up_setup(struct uart_dev_s *dev)
remainder = SYSCLK_FREQUENCY - den * brdi;
divfrac = ((remainder << 6) + (den >> 1)) / den;
up_serialout(priv, LM_UART_IBRD_OFFSET, brdi);
up_serialout(priv, LM_UART_FBRD_OFFSET, divfrac);
up_serialout(priv, TIVA_UART_IBRD_OFFSET, brdi);
up_serialout(priv, TIVA_UART_FBRD_OFFSET, divfrac);
/* Set up the LCRH register */
@ -819,14 +819,14 @@ static int up_setup(struct uart_dev_s *dev)
lcrh |= UART_LCRH_STP2;
}
up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh);
up_serialout(priv, TIVA_UART_LCRH_OFFSET, lcrh);
#endif
/* Set the UART to interrupt whenever the TX FIFO is almost empty or when
* any character is received.
*/
up_serialout(priv, LM_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
up_serialout(priv, TIVA_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
/* Flush the Rx and Tx FIFOs -- How do you do that?*/
@ -836,27 +836,27 @@ static int up_setup(struct uart_dev_s *dev)
* yet because the interrupt is still disabled at the interrupt controller.
*/
up_serialout(priv, LM_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
up_serialout(priv, TIVA_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
/* Enable the FIFOs */
#ifdef CONFIG_SUPPRESS_UART_CONFIG
lcrh = up_serialin(priv, LM_UART_LCRH_OFFSET);
lcrh = up_serialin(priv, TIVA_UART_LCRH_OFFSET);
#endif
lcrh |= UART_LCRH_FEN;
up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh);
up_serialout(priv, TIVA_UART_LCRH_OFFSET, lcrh);
/* Enable Rx, Tx, and the UART */
#ifdef CONFIG_SUPPRESS_UART_CONFIG
ctl = up_serialin(priv, LM_UART_CTL_OFFSET);
ctl = up_serialin(priv, TIVA_UART_CTL_OFFSET);
#endif
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
up_serialout(priv, LM_UART_CTL_OFFSET, ctl);
up_serialout(priv, TIVA_UART_CTL_OFFSET, ctl);
/* Set up the cache IM value */
priv->im = up_serialin(priv, LM_UART_IM_OFFSET);
priv->im = up_serialin(priv, TIVA_UART_IM_OFFSET);
return OK;
}
@ -947,56 +947,56 @@ static int up_interrupt(int irq, void *context)
int passes;
bool handled;
#ifdef CONFIG_LM_UART0
#ifdef CONFIG_TIVA_UART0
if (g_uart0priv.irq == irq)
{
dev = &g_uart0port;
}
else
#endif
#ifdef CONFIG_LM_UART1
#ifdef CONFIG_TIVA_UART1
if (g_uart1priv.irq == irq)
{
dev = &g_uart1port;
}
else
#endif
#ifdef CONFIG_LM_UART2
#ifdef CONFIG_TIVA_UART2
if (g_uart2priv.irq == irq)
{
dev = &g_uart2port;
}
else
#endif
#ifdef CONFIG_LM_UART3
#ifdef CONFIG_TIVA_UART3
if (g_uart3priv.irq == irq)
{
dev = &g_uart3port;
}
else
#endif
#ifdef CONFIG_LM_UART4
#ifdef CONFIG_TIVA_UART4
if (g_uart4priv.irq == irq)
{
dev = &g_uart4port;
}
else
#endif
#ifdef CONFIG_LM_UART5
#ifdef CONFIG_TIVA_UART5
if (g_uart5priv.irq == irq)
{
dev = &g_uart5port;
}
else
#endif
#ifdef CONFIG_LM_UART6
#ifdef CONFIG_TIVA_UART6
if (g_uart6priv.irq == irq)
{
dev = &g_uart6port;
}
else
#endif
#ifdef CONFIG_LM_UART7
#ifdef CONFIG_TIVA_UART7
if (g_uart7priv.irq == irq)
{
dev = &g_uart7port;
@ -1020,8 +1020,8 @@ static int up_interrupt(int irq, void *context)
/* Get the masked UART status and clear the pending interrupts. */
mis = up_serialin(priv, LM_UART_MIS_OFFSET);
up_serialout(priv, LM_UART_ICR_OFFSET, mis);
mis = up_serialin(priv, TIVA_UART_MIS_OFFSET);
up_serialout(priv, TIVA_UART_ICR_OFFSET, mis);
/* Handle incoming, receive bytes (with or without timeout) */
@ -1105,7 +1105,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
/* Get the Rx byte + 4 bits of error information. Return those in status */
rxd = up_serialin(priv, LM_UART_DR_OFFSET);
rxd = up_serialin(priv, TIVA_UART_DR_OFFSET);
*status = rxd;
/* The lower 8bits of the Rx data is the actual recevied byte */
@ -1138,7 +1138,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
{
priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
}
up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
up_serialout(priv, TIVA_UART_IM_OFFSET, priv->im);
}
/****************************************************************************
@ -1152,7 +1152,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
static bool up_rxavailable(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
return ((up_serialin(priv, TIVA_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
}
/****************************************************************************
@ -1166,7 +1166,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
static void up_send(struct uart_dev_s *dev, int ch)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch);
up_serialout(priv, TIVA_UART_DR_OFFSET, (uint32_t)ch);
}
/****************************************************************************
@ -1189,7 +1189,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
priv->im |= UART_IM_TXIM;
up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
up_serialout(priv, TIVA_UART_IM_OFFSET, priv->im);
/* The serial driver wants an interrupt here, but will not get get
* one unless we "prime the pump." I believe that this is because
@ -1209,7 +1209,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
/* Disable the TX interrupt */
priv->im &= ~UART_IM_TXIM;
up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
up_serialout(priv, TIVA_UART_IM_OFFSET, priv->im);
}
irqrestore(flags);
}
@ -1225,7 +1225,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
return ((up_serialin(priv, TIVA_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
}
/****************************************************************************
@ -1239,7 +1239,7 @@ static bool up_txready(struct uart_dev_s *dev)
static bool up_txempty(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
return ((up_serialin(priv, TIVA_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
}
/****************************************************************************
@ -1354,7 +1354,7 @@ int up_putc(int ch)
up_disableuartint(priv, &im);
up_waittxnotfull(priv);
up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch);
up_serialout(priv, TIVA_UART_DR_OFFSET, (uint32_t)ch);
/* Check for LF */
@ -1363,7 +1363,7 @@ int up_putc(int ch)
/* Add CR */
up_waittxnotfull(priv);
up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)'\r');
up_serialout(priv, TIVA_UART_DR_OFFSET, (uint32_t)'\r');
}
up_waittxnotfull(priv);

112
arch/arm/src/tiva/tiva_ssi.c
View file

@ -83,12 +83,12 @@
* such case, the following must be expanded).
*/
#if LM_NSSI == 0
#if TIVA_NSSI == 0
# undef CONFIG_SSI0_DISABLE
# define CONFIG_SSI0_DISABLE 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#elif LM_NSSI == 1
#elif TIVA_NSSI == 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#endif
@ -102,15 +102,15 @@
# define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */
# else
# define NSSI_ENABLED 1 /* One SSI interface: SSI0 */
# define SSI_BASE LM_SSI0_BASE
# define SSI_IRQ LM_IRQ_SSI0
# define SSI_BASE TIVA_SSI0_BASE
# define SSI_IRQ TIVA_IRQ_SSI0
# endif
#else
# ifndef CONFIG_SSI1_DISABLE
# define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */
# define NSSI_ENABLED 1 /* One SSI interface: SSI1 */
# define SSI_BASE LM_SSI1_BASE
# define SSI_IRQ LM_IRQ_SSI1
# define SSI_BASE TIVA_SSI1_BASE
# define SSI_IRQ TIVA_IRQ_SSI1
# else
# define NSSI_ENABLED 0 /* No SSI interfaces */
# endif
@ -124,19 +124,19 @@
/* The number of (16-bit) words that will fit in the Tx FIFO */
#define LM_TXFIFO_WORDS 8
#define TIVA_TXFIFO_WORDS 8
/* Configuration settings */
#ifndef CONFIG_SSI_TXLIMIT
# define CONFIG_SSI_TXLIMIT (LM_TXFIFO_WORDS/2)
# define CONFIG_SSI_TXLIMIT (TIVA_TXFIFO_WORDS/2)
#endif
#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM_TXFIFO_WORDS
#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > TIVA_TXFIFO_WORDS
# error "Invalid range for CONFIG_SSI_TXLIMIT"
#endif
#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM_TXFIFO_WORDS/2)
#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (TIVA_TXFIFO_WORDS/2)
# error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size"
#endif
@ -304,10 +304,10 @@ static struct tiva_ssidev_s g_ssidev[] =
{
.ops = &g_spiops,
#if NSSI_ENABLED > 1
.base = LM_SSI0_BASE,
.base = TIVA_SSI0_BASE,
#endif
#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
.irq = LM_IRQ_SSI0,
.irq = TIVA_IRQ_SSI0,
#endif
},
#endif
@ -315,10 +315,10 @@ static struct tiva_ssidev_s g_ssidev[] =
{
.ops = &g_spiops,
#if NSSI_ENABLED > 1
.base = LM_SSI1_BASE,
.base = TIVA_SSI1_BASE,
#endif
#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
.irq = LM_IRQ_SSI1,
.irq = TIVA_IRQ_SSI1,
#endif
},
#endif
@ -406,9 +406,9 @@ static uint32_t ssi_disable(struct tiva_ssidev_s *priv)
uint32_t retval;
uint32_t regval;
retval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
retval = ssi_getreg(priv, TIVA_SSI_CR1_OFFSET);
regval = (retval & ~SSI_CR1_SSE);
ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
ssi_putreg(priv, TIVA_SSI_CR1_OFFSET, regval);
ssivdbg("CR1: %08x\n", regval);
return retval;
}
@ -432,10 +432,10 @@ static uint32_t ssi_disable(struct tiva_ssidev_s *priv)
static void ssi_enable(struct tiva_ssidev_s *priv, uint32_t enable)
{
uint32_t regval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
uint32_t regval = ssi_getreg(priv, TIVA_SSI_CR1_OFFSET);
regval &= ~SSI_CR1_SSE;
regval |= (enable & SSI_CR1_SSE);
ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
ssi_putreg(priv, TIVA_SSI_CR1_OFFSET, regval);
ssivdbg("CR1: %08x\n", regval);
}
@ -486,14 +486,14 @@ static void ssi_semtake(sem_t *sem)
static void ssi_txnull(struct tiva_ssidev_s *priv)
{
ssivdbg("TX: ->0xffff\n");
ssi_putreg(priv, LM_SSI_DR_OFFSET, 0xffff);
ssi_putreg(priv, TIVA_SSI_DR_OFFSET, 0xffff);
}
static void ssi_txuint16(struct tiva_ssidev_s *priv)
{
uint16_t *ptr = (uint16_t*)priv->txbuffer;
ssivdbg("TX: %p->%04x\n", ptr, *ptr);
ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
ssi_putreg(priv, TIVA_SSI_DR_OFFSET, (uint32_t)(*ptr++));
priv->txbuffer = (void*)ptr;
}
@ -501,7 +501,7 @@ static void ssi_txuint8(struct tiva_ssidev_s *priv)
{
uint8_t *ptr = (uint8_t*)priv->txbuffer;
ssivdbg("TX: %p->%02x\n", ptr, *ptr);
ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
ssi_putreg(priv, TIVA_SSI_DR_OFFSET, (uint32_t)(*ptr++));
priv->txbuffer = (void*)ptr;
}
@ -525,17 +525,17 @@ static void ssi_txuint8(struct tiva_ssidev_s *priv)
static void ssi_rxnull(struct tiva_ssidev_s *priv)
{
#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE)
uint32_t regval = ssi_getreg(priv, LM_SSI_DR_OFFSET);
uint32_t regval = ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
ssivdbg("RX: discard %04x\n", regval);
#else
(void)ssi_getreg(priv, LM_SSI_DR_OFFSET);
(void)ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
#endif
}
static void ssi_rxuint16(struct tiva_ssidev_s *priv)
{
uint16_t *ptr = (uint16_t*)priv->rxbuffer;
*ptr = (uint16_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
*ptr = (uint16_t)ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
priv->rxbuffer = (void*)(++ptr);
}
@ -543,7 +543,7 @@ static void ssi_rxuint16(struct tiva_ssidev_s *priv)
static void ssi_rxuint8(struct tiva_ssidev_s *priv)
{
uint8_t *ptr = (uint8_t*)priv->rxbuffer;
*ptr = (uint8_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
*ptr = (uint8_t)ssi_getreg(priv, TIVA_SSI_DR_OFFSET);
ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
priv->rxbuffer = (void*)(++ptr);
}
@ -564,7 +564,7 @@ static void ssi_rxuint8(struct tiva_ssidev_s *priv)
static inline bool ssi_txfifofull(struct tiva_ssidev_s *priv)
{
return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
return (ssi_getreg(priv, TIVA_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
}
/****************************************************************************
@ -583,7 +583,7 @@ static inline bool ssi_txfifofull(struct tiva_ssidev_s *priv)
static inline bool ssi_rxfifoempty(struct tiva_ssidev_s *priv)
{
return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
return (ssi_getreg(priv, TIVA_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
}
/****************************************************************************
@ -659,7 +659,7 @@ static int ssi_performtx(struct tiva_ssidev_s *priv)
/* Check again... Now have all of the Tx words been sent? */
#ifndef CONFIG_SSI_POLLWAIT
regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
regval = ssi_getreg(priv, TIVA_SSI_IM_OFFSET);
if (priv->ntxwords > 0)
{
/* No.. Enable the Tx FIFO interrupt. This interrupt occurs
@ -680,7 +680,7 @@ static int ssi_performtx(struct tiva_ssidev_s *priv)
regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
}
ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, regval);
#endif /* CONFIG_SSI_POLLWAIT */
}
return ntxd;
@ -730,7 +730,7 @@ static inline void ssi_performrx(struct tiva_ssidev_s *priv)
*/
#ifndef CONFIG_SSI_POLLWAIT
regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
regval = ssi_getreg(priv, TIVA_SSI_IM_OFFSET);
if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords)
{
/* There are no more outgoing words to send, but there are
@ -753,7 +753,7 @@ static inline void ssi_performrx(struct tiva_ssidev_s *priv)
regval &= ~(SSI_IM_RX|SSI_IM_RT);
}
ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, regval);
#endif /* CONFIG_SSI_POLLWAIT */
}
@ -831,7 +831,7 @@ static int ssi_transfer(struct tiva_ssidev_s *priv, const void *txbuffer,
flags = irqsave();
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
priv->ntxwords, priv->nrxwords, priv->nwords,
ssi_getreg(priv, LM_SSI_SR_OFFSET));
ssi_getreg(priv, TIVA_SSI_SR_OFFSET));
ntxd = ssi_performtx(priv);
@ -844,8 +844,8 @@ static int ssi_transfer(struct tiva_ssidev_s *priv, const void *txbuffer,
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
priv->ntxwords, priv->nrxwords, priv->nwords,
ssi_getreg(priv, LM_SSI_SR_OFFSET),
ssi_getreg(priv, LM_SSI_IM_OFFSET));
ssi_getreg(priv, TIVA_SSI_SR_OFFSET),
ssi_getreg(priv, TIVA_SSI_IM_OFFSET));
/* Wait for the transfer to complete. Since there is no handshake
* with SPI, the following should complete even if there are problems
@ -910,11 +910,11 @@ static inline struct tiva_ssidev_s *ssi_mapirq(int irq)
switch (irq)
{
#ifndef CONFIG_SSI0_DISABLE
case LM_IRQ_SSI0:
case TIVA_IRQ_SSI0:
return &g_ssidev[SSI0_NDX];
#endif
#ifndef CONFIG_SSI1_DISABLE
case LM_IRQ_SSI1:
case TIVA_IRQ_SSI1:
return &g_ssidev[SSI1_NDX];
#endif
default:
@ -954,8 +954,8 @@ static int ssi_interrupt(int irq, void *context)
/* Clear pending interrupts */
regval = ssi_getreg(priv, LM_SSI_RIS_OFFSET);
ssi_putreg(priv, LM_SSI_ICR_OFFSET, regval);
regval = ssi_getreg(priv, TIVA_SSI_RIS_OFFSET);
ssi_putreg(priv, TIVA_SSI_ICR_OFFSET, regval);
/* Check for Rx FIFO overruns */
@ -968,7 +968,7 @@ static int ssi_interrupt(int irq, void *context)
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
priv->ntxwords, priv->nrxwords, priv->nwords,
ssi_getreg(priv, LM_SSI_SR_OFFSET));
ssi_getreg(priv, TIVA_SSI_SR_OFFSET));
/* Handle outgoing Tx FIFO transfers */
@ -980,8 +980,8 @@ static int ssi_interrupt(int irq, void *context)
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
priv->ntxwords, priv->nrxwords, priv->nwords,
ssi_getreg(priv, LM_SSI_SR_OFFSET),
ssi_getreg(priv, LM_SSI_IM_OFFSET));
ssi_getreg(priv, TIVA_SSI_SR_OFFSET),
ssi_getreg(priv, TIVA_SSI_IM_OFFSET));
/* Check if the transfer is complete */
@ -989,7 +989,7 @@ static int ssi_interrupt(int irq, void *context)
{
/* Yes.. Disable all SSI interrupt sources */
ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, 0);
/* Wake up the waiting thread */
@ -1138,14 +1138,14 @@ static uint32_t ssi_setfrequencyinternal(struct tiva_ssidev_s *priv,
/* Set CPDVSR */
DEBUGASSERT(cpsdvsr < 255);
ssi_putreg(priv, LM_SSI_CPSR_OFFSET, cpsdvsr);
ssi_putreg(priv, TIVA_SSI_CPSR_OFFSET, cpsdvsr);
/* Set SCR */
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
regval = ssi_getreg(priv, TIVA_SSI_CR0_OFFSET);
regval &= ~SSI_CR0_SCR_MASK;
regval |= (scr << SSI_CR0_SCR_SHIFT);
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval);
ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
/* Calcluate the actual frequency */
@ -1238,10 +1238,10 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv, enum spi_mode_e mode
/* Then set the selected mode: Freescale SPI format, mode0-3 */
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
regval = ssi_getreg(priv, TIVA_SSI_CR0_OFFSET);
regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
regval |= modebits;
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval);
ssivdbg("CR0: %08x\n", regval);
/* Save the mode so that subsequent re-configuratins will be faster */
@ -1290,10 +1290,10 @@ static void ssi_setbitsinternal(struct tiva_ssidev_s *priv, int nbits)
DEBUGASSERT(priv);
if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
{
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
regval = ssi_getreg(priv, TIVA_SSI_CR0_OFFSET);
regval &= ~SSI_CR0_DSS_MASK;
regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval);
ssivdbg("CR0: %08x\n", regval);
priv->nbits = nbits;
@ -1469,9 +1469,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
/* Enable the SSI0 peripheral */
regval = getreg32(LM_SYSCON_RCGC1);
regval = getreg32(TIVA_SYSCON_RCGC1);
regval |= SYSCON_RCGC1_SSI0;
putreg32(regval, LM_SYSCON_RCGC1);
putreg32(regval, TIVA_SYSCON_RCGC1);
ssivdbg("RCGC1: %08x\n", regval);
/* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
@ -1493,9 +1493,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
/* Enable the SSI1 peripheral */
regval = getreg32(LM_SYSCON_RCGC1);
regval = getreg32(TIVA_SYSCON_RCGC1);
regval |= SYSCON_RCGC1_SSI1;
putreg32(regval, LM_SYSCON_RCGC1);
putreg32(regval, TIVA_SYSCON_RCGC1);
ssivdbg("RCGC1: %08x\n", regval);
/* Configure SSI1 GPIOs */
@ -1523,11 +1523,11 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
/* Set all CR1 fields to reset state. This will be master mode. */
ssi_putreg(priv, LM_SSI_CR1_OFFSET, 0);
ssi_putreg(priv, TIVA_SSI_CR1_OFFSET, 0);
/* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */
ssi_putreg(priv, LM_SSI_CR0_OFFSET, 0);
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, 0);
/* Set the initial mode to mode 0. The application may override
* this initial setting using the setmode() method.
@ -1552,7 +1552,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
* while there is an SSI transfer in progress.
*/
ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
ssi_putreg(priv, TIVA_SSI_IM_OFFSET, 0);
/* Attach the interrupt */

34
arch/arm/src/tiva/tiva_syscontrol.c
View file

@ -174,7 +174,7 @@ static inline void tiva_plllock(void)
{
/* Check if the PLL is locked on */
if ((getreg32(LM_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
if ((getreg32(TIVA_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
{
/* Yes.. return now */
@ -206,17 +206,17 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
/* Get the current values of the RCC and RCC2 registers */
rcc = getreg32(LM_SYSCON_RCC);
rcc2 = getreg32(LM_SYSCON_RCC2);
rcc = getreg32(TIVA_SYSCON_RCC);
rcc2 = getreg32(TIVA_SYSCON_RCC2);
/* Temporarily bypass the PLL and system clock dividers */
rcc |= SYSCON_RCC_BYPASS;
rcc &= ~(SYSCON_RCC_USESYSDIV);
putreg32(rcc, LM_SYSCON_RCC);
putreg32(rcc, TIVA_SYSCON_RCC);
rcc2 |= SYSCON_RCC2_BYPASS2;
putreg32(rcc2, LM_SYSCON_RCC2);
putreg32(rcc2, TIVA_SYSCON_RCC2);
/* We are probably using the main oscillator. The main oscillator is disabled on
* reset and so probably must be enabled here. The internal oscillator is enabled
@ -233,7 +233,7 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
/* Enable any selected osciallators (but don't disable any yet) */
rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
putreg32(rcc, LM_SYSCON_RCC);
putreg32(rcc, TIVA_SYSCON_RCC);
/* Wait for the newly selected oscillator(s) to settle. This is tricky because
* the time that we wait can be significant and is determined by the previous
@ -253,7 +253,7 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
/* Clear the PLL lock interrupt */
putreg32(SYSCON_MISC_PLLLMIS, LM_SYSCON_MISC);
putreg32(SYSCON_MISC_PLLLMIS, TIVA_SYSCON_MISC);
/* Write the new RCC/RCC2 values.
*
@ -269,14 +269,14 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
#ifndef LM4F
if ((rcc2 & SYSCON_RCC2_USERCC2) != 0)
{
putreg32(rcc2, LM_SYSCON_RCC2);
putreg32(rcc, LM_SYSCON_RCC);
putreg32(rcc2, TIVA_SYSCON_RCC2);
putreg32(rcc, TIVA_SYSCON_RCC);
}
else
#endif
{
putreg32(rcc, LM_SYSCON_RCC);
putreg32(rcc2, LM_SYSCON_RCC2);
putreg32(rcc, TIVA_SYSCON_RCC);
putreg32(rcc2, TIVA_SYSCON_RCC2);
}
/* Wait for the new crystal value and oscillator source to take effect */
@ -313,11 +313,11 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
* before writing the RCC2 register.
*/
putreg32(rcc, LM_SYSCON_RCC);
putreg32(rcc, TIVA_SYSCON_RCC);
#ifdef LM4F
rcc = getreg32(LM_SYSCON_RCC);
rcc = getreg32(TIVA_SYSCON_RCC);
#endif
putreg32(rcc2, LM_SYSCON_RCC2);
putreg32(rcc2, TIVA_SYSCON_RCC2);
/* Wait for the system divider to be effective */
@ -336,16 +336,16 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
void up_clockconfig(void)
{
#ifdef CONFIG_LM_REVA2
/* Some early silicon returned an increase LDO voltage or 2.75V to work
/* Some early LM3 silicon returned an increase LDO voltage or 2.75V to work
* around a PLL bug
*/
putreg32(SYSCON_LPDOPCTL_2750MV, LM_SYSCON_LDOPCTL);
putreg32(SYSCON_LPDOPCTL_2750MV, TIVA_SYSCON_LDOPCTL);
#endif
/* Set the clocking to run with the default settings provided in the board.h
* header file
*/
tiva_clockconfig(LM_RCC_VALUE, LM_RCC2_VALUE);
tiva_clockconfig(TIVA_RCC_VALUE, TIVA_RCC2_VALUE);
}

4
arch/arm/src/tiva/tiva_timerisr.c
View file

@ -130,7 +130,7 @@ void up_timerinit(void)
/* Attach the timer interrupt vector */
(void)irq_attach(LM_IRQ_SYSTICK, (xcpt_t)up_timerisr);
(void)irq_attach(TIVA_IRQ_SYSTICK, (xcpt_t)up_timerisr);
/* Enable SysTick interrupts */
@ -138,5 +138,5 @@ void up_timerinit(void)
/* And enable the timer interrupt */
up_enable_irq(LM_IRQ_SYSTICK);
up_enable_irq(TIVA_IRQ_SYSTICK);
}

6
arch/arm/src/tiva/tiva_userspace.h
View file

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_LM_USERSPACE_H
#define __ARCH_ARM_SRC_TIVA_LM_USERSPACE_H
#ifndef __ARCH_ARM_SRC_TIVA_TIVA_USERSPACE_H
#define __ARCH_ARM_SRC_TIVA_TIVA_USERSPACE_H
/************************************************************************************
* Included Files
@ -73,4 +73,4 @@
void tiva_userspace(void);
#endif
#endif /* __ARCH_ARM_SRC_TIVA_LM_USERSPACE_H */
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_USERSPACE_H */

20
arch/arm/src/tiva/tiva_vectors.S
View file

@ -180,16 +180,16 @@ _vectors:
.type handlers, function
.thumb_func
handlers:
HANDLER tiva_reserved, LM_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER tiva_nmi, LM_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER tiva_hardfault, LM_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER tiva_mpu, LM_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER tiva_busfault, LM_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER tiva_usagefault, LM_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER tiva_svcall, LM_IRQ_SVCALL /* Vector 11: SVC call */
HANDLER tiva_dbgmonitor, LM_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
HANDLER tiva_pendsv, LM_IRQ_PENDSV /* Vector 14: Penable system service request */
HANDLER tiva_systick, LM_IRQ_SYSTICK /* Vector 15: System tick */
HANDLER tiva_reserved, TIVA_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER tiva_nmi, TIVA_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER tiva_hardfault, TIVA_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER tiva_mpu, TIVA_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER tiva_busfault, TIVA_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER tiva_usagefault, TIVA_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER tiva_svcall, TIVA_IRQ_SVCALL /* Vector 11: SVC call */
HANDLER tiva_dbgmonitor, TIVA_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
HANDLER tiva_pendsv, TIVA_IRQ_PENDSV /* Vector 14: Penable system service request */
HANDLER tiva_systick, TIVA_IRQ_SYSTICK /* Vector 15: System tick */
#undef VECTOR
#define VECTOR(l,i) HANDLER l, i