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mpfs: Allow mapping of RAM/ROM regions from different memory areas
The old implementation needed a contiguous memory block for user ROM/RAM. This is because there was only 1 L3 page table which can only map a contiguous memory area. Also, remove the PMP configuration which just complicates things, rely on the MMU mappings instead.
This commit is contained in:
Ville Juven
Xiang Xiao
parent
ba4277bb13
commit
6cb77a8d84
1 changed files with 80 additions and 79 deletions
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@ -41,17 +41,20 @@
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* Pre-processor Definitions
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****************************************************************************/
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#define PMP_UFLASH_FLAGS (PMPCFG_A_NAPOT | PMPCFG_X | PMPCFG_R)
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#define PMP_USRAM_FLAGS (PMPCFG_A_NAPOT | PMPCFG_W | PMPCFG_R)
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/* Physical and virtual addresses to page tables (vaddr = paddr mapping) */
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#define PGT_L1_PBASE (uint64_t)&m_l1_pgtable
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#define PGT_L2_PBASE (uint64_t)&m_l2_pgtable
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#define PGT_L3_PBASE (uint64_t)&m_l3_pgtable
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#define PGT_L1_VBASE PGT_L1_PBASE
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#define PGT_L2_VBASE PGT_L2_PBASE
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#define PGT_L3_VBASE PGT_L3_PBASE
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#define PGT_L1_PBASE (uint64_t)&m_l1_pgtable
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#define PGT_L2_PBASE (uint64_t)&m_l2_pgtable
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#define PGT_L3_ROMPBASE (uint64_t)&m_l3_romtbl
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#define PGT_L3_RAMPBASE (uint64_t)&m_l3_ramtbl
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#define PGT_L1_VBASE PGT_L1_PBASE
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#define PGT_L2_VBASE PGT_L2_PBASE
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#define PGT_L3_ROMVBASE PGT_L3_ROMPBASE
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#define PGT_L3_RAMVBASE PGT_L3_RAMPBASE
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#define PGT_L1_SIZE (512) /* Enough to map 512 GiB */
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#define PGT_L2_SIZE (512) /* Enough to map 1 GiB */
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#define PGT_L3_SIZE (512) /* Enough to map 2 MiB */
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/****************************************************************************
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* Private Functions
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@ -79,6 +82,24 @@ static void configure_mpu(void);
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static void configure_mmu(void);
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/****************************************************************************
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* Name: map_region
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*
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* Description:
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* Map a region of physical memory to the L3 page table
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*
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* Input Parameters:
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* l3base - L3 page table physical base address
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* paddr - Beginning of the physical address mapping
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* vaddr - Beginning of the virtual address mapping
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* size - Size of the region in bytes
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* mmuflags - The MMU flags to use in the mapping
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*
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****************************************************************************/
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static void map_region(uintptr_t l3base, uintptr_t paddr, uintptr_t vaddr,
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size_t size, uint32_t mmuflags);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@ -92,9 +113,13 @@ static void configure_mmu(void);
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/* L1-L3 tables must be in memory always for this to work */
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static uint64_t m_l1_pgtable[512] locate_data(".pgtables");
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static uint64_t m_l2_pgtable[512] locate_data(".pgtables");
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static uint64_t m_l3_pgtable[512] locate_data(".pgtables");
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static uint64_t m_l1_pgtable[PGT_L1_SIZE] locate_data(".pgtables");
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static uint64_t m_l2_pgtable[PGT_L2_SIZE] locate_data(".pgtables");
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/* Allocate separate tables for ROM/RAM mappings */
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static uint64_t m_l3_romtbl[PGT_L3_SIZE] locate_data(".pgtables");
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static uint64_t m_l3_ramtbl[PGT_L3_SIZE] locate_data(".pgtables");
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/****************************************************************************
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* Public Functions
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@ -162,68 +187,10 @@ void mpfs_userspace(void)
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static void configure_mpu(void)
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{
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/* Configure the PMP to permit user-space access to its ROM and RAM.
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*
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* Note: PMP by default revokes access, thus if different privilege modes
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* are in use, the user space _must_ be granted access here, otherwise
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* an exception will fire when the user space task is started.
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*
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* Note: according to the Polarfire reference manual, address bits [1:0]
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* are not considered (due to 4 octet alignment), so strictly they don't
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* have to be cleared here.
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*
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* Note: do not trust the stext / etc sections to be correctly aligned
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* here, they should be but it is simpler and safer to handle the user
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* region as a whole
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*
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* Access is currently granted by simply adding each userspace memory area
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* to PMP, without further granularity.
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*
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* "RX" for the user progmem
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* "RW" for the user RAM area
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*
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*/
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/* Open everything for PMP */
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int ret;
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int idx;
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/* First, test access to user flash */
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ret = riscv_check_pmp_access(PMP_UFLASH_FLAGS, UFLASH_START, UFLASH_SIZE);
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/* No access or partial access means we must crash */
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DEBUGASSERT(ret != PMP_ACCESS_DENIED);
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if (ret == PMP_ACCESS_OFF)
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{
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idx = riscv_next_free_pmp_region();
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DEBUGASSERT(idx >= 0);
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riscv_config_pmp_region(idx, PMP_UFLASH_FLAGS, UFLASH_START,
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UFLASH_SIZE);
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}
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/* Then, test access to user RAM */
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ret = riscv_check_pmp_access(PMP_USRAM_FLAGS, USRAM_START, USRAM_SIZE);
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DEBUGASSERT(ret != PMP_ACCESS_DENIED);
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if (ret == PMP_ACCESS_OFF)
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{
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idx = riscv_next_free_pmp_region();
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DEBUGASSERT(idx >= 0);
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riscv_config_pmp_region(idx, PMP_USRAM_FLAGS, USRAM_START, USRAM_SIZE);
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}
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/* The supervisor must have access to the page tables */
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ret = riscv_check_pmp_access(PMP_USRAM_FLAGS, KSRAM_START, KSRAM_SIZE);
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DEBUGASSERT(ret != PMP_ACCESS_DENIED);
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if (ret == PMP_ACCESS_OFF)
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{
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idx = riscv_next_free_pmp_region();
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DEBUGASSERT(idx >= 0);
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riscv_config_pmp_region(idx, PMP_USRAM_FLAGS, KSRAM_START, KSRAM_SIZE);
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}
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WRITE_CSR(pmpaddr0, UINT64_C(~0));
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WRITE_CSR(pmpcfg0, (PMPCFG_A_NAPOT | PMPCFG_R | PMPCFG_W | PMPCFG_X));
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}
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/****************************************************************************
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@ -241,17 +208,16 @@ static void configure_mmu(void)
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/* Setup the L3 references for executable memory */
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mmu_ln_map_region(3, PGT_L3_VBASE, UFLASH_START, UFLASH_START,
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UFLASH_SIZE, MMU_UTEXT_FLAGS);
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map_region(PGT_L3_ROMPBASE, UFLASH_START, UFLASH_START, UFLASH_SIZE,
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MMU_UTEXT_FLAGS);
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/* Setup the L3 references for data memory */
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mmu_ln_map_region(3, PGT_L3_VBASE, USRAM_START, USRAM_START,
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USRAM_SIZE, MMU_UDATA_FLAGS);
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map_region(PGT_L3_RAMPBASE, USRAM_START, USRAM_START, USRAM_SIZE,
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MMU_UDATA_FLAGS);
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/* Setup the L2 and L1 references */
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/* Connect the L1 and L2 page tables */
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mmu_ln_setentry(2, PGT_L2_VBASE, PGT_L3_PBASE, UFLASH_START, PTE_G);
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mmu_ln_setentry(1, PGT_L1_VBASE, PGT_L2_PBASE, UFLASH_START, PTE_G);
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/* Enable MMU */
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@ -259,4 +225,39 @@ static void configure_mmu(void)
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mmu_enable(PGT_L1_PBASE, 0);
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}
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/****************************************************************************
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* Name: map_region
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*
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* Description:
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* Map a region of physical memory to the L3 page table
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*
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* Input Parameters:
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* l3base - L3 page table physical base address
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* paddr - Beginning of the physical address mapping
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* vaddr - Beginning of the virtual address mapping
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* size - Size of the region in bytes
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* mmuflags - The MMU flags to use in the mapping
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*
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****************************************************************************/
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static void map_region(uintptr_t l3base, uintptr_t paddr, uintptr_t vaddr,
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size_t size, uint32_t mmuflags)
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{
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uintptr_t end_vaddr;
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/* Map the region to the L3 table as a whole */
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mmu_ln_map_region(3, l3base, paddr, vaddr, size, mmuflags);
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/* Connect to L2 table */
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end_vaddr = vaddr + size;
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while (vaddr < end_vaddr)
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{
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mmu_ln_setentry(2, PGT_L2_VBASE, l3base, vaddr, PTE_G);
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l3base += RV_MMU_L3_PAGE_SIZE;
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vaddr += RV_MMU_L2_PAGE_SIZE;
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}
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}
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#endif /* CONFIG_BUILD_PROTECTED */
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