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Missed definition for 4Kb page case

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2910 42af7a65-404d-4744-a932-0658087f49c3
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patacongo 2010-09-02 17:43:52 +00:00
parent 7c4b74e4f6
commit 6aa5aa20e1
2 changed files with 7 additions and 0 deletions
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1
arch/arm/src/arm/pg_macros.h
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@ -121,6 +121,7 @@
# define MMU_L2_TEXTFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
# define MMU_L1_DATAFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
# define MMU_L2_DATAFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
# define MMU_L2_ALLOCFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
# define MMU_L1_PGTABFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
# define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)

6
arch/arm/src/arm/up_allocpage.c
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@ -209,6 +209,12 @@ int up_allocpage(FAR _TCB *tcb, FAR void **vpage)
/* Invalidate the instruction TLB corresponding to the virtual address */
tlb_inst_invalidate_single(oldvaddr);
/* I do not believe that it is necessary to flush the I-Cache in this
* case: The I-Cache uses a virtual address index and, hence, since the
* NuttX address space is flat, the cached instruction value should be
* correct even if the page mapping is no longer in place.
*/
}
/* Then convert the index to a (physical) page address. */