From 6a5d00f68cd4c10ffcbb3d935b7785053f04b3d6 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Thu, 10 Aug 2023 10:03:27 +0300 Subject: [PATCH] arch/risc-v/src/mpfs: Add CFG_DDR_SGMII_PHY_RPC156 register setting for DDR training Decreasing the value may increase DQ/DQS window size. Keep the default value (1) for the existing board configurations. Signed-off-by: Jukka Laitinen --- arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h | 1 + arch/risc-v/src/mpfs/mpfs_ddr.c | 2 ++ boards/risc-v/mpfs/icicle/include/board_liberodefs.h | 1 + boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h | 1 + 4 files changed, 5 insertions(+) diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h b/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h index aacfabb2153..65959492bee 100644 --- a/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h +++ b/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h @@ -601,6 +601,7 @@ #define MPFS_CFG_DDR_SGMII_PHY_RPC20 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC20_OFFSET) #define MPFS_CFG_DDR_SGMII_PHY_RPC145 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC145_OFFSET) #define MPFS_CFG_DDR_SGMII_PHY_RPC147 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC147_OFFSET) +#define MPFS_CFG_DDR_SGMII_PHY_RPC156 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC156_OFFSET) #define MPFS_CFG_DDR_SGMII_PHY_RPC166 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC166_OFFSET) #define MPFS_CFG_DDR_SGMII_PHY_RPC168 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC168_OFFSET) #define MPFS_CFG_DDR_SGMII_PHY_RPC220 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC220_OFFSET) diff --git a/arch/risc-v/src/mpfs/mpfs_ddr.c b/arch/risc-v/src/mpfs/mpfs_ddr.c index 87121de1b6a..873af8bcdae 100644 --- a/arch/risc-v/src/mpfs/mpfs_ddr.c +++ b/arch/risc-v/src/mpfs/mpfs_ddr.c @@ -582,6 +582,8 @@ static void mpfs_set_ddr_rpc_regs(struct mpfs_ddr_priv_s *priv) #endif + putreg32(LIBERO_SETTING_RPC_156_VALUE, MPFS_CFG_DDR_SGMII_PHY_RPC156); + putreg32(0x2, MPFS_CFG_DDR_SGMII_PHY_RPC27); putreg32(0, MPFS_CFG_DDR_SGMII_PHY_RPC203); diff --git a/boards/risc-v/mpfs/icicle/include/board_liberodefs.h b/boards/risc-v/mpfs/icicle/include/board_liberodefs.h index 63259b7454d..badac2bdf41 100644 --- a/boards/risc-v/mpfs/icicle/include/board_liberodefs.h +++ b/boards/risc-v/mpfs/icicle/include/board_liberodefs.h @@ -82,6 +82,7 @@ #define LIBERO_SETTING_RPC_ODT_DQS 0x00000006 #define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000002 #define LIBERO_SETTING_RPC_ODT_CLK 0x00000002 +#define LIBERO_SETTING_RPC_156_VALUE 0x00000001 #define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000f00 #define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000fff #define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000fe6 diff --git a/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h b/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h index ec80a467a30..edab61a8e23 100644 --- a/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h +++ b/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h @@ -80,6 +80,7 @@ #define LIBERO_SETTING_RPC_ODT_DQS 0x00000006 #define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000006 #define LIBERO_SETTING_RPC_ODT_CLK 0x00000006 +#define LIBERO_SETTING_RPC_156_VALUE 0x00000001 #define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000000 #define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000003 #define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000dc4