diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 19721ae34a8..34d96a62e22 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -277,6 +277,13 @@ config ARCH_CHIP_NRF52 ---help--- Nordic NRF52 architectures (ARM Cortex-M4). +config ARCH_CHIP_NRF53 + bool "Nordic NRF53" + select ARCH_CORTEXM33 + depends on EXPERIMENTAL + ---help--- + Nordic NRF53 architectures (ARM dual Cortex-M33). + config ARCH_CHIP_NUC1XX bool "Nuvoton NUC100/120" select ARCH_CORTEXM0 @@ -937,6 +944,7 @@ config ARCH_CHIP default "max326xx" if ARCH_CHIP_MAX326XX default "moxart" if ARCH_CHIP_MOXART default "nrf52" if ARCH_CHIP_NRF52 + default "nrf53" if ARCH_CHIP_NRF53 default "nuc1xx" if ARCH_CHIP_NUC1XX default "rp2040" if ARCH_CHIP_RP2040 default "s32k1xx" if ARCH_CHIP_S32K1XX @@ -1303,6 +1311,9 @@ endif if ARCH_CHIP_NRF52 source "arch/arm/src/nrf52/Kconfig" endif +if ARCH_CHIP_NRF53 +source "arch/arm/src/nrf53/Kconfig" +endif if ARCH_CHIP_NUC1XX source "arch/arm/src/nuc1xx/Kconfig" endif diff --git a/arch/arm/include/nrf53/chip.h b/arch/arm/include/nrf53/chip.h new file mode 100644 index 00000000000..9ff48e7cdc1 --- /dev/null +++ b/arch/arm/include/nrf53/chip.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/arm/include/nrf53/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_NRF53_CHIP_H +#define __ARCH_ARM_INCLUDE_NRF53_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_NRF53_CHIP_H */ diff --git a/arch/arm/include/nrf53/irq.h b/arch/arm/include/nrf53/irq.h new file mode 100644 index 00000000000..2e933a1e6ad --- /dev/null +++ b/arch/arm/include/nrf53/irq.h @@ -0,0 +1,101 @@ +/**************************************************************************** + * arch/arm/include/nrf53/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_NRF53_IRQ_H +#define __ARCH_ARM_INCLUDE_NRF53_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to bits in + * the NVIC. This does, however, waste several words of memory in the IRQ to + * handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define NRF53_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define NRF53_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define NRF53_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define NRF53_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define NRF53_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define NRF53_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define NRF53_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define NRF53_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define NRF53_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define NRF53_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define NRF53_IRQ_EXTINT (16) /* Vector 16: Vector number of the first external interrupt */ + +/* Cortex-M4 External interrupts (vectors >= 16) */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_NRF5340) +# include +#else +# error "Unsupported NRF53XX MCU" +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*vic_vector_t)(uint32_t *regs); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_NRF53_IRQ_H */ diff --git a/arch/arm/include/nrf53/nrf5340_irq.h b/arch/arm/include/nrf53/nrf5340_irq.h new file mode 100644 index 00000000000..71d3b8206be --- /dev/null +++ b/arch/arm/include/nrf53/nrf5340_irq.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/include/nrf53/nrf5340_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_NRF5340_IRQ_H +#define __ARCH_ARM_INCLUDE_NRF5340_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_NRF5340_CPUAPP) +# include +#elif defined(CONFIG_ARCH_CHIP_NRF5340_CPUNET) +# include +#else +# error "Unsupported NRF5340 CPU" +#endif + +#endif /* __ARCH_ARM_INCLUDE_NRF5340_IRQ_H */ diff --git a/arch/arm/include/nrf53/nrf5340_irq_cpuapp.h b/arch/arm/include/nrf53/nrf5340_irq_cpuapp.h new file mode 100644 index 00000000000..5b0c7820b6f --- /dev/null +++ b/arch/arm/include/nrf53/nrf5340_irq_cpuapp.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/arm/include/nrf53/nrf5340_irq_cpuapp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_NRF53_NRF5340_IRQ_CPUAPP_H +#define __ARCH_ARM_INCLUDE_NRF53_NRF5340_IRQ_CPUAPP_H + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Cortex-M33 External interrupts (vectors >= 16) */ + +/* Application core */ + +#define NRF53_IRQ_FPU (NRF53_IRQ_EXTINT+0) /* FPU interrupt */ +#define NRF53_IRQ_CACHE (NRF53_IRQ_EXTINT+1) /* CACHE interrupt */ +#define NRF53_IRQ_SPU (NRF53_IRQ_EXTINT+3) /* SPU interrupt */ +#define NRF53_IRQ_POWER_CLOCK (NRF53_IRQ_EXTINT+5) /* Power, Clock, Bprot */ +#define NRF53_IRQ_UART0 (NRF53_IRQ_EXTINT+8) /* UART/UARTE 0 */ +#define NRF53_IRQ_UART1 (NRF53_IRQ_EXTINT+9) /* UART/UARTE 1 */ +#define NRF53_IRQ_SPIM4 (NRF53_IRQ_EXTINT+10) /* SPIM4 */ +#define NRF53_IRQ_UART2 (NRF53_IRQ_EXTINT+11) /* UART/UARTE 2 */ +#define NRF53_IRQ_UART3 (NRF53_IRQ_EXTINT+12) /* UART/UARTE 3 */ +#define NRF53_IRQ_GPIOTE0 (NRF53_IRQ_EXTINT+13) /* GPIO Task & Event 0 */ +#define NRF53_IRQ_SAADC (NRF53_IRQ_EXTINT+14) /* Analog to Digital Converter */ +#define NRF53_IRQ_TIMER0 (NRF53_IRQ_EXTINT+15) /* Timer 0 */ +#define NRF53_IRQ_TIMER1 (NRF53_IRQ_EXTINT+16) /* Timer 1 */ +#define NRF53_IRQ_TIMER2 (NRF53_IRQ_EXTINT+17) /* Timer 2 */ +#define NRF53_IRQ_RTC0 (NRF53_IRQ_EXTINT+20) /* Real-time counter 0 */ +#define NRF53_IRQ_RTC1 (NRF53_IRQ_EXTINT+21) /* Real-time counter 1 */ +#define NRF53_IRQ_WDT0 (NRF53_IRQ_EXTINT+24) /* Watchdog Timer 0 */ +#define NRF53_IRQ_WDT1 (NRF53_IRQ_EXTINT+25) /* Watchdog Timer 1 */ +#define NRF53_IRQ_COMP_LPCOMP (NRF53_IRQ_EXTINT+26) /* Low power comparator */ +#define NRF53_IRQ_EGU0 (NRF53_IRQ_EXTINT+27) /* Event Gen. Unit 0 */ +#define NRF53_IRQ_EGU1 (NRF53_IRQ_EXTINT+28) /* Event Gen. Unit 1 */ +#define NRF53_IRQ_EGU2 (NRF53_IRQ_EXTINT+29) /* Event Gen. Unit 2 */ +#define NRF53_IRQ_EGU3 (NRF53_IRQ_EXTINT+30) /* Event Gen. Unit 3 */ +#define NRF53_IRQ_EGU4 (NRF53_IRQ_EXTINT+31) /* Event Gen. Unit 4 */ +#define NRF53_IRQ_EGU5 (NRF53_IRQ_EXTINT+32) /* Event Gen. Unit 5 */ +#define NRF53_IRQ_PWM0 (NRF53_IRQ_EXTINT+33) /* Pulse Width Modulation Unit 0 */ +#define NRF53_IRQ_PWM1 (NRF53_IRQ_EXTINT+34) /* Pulse Width Modulation Unit 1 */ +#define NRF53_IRQ_PWM2 (NRF53_IRQ_EXTINT+35) /* Pulse Width Modulation Unit 2 */ +#define NRF53_IRQ_PWM3 (NRF53_IRQ_EXTINT+36) /* Pulse Width Modulation Unit 3 */ +#define NRF53_IRQ_PDM (NRF53_IRQ_EXTINT+38) /* Pulse Density Modulation (Digital Mic) Interface */ +#define NRF53_IRQ_I2S (NRF53_IRQ_EXTINT+40) /* Inter-IC Sound interface */ +#define NRF53_IRQ_IPC (NRF53_IRQ_EXTINT+42) /* IPC */ +#define NRF53_IRQ_QSPI (NRF53_IRQ_EXTINT+43) /* QSPI */ +#define NRF53_IRQ_NFCT (NRF53_IRQ_EXTINT+45) /* NFCT */ +#define NRF53_IRQ_GPIOTE1 (NRF53_IRQ_EXTINT+47) /* GPIO Task & Event 1 */ +#define NRF53_IRQ_QDEC0 (NRF53_IRQ_EXTINT+51) /* Quadrature decoder 0 */ +#define NRF53_IRQ_QDEC1 (NRF53_IRQ_EXTINT+52) /* Quadrature decoder 1 */ +#define NRF53_IRQ_USBD (NRF53_IRQ_EXTINT+54) /* USBD */ +#define NRF53_IRQ_USBREG (NRF53_IRQ_EXTINT+55) /* USBREGULATOR */ +#define NRF53_IRQ_KMU (NRF53_IRQ_EXTINT+57) /* KMU */ +#define NRF53_IRQ_CRYPTOCELL (NRF53_IRQ_EXTINT+68) /* CRYPTOCELL */ + +#define NRF53_IRQ_NEXTINT (69) + +#define NRF53_IRQ_NIRQS (NRF53_IRQ_EXTINT+NRF53_IRQ_NEXTINT) + +/* Total number of IRQ numbers */ + +#define NR_IRQS NRF53_IRQ_NIRQS + +#endif /* __ARCH_ARM_INCLUDE_NRF53_NRF5340_IRQ_CPUAPP_H */ diff --git a/arch/arm/include/nrf53/nrf5340_irq_cpunet.h b/arch/arm/include/nrf53/nrf5340_irq_cpunet.h new file mode 100644 index 00000000000..010b114c760 --- /dev/null +++ b/arch/arm/include/nrf53/nrf5340_irq_cpunet.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/arm/include/nrf53/nrf5340_irq_cpunet.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_NRF53_NRF5340_IRQ_CPUNET_H +#define __ARCH_ARM_INCLUDE_NRF53_NRF5340_IRQ_CPUNET_H + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Cortex-M33 External interrupts (vectors >= 16) */ + +/* Network core */ + +#define NRF53_IRQ_POWER_CLOCK (NRF53_IRQ_EXTINT+5) /* Power, Clock, Bprot */ +#define NRF53_IRQ_RADIO (NRF53_IRQ_EXTINT+8) /* Radio controller */ +#define NRF53_IRQ_RNG (NRF53_IRQ_EXTINT+9) /* Random Number Generator */ +#define NRF53_IRQ_GPIOTE (NRF53_IRQ_EXTINT+10) /* GPIO Task & Event */ +#define NRF53_IRQ_WDT (NRF53_IRQ_EXTINT+11) /* Watchdog Timer */ +#define NRF53_IRQ_TIMER0 (NRF53_IRQ_EXTINT+12) /* Timer 0 */ +#define NRF53_IRQ_ECB (NRF53_IRQ_EXTINT+13) /* AES ECB Mode Encryption */ +#define NRF53_IRQ_CCM_AAR (NRF53_IRQ_EXTINT+14) /* AES CCM Mode Encryption/Accel. Address Resolve */ +#define NRF53_IRQ_TEMP (NRF53_IRQ_EXTINT+16) /* Temperature Sensor */ +#define NRF53_IRQ_RTC0 (NRF53_IRQ_EXTINT+17) /* Real-time counter 0 */ +#define NRF53_IRQ_IPC (NRF53_IRQ_EXTINT+18) /* IPC */ +#define NRF53_IRQ_UART0 (NRF53_IRQ_EXTINT+19) /* UART/UARTE 0 */ +#define NRF53_IRQ_EGU0 (NRF53_IRQ_EXTINT+20) /* Event Gen. Unit 0 */ +#define NRF53_IRQ_RTC1 (NRF53_IRQ_EXTINT+22) /* Real-time counter 1 */ +#define NRF53_IRQ_TIMER1 (NRF53_IRQ_EXTINT+24) /* Timer 1 */ +#define NRF53_IRQ_TIMER2 (NRF53_IRQ_EXTINT+25) /* Timer 2 */ +#define NRF53_IRQ_SWI0 (NRF53_IRQ_EXTINT+26) /* Software interrupt 0 */ +#define NRF53_IRQ_SWI1 (NRF53_IRQ_EXTINT+27) /* Software interrupt 1 */ +#define NRF53_IRQ_SWI2 (NRF53_IRQ_EXTINT+28) /* Software interrupt 2 */ +#define NRF53_IRQ_SWI3 (NRF53_IRQ_EXTINT+29) /* Software interrupt 3 / Event Gen. Unit 3 */ + +#define NRF53_IRQ_NEXTINT (30) + +#define NRF53_IRQ_NIRQS (NRF53_IRQ_EXTINT+NRF53_IRQ_NEXTINT) + +/* Total number of IRQ numbers */ + +#define NR_IRQS NRF53_IRQ_NIRQS + +#endif /* __ARCH_ARM_INCLUDE_NRF53_NRF5340_IRQ_CPUNET_H */ diff --git a/arch/arm/src/nrf53/Kconfig b/arch/arm/src/nrf53/Kconfig new file mode 100644 index 00000000000..215ffa92d0a --- /dev/null +++ b/arch/arm/src/nrf53/Kconfig @@ -0,0 +1,54 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "NRF53 Configuration Options" + +choice + prompt "NRF53 Chip Selection" + default ARCH_CHIP_NRF5340 + depends on ARCH_CHIP_NRF53 + +config ARCH_CHIP_NRF5340 + bool "NRF5340" + +endchoice # NRF53 Chip Selection + +# NRF53 Families + + +choice + prompt "NRF5340 Core Selection" + default ARCH_CHIP_NRF5340_CPUAPP + depends on ARCH_CHIP_NRF5340 + +config ARCH_CHIP_NRF5340_CPUAPP + bool "NRF53 App core" + +config ARCH_CHIP_NRF5340_CPUNET + bool "NRF53 Net core" + +endchoice # NRF5340 Core Selection + +# Peripheral Selection + +config NRF53_UART + bool + default n + +menu "NRF53 Peripheral Selection" + +config NRF53_UART0 + bool "UART0" + default n + select UART0_SERIALDRIVER + select NRF53_UART + +config NRF53_UART1 + bool "UART1" + default n + select UART1_SERIALDRIVER + select NRF53_UART + +endmenu # NRF53 Peripheral Selection diff --git a/arch/arm/src/nrf53/Make.defs b/arch/arm/src/nrf53/Make.defs new file mode 100644 index 00000000000..f01f7ce30c8 --- /dev/null +++ b/arch/arm/src/nrf53/Make.defs @@ -0,0 +1,33 @@ +############################################################################ +# arch/arm/src/nrf53/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv8-m/Make.defs + +CHIP_CSRCS += nrf53_systick.c +CHIP_CSRCS += nrf53_start.c nrf53_clockconfig.c nrf53_irq.c nrf53_utils.c +CHIP_CSRCS += nrf53_allocateheap.c nrf53_lowputc.c nrf53_gpio.c + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += nrf53_idle.c +endif + +ifeq ($(CONFIG_NRF53_UART),y) +CHIP_CSRCS += nrf53_serial.c +endif \ No newline at end of file diff --git a/arch/arm/src/nrf53/chip.h b/arch/arm/src/nrf53/chip.h new file mode 100644 index 00000000000..2e1c8bf34f5 --- /dev/null +++ b/arch/arm/src/nrf53/chip.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/nrf53/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_CHIP_H +#define __ARCH_ARM_SRC_NRF53_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the memory map and the chip definitions file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include +#include +#include "hardware/nrf53_memorymap.h" + +/* If the common ARMv7-M vector handling logic is used, then it expects the + * following definition in this file that provides the number of supported + * external interrupts which, for this architecture, is provided in the + * arch/nrf53/chip.h header file. + */ + +#define ARMV8M_PERIPHERAL_INTERRUPTS NRF53_IRQ_NEXTINT + +#endif /* __ARCH_ARM_SRC_NRF53_CHIP_H */ diff --git a/arch/arm/src/nrf53/hardware/nrf53_gpio.h b/arch/arm/src/nrf53/hardware/nrf53_gpio.h new file mode 100644 index 00000000000..57b04c53f0c --- /dev/null +++ b/arch/arm/src/nrf53/hardware/nrf53_gpio.h @@ -0,0 +1,118 @@ +/**************************************************************************** + * arch/arm/src/nrf53/hardware/nrf53_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_GPIO_H +#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "hardware/nrf53_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NRF53_GPIO_NPORTS 2 +#define NRF53_GPIO_PORT0 0 +#define NRF53_GPIO_PORT1 1 + +#define NRF53_GPIO_NPINS 32 + +/* Register offsets *********************************************************/ + +#define NRF53_GPIO_OUT_OFFSET 0x0004 /* Write GPIO port */ +#define NRF53_GPIO_OUTSET_OFFSET 0x0008 /* Set individual bits in GPIO port */ +#define NRF53_GPIO_OUTCLR_OFFSET 0x000c /* Clear individual bits in GPIO port */ +#define NRF53_GPIO_IN_OFFSET 0x0010 /* Read GPIO port */ +#define NRF53_GPIO_DIR_OFFSET 0x0014 /* Direction of GPIO pins */ +#define NRF53_GPIO_DIRSET_OFFSET 0x0018 /* DIR set register */ +#define NRF53_GPIO_DIRCLR_OFFSET 0x001c /* DIR clear register */ +#define NRF53_GPIO_LATCH_OFFSET 0x0020 /* Latch register */ +#define NRF53_GPIO_DETECTMODE_OFFSET 0x0024 /* Select between default DETECT signal behaviour and LDETECT mode (non-secure) */ +#define NRF53_GPIO_DETECTMODESEC_OFFSET 0x0024 /* Select between default DETECT signal behaviour and LDETECT mode (secure) */ + +#define NRF53_GPIO_PIN_CNF_OFFSET(n) (0x0200 + (n << 2)) + +/* Register addresses *******************************************************/ + +#define NRF53_GPIO0_OUT (NRF53_GPIO_P0_BASE + NRF53_GPIO_OUT_OFFSET) +#define NRF53_GPIO0_OUTSET (NRF53_GPIO_P0_BASE + NRF53_GPIO_OUTSET_OFFSET) +#define NRF53_GPIO0_OUTCLR (NRF53_GPIO_P0_BASE + NRF53_GPIO_OUTCLR_OFFSET) +#define NRF53_GPIO0_IN (NRF53_GPIO_P0_BASE + NRF53_GPIO_IN_OFFSET) +#define NRF53_GPIO0_DIR (NRF53_GPIO_P0_BASE + NRF53_GPIO_DIR_OFFSET) +#define NRF53_GPIO0_DIRSET (NRF53_GPIO_P0_BASE + NRF53_GPIO_DIRSET_OFFSET) +#define NRF53_GPIO0_DIRCLR (NRF53_GPIO_P0_BASE + NRF53_GPIO_DIRCLR_OFFSET) +#define NRF53_GPIO0_CNF(n) (NRF53_GPIO_P0_BASE + NRF53_GPIO_PIN_CNF_OFFSET(n)) + +#ifdef CONFIG_NRF53_HAVE_PORT1 +# define NRF53_GPIO1_OUT (NRF53_GPIO_P1_BASE + NRF53_GPIO_OUT_OFFSET) +# define NRF53_GPIO1_OUTSET (NRF53_GPIO_P1_BASE + NRF53_GPIO_OUTSET_OFFSET) +# define NRF53_GPIO1_OUTCLR (NRF53_GPIO_P1_BASE + NRF53_GPIO_OUTCLR_OFFSET) +# define NRF53_GPIO1_IN (NRF53_GPIO_P1_BASE + NRF53_GPIO_IN_OFFSET) +# define NRF53_GPIO1_DIR (NRF53_GPIO_P1_BASE + NRF53_GPIO_DIR_OFFSET) +# define NRF53_GPIO1_DIRSET (NRF53_GPIO_P1_BASE + NRF53_GPIO_DIRSET_OFFSET) +# define NRF53_GPIO1_DIRCLR (NRF53_GPIO_P1_BASE + NRF53_GPIO_DIRCLR_OFFSET) +# define NRF53_GPIO1_CNF(n) (NRF53_GPIO_P1_BASE + NRF53_GPIO_PIN_CNF_OFFSET(n)) +#endif + +/* Register bit definitions *************************************************/ + +#define GPIO_DETECTMODE_DEFAULT (0) +#define GPIO_DETECTMODE_LDETECT (1) + +#define GPIO_CNF_DIR (1 << 0) /* Bit 0: Pin direction */ +#define GPIO_CNF_INPUT (1 << 1) /* Bit 1: Input buffer disconnect */ +#define GPIO_CNF_PULL_SHIFT (2) +#define GPIO_CNF_PULL_MASK (0x3 << GPIO_CNF_PULL_SHIFT) +# define GPIO_CNF_PULL_DISABLED (0 << GPIO_CNF_PULL_SHIFT) +# define GPIO_CNF_PULL_DOWN (1 << GPIO_CNF_PULL_SHIFT) +# define GPIO_CNF_PULL_UP (3 << GPIO_CNF_PULL_SHIFT) +#define GPIO_CNF_DRIVE_SHIFT (8) +#define GPIO_CNF_DRIVE_MASK (0xf << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_S0S1 (0 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_H0S1 (1 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_S0H1 (2 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_H0H1 (3 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_D0S1 (4 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_D0H1 (5 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_S0D1 (6 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_H0D1 (7 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_EOS1 (9 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_SOE1 (10 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_EOE1 (11 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_DOE1 (13 << GPIO_CNF_DRIVE_SHIFT) +# define GPIO_CNF_DRIVE_EOD1 (15 << GPIO_CNF_DRIVE_SHIFT) +#define GPIO_CNF_SENSE_SHIFT (16) +#define GPIO_CNF_SENSE_MASK (0x3 << GPIO_CNF_SENSE_SHIFT) +# define GPIO_CNF_SENSE_DISABLED (0 << GPIO_CNF_SENSE_SHIFT) +# define GPIO_CNF_SENSE_HIGH (2 << GPIO_CNF_SENSE_SHIFT) +# define GPIO_CNF_SENSE_LOW (3 << GPIO_CNF_SENSE_SHIFT) +#define GPIO_CNF_MCUSEL_SHIFT (28) +#define GPIO_CNF_MCUSEL_MASK (0x7 << GPIO_CNF_MCUSEL_SHIFT) +# define GPIO_CNF_MCUSEL_CPUAPP (0 << GPIO_CNF_MCUSEL_SHIFT) +# define GPIO_CNF_MCUSEL_CPUNET (1 << GPIO_CNF_MCUSEL_SHIFT) +# define GPIO_CNF_MCUSEL_PERIP (3 << GPIO_CNF_MCUSEL_SHIFT) +# define GPIO_CNF_MCUSEL_TND (4 << GPIO_CNF_MCUSEL_SHIFT) + +#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_GPIO_H */ diff --git a/arch/arm/src/nrf53/hardware/nrf53_memorymap.h b/arch/arm/src/nrf53/hardware/nrf53_memorymap.h new file mode 100644 index 00000000000..dd7b021d651 --- /dev/null +++ b/arch/arm/src/nrf53/hardware/nrf53_memorymap.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/nrf53/hardware/nrf53_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_MEMORYMAP_H +#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_NRF5340_CPUAPP) +# include "hardware/nrf53_memorymap_cpuapp.h" +#elif defined(CONFIG_ARCH_CHIP_NRF5340_CPUNET) +# include "hardware/nrf53_memorymap_cpunet.h" +#else +# error "Unsupported NRF5340 CPU" +#endif + +#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_MEMORYMAP_H */ diff --git a/arch/arm/src/nrf53/hardware/nrf53_memorymap_cpuapp.h b/arch/arm/src/nrf53/hardware/nrf53_memorymap_cpuapp.h new file mode 100644 index 00000000000..288d75f19cf --- /dev/null +++ b/arch/arm/src/nrf53/hardware/nrf53_memorymap_cpuapp.h @@ -0,0 +1,108 @@ +/**************************************************************************** + * arch/arm/src/nrf53/hardware/nrf53_memorymap_cpuapp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_MEMORYMAP_CPUAPP_H +#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_MEMORYMAP_CPUAPP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Memory Map */ + +#define NRF53_FLASH_BASE 0x00000000 /* Flash memory Start Address */ +#define NRF53_SRAM_BASE 0x20000000 /* SRAM Start Address */ + +#define NRF53_CORTEXM33_BASE 0xe0000000 /* Cortex-M33 Private Peripheral Bus */ + +/* APB Peripherals */ + +#define NRF53_DCNF_BASE 0x50000000 +#define NRF53_FPU_BASE 0x50000000 +#define NRF53_CACHE_BASE 0x50001000 +#define NRF53_SPU_BASE 0x50003000 +#define NRF53_OSCILLATORS_BASE 0x50004000 +#define NRF53_REGULATORS_BASE 0x50004000 +#define NRF53_CLOCK_BASE 0x50005000 +#define NRF53_POWER_BASE 0x50005000 +#define NRF53_RESET_BASE 0x50005000 +#define NRF53_CTRLAPPERI_BASE 0x50006000 +#define NRF53_SPIM0_BASE 0x50008000 +#define NRF53_SPIS0_BASE 0x50008000 +#define NRF53_TWIM0_BASE 0x50008000 +#define NRF53_TWIS0_BASE 0x50008000 +#define NRF53_UART0_BASE 0x50008000 +#define NRF53_SPIM1_BASE 0x50009000 +#define NRF53_SPIS1_BASE 0x50009000 +#define NRF53_TWIM1_BASE 0x50009000 +#define NRF53_TWIS1_BASE 0x50009000 +#define NRF53_UART1_BASE 0x50009000 +#define NRF53_SPIM2_BASE 0x5000A000 +#define NRF53_GPIOTE0_BASE 0x5000D000 +#define NRF53_SAADC_BASE 0x5000E000 +#define NRF53_TIMER0_BASE 0x5000F000 +#define NRF53_TIMER1_BASE 0x50010000 +#define NRF53_TIMER2_BASE 0x50011000 +#define NRF53_RTC0_BASE 0x50014000 +#define NRF53_RTC1_BASE 0x50015000 +#define NRF53_DPPIC_BASE 0x50017000 +#define NRF53_WDT0_BASE 0x50018000 +#define NRF53_WDT1_BASE 0x50019000 +#define NRF53_COMP_BASE 0x5001A000 +#define NRF53_LPCOMP_BASE 0x5001A000 +#define NRF53_EGU0_BASE 0x5001B000 +#define NRF53_EGU1_BASE 0x5001C000 +#define NRF53_EGU2_BASE 0x5001D000 +#define NRF53_EGU3_BASE 0x5001E000 +#define NRF53_EGU4_BASE 0x5001F000 +#define NRF53_EGU5_BASE 0x50020000 +#define NRF53_PWM0_BASE 0x50021000 +#define NRF53_PWM1_BASE 0x50022000 +#define NRF53_PWM2_BASE 0x50023000 +#define NRF53_PDM0_BASE 0x50026000 +#define NRF53_I2S0_BASE 0x50028000 +#define NRF53_IPC_BASE 0x5002A000 +#define NRF53_QSPI_BASE 0x5002B000 +#define NRF53_NFCT_BASE 0x5002D000 +#define NRF53_GPIOTE1_BASE 0x4002F000 +#define NRF53_MUTEX_BASE 0x50030000 +#define NRF53_QDEC_BASE 0x50033000 +#define NRF53_USBD_BASE 0x50036000 +#define NRF53_USBREGULATOR_BASE 0x50037000 +#define NRF53_KMU_BASE 0x50039000 +#define NRF53_NVMC_BASE 0x50039000 +#define NRF53_GPIO_P0_BASE 0x50842500 +#define NRF53_GPIO_P1_BASE 0x50842800 +#define NRF53_CRYPTOCELL_BASE 0x50844000 +#define NRF53_VMC_BASE 0x50081000 +#define NRF53_CACHEDATA_BASE 0x00F00000 +#define NRF53_CACHEINFO_BASE 0x00F00000 +#define NRF53_FCIR_BASE 0x00FF0000 +#define NRF53_UICR_BASE 0x00FF8000 +#define NRF53_CTI_BASE 0xE0042000 +#define NRF53_TAD_BASE 0xE0080000 + +#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_MEMORYMAP_CPUAPP_H */ diff --git a/arch/arm/src/nrf53/hardware/nrf53_memorymap_cpunet.h b/arch/arm/src/nrf53/hardware/nrf53_memorymap_cpunet.h new file mode 100644 index 00000000000..8479c61bbd2 --- /dev/null +++ b/arch/arm/src/nrf53/hardware/nrf53_memorymap_cpunet.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/arm/src/nrf53/hardware/nrf53_memorymap_cpunet.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_MEMORYMAP_CPUNET_H +#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_MEMORYMAP_CPUNET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Memory Map */ + +#define NRF53_FLASH_BASE 0x01000000 /* Flash memory Start Address */ +#define NRF53_SRAM_BASE 0x21000000 /* SRAM Start Address */ + +#define NRF53_CORTEXM33_BASE 0xe0000000 /* Cortex-M33 Private Peripheral Bus */ + +/* APB Peripherals */ + +#define NRF53_DCNF_BASE 0x41000000 +#define NRF53_VREQCTRL_BASE 0x41004000 +#define NRF53_CLOCK_BASE 0x41005000 +#define NRF53_POWER_BASE 0x41005000 +#define NRF53_RESET_BASE 0x41005000 +#define NRF53_CTRLAPPERI_BASE 0x41006000 +#define NRF53_RADIO_BASE 0x41008000 +#define NRF53_RNG_BASE 0x41009000 +#define NRF53_GPIOTE_BASE 0x4100A000 +#define NRF53_WDT_BASE 0x4100B000 +#define NRF53_TIMER0_BASE 0x4100C000 +#define NRF53_ECB_BASE 0x4100D000 +#define NRF53_AAR_BASE 0x4100E000 +#define NRF53_CCM_BASE 0x4100E000 +#define NRF53_DPPIC_BASE 0x4100F000 +#define NRF53_TEMP_BASE 0x41010000 +#define NRF53_RTC_BASE 0x41011000 +#define NRF53_IPC_BASE 0x41012000 +#define NRF53_SPIM0_BASE 0x41013000 +#define NRF53_SPIS0_BASE 0x41013000 +#define NRF53_TWIM0_BASE 0x41013000 +#define NRF53_TWIS0_BASE 0x41013000 +#define NRF53_UART0_BASE 0x41013000 +#define NRF53_EGU0_BASE 0x41014000 +#define NRF53_RTC1_BASE 0x41016000 +#define NRF53_TIMER1_BASE 0x41018000 +#define NRF53_TIMER2_BASE 0x41019000 +#define NRF53_SWI0_BASE 0x4101A000 +#define NRF53_SWI1_BASE 0x4101B000 +#define NRF53_SWI2_BASE 0x4101C000 +#define NRF53_SWI3_BASE 0x4101D000 +#define NRF53_ACL_BASE 0x41080000 +#define NRF53_NVMC_BASE 0x41080000 +#define NRF53_VMC_BASE 0x41081000 +#define NRF53_GPIO_P0_BASE 0x418C0500 +#define NRF53_GPIO_P1_BASE 0x418C0800 +#define NRF53_FICR_BASE 0x01FF0000 +#define NRF53_UICR_BASE 0x01FF8000 +#define NRF53_CTI_BASE 0xE0042000 + +#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_MEMORYMAP_CPUNET_H */ diff --git a/arch/arm/src/nrf53/hardware/nrf53_power.h b/arch/arm/src/nrf53/hardware/nrf53_power.h new file mode 100644 index 00000000000..ccbba3cb11b --- /dev/null +++ b/arch/arm/src/nrf53/hardware/nrf53_power.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/arm/src/nrf53/hardware/nrf53_power.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_POWER_H +#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_POWER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nrf53_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define NRF53_POWER_TASKS_CONSTLAT_OFFSET 0x000078 /* Enable constant latency mode */ +#define NRF53_POWER_TASKS_LOWPWR_OFFSET 0x00007c /* Enable low power mode (variable latency) */ +#define NRF53_POWER_EVENTS_POFWARN_OFFSET 0x000108 /* Power failure warning */ +#define NRF53_POWER_EVENTS_SLEEPENTER_OFFSET 0x000114 /* CPU entered WFI/WFE sleep */ +#define NRF53_POWER_EVENTS_SLEEPEXIT_OFFSET 0x000118 /* CPU exited WFI/WFE sleep */ +#define NRF53_POWER_PUBLISH_POFWARN_OFFSET 0x000188 /* Publish configuration for event POFWARN */ +#define NRF53_POWER_PUBLISH_SLEEPENTER_OFFSET 0x000194 /* Publish configuration for event SLEEPENTER */ +#define NRF53_POWER_PUBLISH_SLEEPEXIT_OFFSET 0x000198 /* Publish configuration for event SLEEPEXIT */ +#define NRF53_POWER_INTEN_OFFSET 0x000300 /* Enable or disable interrupt */ +#define NRF53_POWER_INTENSET_OFFSET 0x000304 /* Enable interrupt */ +#define NRF53_POWER_INTENCLR_OFFSET 0x000308 /* Disable interrupt */ +#define NRF53_POWER_GPREGRET0_OFFSET 0x00051c /* General purpose retention register 1 */ +#define NRF53_POWER_GPREGRET1_OFFSET 0x000520 /* General purpose retention register 2 */ + +/* Register definitions *****************************************************/ + +#define NRF53_POWER_TASKS_CONSTLAT (NRF53_POWER_BASE + NRF53_POWER_TASKS_CONSTLAT_OFFSET) +#define NRF53_POWER_TASKS_LOWPWR (NRF53_POWER_BASE + NRF53_POWER_TASKS_LOWPWR_OFFSET) +#define NRF53_POWER_EVENTS_POFWARN (NRF53_POWER_BASE + NRF53_POWER_EVENTS_POFWARN_OFFSET) +#define NRF53_POWER_EVENTS_SLEEPENTER (NRF53_POWER_BASE + NRF53_POWER_EVENTS_SLEEPENTER_OFFSET) +#define NRF53_POWER_EVENTS_SLEEPEXIT (NRF53_POWER_BASE + NRF53_POWER_EVENTS_SLEEPEXIT_OFFSET) +#define NRF53_POWER_PUBLISH_POFWARN (NRF53_POWER_BASE + NRF53_POWER_PUBLISH_POFWARN_OFFSET) +#define NRF53_POWER_PUBLISH_SLEEPENTER (NRF53_POWER_BASE + NRF53_POWER_PUBLISH_SLEEPENTER_OFFSET) +#define NRF53_POWER_PUBLISH_SLEEPEXIT (NRF53_POWER_BASE + NRF53_POWER_PUBLISH_SLEEPEXIT_OFFSET) +#define NRF53_POWER_INTEN (NRF53_POWER_BASE + NRF53_POWER_INTEN_OFFSET) +#define NRF53_POWER_INTENSET (NRF53_POWER_BASE + NRF53_POWER_INTENSET_OFFSET) +#define NRF53_POWER_INTENCLR (NRF53_POWER_BASE + NRF53_POWER_INTENCLR_OFFSET) +#define NRF53_POWER_GPREGRET1 (NRF53_POWER_BASE + NRF53_POWER_GPREGRET1_OFFSET) +#define NRF53_POWER_GPREGRET2 (NRF53_POWER_BASE + NRF53_POWER_GPREGRET2_OFFSET) + +/* Register bit definitions *************************************************/ + +#define NRF53_POWER_INTENSET_POFWARN (1 << 2) /* Read: Enabled */ +#define NRF53_POWER_INTENSET_SLEEPENTER (1 << 5) /* Read: Enabled */ +#define NRF53_POWER_INTENSET_SLEEPEXIT (1 << 6) /* Read: Enabled */ + +#define NRF53_POWER_INTENCLR_POFWARN (1 << 2) /* Read: Enabled */ +#define NRF53_POWER_INTENCLR_SLEEPENTER (1 << 5) /* Read: Enabled */ +#define NRF53_POWER_INTENCLR_SLEEPEXIT (1 << 6) /* Read: Enabled */ + +#define NRF53_POWER_SYSTEMOFF_ENABLE (1 << 0) /* Enable System OFF mode */ + +#define NRF53_POWER_GPREGRET1_MASK (0xff) /* General purpose retention register 1 */ + +#define NRF53_POWER_GPREGRET2_GPREGRET_MASK (0xff) /* General purpose retention register 2*/ + +#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_POWER_H */ diff --git a/arch/arm/src/nrf53/hardware/nrf53_uarte.h b/arch/arm/src/nrf53/hardware/nrf53_uarte.h new file mode 100644 index 00000000000..18669e07e1d --- /dev/null +++ b/arch/arm/src/nrf53/hardware/nrf53_uarte.h @@ -0,0 +1,307 @@ +/*************************************************************************** + * arch/arm/src/nrf53/hardware/nrf53_uarte.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UARTE_H +#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UARTE_H + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include +#include "hardware/nrf53_memorymap.h" + +/*************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* UART/UARTE Register Offsets *********************************************/ + +#define NRF53_UARTE_TASKS_STARTRX_OFFSET 0x0000 /* Start UART receiver */ +#define NRF53_UARTE_TASKS_STOPRX_OFFSET 0x0004 /* Stop UART receiver */ +#define NRF53_UARTE_TASKS_STARTTX_OFFSET 0x0008 /* Start UART transmitter */ +#define NRF53_UARTE_TASKS_STOPTX_OFFSET 0x000c /* Stop UART transmitter */ +#define NRF53_UARTE_TASKS_FLUSHRX_OFFSET 0x002c /* Flush RX FIFO into RX buffer */ +#define NRF53_UARTE_EVENTS_CTS_OFFSET 0x0100 /* CTS is activated (set low). Clear To Send. */ +#define NRF53_UARTE_EVENTS_NCTS_OFFSET 0x0104 /* CTS is deactivated (set high). Not Clear To Send. */ +#define NRF53_UARTE_EVENTS_RXDRDY_OFFSET 0x0108 /* Data received in RXD (but potentially not yet transferred to Data RAM) */ +#define NRF53_UARTE_EVENTS_ENDRX_OFFSET 0x0110 /* Receive buffer is filled up */ +#define NRF53_UARTE_EVENTS_TXDRDY_OFFSET 0x011c /* Data sent from TXD */ +#define NRF53_UARTE_EVENTS_ENDTX_OFFSET 0x0120 /* Last TX byte transmitted */ +#define NRF53_UARTE_EVENTS_ERROR_OFFSET 0x0124 /* Error detected */ +#define NRF53_UARTE_EVENTS_RXTO_OFFSET 0x0144 /* Receiver timeout */ +#define NRF53_UARTE_EVENTS_RXSTARTED_OFFSET 0x014c /* UART receiver has started */ +#define NRF53_UARTE_EVENTS_TXSTARTED_OFFSET 0x0150 /* UART transmitter has started */ +#define NRF53_UARTE_EVENTS_TXSTOPPED_OFFSET 0x0158 /* Transmitter stopped */ +#define NRF53_UARTE_SHORTS_OFFSET 0x0200 /* Shortcut register */ +#define NRF53_UARTE_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */ +#define NRF53_UARTE_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF53_UARTE_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF53_UARTE_ERRORSRC_OFFSET 0x0480 /* Error source */ +#define NRF53_UARTE_ENABLE_OFFSET 0x0500 /* Enable UART */ +#define NRF53_UARTE_PSEL_RTS_OFFSET 0x0508 /* Pin select for RTS signal */ +#define NRF53_UARTE_PSEL_TXD_OFFSET 0x050c /* Pin select for TXD signal */ +#define NRF53_UARTE_PSEL_CTS_OFFSET 0x0510 /* Pin select for CTS signal */ +#define NRF53_UARTE_PSEL_RXD_OFFSET 0x0514 /* Pin select for RXD signal */ +#define NRF53_UARTE_BAUDRATE_OFFSET 0x0524 /* Baud rate. Accuracy depends on the HFCLK source selected. */ +#define NRF53_UARTE_RXD_PTR_OFFSET 0x0534 /* Data pointer */ +#define NRF53_UARTE_RXD_MAXCNT_OFFSET 0x0538 /* Maximum number of bytes in receive buffer */ +#define NRF53_UARTE_RXD_AMOUNT_OFFSET 0x053c /* Number of bytes transferred in the last transaction */ +#define NRF53_UARTE_TXD_PTR_OFFSET 0x0544 /* Data pointer */ +#define NRF53_UARTE_TXD_MAXCNT_OFFSET 0x0548 /* Maximum number of bytes in transmit buffer */ +#define NRF53_UARTE_TXD_AMOUNT_OFFSET 0x054c /* Number of bytes transferred in the last transaction */ +#define NRF53_UARTE_CONFIG_OFFSET 0x056c /* Configuration of parity and hardware flow control */ + +#define NRF53_UART_TASKS_STARTRX_OFFSET 0x0000 /* Start UART receiver */ +#define NRF53_UART_TASKS_STOPRX_OFFSET 0x0004 /* Stop UART receiver */ +#define NRF53_UART_TASKS_STARTTX_OFFSET 0x0008 /* Start UART transmitter */ +#define NRF53_UART_TASKS_STOPTX_OFFSET 0x000c /* Stop UART transmitter */ +#define NRF53_UART_TASKS_SUSPEND_OFFSET 0x001c /* Suspend UART */ +#define NRF53_UART_EVENTS_CTS_OFFSET 0x0100 /* CTS is activated (set low). Clear To Send. */ +#define NRF53_UART_EVENTS_NCTS_OFFSET 0x0104 /* CTS is deactivated (set high). Not Clear To Send. */ +#define NRF53_UART_EVENTS_RXDRDY_OFFSET 0x0108 /* Data received in RXD */ +#define NRF53_UART_EVENTS_TXDRDY_OFFSET 0x011c /* Data sent from TXD */ +#define NRF53_UART_EVENTS_ERROR_OFFSET 0x0124 /* Error detected */ +#define NRF53_UART_EVENTS_RXTO_OFFSET 0x0144 /* Receiver timeout */ +#define NRF53_UART_SHORTS_OFFSET 0x0200 /* Shortcut register */ +#define NRF53_UART_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF53_UART_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF53_UART_ERRORSRC_OFFSET 0x0480 /* Error source */ +#define NRF53_UART_ENABLE_OFFSET 0x0500 /* Enable UART */ +#define NRF53_UART_PSELRTS_OFFSET 0x0508 /* Pin select for RTS */ +#define NRF53_UART_PSELTXD_OFFSET 0x050c /* Pin select for TXD */ +#define NRF53_UART_PSELCTS_OFFSET 0x0510 /* Pin select for CTS */ +#define NRF53_UART_PSELRXD_OFFSET 0x0514 /* Pin select for RXD */ +#define NRF53_UART_RXD_OFFSET 0x0518 /* RXD register */ +#define NRF53_UART_TXD_OFFSET 0x051c /* TXD register */ +#define NRF53_UART_BAUDRATE_OFFSET 0x0524 /* Baud rate */ +#define NRF53_UART_CONFIG_OFFSET 0x056c /* Configuration of parity and hardware flow control */ + +/* UART/UARTE Register Addresses *******************************************/ + +#define NRF53_UARTE0_TASKS_STARTRX (NRF53_UARTE0_BASE + NRF53_UARTE_TASKS_STARTRX_OFFSET) +#define NRF53_UARTE0_TASKS_STOPRX (NRF53_UARTE0_BASE + NRF53_UARTE_TASKS_STOPRX_OFFSET) +#define NRF53_UARTE0_TASKS_STARTTX (NRF53_UARTE0_BASE + NRF53_UARTE_TASKS_STARTTX_OFFSET) +#define NRF53_UARTE0_TASKS_STOPTX (NRF53_UARTE0_BASE + NRF53_UARTE_TASKS_STOPTX_OFFSET) +#define NRF53_UARTE0_TASKS_FLUSHRX (NRF53_UARTE0_BASE + NRF53_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF53_UARTE0_EVENTS_CTS (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_CTS_OFFSET) +#define NRF53_UARTE0_EVENTS_NCTS (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_NCTS_OFFSET) +#define NRF53_UARTE0_EVENTS_RXDRDY (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF53_UARTE0_EVENTS_ENDRX (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_ENDRX_OFFSET) +#define NRF53_UARTE0_EVENTS_TXDRDY (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF53_UARTE0_EVENTS_ENDTX (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_ENDTX_OFFSET) +#define NRF53_UARTE0_EVENTS_ERROR (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_ERROR_OFFSET) +#define NRF53_UARTE0_EVENTS_RXTO (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_RXTO_OFFSET) +#define NRF53_UARTE0_EVENTS_RXSTARTED (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_RXSTARTED_OFFSET) +#define NRF53_UARTE0_EVENTS_TXSTARTED (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_TXSTARTED_OFFSET) +#define NRF53_UARTE0_EVENTS_TXSTOPPED (NRF53_UARTE0_BASE + NRF53_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF53_UARTE0_SHORTS (NRF53_UARTE0_BASE + NRF53_UARTE_SHORTS_OFFSET) +#define NRF53_UARTE0_INTEN (NRF53_UARTE0_BASE + NRF53_UARTE_INTEN_OFFSET) +#define NRF53_UARTE0_INTENSET (NRF53_UARTE0_BASE + NRF53_UARTE_INTENSET_OFFSET) +#define NRF53_UARTE0_INTENCLR (NRF53_UARTE0_BASE + NRF53_UARTE_INTENCLR_OFFSET) +#define NRF53_UARTE0_ERRORSRC (NRF53_UARTE0_BASE + NRF53_UARTE_ERRORSRC_OFFSET) +#define NRF53_UARTE0_ENABLE (NRF53_UARTE0_BASE + NRF53_UARTE_ENABLE_OFFSET) +#define NRF53_UARTE0_PSEL_RTS (NRF53_UARTE0_BASE + NRF53_UARTE_PSEL_RTS_OFFSET) +#define NRF53_UARTE0_PSEL_TXD (NRF53_UARTE0_BASE + NRF53_UARTE_PSEL_TXD_OFFSET) +#define NRF53_UARTE0_PSEL_CTS (NRF53_UARTE0_BASE + NRF53_UARTE_PSEL_CTS_OFFSET) +#define NRF53_UARTE0_PSEL_RXD (NRF53_UARTE0_BASE + NRF53_UARTE_PSEL_RXD_OFFSET) +#define NRF53_UARTE0_BAUDRATE (NRF53_UARTE0_BASE + NRF53_UARTE_BAUDRATE_OFFSET) +#define NRF53_UARTE0_RXD_PTR (NRF53_UARTE0_BASE + NRF53_UARTE_RXD_PTR_OFFSET) +#define NRF53_UARTE0_RXD_MAXCNT (NRF53_UARTE0_BASE + NRF53_UARTE_RXD_MAXCNT_OFFSET) +#define NRF53_UARTE0_RXD_AMOUNT (NRF53_UARTE0_BASE + NRF53_UARTE_RXD_AMOUNT_OFFSET) +#define NRF53_UARTE0_TXD_PTR (NRF53_UARTE0_BASE + NRF53_UARTE_TXD_PTR_OFFSET) +#define NRF53_UARTE0_TXD_MAXCNT (NRF53_UARTE0_BASE + NRF53_UARTE_TXD_MAXCNT_OFFSET) +#define NRF53_UARTE0_TXD_AMOUNT (NRF53_UARTE0_BASE + NRF53_UARTE_TXD_AMOUNT_OFFSET) +#define NRF53_UARTE0_CONFIG (NRF53_UARTE0_BASE + NRF53_UARTE_CONFIG_OFFSET) + +#define NRF53_UART0_TASKS_STARTRX (NRF53_UART0_BASE + NRF53_UART_TASKS_STARTRX_OFFSET) +#define NRF53_UART0_TASKS_STOPRX (NRF53_UART0_BASE + NRF53_UART_TASKS_STOPRX_OFFSET) +#define NRF53_UART0_TASKS_STARTTX (NRF53_UART0_BASE + NRF53_UART_TASKS_STARTTX_OFFSET) +#define NRF53_UART0_TASKS_STOPTX (NRF53_UART0_BASE + NRF53_UART_TASKS_STOPTX_OFFSET) +#define NRF53_UART0_TASKS_SUSPEND (NRF53_UART0_BASE + NRF53_UART_TASKS_SUSPEND_OFFSET) +#define NRF53_UART0_EVENTS_CTS (NRF53_UART0_BASE + NRF53_UART_EVENTS_CTS_OFFSET) +#define NRF53_UART0_EVENTS_NCTS (NRF53_UART0_BASE + NRF53_UART_EVENTS_NCTS_OFFSET) +#define NRF53_UART0_EVENTS_RXDRDY (NRF53_UART0_BASE + NRF53_UART_EVENTS_RXDRDY_OFFSET) +#define NRF53_UART0_EVENTS_TXDRDY (NRF53_UART0_BASE + NRF53_UART_EVENTS_TXDRDY_OFFSET) +#define NRF53_UART0_EVENTS_ERROR (NRF53_UART0_BASE + NRF53_UART_EVENTS_ERROR_OFFSET) +#define NRF53_UART0_EVENTS_RXTO (NRF53_UART0_BASE + NRF53_UART_EVENTS_RXTO_OFFSET) +#define NRF53_UART0_SHORTS (NRF53_UART0_BASE + NRF53_UART_SHORTS_OFFSET) +#define NRF53_UART0_INTENSET (NRF53_UART0_BASE + NRF53_UART_INTENSET_OFFSET) +#define NRF53_UART0_INTENCLR (NRF53_UART0_BASE + NRF53_UART_INTENCLR_OFFSET) +#define NRF53_UART0_ERRORSRC (NRF53_UART0_BASE + NRF53_UART_ERRORSRC_OFFSET) +#define NRF53_UART0_ENABLE (NRF53_UART0_BASE + NRF53_UART_ENABLE_OFFSET) +#define NRF53_UART0_PSELRTS (NRF53_UART0_BASE + NRF53_UART_PSELRTS_OFFSET) +#define NRF53_UART0_PSELTXD (NRF53_UART0_BASE + NRF53_UART_PSELTXD_OFFSET) +#define NRF53_UART0_PSELCTS (NRF53_UART0_BASE + NRF53_UART_PSELCTS_OFFSET) +#define NRF53_UART0_PSELRXD (NRF53_UART0_BASE + NRF53_UART_PSELRXD_OFFSET) +#define NRF53_UART0_RXD (NRF53_UART0_BASE + NRF53_UART_RXD_OFFSET) +#define NRF53_UART0_TXD (NRF53_UART0_BASE + NRF53_UART_TXD_OFFSET) +#define NRF53_UART0_BAUDRATE (NRF53_UART0_BASE + NRF53_UART_BAUDRATE_OFFSET) +#define NRF53_UART0_CONFIG (NRF53_UART0_BASE + NRF53_UART_CONFIG_OFFSET) + +#ifdef CONFIG_NRF53_UART1 +# define NRF53_UARTE1_TASKS_STARTRX (NRF53_UARTE1_BASE + NRF53_UARTE_TASKS_STARTRX_OFFSET) +# define NRF53_UARTE1_TASKS_STOPRX (NRF53_UARTE1_BASE + NRF53_UARTE_TASKS_STOPRX_OFFSET) +# define NRF53_UARTE1_TASKS_STARTTX (NRF53_UARTE1_BASE + NRF53_UARTE_TASKS_STARTTX_OFFSET) +# define NRF53_UARTE1_TASKS_STOPTX (NRF53_UARTE1_BASE + NRF53_UARTE_TASKS_STOPTX_OFFSET) +# define NRF53_UARTE1_TASKS_FLUSHRX (NRF53_UARTE1_BASE + NRF53_UARTE_TASKS_FLUSHRX_OFFSET) +# define NRF53_UARTE1_EVENTS_CTS (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_CTS_OFFSET) +# define NRF53_UARTE1_EVENTS_NCTS (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_NCTS_OFFSET) +# define NRF53_UARTE1_EVENTS_RXDRDY (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_RXDRDY_OFFSET) +# define NRF53_UARTE1_EVENTS_ENDRX (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_ENDRX_OFFSET) +# define NRF53_UARTE1_EVENTS_TXDRDY (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_TXDRDY_OFFSET) +# define NRF53_UARTE1_EVENTS_ENDTX (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_ENDTX_OFFSET) +# define NRF53_UARTE1_EVENTS_ERROR (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_ERROR_OFFSET) +# define NRF53_UARTE1_EVENTS_RXTO (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_RXTO_OFFSET) +# define NRF53_UARTE1_EVENTS_RXSTARTED (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_RXSTARTED_OFFSET) +# define NRF53_UARTE1_EVENTS_TXSTARTED (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_TXSTARTED_OFFSET) +# define NRF53_UARTE1_EVENTS_TXSTOPPED (NRF53_UARTE1_BASE + NRF53_UARTE_EVENTS_TXSTOPPED_OFFSET) +# define NRF53_UARTE1_SHORTS (NRF53_UARTE1_BASE + NRF53_UARTE_SHORTS_OFFSET) +# define NRF53_UARTE1_INTEN (NRF53_UARTE1_BASE + NRF53_UARTE_INTEN_OFFSET) +# define NRF53_UARTE1_INTENSET (NRF53_UARTE1_BASE + NRF53_UARTE_INTENSET_OFFSET) +# define NRF53_UARTE1_INTENCLR (NRF53_UARTE1_BASE + NRF53_UARTE_INTENCLR_OFFSET) +# define NRF53_UARTE1_ERRORSRC (NRF53_UARTE1_BASE + NRF53_UARTE_ERRORSRC_OFFSET) +# define NRF53_UARTE1_ENABLE (NRF53_UARTE1_BASE + NRF53_UARTE_ENABLE_OFFSET) +# define NRF53_UARTE1_PSEL_RTS (NRF53_UARTE1_BASE + NRF53_UARTE_PSEL_RTS_OFFSET) +# define NRF53_UARTE1_PSEL_TXD (NRF53_UARTE1_BASE + NRF53_UARTE_PSEL_TXD_OFFSET) +# define NRF53_UARTE1_PSEL_CTS (NRF53_UARTE1_BASE + NRF53_UARTE_PSEL_CTS_OFFSET) +# define NRF53_UARTE1_PSEL_RXD (NRF53_UARTE1_BASE + NRF53_UARTE_PSEL_RXD_OFFSET) +# define NRF53_UARTE1_BAUDRATE (NRF53_UARTE1_BASE + NRF53_UARTE_BAUDRATE_OFFSET) +# define NRF53_UARTE1_RXD_PTR (NRF53_UARTE1_BASE + NRF53_UARTE_RXD_PTR_OFFSET) +# define NRF53_UARTE1_RXD_MAXCNT (NRF53_UARTE1_BASE + NRF53_UARTE_RXD_MAXCNT_OFFSET) +# define NRF53_UARTE1_RXD_AMOUNT (NRF53_UARTE1_BASE + NRF53_UARTE_RXD_AMOUNT_OFFSET) +# define NRF53_UARTE1_TXD_PTR (NRF53_UARTE1_BASE + NRF53_UARTE_TXD_PTR_OFFSET) +# define NRF53_UARTE1_TXD_MAXCNT (NRF53_UARTE1_BASE + NRF53_UARTE_TXD_MAXCNT_OFFSET) +# define NRF53_UARTE1_TXD_AMOUNT (NRF53_UARTE1_BASE + NRF53_UARTE_TXD_AMOUNT_OFFSET) +# define NRF53_UARTE1_CONFIG (NRF53_UARTE1_BASE + NRF53_UARTE_CONFIG_OFFSET) + +# define NRF53_UART1_TASKS_STARTRX (NRF53_UART1_BASE + NRF53_UART_TASKS_STARTRX_OFFSET) +# define NRF53_UART1_TASKS_STOPRX (NRF53_UART1_BASE + NRF53_UART_TASKS_STOPRX_OFFSET) +# define NRF53_UART1_TASKS_STARTTX (NRF53_UART1_BASE + NRF53_UART_TASKS_STARTTX_OFFSET) +# define NRF53_UART1_TASKS_STOPTX (NRF53_UART1_BASE + NRF53_UART_TASKS_STOPTX_OFFSET) +# define NRF53_UART1_TASKS_SUSPEND (NRF53_UART1_BASE + NRF53_UART_TASKS_SUSPEND_OFFSET) +# define NRF53_UART1_EVENTS_CTS (NRF53_UART1_BASE + NRF53_UART_EVENTS_CTS_OFFSET) +# define NRF53_UART1_EVENTS_NCTS (NRF53_UART1_BASE + NRF53_UART_EVENTS_NCTS_OFFSET) +# define NRF53_UART1_EVENTS_RXDRDY (NRF53_UART1_BASE + NRF53_UART_EVENTS_RXDRDY_OFFSET) +# define NRF53_UART1_EVENTS_TXDRDY (NRF53_UART1_BASE + NRF53_UART_EVENTS_TXDRDY_OFFSET) +# define NRF53_UART1_EVENTS_ERROR (NRF53_UART1_BASE + NRF53_UART_EVENTS_ERROR_OFFSET) +# define NRF53_UART1_EVENTS_RXTO (NRF53_UART1_BASE + NRF53_UART_EVENTS_RXTO_OFFSET) +# define NRF53_UART1_SHORTS (NRF53_UART1_BASE + NRF53_UART_SHORTS_OFFSET) +# define NRF53_UART1_INTENSET (NRF53_UART1_BASE + NRF53_UART_INTENSET_OFFSET) +# define NRF53_UART1_INTENCLR (NRF53_UART1_BASE + NRF53_UART_INTENCLR_OFFSET) +# define NRF53_UART1_ERRORSRC (NRF53_UART1_BASE + NRF53_UART_ERRORSRC_OFFSET) +# define NRF53_UART1_ENABLE (NRF53_UART1_BASE + NRF53_UART_ENABLE_OFFSET) +# define NRF53_UART1_PSELRTS (NRF53_UART1_BASE + NRF53_UART_PSELRTS_OFFSET) +# define NRF53_UART1_PSELTXD (NRF53_UART1_BASE + NRF53_UART_PSELTXD_OFFSET) +# define NRF53_UART1_PSELCTS (NRF53_UART1_BASE + NRF53_UART_PSELCTS_OFFSET) +# define NRF53_UART1_PSELRXD (NRF53_UART1_BASE + NRF53_UART_PSELRXD_OFFSET) +# define NRF53_UART1_RXD (NRF53_UART1_BASE + NRF53_UART_RXD_OFFSET) +# define NRF53_UART1_TXD (NRF53_UART1_BASE + NRF53_UART_TXD_OFFSET) +# define NRF53_UART1_BAUDRATE (NRF53_UART1_BASE + NRF53_UART_BAUDRATE_OFFSET) +# define NRF53_UART1_CONFIG (NRF53_UART1_BASE + NRF53_UART_CONFIG_OFFSET) +#endif + +/* UART Register Bitfield Definitions **************************************/ + +/* PSELRTS Register */ + +#define UART_PSELRTS_PIN_SHIFT (0) /* Bits 0-4: Pin number*/ +#define UART_PSELRTS_PIN_MASK (0x1f << UART_PSELRTS_PIN_SHIFT) +#define UART_PSELRTS_PORT_SHIFT (5) /* Bit 5: Port number */ +#define UART_PSELRTS_PORT_MASK (0x1 << UART_PSELRTS_PORT_SHIFT) +#define UART_PSELRTS_CONNECT (1 << 31) /* Bit 31: Connection */ +#define UART_PSELRTS_RESET (0xffffffff) + +/* PSELTXD Register */ + +#define UART_PSELTXD_PIN_SHIFT (0) /* Bits 0-4: Pin number*/ +#define UART_PSELTXD_PIN_MASK (0x1f << UART_PSELTXD_PIN_SHIFT) +#define UART_PSELTXD_PORT_SHIFT (5) /* Bit 5: Port number */ +#define UART_PSELTXD_PORT_MASK (0x1 << UART_PSELTXD_PORT_SHIFT) +#define UART_PSELTXD_CONNECT (1 << 31) /* Bit 31: Connection */ +#define UART_PSELTXD_RESET (0xffffffff) + +/* PSELCTS Register */ + +#define UART_PSELCTS_PIN_SHIFT (0) /* Bits 0-4: Pin number*/ +#define UART_PSELCTS_PIN_MASK (0x1f << UART_PSELCTS_PIN_SHIFT) +#define UART_PSELCTS_PORT_SHIFT (5) /* Bit 5: Port number */ +#define UART_PSELCTS_PORT_MASK (0x1 << UART_PSELCTS_PORT_SHIFT) +#define UART_PSELCTS_CONNECT (1 << 31) /* Bit 31: Connection */ +#define UART_PSELCTS_RESET (0xffffffff) + +/* PSELRXD Register */ + +#define UART_PSELRXD_PIN_SHIFT (0) /* Bits 0-4: Pin number*/ +#define UART_PSELRXD_PIN_MASK (0x1f << UART_PSELRXD_PIN_SHIFT) +#define UART_PSELRXD_PORT_SHIFT (5) /* Bit 5: Port number */ +#define UART_PSELRXD_PORT_MASK (0x1 << UART_PSELRXD_PORT_SHIFT) +#define UART_PSELRXD_CONNECT (1 << 31) /* Bit 31: Connection */ +#define UART_PSELRXD_RESET (0xffffffff) + +/* ENABLE Register */ + +#define NRF53_UART_ENABLE_DISABLE (0) +#define NRF53_UART_ENABLE_ENABLE (4) + +/* INTEN/INTENSET/INTENCLR Register */ + +#define UART_INT_CTS (1 << 0) +#define UART_INT_NCTS (1 << 1) +#define UART_INT_RXDRDY (1 << 2) +#define UART_INT_ENDRX (1 << 4) +#define UART_INT_TXDRDY (1 << 7) +#define UART_INT_ENDTX (1 << 8) +#define UART_INT_ERROR (1 << 9) +#define UART_INT_RXTO (1 << 17) +#define UART_INT_RXSTARTED (1 << 19) +#define UART_INT_TXSTARTED (1 << 20) +#define UART_INT_TXSTOPPED (1 << 22) + +/* BAUDRATE Register */ + +#define UART_BAUDRATE_1200 (0x0004f000) +#define UART_BAUDRATE_2400 (0x0009d000) +#define UART_BAUDRATE_4800 (0x0013b000) +#define UART_BAUDRATE_9600 (0x00275000) +#define UART_BAUDRATE_14400 (0x003af000) +#define UART_BAUDRATE_19200 (0x004ea000) +#define UART_BAUDRATE_28800 (0x0075c000) +#define UART_BAUDRATE_31250 (0x00800000) +#define UART_BAUDRATE_38400 (0x009d0000) +#define UART_BAUDRATE_56000 (0x00e50000) +#define UART_BAUDRATE_57600 (0x00eb0000) +#define UART_BAUDRATE_76000 (0x013a9000) +#define UART_BAUDRATE_115200 (0x01d60000) +#define UART_BAUDRATE_230400 (0x03b00000) +#define UART_BAUDRATE_250000 (0x04000000) +#define UART_BAUDRATE_460800 (0x07400000) +#define UART_BAUDRATE_921600 (0x0f000000) +#define UART_BAUDRATE_1000000 (0x10000000) + +/* CONFIG Register */ + +#define UART_CONFIG_HWFC (1 << 0) /* Bit 0: Hardware flow control */ +#define UART_CONFIG_PARITY_SHIFT (1) /* Bits 1-3: Parity */ +#define UART_CONFIG_PARITY (7 << UART_CONFIG_PARITY_SHIFT) +#define UART_CONFIG_STOP (1 << 4) /* Bit 4: Stop bits */ +#define UART_CONFIG_PARITYTYPE (1 << 8) /* Bit 8: Parity type */ + +#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UARTE_H */ diff --git a/arch/arm/src/nrf53/hardware/nrf53_utils.h b/arch/arm/src/nrf53/hardware/nrf53_utils.h new file mode 100644 index 00000000000..9a304bad3a9 --- /dev/null +++ b/arch/arm/src/nrf53/hardware/nrf53_utils.h @@ -0,0 +1,110 @@ +/**************************************************************************** + * arch/arm/src/nrf53/hardware/nrf53_utils.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UTILS_H +#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UTILS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes / Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. + * + ****************************************************************************/ + +void nrf53_clrpend(int irq); + +/**************************************************************************** + * Name: nrf53832_errdata_init + * + * Description: + * ErrData correction for 52832 + * required for most interrupts. + * + ****************************************************************************/ + +void nrf53832_errdata_init(void); + +/**************************************************************************** + * Name: nrf53_task_trigger + * + * Description: + * trigger the special task which is passed from task parameter + * + ****************************************************************************/ + +static inline void nrf53_task_trigger(uint32_t task) +{ + putreg32(1, task); +} + +/**************************************************************************** + * Name: nrf53_event_clear + * + * Description: + * clear the Event + * + ****************************************************************************/ + +static inline void nrf53_event_clear(uint32_t event) +{ + putreg32(0, event); +} + +/**************************************************************************** + * Name: nrf53_interrupt_enable + * + * Description: + * Enable the bitfield interrupt + * + ****************************************************************************/ + +static inline void nrf53_interrupt_enable(uint32_t reg_intenset, + uint32_t bitfield) +{ + putreg32(bitfield, reg_intenset); +} + +/**************************************************************************** + * Name: nrf53_interrupt_disable + * + * Description: + * Disable the bitfield interrupt + * + ****************************************************************************/ + +static inline void nrf53_interrupt_disable(uint32_t reg_intenclr, + uint32_t bitfield) +{ + putreg32(bitfield, reg_intenclr); +} + +#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_UTILS_H */ diff --git a/arch/arm/src/nrf53/nrf53_allocateheap.c b/arch/arm/src/nrf53/nrf53_allocateheap.c new file mode 100644 index 00000000000..9ba1616e03e --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_allocateheap.c @@ -0,0 +1,191 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/nrf53_memorymap.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* .bss and .data is always positioned in internal SRAM. The remaining SRAM + * after the static .bss, .data, and IDLE stack allocations are always added + * to the heap. + */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* _sbss is the start of the BSS region (see the linker script) _ebss is the + * end of the BSS region (see the linker script). The idle task stack starts + * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE + * thread is the thread that the system boots on and, eventually, becomes the + * idle, do nothing task that runs only when there is nothing else to run. + * The heap continues from there until the configured end of memory. + * g_idle_topstack is the beginning of this heap region (not necessarily + * aligned). + */ + +const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + + CONFIG_IDLETHREAD_STACKSIZE; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap/up_allocate_kheap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * - For the normal "flat" build, this function returns the size of the + * single heap. + * - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function + * provides the size of the unprotected, user-space heap. + * - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides + * the size of the protected, kernel-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated by an analogous up_allocate_kheap(). A custom version of this + * file is needed if memory protection of the kernel heap is required. + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +void up_allocate_kheap(void **heap_start, size_t *heap_size) +#else +void up_allocate_heap(void **heap_start, size_t *heap_size) +#endif +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)ubase; + *heap_size = usize; +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * the kernel-space heap. A custom version of this function is needed if + * memory protection of the kernel heap is required. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif + +/**************************************************************************** + * Name: arm_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void arm_addregion(void) +{ +} +#endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/arch/arm/src/nrf53/nrf53_clockconfig.c b/arch/arm/src/nrf53/nrf53_clockconfig.c new file mode 100644 index 00000000000..46b4ba1d97c --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_clockconfig.c @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "nrf53_clockconfig.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_clockconfig + * + * Description: + * Called to initialize the NRF53xxx. This does whatever setup is needed + * to put the MCU in a usable state. This includes the initialization of + * clocking using the settings in board.h. This function also performs + * other low-level chip as necessary. + * + ****************************************************************************/ + +void nrf53_clockconfig(void) +{ + /* TODO */ +} diff --git a/arch/arm/src/nrf53/nrf53_clockconfig.h b/arch/arm/src/nrf53/nrf53_clockconfig.h new file mode 100644 index 00000000000..050fce088bb --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_clockconfig.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_NRF53_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_NRF53_NRF53_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Frequencies of internal clocks */ + +#define NRF53_SYSTEM_CLOCK 64000000 /* Default System clock value */ +#define NRF53_RTC_CLOCK 32768 /* RTC oscillator 32 kHz output + * (32k_clk) + */ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_clockconfig + * + * Description: + * Called to initialize the NRF53xxx. This does whatever setup is needed + * to put the MCU in a usable state. This includes the initialization of + * clocking using the settings in board.h. This function also performs + * other low-level chip as necessary. + * + ****************************************************************************/ + +void nrf53_clockconfig(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_NRF53_NRF53_CLOCKCONFIG_H */ diff --git a/arch/arm/src/nrf53/nrf53_config.h b/arch/arm/src/nrf53/nrf53_config.h new file mode 100644 index 00000000000..1c6d4c46459 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_config.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_config.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_NRF53_CONFIG_H +#define __ARCH_ARM_SRC_NRF53_NRF53_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Make sure that no unsupported UART, I2C master, or SPI master peripherals + * are enabled. + */ + +/* Map logical UART names (Just for simplicity of naming) */ + +#undef HAVE_UART0 +#undef HAVE_UART1 + +#ifdef CONFIG_NRF53_UART0 +# define HAVE_UART0 1 +#endif + +#ifdef CONFIG_NRF53_UART1 +# define HAVE_UART1 1 +#endif + +/* Check if we have a UART device */ + +#undef CONFIG_NRF53_HAVE_UART +#undef HAVE_UART_DEVICE + +#if defined(HAVE_UART0) +# define HAVE_UART_DEVICE 1 +#endif + +#if defined(HAVE_UART1) +# define HAVE_UART_DEVICE 1 +#endif + +/* Is there a serial console? There should be at most one defined. */ + +#undef HAVE_UART_CONSOLE + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(HAVE_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#endif + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(HAVE_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#endif + +#endif /* __ARCH_ARM_SRC_NRF53_NRF53_CONFIG_H */ diff --git a/arch/arm/src/nrf53/nrf53_gpio.c b/arch/arm/src/nrf53/nrf53_gpio.c new file mode 100644 index 00000000000..44a17068d23 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_gpio.c @@ -0,0 +1,490 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/nrf53_gpio.h" +#include "nrf53_gpio.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_gpio_regget + * + * Description: + * Get a register address for given GPIO port and register offset + * + ****************************************************************************/ + +static inline uint32_t nrf53_gpio_regget(int port, uint32_t offset) +{ + uint32_t base = 0; + + /* Get base address for port */ + + if (port == 0) + { + base = NRF53_GPIO_P0_BASE; + } + else if (port == 1) + { + base = NRF53_GPIO_P1_BASE; + } + + return (base + offset); +} + +/**************************************************************************** + * Name: nrf53_gpio_input + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void nrf53_gpio_input(unsigned int port, unsigned int pin) +{ + uint32_t offset; + + offset = nrf53_gpio_regget(port, NRF53_GPIO_DIRCLR_OFFSET); + + /* Configure the pin as an input */ + + putreg32(1U << pin, offset); + + /* Enable input buffer */ + + offset = nrf53_gpio_regget(port, NRF53_GPIO_PIN_CNF_OFFSET(pin)); + modifyreg32(offset, GPIO_CNF_INPUT, 0); +} + +/**************************************************************************** + * Name: nrf53_gpio_output + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void nrf53_gpio_output(nrf53_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t offset; + + /* Disable input buffer */ + + offset = nrf53_gpio_regget(port, NRF53_GPIO_PIN_CNF_OFFSET(pin)); + modifyreg32(offset, 0, GPIO_CNF_INPUT); + + offset = nrf53_gpio_regget(port, NRF53_GPIO_DIRSET_OFFSET); + + nrf53_gpio_write(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); + + /* Configure the pin as an output */ + + putreg32(1U << pin, offset); +} + +/**************************************************************************** + * Name: nrf53_gpio_mode + * + * Description: + * Configure a GPIO mode based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void nrf53_gpio_mode(nrf53_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t mode; + uint32_t regval; + uint32_t offset; + + offset = nrf53_gpio_regget(port, NRF53_GPIO_PIN_CNF_OFFSET(pin)); + + mode = cfgset & GPIO_MODE_MASK; + + regval = getreg32(offset); + regval &= ~GPIO_CNF_PULL_MASK; + + if (mode == GPIO_PULLUP) + { + regval |= GPIO_CNF_PULL_UP; + } + else if (mode == GPIO_PULLDOWN) + { + regval |= GPIO_CNF_PULL_DOWN; + } + + putreg32(regval, offset); +} + +/**************************************************************************** + * Name: nrf53_gpio_sense + * + * Description: + * Set SENSE configuration for an input pin + * + ****************************************************************************/ + +static inline void nrf53_gpio_sense(nrf53_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t mode; + uint32_t regval; + uint32_t offset; + + mode = cfgset & GPIO_SENSE_MASK; + + offset = nrf53_gpio_regget(port, NRF53_GPIO_PIN_CNF_OFFSET(pin)); + regval = getreg32(offset); + + regval &= ~GPIO_CNF_SENSE_MASK; + + if (mode == GPIO_SENSE_HIGH) + { + regval |= GPIO_CNF_SENSE_HIGH; + } + else if (mode == GPIO_SENSE_LOW) + { + regval |= GPIO_CNF_SENSE_LOW; + } + + putreg32(regval, offset); +} + +/**************************************************************************** + * Name: nrf53_gpio_drive + * + * Description: + * Set DRIVE configuration for a pin + * + ****************************************************************************/ + +static inline void nrf53_gpio_drive(nrf53_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t drive; + uint32_t regval; + uint32_t offset; + + drive = cfgset & GPIO_DRIVE_MASK; + + offset = nrf53_gpio_regget(port, NRF53_GPIO_PIN_CNF_OFFSET(pin)); + regval = getreg32(offset); + + regval &= ~GPIO_CNF_DRIVE_MASK; + + switch (drive) + { + case GPIO_DRIVE_S0S1: + regval |= GPIO_CNF_DRIVE_S0S1; + break; + case GPIO_DRIVE_S0H1: + regval |= GPIO_CNF_DRIVE_S0H1; + break; + case GPIO_DRIVE_S0D1: + regval |= GPIO_CNF_DRIVE_S0D1; + break; + case GPIO_DRIVE_H0D1: + regval |= GPIO_CNF_DRIVE_H0D1; + break; + case GPIO_DRIVE_H0H1: + regval |= GPIO_CNF_DRIVE_H0H1; + break; + case GPIO_DRIVE_H0S1: + regval |= GPIO_CNF_DRIVE_H0S1; + break; + case GPIO_DRIVE_D0H1: + regval |= GPIO_CNF_DRIVE_D0H1; + break; + case GPIO_DRIVE_D0S1: + regval |= GPIO_CNF_DRIVE_D0S1; + break; + case GPIO_DRIVE_EOS1: + regval |= GPIO_CNF_DRIVE_EOS1; + break; + case GPIO_DRIVE_SOE1: + regval |= GPIO_CNF_DRIVE_SOE1; + break; + case GPIO_DRIVE_EOE1: + regval |= GPIO_CNF_DRIVE_EOE1; + break; + case GPIO_DRIVE_DOE1: + regval |= GPIO_CNF_DRIVE_DOE1; + break; + case GPIO_DRIVE_EOD1: + regval |= GPIO_CNF_DRIVE_EOD1; + break; + } + + putreg32(regval, offset); +} + +/**************************************************************************** + * Name: nrf53_gpio_mcusel + * + * Description: + * Set MCUSEL configuration for a pin + * + ****************************************************************************/ + +static inline void nrf53_gpio_mcusel(nrf53_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uint32_t mcusel; + uint32_t regval; + uint32_t offset; + + mcusel = cfgset & GPIO_MCUSEL_MASK; + + offset = nrf53_gpio_regget(port, NRF53_GPIO_PIN_CNF_OFFSET(pin)); + regval = getreg32(offset); + + regval &= ~GPIO_CNF_MCUSEL_MASK; + + switch (mcusel) + { + case GPIO_MCUSEL_APP: + regval |= GPIO_CNF_MCUSEL_CPUAPP; + break; + case GPIO_MCUSEL_NET: + regval |= GPIO_CNF_MCUSEL_CPUNET; + break; + case GPIO_MCUSEL_PERIP: + regval |= GPIO_CNF_MCUSEL_PERIP; + break; + case GPIO_MCUSEL_TND: + regval |= GPIO_CNF_MCUSEL_TND; + break; + } + + putreg32(regval, offset); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int nrf53_gpio_config(nrf53_pinset_t cfgset) +{ + unsigned int port = 0; + unsigned int pin; + irqstate_t flags; + int ret = OK; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + + if (port < NRF53_GPIO_NPORTS) + { + /* Get the pin number and select the port configuration register for + * that pin. + */ + + pin = GPIO_PIN_DECODE(cfgset); + + flags = spin_lock_irqsave(NULL); + + /* First, configure the port as a generic input so that we have a + * known starting point and consistent behavior during the re- + * configuration. + */ + + nrf53_gpio_input(port, pin); + + /* Set the mode bits */ + + nrf53_gpio_mode(cfgset, port, pin); + + /* Set the drive bits (needed also for input pins + * for some peripherals). + */ + + nrf53_gpio_drive(cfgset, port, pin); + + /* Select which MCU/Subsystem controls this pin. + * NOTE: accessible only from secure code. + */ + + nrf53_gpio_mcusel(cfgset, port, pin); + + /* Handle according to pin function */ + + switch (cfgset & GPIO_FUNC_MASK) + { + case GPIO_INPUT: /* GPIO input pin */ + nrf53_gpio_sense(cfgset, port, pin); + break; + + case GPIO_OUTPUT: /* GPIO outpout pin */ + nrf53_gpio_output(cfgset, port, pin); + break; + + default: + ret = -EINVAL; + } + + spin_unlock_irqrestore(NULL, flags); + } + else + { + ret = -EINVAL; + } + + return ret; +} + +/**************************************************************************** + * Name: nrf53_gpio_unconfig + * + * Description: + * Unconfigure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int nrf53_gpio_unconfig(nrf53_pinset_t cfgset) +{ + unsigned int pin; + unsigned int port = 0; + uint32_t offset; + + /* Get port and pin number */ + + pin = GPIO_PIN_DECODE(cfgset); + port = GPIO_PORT_DECODE(cfgset); + + /* Get address offset */ + + offset = nrf53_gpio_regget(port, NRF53_GPIO_PIN_CNF_OFFSET(pin)); + + /* Configure as input and disconnect input buffer */ + + putreg32(GPIO_CNF_INPUT, offset); + + return OK; +} + +/**************************************************************************** + * Name: nrf53_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void nrf53_gpio_write(nrf53_pinset_t pinset, bool value) +{ + unsigned int pin; + unsigned int port = 0; + uint32_t offset; + + /* Get port and pin number */ + + pin = GPIO_PIN_DECODE(pinset); + port = GPIO_PORT_DECODE(pinset); + + /* Get register address */ + + if (value) + { + offset = nrf53_gpio_regget(port, NRF53_GPIO_OUTSET_OFFSET); + } + else + { + offset = nrf53_gpio_regget(port, NRF53_GPIO_OUTCLR_OFFSET); + } + + /* Put register value */ + + putreg32(1 << pin, offset); +} + +/**************************************************************************** + * Name: nrf53_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool nrf53_gpio_read(nrf53_pinset_t pinset) +{ + unsigned int port; + unsigned int pin; + uint32_t regval; + uint32_t offset; + + /* Get port and pin number */ + + pin = GPIO_PIN_DECODE(pinset); + port = GPIO_PORT_DECODE(pinset); + + /* Get register address */ + + offset = nrf53_gpio_regget(port, NRF53_GPIO_IN_OFFSET); + + /* Get register value */ + + regval = getreg32(offset); + + return (regval >> pin) & 1UL; +} + +/**************************************************************************** + * Name: nrf53_gpio_detectmode + * + * Description: + * Set DETECTMODE to either default or latched + * + ****************************************************************************/ + +void nrf53_gpio_detectmode(int port, enum nrf53_gpio_detectmode_e mode) +{ + uint32_t offset = nrf53_gpio_regget(port, NRF53_GPIO_DETECTMODE_OFFSET); + + putreg32(mode == NRF53_GPIO_DETECTMODE_DETECT ? + GPIO_DETECTMODE_DEFAULT : + GPIO_DETECTMODE_LDETECT, offset); +} diff --git a/arch/arm/src/nrf53/nrf53_gpio.h b/arch/arm/src/nrf53/nrf53_gpio.h new file mode 100644 index 00000000000..3d2fb858562 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_gpio.h @@ -0,0 +1,277 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_NRF53_GPIO_H +#define __ARCH_ARM_SRC_NRF53_NRF53_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#include +#include "hardware/nrf53_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Bit-encoded input to nrf53_gpio_config() *********************************/ + +/* 32-Bit Encoding: .... .... .... .GGF FSSD DDDM MVPN NNNN + * + * MCU selection: GG + * Pin Function: FF + * Pin Sense: SS + * Pin Drive: DDDD + * Pin Mode bits: MM + * Initial value: V (output pins) + * Port number: P (0-1) + * Pin number: NNNNN (0-31) + */ + +/* MCU selection bits: + * + * .... .... .... .GG. .... .... .... .... + */ + +#define GPIO_MCUSEL_SHIFT (17) /* Bits 17-18: MCUSEL mode */ +#define GPIO_MCUSEL_MASK (0x03 << GPIO_MCUSEL_SHIFT) +# define GPIO_MCUSEL_APP (0x00 << GPIO_MCUSEL_SHIFT) /* 00000 CPU APP */ +# define GPIO_MCUSEL_NET (0x01 << GPIO_MCUSEL_SHIFT) /* 00001 CPU NET */ +# define GPIO_MCUSEL_PERIP (0x02 << GPIO_MCUSEL_SHIFT) /* 00002 Periphneral */ +# define GPIO_MCUSEL_TND (0x03 << GPIO_MCUSEL_SHIFT) /* 00003 Trace and Debug System */ + +/* Pin Function bits: + * Only meaningful when the GPIO function is GPIO_PIN + * + * .... .... .... ...F F... .... .... .... + */ + +#define GPIO_FUNC_SHIFT (15) /* Bits 15-16: GPIO mode */ +#define GPIO_FUNC_MASK (0x03 << GPIO_FUNC_SHIFT) +# define GPIO_INPUT (0x00 << GPIO_FUNC_SHIFT) /* 00000 GPIO input pin */ +# define GPIO_OUTPUT (0x01 << GPIO_FUNC_SHIFT) /* 00001 GPIO output pin */ + +/* Pin Sense bits: + * + * .... .... .... .... .SS. .... .... .... + */ + +#define GPIO_SENSE_SHIFT (13) /* Bits 13-14: Pin Sense mode */ +#define GPIO_SENSE_MASK (0x3 << GPIO_SENSE_SHIFT) +# define GPIO_SENSE_NONE (0 << GPIO_SENSE_SHIFT) +# define GPIO_SENSE_HIGH (2 << GPIO_SENSE_SHIFT) +# define GPIO_SENSE_LOW (3 << GPIO_SENSE_SHIFT) + +/* Pin Drive bits: + * + * .... .... .... .... ...D DDD. .... .... + */ + +#define GPIO_DRIVE_SHIFT (9) /* Bits 9-12: Pin pull-up mode */ +#define GPIO_DRIVE_MASK (0xf << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_S0S1 (0 << GPIO_DRIVE_SHIFT) /* Standard '0', standard '1' */ +# define GPIO_DRIVE_H0S1 (1 << GPIO_DRIVE_SHIFT) /* High drive '0', standard '1' */ +# define GPIO_DRIVE_S0H1 (2 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_H0H1 (3 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_D0S1 (4 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_D0H1 (5 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_S0D1 (6 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_H0D1 (7 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_EOS1 (8 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_SOE1 (9 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_EOE1 (10 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_DOE1 (11 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_EOD1 (12 << GPIO_DRIVE_SHIFT) + +/* Pin Mode: MM + * + * .... .... .... .... .... ...M M... .... + */ + +#define GPIO_MODE_SHIFT (7) /* Bits 7-8: Pin pull-up mode */ +#define GPIO_MODE_MASK (0x3 << GPIO_MODE_SHIFT) +# define GPIO_FLOAT (0 << GPIO_MODE_SHIFT) /* Neither pull-up nor -down */ +# define GPIO_PULLDOWN (1 << GPIO_MODE_SHIFT) /* Pull-down resistor enabled */ +# define GPIO_PULLUP (2 << GPIO_MODE_SHIFT) /* Pull-up resistor enabled */ + +/* Initial value: V + * + * .... .... .... .... .... .... .V.. .... + */ + +#define GPIO_VALUE (1 << 6) /* Bit 6: Initial GPIO output value */ +# define GPIO_VALUE_ONE GPIO_VALUE +# define GPIO_VALUE_ZERO (0) + +/* Port number: PPP (0-5) + * + * .... .... .... .... .... .... ..P. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5: Port number */ +#define GPIO_PORT_MASK (0x1 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) + +/* Pin number: NNNNN (0-31) + * + * .... .... .... .... .... .... ...N NNNN + */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) +# define GPIO_PIN(n) ((n) << GPIO_PIN_SHIFT) + +/* Helper macros */ + +#define GPIO_PIN_DECODE(p) (((p) & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT) +#define GPIO_PORT_DECODE(p) (((p) & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef uint32_t nrf53_pinset_t; + +enum nrf53_gpio_detectmode_e +{ + NRF53_GPIO_DETECTMODE_DETECT, + NRF53_GPIO_DETECTMODE_LDETECT, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int nrf53_gpio_config(nrf53_pinset_t cfgset); + +/**************************************************************************** + * Name: nrf53_gpio_unconfig + * + * Description: + * Unconfigure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int nrf53_gpio_unconfig(nrf53_pinset_t cfgset); + +/**************************************************************************** + * Name: rnf52_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void nrf53_gpio_write(nrf53_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: nrf53_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool nrf53_gpio_read(nrf53_pinset_t pinset); + +/**************************************************************************** + * Function: nf52_gpio_dump + * + * Description: + * Dump all GPIO registers associated with the base address of the provided + * pinset. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO_INFO +int nrf53_gpio_dump(nrf53_pinset_t pinset, const char *msg); +#else +# define nrf53_gpio_dump(p,m) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_NRF53_NRF53_GPIO_H */ diff --git a/arch/arm/src/nrf53/nrf53_idle.c b/arch/arm/src/nrf53/nrf53_idle.c new file mode 100644 index 00000000000..d5cc37f43b5 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_idle.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when there is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power + * + * The SysTick's clock will only tick when the CPU is + * running (not in WFE/WFI) or when the system is in debug interface mode. + */ + +#ifdef CONFIG_NRF53_SYSTIMER_RTC + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +#endif +} diff --git a/arch/arm/src/nrf53/nrf53_irq.c b/arch/arm/src/nrf53/nrf53_irq.c new file mode 100644 index 00000000000..255ae23a637 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_irq.c @@ -0,0 +1,563 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "chip.h" +#include "nvic.h" +#include "ram_vectors.h" +#include "arm_internal.h" +#include "nrf53_irq.h" +#ifdef CONFIG_NRF53_GPIOTE +# include "nrf53_gpiote.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/* This is the address of the exception vector table (determined by the + * linker script). + */ + +extern uint32_t _vectors[]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void nrf53_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), + getreg32(NVIC_SYSHCON_BUSFAULTENA)); + irqinfo(" USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_USGFAULTENA), + getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + irqinfo(" IRQ ENABLE: %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), + getreg32(NVIC_IRQ32_63_ENABLE)); + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), + getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), + getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), + getreg32(NVIC_IRQ12_15_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), + getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), + getreg32(NVIC_IRQ28_31_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), + getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), + getreg32(NVIC_IRQ44_47_PRIORITY)); + irqinfo(" %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), + getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY)); + + leave_critical_section(flags); +} +#else +# define nrf53_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: nrf53_nmi, nrf53_busfault, nrf53_usagefault, nrf53_pendsv, + * nrf53_dbgmonitor, nrf53_pendsv, nrf53_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int nrf53_nmi(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int nrf53_busfault(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Bus fault received\n"); + PANIC(); + return 0; +} + +static int nrf53_usagefault(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Usage fault received\n"); + PANIC(); + return 0; +} + +static int nrf53_pendsv(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int nrf53_dbgmonitor(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Debug Monitor received\n"); + PANIC(); + return 0; +} + +static int nrf53_reserved(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: nrf53_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV8M_USEBASEPRI +static inline void nrf53_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** + * Name: nrf53_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int nrf53_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + int n; + + DEBUGASSERT(irq >= NRF53_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= NRF53_IRQ_EXTINT) + { + n = irq - NRF53_IRQ_EXTINT; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + *bit = (uint32_t)1 << (n & 0x1f); + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == NRF53_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == NRF53_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == NRF53_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == NRF53_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + * + * Description: + * Complete initialization of the interrupt system and enable normal, + * interrupt processing. + * + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; +#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV8M_USEBASEPRI) + uint32_t regval; +#endif + int num_priority_registers; + int i; + + /* Disable all interrupts */ + + for (i = 0; i < NRF53_IRQ_NEXTINT; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } + + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + arm_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* The NVIC ICTR register (bits 0-4) holds the number of interrupt + * lines that the NVIC supports: + * + * 0 -> 32 interrupt lines, 8 priority registers + * 1 -> 64 " " " ", 16 priority registers + * 2 -> 96 " " " ", 32 priority registers + * ... + */ + + num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; + + /* Now set all of the interrupt lines to the default priority */ + + regaddr = NVIC_IRQ0_3_PRIORITY; + while (num_priority_registers--) + { + putreg32(DEFPRIORITY32, regaddr); + regaddr += 4; + } + + /* currents_regs is non-NULL only while processing an interrupt */ + + CURRENT_REGS = NULL; + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(NRF53_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(NRF53_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO +# if 0 + up_prioritize_irq(NRF53_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); +# endif +#endif + +#ifdef CONFIG_ARMV8M_USEBASEPRI + nrf53_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif + +#ifdef CONFIG_ARM_MPU + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + + irq_attach(NRF53_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(NRF53_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(NRF53_IRQ_NMI, nrf53_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(NRF53_IRQ_MEMFAULT, arm_memfault, NULL); +#endif + irq_attach(NRF53_IRQ_BUSFAULT, nrf53_busfault, NULL); + irq_attach(NRF53_IRQ_USAGEFAULT, nrf53_usagefault, NULL); + irq_attach(NRF53_IRQ_PENDSV, nrf53_pendsv, NULL); + irq_attach(NRF53_IRQ_DBGMONITOR, nrf53_dbgmonitor, NULL); + irq_attach(NRF53_IRQ_RESERVED, nrf53_reserved, NULL); +#endif + + nrf53_dumpnvic("initial", NRF53_IRQ_NIRQS); + +#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV8M_USEBASEPRI) + /* If a debugger is connected, try to prevent it from catching hardfaults. + * If CONFIG_ARMV8M_USEBASEPRI, no hardfaults are expected in normal + * operation. + */ + + regval = getreg32(NVIC_DEMCR); + regval &= ~NVIC_DEMCR_VCHARDERR; + putreg32(regval, NVIC_DEMCR); +#endif + +#ifdef CONFIG_NRF53_GPIOTE + /* Initialize GPIOTE */ + + nrf53_gpiote_init(); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (nrf53_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= NRF53_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } + + nrf53_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (nrf53_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= NRF53_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } + + nrf53_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ + nrf53_clrpend(irq); +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= NRF53_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < NRF53_IRQ_EXTINT) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= NRF53_IRQ_EXTINT; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + nrf53_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/nrf53/nrf53_irq.h b/arch/arm/src/nrf53/nrf53_irq.h new file mode 100644 index 00000000000..eed6a17dfec --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_irq.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_NRF53_IRQ_H +#define __ARCH_ARM_SRC_NRF53_NRF53_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. + * + ****************************************************************************/ + +void nrf53_clrpend(int irq); + +#endif /* __ARCH_ARM_SRC_NRF53_NRF53_IRQ_H */ diff --git a/arch/arm/src/nrf53/nrf53_lowputc.c b/arch/arm/src/nrf53/nrf53_lowputc.c new file mode 100644 index 00000000000..a6d65086c1d --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_lowputc.c @@ -0,0 +1,449 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "arm_internal.h" +#include "hardware/nrf53_memorymap.h" +#include "hardware/nrf53_uarte.h" + +#include "nrf53_config.h" +#include "nrf53_clockconfig.h" +#include "nrf53_gpio.h" +#include "nrf53_lowputc.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef HAVE_UART_CONSOLE + +#ifdef CONFIG_UART0_SERIAL_CONSOLE +# define CONSOLE_BASE NRF53_UART0_BASE +# define CONSOLE_BAUD CONFIG_UART0_BAUD +# define CONSOLE_BITS CONFIG_UART0_BITS +# define CONSOLE_PARITY CONFIG_UART0_PARITY +# define CONSOLE_2STOP CONFIG_UART0_2STOP +# define CONSOLE_TX_PIN BOARD_UART0_TX_PIN +# define CONSOLE_RX_PIN BOARD_UART0_RX_PIN +#elif CONFIG_UART1_SERIAL_CONSOLE +# define CONSOLE_BASE NRF53_UART1_BASE +# define CONSOLE_BAUD CONFIG_UART1_BAUD +# define CONSOLE_BITS CONFIG_UART1_BITS +# define CONSOLE_PARITY CONFIG_UART1_PARITY +# define CONSOLE_2STOP CONFIG_UART1_2STOP +# define CONSOLE_TX_PIN BOARD_UART1_TX_PIN +# define CONSOLE_RX_PIN BOARD_UART1_RX_PIN +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* UART console configuration */ + +static const struct uart_config_s g_console_config = +{ + .baud = CONSOLE_BAUD, + .parity = CONSOLE_PARITY, + .bits = CONSOLE_BITS, + .stopbits2 = CONSOLE_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .iflow = CONSOLE_IFLOW, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .oflow = CONSOLE_OFLOW, +#endif + .txpin = CONSOLE_TX_PIN, + .rxpin = CONSOLE_RX_PIN, +}; +#endif /* HAVE_UART_CONSOLE */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_setbaud + * + * Description: + * Configure the UART BAUD. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +static void nrf53_setbaud(uintptr_t base, const struct uart_config_s *config) +{ + uint32_t br = 0; + + switch (config->baud) + { + case 1200: + { + br = UART_BAUDRATE_1200; + break; + } + + case 2400: + { + br = UART_BAUDRATE_2400; + break; + } + + case 4800: + { + br = UART_BAUDRATE_4800; + break; + } + + case 9600: + { + br = UART_BAUDRATE_9600; + break; + } + + case 14400: + { + br = UART_BAUDRATE_14400; + break; + } + + case 19200: + { + br = UART_BAUDRATE_19200; + break; + } + + case 28800: + { + br = UART_BAUDRATE_28800; + break; + } + +#ifdef UART_BAUDRATE_31250 + case 31250: + { + br = UART_BAUDRATE_31250; + break; + } +#endif + + case 38400: + { + br = UART_BAUDRATE_38400; + break; + } + +#ifdef UART_BAUDRATE_56000 + case 56000: + { + br = UART_BAUDRATE_56000; + break; + } +#endif + + case 57600: + { + br = UART_BAUDRATE_57600; + break; + } + + case 76000: + { + br = UART_BAUDRATE_76000; + break; + } + + case 115200: + { + br = UART_BAUDRATE_115200; + break; + } + + case 230400: + { + br = UART_BAUDRATE_230400; + break; + } + + case 250000: + { + br = UART_BAUDRATE_250000; + break; + } + + case 460800: + { + br = UART_BAUDRATE_460800; + break; + } + + case 921600: + { + br = UART_BAUDRATE_921600; + break; + } + + default: + { + DEBUGPANIC(); + break; + } + } + + putreg32(br, base + NRF53_UART_BAUDRATE_OFFSET); +} + +/**************************************************************************** + * Name: nrf53_setparity + ****************************************************************************/ + +static void nrf53_setparity(uintptr_t base, + const struct uart_config_s *config) +{ + uint32_t regval = 0; + + regval = getreg32(base + NRF53_UART_CONFIG_OFFSET); + + if (config->parity == 2) + { + /* Include even parity */ + + regval |= UART_CONFIG_PARITY; + } + else + { + /* Exclude parity */ + + regval &= ~UART_CONFIG_PARITY; + } + + putreg32(regval, base + NRF53_UART_CONFIG_OFFSET); +} + +/**************************************************************************** + * Name: nrf53_setstops + ****************************************************************************/ + +#ifdef HAVE_UART_STOPBITS +static void nrf53_setstops(uintptr_t base, + const struct uart_config_s *config) +{ + uint32_t regval = 0; + + regval = getreg32(base + NRF53_UART_CONFIG_OFFSET); + + if (config->stopbits2 == true) + { + regval |= UART_CONFIG_STOP; + } + else + { + regval &= ~UART_CONFIG_STOP; + } + + putreg32(regval, base + NRF53_UART_CONFIG_OFFSET); +} +#endif + +/**************************************************************************** + * Name: nrf53_sethwflow + ****************************************************************************/ + +static void nrf53_sethwflow(uintptr_t base, + const struct uart_config_s *config) +{ + /* TODO */ +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. + * This UART initialization is done early so that the serial console is + * available for debugging very early in the boot sequence. + * + ****************************************************************************/ + +void nrf53_lowsetup(void) +{ +#ifdef HAVE_UART_DEVICE +#ifdef HAVE_UART_CONSOLE + /* Configure the console UART (if any) */ + + nrf53_usart_configure(CONSOLE_BASE, &g_console_config); + +#endif /* HAVE_UART_CONSOLE */ +#endif /* HAVE_UART_DEVICE */ +} + +/**************************************************************************** + * Name: nrf53_usart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void nrf53_usart_configure(uintptr_t base, + const struct uart_config_s *config) +{ + uint32_t pin = 0; + uint32_t port = 0; + uint32_t regval = 0; + + putreg32(1, base + NRF53_UART_TASKS_STOPRX_OFFSET); + putreg32(1, base + NRF53_UART_TASKS_STOPTX_OFFSET); + putreg32(NRF53_UART_ENABLE_DISABLE, base + NRF53_UART_ENABLE_OFFSET); + + /* Set UART format */ + + nrf53_usart_setformat(base, config); + + /* Config GPIO pins for uart */ + + nrf53_gpio_config(config->txpin); + nrf53_gpio_config(config->rxpin); + + /* Setect TX pins for UART */ + + pin = GPIO_PIN_DECODE(config->txpin); + port = GPIO_PORT_DECODE(config->txpin); + + regval = (pin << UART_PSELTXD_PIN_SHIFT); + regval |= (port << UART_PSELTXD_PORT_SHIFT); + putreg32(regval, base + NRF53_UART_PSELTXD_OFFSET); + + /* Setect RX pins for UART */ + + pin = GPIO_PIN_DECODE(config->rxpin); + port = GPIO_PORT_DECODE(config->rxpin); + + regval = (pin << UART_PSELRXD_PIN_SHIFT); + regval |= (port << UART_PSELRXD_PORT_SHIFT); + putreg32(regval, base + NRF53_UART_PSELRXD_OFFSET); + + /* Enable UART */ + + putreg32(NRF53_UART_ENABLE_ENABLE, base + NRF53_UART_ENABLE_OFFSET); +} + +/**************************************************************************** + * Name: nrf53_usart_disable + * + * Description: + * Disable a UART. it will be necessary to again call + * nrf53_usart_configure() in order to use this UART channel again. + * + ****************************************************************************/ + +void nrf53_usart_disable(uintptr_t base, const struct uart_config_s *config) +{ + /* Disable interrupts */ + + /* Disable the UART */ + + putreg32(1, base + NRF53_UART_TASKS_STOPRX_OFFSET); + putreg32(1, base + NRF53_UART_TASKS_STOPTX_OFFSET); + putreg32(NRF53_UART_ENABLE_DISABLE, base + NRF53_UART_ENABLE_OFFSET); + + putreg32(0xffffffff, base + NRF53_UART_PSELTXD_OFFSET); + putreg32(0xffffffff, base + NRF53_UART_PSELRXD_OFFSET); + + /* Unconfigure GPIO */ + + nrf53_gpio_unconfig(config->rxpin); + nrf53_gpio_unconfig(config->txpin); + + /* Deatach TWI from GPIO */ + + putreg32(UART_PSELTXD_RESET, base + NRF53_UART_PSELTXD_OFFSET); + putreg32(UART_PSELRXD_RESET, base + NRF53_UART_PSELRXD_OFFSET); +} + +/**************************************************************************** + * Name: nrf53_usart_setformat + * + * Description: + * Set the USART line format and speed. + * + ****************************************************************************/ + +void nrf53_usart_setformat(uintptr_t base, + const struct uart_config_s *config) +{ + /* Configure baud */ + + nrf53_setbaud(base, config); + + /* Configure polarity */ + + nrf53_setparity(base, config); + +#ifdef HAVE_UART_STOPBITS + /* Configure STOP bits */ + + nrf53_setstops(base, config); +#endif + + /* Configure hardware flow control */ + + nrf53_sethwflow(base, config); +} +#endif + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef HAVE_UART_CONSOLE + putreg32(1, CONSOLE_BASE + NRF53_UART_TASKS_STARTTX_OFFSET); + putreg32(0, CONSOLE_BASE + NRF53_UART_EVENTS_TXDRDY_OFFSET); + putreg32(ch, CONSOLE_BASE + NRF53_UART_TXD_OFFSET); + while (getreg32(CONSOLE_BASE + NRF53_UART_EVENTS_TXDRDY_OFFSET) == 0) + { + } + + putreg32(1, CONSOLE_BASE + NRF53_UART_TASKS_STOPTX_OFFSET); +#endif +} diff --git a/arch/arm/src/nrf53/nrf53_lowputc.h b/arch/arm/src/nrf53/nrf53_lowputc.h new file mode 100644 index 00000000000..a9d8f1f5788 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_lowputc.h @@ -0,0 +1,117 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_NRF53_LOWPUTC_H +#define __ARCH_ARM_SRC_NRF53_NRF53_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nrf53_gpio.h" +#include "nrf53_config.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; /* Input flow control supported */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; /* Output flow control supported. */ +#endif + nrf53_pinset_t txpin; /* TX pin */ + nrf53_pinset_t rxpin; /* RX pin */ +}; +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART + * initialization is done early so that the serial console is available + * for debugging very early in the boot sequence. + * + ****************************************************************************/ + +void nrf53_lowsetup(void); + +/**************************************************************************** + * Name: nrf53_usart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void nrf53_usart_configure(uintptr_t base, + const struct uart_config_s *config); +#endif + +/**************************************************************************** + * Name: nrf53_usart_disable + * + * Description: + * Disable a UART. it will be necessary to again call + * nrf53_usart_configure() in order to use this UART channel again. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void nrf53_usart_disable(uintptr_t base, + const struct uart_config_s *config); +#endif + +/**************************************************************************** + * Name: nrf53_usart_setformat + * + * Description: + * Set the USART line format and speed. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void nrf53_usart_setformat(uintptr_t base, + const struct uart_config_s *config); +#endif + +#endif /* __ARCH_ARM_SRC_NRF53_NRF53_LOWPUTC_H */ diff --git a/arch/arm/src/nrf53/nrf53_serial.c b/arch/arm/src/nrf53/nrf53_serial.c new file mode 100644 index 00000000000..cfa2c4d8ce4 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_serial.c @@ -0,0 +1,865 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "nrf53_config.h" +#include "hardware/nrf53_uarte.h" +#include "nrf53_clockconfig.h" +#include "nrf53_lowputc.h" +#include "nrf53_serial.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* How many UARTs are supported */ + +#ifdef HAVE_UART1 +# define NRF53_NUART 2 +#else +# define NRF53_NUART 1 +#endif + +/* Some sanity checks *******************************************************/ + +/* Is there at least one UART enabled and configured as a RS-232 device? */ + +#ifndef HAVE_UART_DEVICE +# warning "No UARTs enabled" +#endif + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#if defined(HAVE_UART_DEVICE) && defined(USE_SERIALDRIVER) + +/* Which UART with be tty0/console and which tty1-4? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered UART. + */ + +#ifdef CONFIG_UART0_SERIAL_CONSOLE +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +#elif CONFIG_UART1_SERIAL_CONSOLE +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the state of one UART device */ + +struct nrf53_dev_s +{ + uintptr_t uartbase; /* Base address of UART registers */ + uint8_t irq; /* IRQ associated with this UART */ + bool rx_available; /* rx byte available */ + + /* UART configuration */ + + struct uart_config_s config; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int nrf53_setup(struct uart_dev_s *dev); +static void nrf53_shutdown(struct uart_dev_s *dev); +static int nrf53_attach(struct uart_dev_s *dev); +static void nrf53_detach(struct uart_dev_s *dev); +static int nrf53_interrupt(int irq, void *context, void *arg); +static int nrf53_ioctl(struct file *filep, int cmd, unsigned long arg); +static int nrf53_receive(struct uart_dev_s *dev, unsigned int *status); +static void nrf53_rxint(struct uart_dev_s *dev, bool enable); +static bool nrf53_rxavailable(struct uart_dev_s *dev); +static void nrf53_send(struct uart_dev_s *dev, int ch); +static void nrf53_txint(struct uart_dev_s *dev, bool enable); +static bool nrf53_txready(struct uart_dev_s *dev); +static bool nrf53_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = nrf53_setup, + .shutdown = nrf53_shutdown, + .attach = nrf53_attach, + .detach = nrf53_detach, + .ioctl = nrf53_ioctl, + .receive = nrf53_receive, + .rxint = nrf53_rxint, + .rxavailable = nrf53_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = nrf53_send, + .txint = nrf53_txint, + .txready = nrf53_txready, + .txempty = nrf53_txempty, +}; + +/* I/O buffers */ + +#ifdef HAVE_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef HAVE_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif + +/* This describes the state of the NRF53 UART0 port. */ + +#ifdef HAVE_UART0 +static struct nrf53_dev_s g_uart0priv = +{ + .uartbase = NRF53_UART0_BASE, + .irq = NRF53_IRQ_UART0, + .rx_available = false, + .config = + { + .baud = CONFIG_UART0_BAUD, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +#ifdef CONFIG_UART0_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_UART0_OFLOWCONTROL + .oflow = true, +#endif + .txpin = BOARD_UART0_TX_PIN, + .rxpin = BOARD_UART0_RX_PIN, + } +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the NRF53 UART1 port. */ + +#ifdef HAVE_UART1 +static struct nrf53_dev_s g_uart1priv = +{ + .uartbase = NRF53_UART1_BASE, + .irq = NRF53_IRQ_UART1, + .rx_available = false, + .config = + { + .baud = CONFIG_UART1_BAUD, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +#ifdef CONFIG_UART1_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_UART1_OFLOWCONTROL + .oflow = true, +#endif + .txpin = BOARD_UART1_TX_PIN, + .rxpin = BOARD_UART1_RX_PIN, + } +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This table lets us iterate over the configured UARTs */ + +static struct uart_dev_s * const g_uart_devs[NRF53_NUART] = +{ +#ifdef HAVE_UART0 + [0] = &g_uart0port, +#endif +#ifdef HAVE_UART1 + [1] = &g_uart1port +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int nrf53_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + + /* TODO: Configure the UART as an RS-232 UART */ + + /* REVISIT: If nrf53_usart_configure() called 2nd time uart stops working. + * Rx interrupt keeps firing. + * configuring is done on __start + * + * UPDATE 19.12.2019: No problems described above were observed, + * but just in case we leave the above note for some time. + */ + + nrf53_usart_configure(priv->uartbase, &priv->config); +#endif + + /* TODO: configure UART if not selected as console */ + + return OK; +} + +/**************************************************************************** + * Name: nrf53_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void nrf53_shutdown(struct uart_dev_s *dev) +{ + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + + /* Disable interrupts */ + + /* Reset hardware and disable Rx and Tx */ + + nrf53_usart_disable(priv->uartbase, &priv->config); +} + +/**************************************************************************** + * Name: nrf53_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the the setup() method is called, however, the serial console may + * operate in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). + * The RX and TX interrupts are not enabled until the txint() and rxint() + * methods are called. + * + ****************************************************************************/ + +static int nrf53_attach(struct uart_dev_s *dev) +{ + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ(s). The interrupts are (probably) still + * disabled in the C2 register. + */ + + ret = irq_attach(priv->irq, nrf53_interrupt, dev); + if (ret == OK) + { + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: nrf53_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. + * The exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void nrf53_detach(struct uart_dev_s *dev) +{ + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + + /* Disable interrupts */ + + putreg32(UART_INT_RXDRDY, priv->uartbase + NRF53_UART_INTENCLR_OFFSET); + up_disable_irq(priv->irq); + + /* Detach from the interrupt(s) */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: nrf53_interrupt + * + * Description: + * This is the UART status interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int nrf53_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct nrf53_dev_s *priv; + uint32_t regval; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct nrf53_dev_s *)dev->priv; + + /* Check RX event */ + + regval = getreg32(priv->uartbase + NRF53_UART_EVENTS_RXDRDY_OFFSET); + + if (regval != 0) + { + putreg32(0, priv->uartbase + NRF53_UART_EVENTS_RXDRDY_OFFSET); + priv->rx_available = true; + uart_recvchars(dev); + } + + /* Clear errors */ + + putreg32(0, priv->uartbase + NRF53_UART_ERRORSRC_OFFSET); + + return OK; +} + +/**************************************************************************** + * Name: nrf53_set_format + * + * Description: + * Set the serial line format and speed. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_TERMIOS +void nrf53_set_format(struct uart_dev_s *dev) +{ + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + + nrf53_usart_setformat(priv->uartbase, &priv->config); +} +#endif + +/**************************************************************************** + * Name: nrf53_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int nrf53_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#ifdef CONFIG_SERIAL_TERMIOS + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + struct uart_config_s *config = &priv->config; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + termiosp->c_cflag = ((config->parity != 0) ? PARENB : 0) + | ((config->parity == 1) ? PARODD : 0) + | ((config->stopbits2) ? CSTOPB : 0) | +#ifdef CONFIG_SERIAL_OFLOWCONTROL + ((config->oflow) ? CCTS_OFLOW : 0) | +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + ((config->iflow) ? CRTS_IFLOW : 0) | +#endif + CS8; + + cfsetispeed(termiosp, config->baud); + + break; + } + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Perform some sanity checks before accepting any changes */ + + if ((termiosp->c_cflag & CSIZE) != CS8) + { + ret = -EINVAL; + break; + } + +#ifndef HAVE_UART_STOPBITS + if ((termiosp->c_cflag & CSTOPB) != 0) + { + ret = -EINVAL; + break; + } +#endif + + if (termiosp->c_cflag & PARODD) + { + ret = -EINVAL; + break; + } + + /* TODO: CCTS_OFLOW and CRTS_IFLOW */ + + /* Parity */ + + if (termiosp->c_cflag & PARENB) + { + config->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + config->parity = 0; + } + +#ifdef HAVE_UART_STOPBITS + /* Stop bits */ + + config->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; +#endif + + /* Note that only cfgetispeed is used because we have knowledge + * that only one speed is supported. + */ + + config->baud = cfgetispeed(termiosp); + + /* Effect the changes */ + + nrf53_set_format(dev); + + break; + } +#endif + + default: + { + ret = -ENOTTY; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: nrf53_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int nrf53_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + uint32_t data; + + /* Get input data along with receiver control information */ + + data = getreg32(priv->uartbase + NRF53_UART_RXD_OFFSET); + priv->rx_available = false; + + /* Return receiver control information */ + + if (status) + { + *status = 0x00; + } + + /* Then return the actual received data. */ + + return data; +} + +/**************************************************************************** + * Name: nrf53_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void nrf53_rxint(struct uart_dev_s *dev, bool enable) +{ + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + /* Receive an interrupt when their is anything in the Rx data register + * (or an Rx timeout occurs). + */ + + putreg32(UART_INT_RXDRDY, priv->uartbase + NRF53_UART_INTENSET_OFFSET); + putreg32(1, priv->uartbase + NRF53_UART_TASKS_STARTRX_OFFSET); + +#endif + } + else + { + putreg32(UART_INT_RXDRDY, priv->uartbase + NRF53_UART_INTENCLR_OFFSET); + putreg32(1, priv->uartbase + NRF53_UART_TASKS_STOPRX_OFFSET); + } +} + +/**************************************************************************** + * Name: nrf53_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool nrf53_rxavailable(struct uart_dev_s *dev) +{ + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + + /* Return true if the receive buffer/fifo is not "empty." */ + + return priv->rx_available; +} + +/**************************************************************************** + * Name: nrf53_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void nrf53_send(struct uart_dev_s *dev, int ch) +{ + struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; + + putreg32(0, priv->uartbase + NRF53_UART_EVENTS_TXDRDY_OFFSET); + putreg32(1, priv->uartbase + NRF53_UART_TASKS_STARTTX_OFFSET); + + putreg32(ch, priv->uartbase + NRF53_UART_TXD_OFFSET); + while (getreg32(priv->uartbase + NRF53_UART_EVENTS_TXDRDY_OFFSET) == 0) + { + } + + putreg32(1, priv->uartbase + NRF53_UART_TASKS_STOPTX_OFFSET); +} + +/**************************************************************************** + * Name: nrf53_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void nrf53_txint(struct uart_dev_s *dev, bool enable) +{ + /* struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; */ + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + irqstate_t flags; + + /* Enable the TX interrupt */ + + flags = enter_critical_section(); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + leave_critical_section(flags); +#endif + } + else + { + /* Disable the TX interrupt */ + } +} + +/**************************************************************************** + * Name: nrf53_txready + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool nrf53_txready(struct uart_dev_s *dev) +{ + /* struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; */ + + /* Return true if the transmit FIFO is "not full." */ + + return true; +} + +/**************************************************************************** + * Name: nrf53_txempty + * + * Description: + * Return true if the transmit data register is empty + * + ****************************************************************************/ + +static bool nrf53_txempty(struct uart_dev_s *dev) +{ + /* struct nrf53_dev_s *priv = (struct nrf53_dev_s *)dev->priv; */ + + /* Return true if the transmit FIFO is "empty." */ + + return true; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before nrf53_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in nrf53_lowsetup() and main clock + * initialization performed in nrf_clock_configure(). + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void nrf53_earlyserialinit(void) +{ + /* Configuration whichever one is the console */ + +#ifdef HAVE_UART_CONSOLE + CONSOLE_DEV.isconsole = true; + nrf53_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that nrf53_earlyserialinit was called previously. + * + * Input Parameters: + * None + * + * Returns Value: + * None + * + ****************************************************************************/ + +void arm_serialinit(void) +{ + unsigned minor = 0; + unsigned i = 0; + char devname[16]; + +#ifdef HAVE_UART_CONSOLE + /* Register the serial console */ + + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + uart_register("/dev/ttyS0", &TTYS0_DEV); + minor = 1; + + /* Register all remaining UARTs */ + + strcpy(devname, "/dev/ttySx"); + + for (i = 0; i < NRF53_NUART; i++) + { + /* Don't create a device for non-configured ports. */ + + if (g_uart_devs[i] == 0) + { + continue; + } + + /* Don't create a device for the console - we did that above */ + + if (g_uart_devs[i]->isconsole) + { + continue; + } + + /* Register USARTs as devices in increasing order */ + + devname[9] = '0' + minor++; + uart_register(devname, g_uart_devs[i]); + } +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + /* struct nrf53_dev_s *priv = (struct nrf53_dev_s *)CONSOLE_DEV.priv; */ + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + arm_lowputc('\r'); + } + + arm_lowputc(ch); +#endif + + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + arm_lowputc('\r'); + } + + arm_lowputc(ch); + return ch; +#endif +} + +#endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER */ diff --git a/arch/arm/src/nrf53/nrf53_serial.h b/arch/arm/src/nrf53/nrf53_serial.h new file mode 100644 index 00000000000..2b1d8edafcd --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_serial.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_serial.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_NRF53_SERIAL_H +#define __ARCH_ARM_SRC_NRF53_NRF53_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf53_config.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before nrf53_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in xmc_lowsetup() and main clock initialization + * performed in xmc_clock_configure(). + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void nrf53_earlyserialinit(void); +#endif + +#endif /* __ARCH_ARM_SRC_NRF53_NRF53@_SERIAL_H */ diff --git a/arch/arm/src/nrf53/nrf53_start.c b/arch/arm/src/nrf53/nrf53_start.c new file mode 100644 index 00000000000..c2724238327 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_start.c @@ -0,0 +1,179 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "nvic.h" + +#include "nrf53_clockconfig.h" +#include "hardware/nrf53_utils.h" +#include "nrf53_lowputc.h" +#include "nrf53_start.h" +#include "nrf53_gpio.h" +#include "nrf53_serial.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) arm_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_ARMV8M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) noinstrument_function; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + +#ifdef CONFIG_ARMV8M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile("sub r10, sp, %0" : : + "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); +#endif + + /* Make sure that interrupts are disabled */ + + __asm__ __volatile__ ("\tcpsid i\n"); + + /* Configure the clocking and the console uart so that we can get debug + * output as soon as possible. NOTE: That this logic must not assume that + * .bss or .data have beeninitialized. + */ + + nrf53_clockconfig(); + nrf53_lowsetup(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + showprogress('B'); + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + showprogress('C'); + +#if defined(CONFIG_ARCH_CHIP_NRF53832) + /* Initialize the errdata work-around */ + + nrf53832_errdata_init(); +#endif + + /* Initialize the FPU (if configured) */ + + arm_fpuconfig(); + + showprogress('D'); + +#ifdef USE_EARLYSERIALINIT + /* Perform early serial initialization */ + + nrf53_earlyserialinit(); +#endif + showprogress('E'); + +#ifdef CONFIG_BUILD_PROTECTED + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + + nrf53_userspace(); + showprogress('F'); +#endif + + /* Initialize onboard resources */ + + nrf53_board_initialize(); + showprogress('G'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/arm/src/nrf53/nrf53_start.h b/arch/arm/src/nrf53/nrf53_start.h new file mode 100644 index 00000000000..c08b37327a6 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_start.h @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_start.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_NRF53_START_H +#define __ARCH_ARM_SRC_NRF53_NRF53_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_board_initialize + * + * Description: + * All NRF53xxx architectures must provide the following entry point. + * This entry point is called early in the initialization -- after clocking + * and memory have been configured but before caches have been enabled and + * before any devices have been initialized. + * + ****************************************************************************/ + +void nrf53_board_initialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_NRF53_NRF53_START_H */ diff --git a/arch/arm/src/nrf53/nrf53_systick.c b/arch/arm/src/nrf53/nrf53_systick.c new file mode 100644 index 00000000000..f01b31092e8 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_systick.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_systick.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include +#include "systick.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + /* Use SysTick to drive system timer */ + + up_timer_set_lowerhalf(systick_initialize(true, BOARD_SYSTICK_CLOCK, -1)); +} diff --git a/arch/arm/src/nrf53/nrf53_utils.c b/arch/arm/src/nrf53/nrf53_utils.c new file mode 100644 index 00000000000..215b2c0d250 --- /dev/null +++ b/arch/arm/src/nrf53/nrf53_utils.c @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/arm/src/nrf53/nrf53_utils.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nvic.h" +#include "arm_internal.h" +#include "nrf53_irq.h" +#include "hardware/nrf53_utils.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf53_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. + * + * This function is logically a part of nrf53_irq.c, but I will keep it in + * a separate file so that it will not increase the footprint on NRF53 + * platforms that do not need this function. + * + ****************************************************************************/ + +void nrf53_clrpend(int irq) +{ + /* Check for external interrupt */ + + if (irq >= NRF53_IRQ_EXTINT) + { + if (irq < (NRF53_IRQ_EXTINT + 32)) + { + putreg32(1 << (irq - NRF53_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND); + } + else if (irq < NRF53_IRQ_NIRQS) + { + putreg32(1 << (irq - NRF53_IRQ_EXTINT - 32), + NVIC_IRQ32_63_CLRPEND); + } + } +}