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arch/mips/pic32mz: fix nxstyle issues in pic32mz_serial.c.
Re-indent the case labels of up_ioctl() and fix the remaining nxstyle errors (long comment line, missing blank lines after declarations). No functional change. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
This commit is contained in:
Daniel P. Carvalho
Alan C. Assis
parent
7e5cf3d5d0
commit
67971964b2
1 changed files with 166 additions and 163 deletions
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@ -914,226 +914,228 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
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switch (cmd)
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{
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#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
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case TIOCSERGSTRUCT:
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{
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struct up_dev_s *user = (struct up_dev_s *)arg;
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if (!user)
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{
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ret = -EINVAL;
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}
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else
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{
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memcpy(user, dev, sizeof(struct up_dev_s));
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}
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}
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break;
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case TIOCSERGSTRUCT:
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{
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struct up_dev_s *user = (struct up_dev_s *)arg;
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if (!user)
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{
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ret = -EINVAL;
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}
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else
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{
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memcpy(user, dev, sizeof(struct up_dev_s));
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}
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}
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break;
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#endif
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#ifdef CONFIG_SERIAL_TERMIOS
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case TCGETS:
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{
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struct termios *termiosp = (struct termios *)arg;
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tcflag_t ccflag = 0;
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case TCGETS:
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{
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struct termios *termiosp = (struct termios *)arg;
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tcflag_t ccflag = 0;
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if (!termiosp)
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{
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ret = -EINVAL;
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break;
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}
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if (!termiosp)
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{
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ret = -EINVAL;
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break;
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}
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if (priv->bits >= 5 && priv->bits <= 8)
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{
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ccflag |= (CS5 + (priv->bits - 5));
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}
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if (priv->bits >= 5 && priv->bits <= 8)
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{
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ccflag |= (CS5 + (priv->bits - 5));
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}
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if (priv->stopbits2)
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{
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ccflag |= CSTOPB;
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}
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if (priv->stopbits2)
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{
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ccflag |= CSTOPB;
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}
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if (priv->parity == 1)
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{
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ccflag |= PARENB;
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}
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else if (priv->parity == 2)
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{
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ccflag |= PARENB | PARODD;
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}
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if (priv->parity == 1)
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{
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ccflag |= PARENB;
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}
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else if (priv->parity == 2)
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{
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ccflag |= PARENB | PARODD;
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}
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/* TODO: Other termios fields are not yet returned.
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*
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* TODO: append support for CCTS_OFLOW, CRTS_IFLOW, HUPCL, and
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* CLOCAL as well as os-compliant break sequence.
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*
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* Note that cfsetospeed is not necessary because we have
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* knowledge that only one speed is supported.
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*/
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/* TODO: Other termios fields are not yet returned.
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*
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* TODO: append support for CCTS_OFLOW, CRTS_IFLOW, HUPCL, and
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* CLOCAL as well as os-compliant break sequence.
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*
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* Note that cfsetospeed is not necessary because we have
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* knowledge that only one speed is supported.
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*/
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termiosp->c_cflag = ccflag;
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termiosp->c_cflag = ccflag;
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cfsetispeed(termiosp, priv->baud);
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}
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break;
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cfsetispeed(termiosp, priv->baud);
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}
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break;
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case TCSETS:
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{
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struct termios *termiosp = (struct termios *)arg;
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unsigned int nbits;
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case TCSETS:
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{
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struct termios *termiosp = (struct termios *)arg;
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unsigned int nbits;
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if (!termiosp)
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{
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ret = -EINVAL;
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break;
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}
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if (!termiosp)
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{
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ret = -EINVAL;
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break;
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}
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/* Perform some sanity checks before accepting any changes */
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/* Perform some sanity checks before accepting any changes */
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if (termiosp->c_cflag & CRTSCTS)
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{
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/* We don't support flow control right now, so we report an
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* error
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*/
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if (termiosp->c_cflag & CRTSCTS)
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{
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/* We don't support flow control right now, so we report an
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* error
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*/
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ret = -EINVAL;
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break;
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}
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ret = -EINVAL;
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break;
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}
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nbits = (termiosp->c_cflag & CSIZE) + 5;
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if ((nbits < 8) || (nbits > 9))
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{
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/* We only support 8 or 9 data bits on this arch, so we
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* report an error
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*/
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nbits = (termiosp->c_cflag & CSIZE) + 5;
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if ((nbits < 8) || (nbits > 9))
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{
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/* We only support 8 or 9 data bits on this arch, so we
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* report an error
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*/
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ret = -EINVAL;
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break;
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}
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ret = -EINVAL;
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break;
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}
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/* Sanity checks passed; apply settings. */
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/* Sanity checks passed; apply settings. */
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priv->bits = nbits;
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priv->bits = nbits;
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if (termiosp->c_cflag & PARENB)
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{
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priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
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}
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else
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{
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priv->parity = 0;
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}
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if (termiosp->c_cflag & PARENB)
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{
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priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
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}
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else
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{
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priv->parity = 0;
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}
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priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0;
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priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0;
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/* TODO: Handle other termios settings.
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* Note that only cfgetispeed is used because we have knowledge
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* that only one speed is supported.
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*/
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/* TODO: Handle other termios settings.
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* Note that only cfgetispeed is used because we have knowledge
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* that only one speed is supported.
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*/
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priv->baud = cfgetispeed(termiosp);
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pic32mz_uartconfigure(priv->uartbase, priv->baud, priv->parity,
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priv->bits, priv->stopbits2);
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}
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break;
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priv->baud = cfgetispeed(termiosp);
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pic32mz_uartconfigure(priv->uartbase, priv->baud, priv->parity,
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priv->bits, priv->stopbits2);
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}
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break;
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#endif /* CONFIG_SERIAL_TERMIOS */
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#ifdef CONFIG_PIC32MZ_UART_BREAKS
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# ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
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{
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irqstate_t flags;
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case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
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{
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irqstate_t flags;
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flags = enter_critical_section();
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flags = enter_critical_section();
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/* Disable any further TX activity */
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/* Disable any further TX activity */
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priv->brk = true;
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up_txint(dev, false);
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priv->brk = true;
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up_txint(dev, false);
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/* Configure TX as a GPIO output pin driven low to send break */
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/* Configure TX as a GPIO output pin driven low to send break */
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pic32mz_configgpio(priv->tx_gpio);
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putreg32(0, priv->tx_pps_reg);
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pic32mz_configgpio(priv->tx_gpio);
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putreg32(0, priv->tx_pps_reg);
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leave_critical_section(flags);
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}
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break;
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leave_critical_section(flags);
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}
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break;
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case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
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{
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irqstate_t flags;
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case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
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{
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irqstate_t flags;
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flags = enter_critical_section();
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flags = enter_critical_section();
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/* Configure TX back to UART */
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/* Configure TX back to UART */
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putreg32(priv->tx_pps_val, priv->tx_pps_reg);
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putreg32(priv->tx_pps_val, priv->tx_pps_reg);
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/* Enable further tx activity */
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/* Enable further tx activity */
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priv->brk = false;
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up_txint(dev, true);
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priv->brk = false;
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up_txint(dev, true);
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leave_critical_section(flags);
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}
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break;
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leave_critical_section(flags);
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}
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break;
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# else
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case TIOCSBRK: /* No BSD compatibility: Turn break on for 12 bit times */
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{
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uint32_t regval;
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irqstate_t flags;
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case TIOCSBRK: /* No BSD compatibility: Turn break on for 12 bit times */
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{
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uint32_t regval;
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irqstate_t flags;
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flags = enter_critical_section();
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flags = enter_critical_section();
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/* Disable any further TX activity */
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/* Disable any further TX activity */
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priv->brk = true;
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up_txint(dev, false);
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priv->brk = true;
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up_txint(dev, false);
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/* Enable break transmission */
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/* Enable break transmission */
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regval = up_serialin(priv, PIC32MZ_UART_STA_OFFSET);
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regval |= UART_STA_UTXBRK;
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up_serialout(priv, PIC32MZ_UART_STA_OFFSET, regval);
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regval = up_serialin(priv, PIC32MZ_UART_STA_OFFSET);
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regval |= UART_STA_UTXBRK;
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up_serialout(priv, PIC32MZ_UART_STA_OFFSET, regval);
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/* A dummy write to TXREG is needed to start sending the break. The
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* caller should ensure that there are no pending transmit data in
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* the UART FIFO before executing this IOCTL or the break will
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* consume a byte of that data instead of the dummy write.
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*/
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/* A dummy write to TXREG is needed to start sending the break. The
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* caller should ensure that there are no pending transmit data in
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* the UART FIFO before executing this IOCTL or the break will
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* consume a byte of that data instead of the dummy write.
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*/
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up_send(dev, 0);
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up_send(dev, 0);
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leave_critical_section(flags);
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}
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break;
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leave_critical_section(flags);
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}
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break;
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case TIOCCBRK: /* No BSD compatibility: May turn off break too soon */
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{
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irqstate_t flags;
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case TIOCCBRK: /* No BSD compatibility: May turn off break too soon */
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{
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irqstate_t flags;
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flags = enter_critical_section();
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flags = enter_critical_section();
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/* Enable further tx activity. We do not clear the UTXBRK bit
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* because hardware does it automatically after transmitting the
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* break. In fact, the PIC32MZ manual, rev G, section 21.5.4, says:
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* "If the user application clears the UTXBRK bit prior to sequence
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* completion, unexpected module behavior can result." It should be
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* safe to re-enable transmit here because the hardware specifically
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* allows to queue up the next character to follow the break.
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*/
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/* Enable further tx activity. We do not clear the UTXBRK bit
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* because hardware does it automatically after transmitting the
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* break. In fact, the PIC32MZ manual, rev G, section 21.5.4,
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* says: "If the user application clears the UTXBRK bit prior to
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* sequence completion, unexpected module behavior can result." It
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* should be safe to re-enable transmit here because the hardware
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* specifically allows to queue up the next character to follow
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* the break.
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*/
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priv->brk = false;
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up_txint(dev, true);
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priv->brk = false;
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up_txint(dev, true);
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leave_critical_section(flags);
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}
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break;
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leave_critical_section(flags);
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}
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break;
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# endif
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#endif
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default:
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ret = -ENOTTY;
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break;
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default:
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ret = -ENOTTY;
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break;
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}
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return ret;
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@ -1237,6 +1239,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
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static void up_send(struct uart_dev_s *dev, int ch)
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{
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struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
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up_serialout(priv, PIC32MZ_UART_TXREG_OFFSET, (uint32_t)ch);
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}
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