diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h index 8106886567e..0e962104f91 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h @@ -949,13 +949,13 @@ /* Timer X Chopper Register */ -#define HRTIM_TIMCHP_CARFRQ_SHIFT 0 /* Bits 0-3 */ +#define HRTIM_TIMCHP_CARFRQ_SHIFT 0 /* Bits 0-3: Chopper carrier frequency */ #define HRTIM_TIMCHP_CARFRQ_MASK (15 << HRTIM_TIMCHP_CARFRQ_SHIFT) -#define HRTIM_TIMCHP_CARDTY_SHIFT 4 /* Bits 4-6 */ +#define HRTIM_TIMCHP_CARDTY_SHIFT 4 /* Bits 4-6: Chopper duty cycle */ #define HRTIM_TIMCHP_CARDTY_MASK (7 << HRTIM_TIMCHP_CARDTY_SHIFT) -#define HRTIM_TIMCHP_STRTPW_SHIFT 7 /* Bits 7-10 */ +#define HRTIM_TIMCHP_STRTPW_SHIFT 7 /* Bits 7-10: Chopper start pulsewidth */ #define HRTIM_TIMCHP_STRTPW_MASK (15 << HRTIM_TIMCHP_STRTPW_SHIFT) /* Timer X Capture 1 Control Register */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index b1d1e6e6e0c..363ec14b84b 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -59,66 +59,130 @@ #warning "HRTIM UNDER DEVELOPMENT !" -#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMA_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) +#if defined(CONFIG_STM32_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMA_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMA_CHOP) # ifndef CONFIG_STM32_HRTIM_TIMA # error "CONFIG_STM32_HRTIM_TIMA must be set" # endif #endif -#if defined(CONFIG_STM32_HRTIM_TIMB_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMB_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_IRQ) +#if defined(CONFIG_STM32_TIMB_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMB_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMB_DT) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) # ifndef CONFIG_STM32_HRTIM_TIMB # error "CONFIG_STM32_HRTIM_TIMB must be set" # endif #endif -#if defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) +#if defined(CONFIG_STM32_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMC_CHOP) # ifndef CONFIG_STM32_HRTIM_TIMC # error "CONFIG_STM32_HRTIM_TIMC must be set" # endif #endif -#if defined(CONFIG_STM32_HRTIM_TIMD_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMD_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_IRQ) +#if defined(CONFIG_STM32_TIMD_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMD_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMD_DT) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) # ifndef CONFIG_STM32_HRTIM_TIMD # error "CONFIG_STM32_HRTIM_TIMD must be set" # endif #endif -#if defined(CONFIG_STM32_HRTIM_TIME_PWM) || defined(CONFIG_STM32_HRTIM_TIME_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIME_CAP) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) +#if defined(CONFIG_STM32_TIME_PWM) || defined(CONFIG_STM32_HRTIM_TIME_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIME_CAP) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIME_DT) || defined(CONFIG_STM32_HRTIM_TIME_CHOP) # ifndef CONFIG_STM32_HRTIM_TIME # error "CONFIG_STM32_HRTIM_TIME must be set" # endif #endif -#ifdef CONFIG_STM32_HRTIM_ADC -# error HRTIM ADC Triggering not supported yet +#if defined(CONFIG_STM32_HRTIM_PWM) +#if !defined(CONFIG_STM32_HRTIM_TIMA_PWM) && !defined(CONFIG_STM32_HRTIM_TIMB_PWM) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_PWM) && !defined(CONFIG_STM32_HRTIM_TIMD_PWM) && \ + !defined(CONFIG_STM32_HRTIM_TIME_PWM) +# warning "CONFIG_STM32_HRTIM_PWM enabled but no timer selected" +# endif #endif - #if defined(CONFIG_STM32_HRTIM_DAC) #if !defined(CONFIG_STM32_HRTIM_MASTER_DAC) && !defined(CONFIG_STM32_HRTIM_TIMA_DAC) && \ - !defined(CONFIG_STM32_HRTIM_TIMB_DAC) && !defined(CONFIG_STM32_HRTIM_TIMC_DAC) && \ - !defined(CONFIG_STM32_HRTIM_TIMD_DAC) && !defined(CONFIG_STM32_HRTIM_TIME_DAC) + !defined(CONFIG_STM32_HRTIM_TIMB_DAC) && !defined(CONFIG_STM32_HRTIM_TIMC_DAC) && \ + !defined(CONFIG_STM32_HRTIM_TIMD_DAC) && !defined(CONFIG_STM32_HRTIM_TIME_DAC) # warning "CONFIG_STM32_HRTIM_DAC enabled but no timer selected" # endif #endif +#if defined(CONFIG_STM32_HRTIM_CAPTURE) +#if !defined(CONFIG_STM32_HRTIM_TIMA_CAP) && !defined(CONFIG_STM32_HRTIM_TIMB_CAP) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_CAP) && !defined(CONFIG_STM32_HRTIM_TIMD_CAP) && \ + !defined(CONFIG_STM32_HRTIM_TIME_CAP) +# warning "CONFIG_STM32_HRTIM_CAPTURE enabled but no timer selected" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_INTERRUPTS) +#if !defined(CONFIG_STM32_HRTIM_TIMA_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMB_IRQ) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_IRQ) && !defined(CONFIG_STM32_HRTIM_TIMD_IRQ) && \ + !defined(CONFIG_STM32_HRTIM_TIME_IRQ) +# warning "CONFIG_STM32_HRTIM_INTERRUPTS enabled but no timer selected" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_DEADTIME) +#if !defined(CONFIG_STM32_HRTIM_TIMA_DT) && !defined(CONFIG_STM32_HRTIM_TIMB_DT) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_DT) && !defined(CONFIG_STM32_HRTIM_TIMD_DT) && \ + !defined(CONFIG_STM32_HRTIM_TIME_DT) +# warning "CONFIG_STM32_HRTIM_DEADTIME enabled but no timer selected" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_CHOPPER) +#if !defined(CONFIG_STM32_HRTIM_TIMA_CHOP) && !defined(CONFIG_STM32_HRTIM_TIMB_CHOP) && \ + !defined(CONFIG_STM32_HRTIM_TIMC_CHOP) && !defined(CONFIG_STM32_HRTIM_TIMD_CHOP) && \ + !defined(CONFIG_STM32_HRTIM_TIME_CHOP) +# warning "CONFIG_STM32_HRTIM_CHOPPER enabled but no timer selected" +# endif +#endif + +#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \ + defined(CONFIG_STM32_HRTIM_TIME_PWM) +# ifndef CONFIG_STM32_HRTIM_PWM +# error "CONFIG_STM32_HRTIM_PWM must be set" +# endif +#endif #if defined(CONFIG_STM32_HRTIM_MASTER_DAC) || defined(CONFIG_STM32_HRTIM_TIMA_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMB_DAC) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \ - defined(CONFIG_STM32_HRTIM_TIMD_DAC) || defined(CONFIG_STM32_HRTIM_TIME_DAC) + defined(CONFIG_STM32_HRTIM_TIMB_DAC) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \ + defined(CONFIG_STM32_HRTIM_TIMD_DAC) || defined(CONFIG_STM32_HRTIM_TIME_DAC) # ifndef CONFIG_STM32_HRTIM_DAC # error "CONFIG_STM32_HRTIM_DAC must be set" # endif #endif - -#ifdef CONFIG_STM32_HRTIM_CAPTURE -# error HRTIM Capture not supported yet +#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CAP) +# ifndef CONFIG_STM32_HRTIM_CAPTURE +# error "CONFIG_STM32_HRTIM_CAPTURE must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIME_IRQ) +# ifndef CONFIG_STM32_HRTIM_INTERRUPTS +# error "CONFIG_STM32_HRTIM_INTERRUPTS must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \ + defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \ + defined(CONFIG_STM32_HRTIM_TIME_DT) +# ifndef CONFIG_STM32_HRTIM_DEADTIME +# error "CONFIG_STM32_HRTIM_DEADTIME must be set" +# endif +#endif +#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \ + defined(CONFIG_STM32_HRTIM_TIME_CHOP) +# ifndef CONFIG_STM32_HRTIM_CHOPPER +# error "CONFIG_STM32_HRTIM_CHOPPER must be set" +# endif #endif -#ifdef CONFIG_STM32_HRTIM_DEADTIME -# error HRTIM Deadtime not supported yet -#endif - -#ifdef CONFIG_STM32_HRTIM_CHOPPER -# error HRTIM Chopper not supported yet +#ifdef CONFIG_STM32_HRTIM_ADC +# error HRTIM ADC Triggering not supported yet #endif #ifdef CONFIG_STM32_HRTIM_INTERRUPTS @@ -207,30 +271,6 @@ # define HRTIM_IRQ_COMMON 0 #endif -/* HRTIM clock source configuration */ - -#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL -# if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL -# if (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLK) && \ - (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLKd2) -# error "APB2 prescaler factor can not be greater than 2" -# else -# define HRTIM_HAVE_CLK_FROM_PLL 1 -# define HRTIM_CLOCK 2*STM32_PLL_FREQUENCY -# endif -# else -# error "Clock system must be set to PLL" -# endif -#else -# error "Not supported yet: system freezes when no PLL selected." -# define HRTIM_HAVE_CLK_FROM_APB2 1 -# if STM32_RCC_CFGR_PPRE2 == RCC_CFGR_PPRE2_HCLK -# define HRTIM_CLOCK STM32_PCLK2_FREQUENCY -# else -# define HRTIM_CLOCK 2*STM32_PCLK2_FREQUENCY -# endif -#endif - /**************************************************************************** * Private Types ****************************************************************************/ @@ -262,10 +302,15 @@ struct stm32_hrtim_chopper_s #ifdef CONFIG_STM32_HRTIM_DEADTIME struct stm32_hrtim_deadtime_s { - uint8_t falling_lock:2; /* Deadtime falling value and sign lock */ - uint8_t rising_lock:2; /* Deadtime rising value and sign lock */ - uint8_t prescaler:3; /* Deadtime Prescaler */ - uint8_t _res:1; /* Reserved */ + uint8_t fsign_lock:1; /* Deadtime falling sing lock */ + uint8_t rsign_lock:1; /* Deadtime rising sing lock */ + uint8_t rising_lock:1; /* Deadtime rising value lock */ + uint8_t falling_lock:1; /* Deadtime falling value lock */ + uint8_t fsign:1; /* Deadtime falling sign */ + uint8_t rsign:1; /* Deadtime rising sign */ + uint8_t prescaler:3; /* Deadtime prescaler */ + uint16_t rising:9; /* Deadtime rising value */ + uint16_t falling:9; /* Deadtime falling value */ }; #endif @@ -297,14 +342,17 @@ struct stm32_hrtim_pwm_s struct stm32_hrtim_deadtime_s dt; #endif }; - #endif + +/* HRTIM TIMER Capture sturcutre */ + #ifdef CONFIG_STM32_HRTIM_CAPTURE struct stm32_hrtim_capture_s { - uint32_t reserved; /* Reserved */ -} + uint32_t cap1; /* Capture 1 configuration */ + uint32_t cap2; /* Capture 2 configuration */ +}; #endif /* Common data structure for Master Timer and Slave Timers*/ @@ -550,13 +598,20 @@ static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t offset, uint32_t clrbits, uint32_t setbits); +#ifdef CONFIG_DEBUG_POWER_INFO +static void hrtim_dumpregs(FAR struct stm32_hrtim_s *priv, uint8_t timer, + FAR const char *msg); +#else +# define hrtim_dumpregs(priv, timer, msg) +#endif + /* HRTIM helper */ static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t offset); static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *priv, - uint8_t timer); -static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s* priv, uint8_t timer); + uint8_t timer); +static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s *priv, uint8_t timer); /* Configuration */ @@ -564,12 +619,13 @@ static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv); static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint8_t pre); static int hrtim_tim_clocks_config(FAR struct stm32_hrtim_s *priv); -#if defined(CONFIG_STM32_HRTIM_CAPTURE) || defined(CONFIG_STM32_HRTIM_PWM) || \ - defined(CONFIG_STM32_HRTIM_SYNC) +#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_SYNC) static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv); #endif #if defined(CONFIG_STM32_HRTIM_CAPTURE) -static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_capture_config(FAR struct stm32_hrtim_s *priv); +static uint16_t hrtim_capture_get(FAR struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index); #endif #if defined(CONFIG_STM32_HRTIM_SYNC) static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv); @@ -591,14 +647,25 @@ static int hrtim_tim_dma_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint16_t dma); #endif #ifdef CONFIG_STM32_HRTIM_DEADTIME +static int hrtim_deadtime_update(FAR struct stm32_dev_s *dev, uint8_t dt, + uint16_t value) +static uint16_t hrtim_deadtime_get(FAR struct stm32_dev_s *dev, uint8_t dt); static int hrtim_deadtime_config(FAR struct stm32_hrtim_s *priv); #endif +#ifdef CONFIG_STM32_HRTIM_CHOPPER +static int hrtim_chopper_enable(FAR struct stm32_dev_s *dev, uint8_t timer, + uint8_t chan, bool state); +static int hrtim_tim_chopper_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer); +static int hrtim_chopper_config(FAR struct stm32_hrtim_s *priv); +#endif #ifdef CONFIG_STM32_HRTIM_BURST static int hrtim_burst_enable(FAR struct hrtim_dev_s *dev, bool state); static int hrtim_burst_cmp_update(FAR struct hrtim_dev_s *dev, uint16_t cmp); static int hrtim_burst_per_update(FAR struct hrtim_dev_s *dev, uint16_t per); static uint16_t hrtim_burst_cmp_get(FAR struct hrtim_dev_s *dev); static uint16_t hrtim_burst_per_get(FAR struct hrtim_dev_s *dev); +static int hrtim_burst_pre_update(FAR struct hrtim_dev_s *dev, uint8_t pre); +static int hrtim_burst_pre_get(FAR struct hrtim_dev_s *dev); static int hrtim_burst_config(FAR struct stm32_hrtim_s *priv); #endif #ifdef CONFIG_STM32_HRTIM_FAULTS @@ -612,7 +679,7 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index); #endif #ifdef CONFIG_STM32_HRTIM_INTERRUPTS static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv); -void hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); +static void hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); #endif static int hrtim_cmp_update(FAR struct hrtim_dev_s *dev, uint8_t timer, uint8_t index, uint16_t cmp); @@ -620,7 +687,7 @@ static int hrtim_per_update(FAR struct hrtim_dev_s *dev, uint8_t timer, uint16_t per); static uint16_t hrtim_per_get(FAR struct hrtim_dev_s *dev, uint8_t timer); static uint16_t hrtim_cmp_get(FAR struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index); + uint8_t index); static int hrtim_tim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t reset); static int hrtim_reset_config(FAR struct stm32_hrtim_s *priv); @@ -738,9 +805,13 @@ static struct stm32_hrtim_slave_priv_s g_tima_priv = #ifdef CONFIG_STM32_HRTIM_TIMA_DT .dt = { - .falling_lock = HRTIM_TIMA_DT_FLOCK, - .rising_lock = HRTIM_TIMA_DT_RLOCK, - .prescaler = HRTIM_TIMA_DT_PRESCALER, + .fsign_lock = HRTIM_TIMA_DT_RSLOCK, + .rsign_lock = HRTIM_TIMA_DT_RSLOCK, + .rising_lock = HRTIM_TIMA_DT_RVLOCK, + .falling_lock = HRTIM_TIMA_DT_FVLOCK, + .fsign = HRTIM_TIMA_DT_FSIGN, + .rsign = HRTIM_TIMA_DT_RSIGN, + .prescaler = HRTIM_TIMA_DT_PRESALER } #endif }, @@ -748,7 +819,8 @@ static struct stm32_hrtim_slave_priv_s g_tima_priv = #ifdef CONFIG_STM32_HRTIM_TIMA_CAP .cap = { - .reserved = 0 + .cap1 = HRTIM_TIMA_CAPTURE1, + .cap2 = HRTIM_TIMA_CAPTURE2, } #endif }; @@ -829,9 +901,13 @@ static struct stm32_hrtim_slave_priv_s g_timb_priv = #ifdef CONFIG_STM32_HRTIM_TIMB_DT .dt = { - .falling_lock = HRTIM_TIMB_DT_FLOCK, - .rising_lock = HRTIM_TIMB_DT_RLOCK, - .prescaler = HRTIM_TIMB_DT_PRESCALER, + .fsign_lock = HRTIM_TIMB_DT_RSLOCK, + .rsign_lock = HRTIM_TIMB_DT_RSLOCK, + .rising_lock = HRTIM_TIMB_DT_RVLOCK, + .falling_lock = HRTIM_TIMB_DT_FVLOCK, + .fsign = HRTIM_TIMB_DT_FSIGN, + .rsign = HRTIM_TIMB_DT_RSIGN, + .prescaler = HRTIM_TIMB_DT_PRESALER } #endif }, @@ -839,7 +915,8 @@ static struct stm32_hrtim_slave_priv_s g_timb_priv = #ifdef CONFIG_STM32_HRTIM_TIMB_CAP .cap = { - .reserved = 0 + .cap1 = HRTIM_TIMB_CAPTURE1, + .cap2 = HRTIM_TIMB_CAPTURE2, } #endif }; @@ -920,9 +997,13 @@ static struct stm32_hrtim_slave_priv_s g_timc_priv = #ifdef CONFIG_STM32_HRTIM_TIMC_DT .dt = { - .falling_lock = HRTIM_TIMC_DT_FLOCK, - .rising_lock = HRTIM_TIMC_DT_RLOCK, - .prescaler = HRTIM_TIMC_DT_PRESCALER, + .fsign_lock = HRTIM_TIMC_DT_RSLOCK, + .rsign_lock = HRTIM_TIMC_DT_RSLOCK, + .rising_lock = HRTIM_TIMC_DT_RVLOCK, + .falling_lock = HRTIM_TIMC_DT_FVLOCK, + .fsign = HRTIM_TIMC_DT_FSIGN, + .rsign = HRTIM_TIMC_DT_RSIGN, + .prescaler = HRTIM_TIMC_DT_PRESALER } #endif }, @@ -930,7 +1011,8 @@ static struct stm32_hrtim_slave_priv_s g_timc_priv = #ifdef CONFIG_STM32_HRTIM_TIMC_CAP .cap = { - .reserved = 0 + .cap1 = HRTIM_TIMC_CAPTURE1, + .cap2 = HRTIM_TIMC_CAPTURE2, } #endif }; @@ -1011,9 +1093,13 @@ static struct stm32_hrtim_slave_priv_s g_timd_priv = #ifdef CONFIG_STM32_HRTIM_TIMD_DT .dt = { - .falling_lock = HRTIM_TIMD_DT_FLOCK, - .rising_lock = HRTIM_TIMD_DT_RLOCK, - .prescaler = HRTIM_TIMD_DT_PRESCALER, + .fsign_lock = HRTIM_TIMD_DT_RSLOCK, + .rsign_lock = HRTIM_TIMD_DT_RSLOCK, + .rising_lock = HRTIM_TIMD_DT_RVLOCK, + .falling_lock = HRTIM_TIMD_DT_FVLOCK, + .fsign = HRTIM_TIMD_DT_FSIGN, + .rsign = HRTIM_TIMD_DT_RSIGN, + .prescaler = HRTIM_TIMD_DT_PRESALER } #endif }, @@ -1021,7 +1107,8 @@ static struct stm32_hrtim_slave_priv_s g_timd_priv = #ifdef CONFIG_STM32_HRTIM_TIMD_CAP .cap = { - .reserved = 0 + .cap1 = HRTIM_TIMD_CAPTURE1, + .cap2 = HRTIM_TIMD_CAPTURE2, } #endif }; @@ -1102,9 +1189,13 @@ static struct stm32_hrtim_slave_priv_s g_time_priv = #ifdef CONFIG_STM32_HRTIM_TIME_DT .dt = { - .falling_lock = HRTIM_TIME_DT_FLOCK, - .rising_lock = HRTIM_TIME_DT_RLOCK, - .prescaler = HRTIM_TIME_DT_PRESCALER, + .fsign_lock = HRTIM_TIME_DT_RSLOCK, + .rsign_lock = HRTIM_TIME_DT_RSLOCK, + .rising_lock = HRTIM_TIME_DT_RVLOCK, + .falling_lock = HRTIM_TIME_DT_FVLOCK, + .fsign = HRTIM_TIME_DT_FSIGN, + .rsign = HRTIM_TIME_DT_RSIGN, + .prescaler = HRTIM_TIME_DT_PRESALER } #endif }, @@ -1112,7 +1203,8 @@ static struct stm32_hrtim_slave_priv_s g_time_priv = #ifdef CONFIG_STM32_HRTIM_TIME_CAP .cap = { - .reserved = 0 + .cap1 = HRTIM_TIME_CAPTURE1, + .cap2 = HRTIM_TIME_CAPTURE2, } #endif }; @@ -1389,8 +1481,20 @@ static const struct stm32_hrtim_ops_s g_hrtim1ops = .burst_enable = hrtim_burst_enable, .burst_cmp_set = hrtim_burst_cmp_update, .burst_per_set = hrtim_burst_per_update, + .burst_pre_set = hrtim_burst_pre_update, .burst_cmp_get = hrtim_burst_cmp_get, .burst_per_get = hrtim_burst_per_get, + .burst_pre_get = hrtim_burst_pre_get, +#endif +#ifdef CONFIG_STM32_HRTIM_CHOPPER + .chopper_enable = hrtim_chopper_enable +#endif +#ifdef CONFIG_STM32_HRTIM_DEADTIME + .deadtime_update = hrtim_deadtime_update, + .deadtime_get = hrtim_deadtime_get, +#endif +#ifdef CONFIG_STM32_HRTIM_CAPTURE + .capture_get = hrtim_capture_get, #endif }; @@ -1759,6 +1863,159 @@ static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, (hrtim_tim_getreg(priv, timer, offset) & ~clrbits) | setbits); } +#ifdef CONFIG_DEBUG_POWER_INFO +static void hrtim_dumpregs(FAR struct stm32_hrtim_s *priv, uint8_t timer, + FAR const char *msg) +{ + pwrinfo("%s:\n", msg); + + switch (timer) + { + case HRTIM_TIMER_MASTER: + { + pwrinfo("\tCR:\t0x%08x\tISR:\t0x%08x\tICR:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET)); + + pwrinfo("\tDIER:\t0x%08x\tCNTR:\t0x%08x\tPER:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET)); + + pwrinfo("\tREP:\t0x%08x\tCMP1:\t0x%08x\tCMP2:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP1R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP2R_OFFSET)); + + pwrinfo("\tCMP3:\t0x%08x\tCMP4:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP3R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP4R_OFFSET)); + break; + } + +#ifdef CONFIG_STM32_HRTIM_TIMA + case HRTIM_TIMER_TIMA: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMB + case HRTIM_TIMER_TIMB: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMC + case HRTIM_TIMER_TIMC: +#endif +#ifdef CONFIG_STM32_HRTIM_TIMD + case HRTIM_TIMER_TIMD: +#endif +#ifdef CONFIG_STM32_HRTIM_TIME + case HRTIM_TIMER_TIME: +#endif + { + pwrinfo("\tCR:\t0x%08x\tISR:\t0x%08x\tICR:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ISR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_ICR_OFFSET)); + + pwrinfo("\tDIER:\t0x%08x\tCNTR:\t0x%08x\tPER:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DIER_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CNTR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET)); + + pwrinfo("\tREP:\t0x%08x\tCMP1:\t0x%08x\tCMP1C:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_REPR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP1R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP1CR_OFFSET)); + + pwrinfo("\tCMP2:\t0x%08x\tCMP3:\t0x%08x\tCMP4:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP2R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP3R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CMP4R_OFFSET)); + + pwrinfo("\tCPT1:\t0x%08x\tCPT2:\t0x%08x\tDTR:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CPT1R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CPT2R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET)); + + pwrinfo("\tSET1:\t0x%08x\tRST1:\t0x%08x\tSET2:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_SET1R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_RST1R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_SET2R_OFFSET)); + + pwrinfo("\tRST2:\t0x%08x\tEEF1:\t0x%08x\tEEF2:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_EEFR1_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_EEFR2_OFFSET)); + + pwrinfo("\tRSTR:\t0x%08x\tCHPR:\t0x%08x\tCPT1C:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CPT1CR_OFFSET)); + + pwrinfo("\tCPT2C:\t0x%08x\tOUT:\t0x%08x\tFLT:\t0x%08x\n", + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CPT2CR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET), + hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_FLTR_OFFSET)); + + break; + } + + case HRTIM_TIMER_COMMON: + { + pwrinfo("\tCR1:\t0x%08x\tCR2:\t0x%08x\tISR:\t0x%08x\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR1_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_CR2_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ISR_OFFSET)); + + pwrinfo("\tICR:\t0x%08x\tIER:\t0x%08x\tOENR:\t0x%08x\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ICR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_IER_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_OENR_OFFSET)); + + pwrinfo("\tODISR:\t0x%08x\tODSR:\t0x%08x\tBMCR:\t0x%08x\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODISR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ODSR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET)); + + pwrinfo("\tBMTRG:\t0x%08x\tBMCMPR:\t0x%08x\tBMPER:\t0x%08x\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET)); + + pwrinfo("\tADC1R:\t0x%08x\tADC2R:\t0x%08x\tADC3R:\t0x%08x\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET)); + + pwrinfo("\tADC4R:\t0x%08x\tDLLCR:\t0x%08x\tFLTIN1:\t0x%08x\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_DLLCR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET)); + + pwrinfo("\tFLTIN2:\t0x%08x\tBDMUPD:\t0x%08x\tBDTAUP:\t0x%08x\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMUPDR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTAUPR_OFFSET)); + + pwrinfo("\tBDTBUP: 0x%08x\tBDTCUP:\t0x%08x\tBDTDUP:\t0x%08x\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTBUPR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTCUPR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTDUPR_OFFSET)); + + pwrinfo("\tBDTEUP:\t0x%08x\tBDMAD:\t0x%08x\n", + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDTEUPR_OFFSET), + hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BDMADR_OFFSET)); + + break; + } + + default: + { + tmrerr("ERROR: No such timer index: %d\n", timer); + break; + } + } +} +#endif + /**************************************************************************** * Name: hrtim_dll_cal * @@ -1977,8 +2234,7 @@ errout: * ****************************************************************************/ -#if defined(CONFIG_STM32_HRTIM_CAPTURE) || defined(CONFIG_STM32_HRTIM_PWM) || \ - defined(CONFIG_STM32_HRTIM_SYNC) +#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_SYNC) static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv) { #ifdef CONFIG_STM32_HRTIM_EVENTS @@ -2037,6 +2293,7 @@ static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv) #ifdef CONFIG_STM32_HRTIM_TIME_PWM_CH2 stm32_configgpio(GPIO_HRTIM1_CHE2); #endif + /* Configure SCOUT */ #ifdef CONFIG_STM32_HRTIM_SCOUT @@ -2162,33 +2419,163 @@ static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv) } #endif +#if defined(CONFIG_STM32_HRTIM_CAPTURE) + /**************************************************************************** - * Name: hrtim_inputs_config + * Name: hrtim_tim_capture_cfg * * Description: - * Configure HRTIM Inputs + * Configure HRTIM Captures * - * Input Parameters: - * priv - A reference to the HRTIM structure + * Input parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * capture - capture trigers configuration * * Returned Value: - * 0 on success, a negated errno value on failure + * None * ****************************************************************************/ -#if defined(CONFIG_STM32_HRTIM_CAPTURE) -static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv) +static int hrtim_tim_capture_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t index, uint32_t capture) { -#warning "hrtim_inputs_config: missing logic" + int ret = OK; + uint32_t offset = 0; - /* source */ + if (timer == HRTIM_TIMER_MASTER) + { + ret = -EINVAL; + goto errout; + } - /* polarity */ + switch (index) + { + case HRTIM_CAPTURE1: + { + offset = STM32_HRTIM_TIM_CPT1CR_OFFSET; + break; + } - /* edge-sensitivity */ + case HRTIM_CAPTURE2: + { + offset = STM32_HRTIM_TIM_CPT2CR_OFFSET; + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + hrtim_tim_putreg(priv, timer, offset, capture); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_capture_config + * + * Description: + * Configure HRTIM Captures + * + * Input parameters: + * priv - A reference to the HRTIM block + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int hrtim_capture_config(FAR struct stm32_hrtim_s *priv) +{ + FAR struct stm32_hrtim_slave_priv_s* slave; + +#ifdef CONFIG_STM32_HRTIM_TIMA_CAP + slave = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMA, HRTIM_CAPTURE1, slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMA, HRTIM_CAPTURE2, slave->cap.cap2); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_CAP + slave = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMB, HRTIM_CAPTURE1, slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMB, HRTIM_CAPTURE2, slave->cap.cap2); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC_CAP + slave = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMC, HRTIM_CAPTURE1, slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMC, HRTIM_CAPTURE2, slave->cap.cap2); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD_CAP + slave = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMD, HRTIM_CAPTURE1, slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIMD, HRTIM_CAPTURE2, slave->cap.cap2); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME_CAP + slave = (struct stm32_hrtim_slave_priv_s*)priv->time->priv; + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIME, HRTIM_CAPTURE1, slave->cap.cap1); + hrtim_tim_capture_cfg(priv, HRTIM_TIMER_TIME, HRTIM_CAPTURE2, slave->cap.cap2); +#endif return OK; } + +/**************************************************************************** + * Name: hrtim_capture_get + * + * Description: + * Get HRTIM Timer Capture register + * + * Input parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * index - Capture register index + * + * Returned Value: + * None + * + ****************************************************************************/ + +static uint16_t hrtim_capture_get(FAR struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + uint32_t regval = 0; + uint32_t offset = 0; + + switch (index) + { + case HRTIM_CAPTURE1: + { + offset = STM32_HRTIM_TIM_CPT1CR_OFFSET; + break; + } + + case HRTIM_CAPTURE2: + { + offset = STM32_HRTIM_TIM_CPT2CR_OFFSET; + break; + } + + default: + { + regval = 0; + goto errout; + } + } + + regval = (uint16_t)hrtim_tim_getreg(priv, timer, offset); + +errout: + return regval; +} #endif /**************************************************************************** @@ -2414,22 +2801,22 @@ static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs, bool state) { FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; - uint32_t reg = 0; + uint32_t offset = 0; /* Get register offset */ if (state == true) { - reg = STM32_HRTIM_CMN_OENR_OFFSET; + offset = STM32_HRTIM_CMN_OENR_OFFSET; } else { - reg = STM32_HRTIM_CMN_ODISR_OFFSET; + offset = STM32_HRTIM_CMN_ODISR_OFFSET; } /* Write register */ - hrtim_cmn_putreg(priv, reg, outputs); + hrtim_cmn_putreg(priv, offset, outputs); return OK; } @@ -2452,16 +2839,26 @@ static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs, #ifdef CONFIG_STM32_HRTIM_ADC static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv) { + /* Configure ADC Trigger 1 */ #ifdef CONFIG_STM32_HRTIM_ADC_TRG1 hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET, priv->adc->trg1); #endif + + /* Configure ADC Trigger 2 */ + #ifdef CONFIG_STM32_HRTIM_ADC_TRG2 hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET, priv->adc->trg2); #endif + + /* Configure ADC Trigger 3 */ + #ifdef CONFIG_STM32_HRTIM_ADC_TRG3 hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET, priv->adc->trg3); #endif + + /* Configure ADC Trigger 4 */ + #ifdef CONFIG_STM32_HRTIM_ADC_TRG4 hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET, priv->adc->trg4); #endif @@ -2509,7 +2906,7 @@ static int hrtim_tim_dac_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer, * Name: hrtim_dac_config * * Description: - * Configure HRTIM DAC triggers + * Configure HRTIM DAC synchronization * * Input Parameters: * priv - A reference to the HRTIM structure @@ -2523,31 +2920,43 @@ static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv) { FAR struct stm32_hrtim_timcmn_s *tim; + /* Configure DAC synchronization for Master Timer */ + #ifdef CONFIG_STM32_HRTIM_MASTER_DAC tim = (struct stm32_hrtim_timcmn_s*)priv->master; hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, tim->dac); #endif + /* Configure DAC synchronization for Timer A */ + #ifdef CONFIG_STM32_HRTIM_TIMA_DAC tim = (struct stm32_hrtim_timcmn_s*)priv->tima; hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, tim->dac); #endif + /* Configure DAC synchronization for Timer B */ + #ifdef CONFIG_STM32_HRTIM_TIMB_DAC tim = (struct stm32_hrtim_timcmn_s*)priv->timb; hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMB, tim->dac); #endif + /* Configure DAC synchronization for Timer C */ + #ifdef CONFIG_STM32_HRTIM_TIMC_DAC tim = (struct stm32_hrtim_timcmn_s*)priv->timc; hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMC, tim->dac); #endif + /* Configure DAC synchronization for Timer D */ + #ifdef CONFIG_STM32_HRTIM_TIMD_DAC tim = (struct stm32_hrtim_timcmn_s*)priv->timd; hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMD, tim->dac); #endif + /* Configure DAC synchronization for Timer E */ + #ifdef CONFIG_STM32_HRTIM_TIME_DAC tim = (struct stm32_hrtim_timcmn_s*)priv->time; hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIME, tim->dac); @@ -2638,16 +3047,340 @@ static int hrtim_dma_cfg(FAR struct stm32_hrtim_s *priv) #ifdef CONFIG_STM32_HRTIM_DEADTIME +/**************************************************************************** + * Name: hrtim_deadtime_update + ****************************************************************************/ + +static int hrtim_deadtime_update(FAR struct stm32_dev_s *dev, uint8_t timer, + uint8_t dt, uint16_t value) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + int ret = OK; + uint32_t regval = 0; + uint32_t shift = 0; + uint32_t mask = 0; + + /* Sanity check */ + + if (value > 0x1FF) + { + ret = -EINVAL; + goto errout; + } + + /* Get shift value */ + + switch (index) + { + case HRTIM_DT_EDGE_RISING: + { + shift = HRTIM_TIMDT_DTR_SHIFT; + mask = HRTIM_TIMDT_DTR_MASK; + break; + } + + case HRTIM_DT_EDGE_FALLING: + { + shift = HRTIM_TIMDT_DTF_SHIFT; + mask = HRTIM_TIMDT_DTF_MASK; + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + regval = value << shift; + + /* Update register */ + + hrtim_tim_modify(priv, timer, STM32_HRTIM_TIM_DTR_OFFSET, mask, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_deadtime_get + ****************************************************************************/ + +static uint16_t hrtim_deadtime_get(FAR struct stm32_dev_s *dev, uint8_t dt) +{ +#warinig missing logic +} + +/**************************************************************************** + * Name: hrtim_tim_deadtime_cfg + ****************************************************************************/ + +static int hrtim_tim_deadtime_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) +{ + FAR struct stm32_hrtim_slave_priv_s* slave; + uint32_t regval = 0; + int ret = OK; + + if (timer == HRTIM_TIMER_MASTER) + { + ret = -EINVAL; + goto errout; + } + + slave = (struct stm32_hrtim_slave_priv_s*)tim->priv; + + /* Configure rising deadtime */ + + regval |= slave->pwm.dt.rising << HRTIM_TIMDT_DTR_SHIFT; + + /* Configure falling deadtime */ + + regval |= slave->pwm.dt.falling << HRTIM_TIMDT_DTF_SHIFT; + + /* Configure falling deadtime sign */ + + if(slave->pwm.dt.fsign == HRTIM_DT_SIGN_POSITIVE) + { + regval |= HRTIM_TIMDT_SDTF; + } + + /* Configure risign deadtime sign */ + + if(slave->pwm.dt.rsign == HRTIM_DT_SIGN_POSITIVE) + { + regval |= HRTIM_TIMDT_SDTR; + } + + /* Configure falling sing lock */ + + if(slave->pwm.dt.fsign_lock == HRTIM_DT_LOCK) + { + regval |= HRTIM_TIMDT_DTFSLK; + } + + /* Configure rising sing lock */ + + if(slave->pwm.dt.rsign_lock == HRTIM_DT_LOCK) + { + regval |= HRTIM_TIMDT_DTRSLK; + } + + /* Configure rising value lock */ + + if(slave->pwm.dt.rising_lock == HRTIM_DT_LOCK) + { + regval |= HRTIM_TIMDT_DTRLK; + } + + /* Configure falling value lock */ + + if(slave->pwm.dt.falling_lock == HRTIM_DT_LOCK) + { + regval |= HRTIM_TIMDT_DTFLK; + } + +errout: + return ret; +} + /**************************************************************************** * Name: hrtim_deadtime_config ****************************************************************************/ static int hrtim_deadtime_config(FAR struct stm32_hrtim_s *priv) { + /* Configure Timer A deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIMA + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMA); +#endif + + /* Configure Timer B deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIMB + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMB); +#endif + + /* Configure Timer C deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIMC + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMC); +#endif + + /* Configure Timer D deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIMD + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIMD); +#endif + + /* Configure Timer E deadtime */ + +#ifdef CONFIG_STM32_HRTIM_TIME + hrtim_tim_deadtime_cfg(priv, HRTIM_TIMER_TIME); +#endif + + return OK; +} +#endif /* CONFIG_STM32_HRTIM_DEADTIME */ + +#ifdef CONFIG_STM32_HRTIM_CHOPPER + +/**************************************************************************** + * Name: hrtim_chopper_enable + * + * Description: + * Enable/disable HRTIM outputs (bulk operation) + * + * Input Parameters: + * dev - HRTIM device structure + * timer - An HRTIM Timer index + * chan - Output channel + * state - Enable/disable operation + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_chopper_enable(FAR struct stm32_dev_s *dev, uint8_t timer, + uint8_t chan, bool state) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + uint32_t val = 0; + int ret = OK; + + /* Get bit to change */ + + switch (chan) + { + case HRTIM_OUT_CH1: + { + val = HRTIM_TIMOUT_CHP1; + break; + } + + case HRTIM_OUT_CH2: + { + val = HRTIM_TIMOUT_CHP2; + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + /* Update register */ + + if (state == true) + { + /* Set enable bit */ + + hrtim_tim_modifyreg(priv, index, STM32_HRTIM_TIM_OUTR_OFFSET, 0, val); + } + else + { + /* Clear enable bit */ + + hrtim_tim_modifyreg(priv, index, STM32_HRTIM_TIM_OUTR_OFFSET, val, 0); + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_chopper_cfg + ****************************************************************************/ + +static int hrtim_tim_chopper_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer) +{ + FAR struct stm32_hrtim_tim_s* tim; + FAR struct stm32_hrtim_slave_priv_s* slave; + + int ret = OK; + uint32_t regval = 0; + + /* Master Timer has no outputs */ + + if (timer == HRTIM_TIMER_MASTER) + { + ret = -EINVAL; + goto errout; + } + + /* Get Timer data strucutre */ + + tim = hrtim_tim_get(priv, timer); + if (tim == NULL) + { + ret = -EINVAL; + goto errout; + } + + slave = (struct stm32_hrtim_slave_priv_s*)tim->priv; + + /* Configure start pulsewidth */ + + regval |= slave->pwm.chp.start_pulse << HRTIM_TIMCHP_STRTPW_SHIFT; + + /* Configure chopper duty cycle */ + + regval |= slave->pwm.chp.duty << HRTIM_TIMCHP_CARDTY_SHIFT; + + /* Configure carrier frequency */ + + regval |= slave->pwm.chp.freq << HRTIM_TIMCHP_CARFRQ_SHIFT; + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CHPR_OFFSET, regval); + return OK; } -#endif /* CONFIG_STM32_HRTIM_DEADTIME */ +/**************************************************************************** + * Name: hrtim_chopper_config + ****************************************************************************/ + +static int hrtim_chopper_config(FAR struct stm32_hrtim_s *priv) +{ + /* Configure chopper for Timer A */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMA); +#endif + + /* Configure chopper for Timer B */ + +#ifdef CONFIG_STM32_HRTIM_TIMB_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMB); +#endif + + /* Configure chopper for Timer C */ + +#ifdef CONFIG_STM32_HRTIM_TIMC_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMC); +#endif + + /* Configure chopper for Timer D */ + +#ifdef CONFIG_STM32_HRTIM_TIMD_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIMD); +#endif + + /* Configure chopper for Timer E */ + +#ifdef CONFIG_STM32_HRTIM_TIME_CHOP + hrtim_tim_chopper_cfg(priv, HRTIM_TIMER_TIME); +#endif + + return OK; +} +#endif #ifdef CONFIG_STM32_HRTIM_BURST @@ -2661,15 +3394,19 @@ static int hrtim_burst_enable(FAR struct hrtim_dev_s *dev, bool state) if (state) { + /* Enable Burst mode */ + + hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, 0, HRTIM_BMCR_BME); + /* Software start */ hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET, 0, HRTIM_BMTRGR_SW); } else { - /* Software termination */ + /* Disable Burst mode */ - hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, HRTIM_BMCR_BMSTAT, 0); + hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, HRTIM_BMCR_BME, 0); } return OK; @@ -2723,6 +3460,67 @@ static uint16_t hrtim_burst_per_get(FAR struct hrtim_dev_s *dev) return (uint16_t)hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET); } +/**************************************************************************** + * Name: hrtim_burst_pre_update + ****************************************************************************/ + +static int hrtim_burst_pre_update(FAR struct hrtim_dev_s *dev, uint8_t pre) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + int ret = OK; + uint32_t regval = 0; + + /* Sanity checking */ + + if (priv->burst->clk != HRTIM_BURST_CLOCK_HRTIM) + { + ret = -EPERM; + goto errout; + } + + if (pre > HRTIM_BURST_PRESCALER_32768) + { + ret = -EINVAL; + goto errout; + } + + /* Make sure that Burst mode is disabled */ + + hrtim_burst_enable(dev, false); + + /* Change prescaler */ + + priv->burst->presc = pre; + regval = pre << HRTIM_BMCR_BMPRSC_SHIFT; + + hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, 0, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_burst_pre_get + ****************************************************************************/ + +static int hrtim_burst_pre_get(FAR struct hrtim_dev_s *dev) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + int ret = OK; + + if (priv->burst->clk != HRTIM_BURST_CLOCK_HRTIM) + { + ret = -EPERM; + goto errout; + } + + ret = priv->burst->presc; + +errout: + return ret; +} + + /**************************************************************************** * Name: hrtim_burst_config ****************************************************************************/ @@ -2759,10 +3557,6 @@ static int hrtim_burst_config(FAR struct stm32_hrtim_s *priv) regval |= HRTIM_BMCR_BMOM; - /* Enable burst mode */ - - regval |= HRTIM_BMCR_BME; - /* Write Burst Mode CR */ hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, regval); @@ -2791,20 +3585,20 @@ static int hrtim_burst_config(FAR struct stm32_hrtim_s *priv) static int hrtim_tim_faults_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer) { FAR struct stm32_hrtim_tim_s *tim; - FAR struct stm32_hrtim_slave_priv_s *slave_priv; + FAR struct stm32_hrtim_slave_priv_s *slave; uint32_t regval = 0; tim = hrtim_tim_get(priv, timer); - slave_priv = tim->priv; + slave = tim->priv; /* Get lock configuration */ - regval = ((slave_priv->flt & HRTIM_TIM_FAULT_LOCK) ? HRTIM_TIMFLT_FLTLCK : 0); + regval = ((slave->flt & HRTIM_TIM_FAULT_LOCK) ? HRTIM_TIMFLT_FLTLCK : 0); /* Get sources configuration */ - regval |= slave_priv->flt & 0x1f; + regval |= slave->flt & 0x1f; /* Write register */ @@ -3617,31 +4411,31 @@ errout: static int hrtim_reset_config(FAR struct stm32_hrtim_s *priv) { - FAR struct stm32_hrtim_slave_priv_s *slave_priv; + FAR struct stm32_hrtim_slave_priv_s *slave; #ifdef CONFIG_STM32_HRTIM_TIMA - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMA, slave_priv->reset); + slave = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMA, slave->reset); #endif #ifdef CONFIG_STM32_HRTIM_TIMB - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMB, slave_priv->reset); + slave = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMB, slave->reset); #endif #ifdef CONFIG_STM32_HRTIM_TIMC - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMC, slave_priv->reset); + slave = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMC, slave->reset); #endif #ifdef CONFIG_STM32_HRTIM_TIMD - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMD, slave_priv->reset); + slave = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIMD, slave->reset); #endif #ifdef CONFIG_STM32_HRTIM_TIME - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->time->priv; - hrtim_tim_reset_set(priv, HRTIM_TIMER_TIME, slave_priv->reset); + slave = (struct stm32_hrtim_slave_priv_s*)priv->time->priv; + hrtim_tim_reset_set(priv, HRTIM_TIMER_TIME, slave->reset); #endif return OK; @@ -3667,31 +4461,31 @@ static int hrtim_tim_update_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, static int hrtim_update_config(FAR struct stm32_hrtim_s *priv) { - FAR struct stm32_hrtim_slave_priv_s *slave_priv; + FAR struct stm32_hrtim_slave_priv_s *slave; #ifdef CONFIG_STM32_HRTIM_TIMA - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIMA, slave_priv->update); + slave = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMA, slave->update); #endif #ifdef CONFIG_STM32_HRTIM_TIMB - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIMB, slave_priv->update); + slave = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMB, slave->update); #endif #ifdef CONFIG_STM32_HRTIM_TIMC - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIMC, slave_priv->update); + slave = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMC, slave->update); #endif #ifdef CONFIG_STM32_HRTIM_TIMD - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIMD, slave_priv->update); + slave = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIMD, slave->update); #endif #ifdef CONFIG_STM32_HRTIM_TIME - slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->time->priv; - hrtim_tim_update_set(priv, HRTIM_TIMER_TIME, slave_priv->update); + slave = (struct stm32_hrtim_slave_priv_s*)priv->time->priv; + hrtim_tim_update_set(priv, HRTIM_TIMER_TIME, slave->update); #endif return OK; @@ -3754,8 +4548,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) /* Configure HRTIM GPIOs */ -#if defined(CONFIG_STM32_HRTIM_CAPTURE) || defined(CONFIG_STM32_HRTIM_PWM) || \ - defined(CONFIG_STM32_HRTIM_SYNC) +#if defined(CONFIG_STM32_HRTIM_PWM) || defined(CONFIG_STM32_HRTIM_SYNC) ret = hrtim_gpios_config(priv); if (ret != OK) { @@ -3764,13 +4557,13 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) } #endif - /* Configure HRTIM inputs */ + /* Configure HRTIM capture */ #if defined(CONFIG_STM32_HRTIM_CAPTURE) - ret = hrtim_inputs_config(priv); + ret = hrtim_capture_config(priv); if (ret != OK) { - tmrerr("ERROR: HRTIM inputs configuration failed!\n"); + tmrerr("ERROR: HRTIM capture configuration failed!\n"); goto errout; } #endif @@ -3906,6 +4699,44 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) hrtim_tim_modifyreg(priv, HRTIM_TIMER_MASTER, STM32_HRTIM_TIM_CR_OFFSET, 0, regval); + /* Dump registers for Master */ + + hrtim_dumpregs(priv, HRTIM_TIMER_MASTER, "Master after configuration"); + + /* Dump registers for Timer A */ + +#ifdef CONFIG_STM32_HRTIM_TIMA + hrtim_dumpregs(priv, HRTIM_TIMER_TIMA, "Timer A after configuration"); +#endif + + /* Dump registers for Timer B */ + +#ifdef CONFIG_STM32_HRTIM_TIMB + hrtim_dumpregs(priv, HRTIM_TIMER_TIMB, "Timer B after configuration"); +#endif + + /* Dump registers for Timer C */ + +#ifdef CONFIG_STM32_HRTIM_TIMC + hrtim_dumpregs(priv, HRTIM_TIMER_TIMC, "Timer C after configuration"); +#endif + + /* Dump registers for Timer D */ + +#ifdef CONFIG_STM32_HRTIM_TIMD + hrtim_dumpregs(priv, HRTIM_TIMER_TIMD, "Timer D after configuration"); +#endif + + /* Dump registers for Timer E */ + +#ifdef CONFIG_STM32_HRTIM_TIME + hrtim_dumpregs(priv, HRTIM_TIMER_TIME, "Timer E after configuration"); +#endif + + /* Dump common registers */ + + hrtim_dumpregs(priv, HRTIM_TIMER_COMMON, "Common after configuration"); + errout: return ret; } diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index 5c5e2e42917..0b192377e4d 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -42,6 +42,8 @@ #include +#include + #include "chip.h" #ifdef CONFIG_STM32_HRTIM1 @@ -127,8 +129,8 @@ #endif #if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ - defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ defined(CONFIG_STM32_HRTIM_CMN_IRQ) # ifndef CONFIG_STM32_HRTIM_INTERRUPTS # error "CONFIG_STM32_HRTIM_INTERRUPTS must be set" @@ -170,11 +172,34 @@ #endif #ifdef CONFIG_STM32_HRTIM_TIME_PWM # if !defined(CONFIG_STM32_HRTIM_TIME_PWM_CH1) && \ - !defined(CONFIG_STM32_HRTIM_TIME_PWM_CH2) + !defined(CONFIG_STM32_HRTIM_TIME_PWM_CH2) # error "HRTIM TIME PWM set but no channel selected" # endif #endif +/* HRTIM clock source configuration */ + +#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL +# if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL +# if (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLK) && \ + (STM32_RCC_CFGR_PPRE2 != RCC_CFGR_PPRE2_HCLKd2) +# error "APB2 prescaler factor can not be greater than 2" +# else +# define HRTIM_HAVE_CLK_FROM_PLL 1 +# define HRTIM_CLOCK 2*STM32_PLL_FREQUENCY +# endif +# else +# error "Clock system must be set to PLL" +# endif +#else +# error "Not supported yet: system freezes when no PLL selected." +# define HRTIM_HAVE_CLK_FROM_APB2 1 +# if STM32_RCC_CFGR_PPRE2 == RCC_CFGR_PPRE2_HCLK +# define HRTIM_CLOCK STM32_PCLK2_FREQUENCY +# else +# define HRTIM_CLOCK 2*STM32_PCLK2_FREQUENCY +# endif +#endif /************************************************************************************ * Public Types @@ -498,7 +523,15 @@ enum stm32_hrtim_cmp_index_e HRTIM_CMP4 }; -/* HRTIM Slave Timer Outputs */ +/* HRTIM Slave Timer Outputs index */ + +enum stm32_output_s +{ + HRTIM_OUT_CH1 = (1 << 0), + HRTIM_OUT_CH2 = (1 << 1) +}; + +/* HRTIM Slave Timers Outputs */ enum stm32_outputs_e { @@ -514,20 +547,42 @@ enum stm32_outputs_e HRTIM_OUT_TIME_CH2 = (1 << 9) }; -/* HRTIM Deadtime Locks */ +/* HRTIM Deadtime sign */ -enum stm32_hrtim_deadtime_lock_e +enum stm32_hrtim_deadtime_sign_e { - HRTIM_DT_VALUE_LOCK = (1 << 0), /* Lock Deadtime value */ - HRTIM_DT_SIGN_LOCK = (1 << 1) /* Lock Deadtime sign */ + HRTIM_DT_SIGN_POSITIVE = 0, + HRTIM_DT_DIGN_NEGATIVE = 1 }; /* HRTIM Deadtime types */ enum stm32_hrtim_deadtime_edge_e { - HRTIM_DT_RISING = 0, - HRTIM_DT_FALLING = 1 + HRTIM_DT_EDGE_RISING = 0, + HRTIM_DT_EDGE_FALLING = 1 +}; + +/* HRTIM Deadtime lock */ + +enum stm32_hrtim_deadtime_lock_e +{ + HRTIM_DT_RW = 0, + HRTIM_DT_LOCK = 1 +}; + +/* HRTIM Deadtime prescaler */ + +enum stm32_hrtim_deadtime_prescaler_e +{ + HRTIM_DEADTIME_PRESCALER_1 = 0, + HRTIM_DEADTIME_PRESCALER_2 = 1, + HRTIM_DEADTIME_PRESCALER_4 = 2, + HRTIM_DEADTIME_PRESCALER_8 = 3, + HRTIM_DEADTIME_PRESCALER_16 = 4, + HRTIM_DEADTIME_PRESCALER_32 = 5, + HRTIM_DEADTIME_PRESCALER_64 = 6, + HRTIM_DEADTIME_PRESCALER_128 = 7 }; /* Chopper start pulsewidth */ @@ -837,30 +892,89 @@ enum stm32_hrtim_burst_triggers_e HRTIM_BURST_TRG_OCHPEV = (1 << 31), }; +/* HRTIM Capture triggers */ +enum stm32_hrtim_capture_index_e +{ + HRTIM_CAPTURE1 = 0, + HRTIM_CAPTURE2 = 1 +}; + +/* HRTIM Capture triggers */ + +enum stm32_hrtim_capture_triggers_e +{ + HRTIM_CAPTURE_TRG_SW = (1 << 0), + HRTIM_CAPTURE_TRG_UPD = (1 << 1), + HRTIM_CAPTURE_TRG_EXEV1 = (1 << 2), + HRTIM_CAPTURE_TRG_EXEV2 = (1 << 3), + HRTIM_CAPTURE_TRG_EXEV3 = (1 << 4), + HRTIM_CAPTURE_TRG_EXEV4 = (1 << 5), + HRTIM_CAPTURE_TRG_EXEV5 = (1 << 6), + HRTIM_CAPTURE_TRG_EXEV6 = (1 << 7), + HRTIM_CAPTURE_TRG_EXEV7 = (1 << 8), + HRTIM_CAPTURE_TRG_EXEV8 = (1 << 9), + HRTIM_CAPTURE_TRG_EXEV9 = (1 << 10), + HRTIM_CAPTURE_TRG_EXEV10 = (1 << 11), + HRTIM_CAPTURE_TRG_TA1SET = (1 << 12), + HRTIM_CAPTURE_TRG_TA1RST = (1 << 13), + HRTIM_CAPTURE_TRG_TACMP1 = (1 << 14), + HRTIM_CAPTURE_TRG_TACMP2 = (1 << 15), + HRTIM_CAPTURE_TRG_TB1SET = (1 << 16), + HRTIM_CAPTURE_TRG_TB1RST = (1 << 17), + HRTIM_CAPTURE_TRG_TBCMP1 = (1 << 18), + HRTIM_CAPTURE_TRG_TBCMP2 = (1 << 19), + HRTIM_CAPTURE_TRG_TC1SET = (1 << 20), + HRTIM_CAPTURE_TRG_TC1RST = (1 << 21), + HRTIM_CAPTURE_TRG_TCCMP1 = (1 << 22), + HRTIM_CAPTURE_TRG_TCCMP2 = (1 << 23), + HRTIM_CAPTURE_TRG_TD1SET = (1 << 24), + HRTIM_CAPTURE_TRG_TD1RST = (1 << 25), + HRTIM_CAPTURE_TRG_TDCMP1 = (1 << 26), + HRTIM_CAPTURE_TRG_TDCMP2 = (1 << 27), + HRTIM_CAPTURE_TRG_TE1SET = (1 << 28), + HRTIM_CAPTURE_TRG_TE1RST = (1 << 29), + HRTIM_CAPTURE_TRG_TECMP1 = (1 << 30), + HRTIM_CAPTURE_TRG_TECMP2 = (1 << 31), +}; + /* HRTIM vtable */ struct hrtim_dev_s; struct stm32_hrtim_ops_s { - int (*cmp_update)(FAR struct hrtim_dev_s *dev, uint8_t timer, - uint8_t index, uint16_t cmp); - int (*per_update)(FAR struct hrtim_dev_s *dev, uint8_t timer, uint16_t per); + int (*cmp_update)(FAR struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index, uint16_t cmp); + int (*per_update)(FAR struct hrtim_dev_s *dev, uint8_t timer, uint16_t per); uint16_t (*per_get)(FAR struct hrtim_dev_s *dev, uint8_t timer); uint16_t (*cmp_get)(FAR struct hrtim_dev_s *dev, uint8_t timer, uint8_t index); #ifdef CONFIG_STM32_HRTIM_INTERRUPTS - void (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); + void (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); #endif #ifdef CONFIG_STM32_HRTIM_PWM - int (*outputs_enable)(FAR struct hrtim_dev_s *dev, uint16_t outputs, - bool state); + int (*outputs_enable)(FAR struct hrtim_dev_s *dev, uint16_t outputs, + bool state); #endif #ifdef CONFIG_STM32_HRTIM_BURST - int (*burst_enable)(FAR struct hrtim_dev_s *dev, bool state); - int (*burst_cmp_set)(FAR struct hrtim_dev_s *dev, uint16_t cmp); - int (*burst_per_set)(FAR struct hrtim_dev_s *dev, uint16_t per); + int (*burst_enable)(FAR struct hrtim_dev_s *dev, bool state); + int (*burst_cmp_set)(FAR struct hrtim_dev_s *dev, uint16_t cmp); + int (*burst_per_set)(FAR struct hrtim_dev_s *dev, uint16_t per); + int (*burst_pre_set)(FAR struct hrtim_dev_s *dev, uint8_t pre); uint16_t (*burst_cmp_get)(FAR struct hrtim_dev_s *dev); uint16_t (*burst_per_get)(FAR struct hrtim_dev_s *dev); + int (*burst_pre_get)(FAR struct hrtim_dev_s *dev); +#endif +#ifdef CONFIG_STM32_HRTIM_CHOPPER + int (*chopper_enable)(FAR struct hrtim_dev_s *dev, uint8_t timer, + uint8_t chan, bool state); +#endif +#ifdef CONFIG_STM32_HRTIM_DEADTIME + int (*deadtime_update)(FAR struct hrtim_dev_s *dev, uint8_t dt, uint16_t value); + uint16_t (*deadtime_get)(FAR struct hrtim_dev_s *dev, uint8_t dt); +#endif +#ifdef CONFIG_STM32_HRTIM_CAPTURE + uint16_t (*capture_get)(FAR struct hrtim_dev_s *dev, uint8_t timer, + uint8_t index); #endif };