mirror of
https://github.com/apache/nuttx.git
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support for SAMA5D27 SDMMC peripheral
- MMC and SD Card driver
- ported from imxrt_usdhc.c
Squashed commit of the following:
commit 46cbe18ad6a6e41ec2727d839f86f5670577878a
Author: Adam Feuer <adam@starcat.io>
Date: Wed Jul 15 10:28:02 2020 -0700
nxstyle change - Public Function Prototypes
- instead of Public Functions
commit 486b7b62e83a78ae15b114e34846900d8fef8248
Author: Adam Feuer <adam@starcat.io>
Date: Wed Jul 15 10:06:51 2020 -0700
nxstyle changes
commit 28280d585a40aac99fd0e538295828ea013739b7
Author: Adam Feuer <adam@starcat.io>
Date: Wed Jul 15 10:06:29 2020 -0700
removing unused enum value
commit 7da6ba437e7e023d348e63c497732fea985a2d1b
Author: Adam Feuer <adam@starcat.io>
Date: Tue Jul 14 21:17:49 2020 -0700
CI build error fixes
- unused vars
- incorrect method calls
commit 145a73449b9d1eaed8a6cbf47cb53fb5b7a551f6
Author: Adam Feuer <adam@starcat.io>
Date: Tue Jul 14 17:29:56 2020 -0700
adding #defines to prevent unused var warning
commit 47ed2c08235816caded26a019cf33899daed1621
Author: Adam Feuer <adam@starcat.io>
Date: Tue Jul 14 16:29:07 2020 -0700
removing obsolete config values
commit b43f129c03a8bb8dc57ae6984d124ce9e9306196
Author: Adam Feuer <adam@starcat.io>
Date: Tue Jul 14 09:58:42 2020 -0700
removed obsolete config setting
commit 23e3af846ac24cac928442c7af86c5d0ef183ad3
Merge: 8b47330fe5 6f6d61eec4
Author: Adam Feuer <adam@starcat.io>
Date: Tue Jul 14 09:53:12 2020 -0700
Merge remote-tracking branch 'upstream/master' into feature/sama5d27-sdmmc-support
commit 8b47330fe5bb49bbd1991f2f3e2c69bdfb833d2c
Author: Adam Feuer <adam@starcat.io>
Date: Tue Jul 14 09:51:56 2020 -0700
replaced license headers with Apache License 2.0
commit 865e69b9a84d077ab9e05c2056dc7a515222c6c7
Author: Adam Feuer <adam@starcat.io>
Date: Thu Jul 9 18:38:01 2020 -0700
SAMA5D2x SDMMC peripheral support (SD Card driver)
- reading and writing at 25 MHz and 50Mhz
- UHS_SDR50, UHS_DDR50, and UHS_SDR104 are supported
- ported from imxrt_usdhc.c
- only tested on SAMA5D27
Squashed commit of the following:
commit e3122baef2feaeb32bb00798ae56310b2cc5c448
Author: Adam Feuer <adam@starcat.io>
Date: Thu Jul 9 18:30:03 2020 -0700
added sdmmcnsh defconfig and basic docs
commit 12a290d7465a0a006473ba67893bf891a7bcea83
Author: Adam Feuer <adam@starcat.io>
Date: Thu Jul 9 17:50:06 2020 -0700
nxstyle changes
commit 33409c0f63c328dc200150ba883327cadf0300b2
Author: Adam Feuer <adam@starcat.io>
Date: Thu Jul 9 16:15:00 2020 -0700
add short delay to in recvshortcrc
- to allow SDMMC to respond
commit 3be7a7fb6f79900042d1fdbef72810f364ac5f62
Author: Adam Feuer <adam@adamfeuer.com>
Date: Thu Jul 9 10:54:59 2020 -0700
added SDR50 and SDR104 SDMMC bus modes
commit 2888408866548ca53e582ea1525178a7733617b4
Author: Adam Feuer <adam@adamfeuer.com>
Date: Thu Jul 9 10:54:25 2020 -0700
comment formatting cleanup
commit 06cf2c39193971155eaa6f9c89a39a88b53964a8
Author: Adam Feuer <adam@adamfeuer.com>
Date: Thu Jul 9 10:34:01 2020 -0700
removed unneeded comment
commit ac89b69231bdf19563754865fda93d4bbbb4488d
Author: Adam Feuer <adam@adamfeuer.com>
Date: Thu Jul 9 10:30:23 2020 -0700
code cleanup
- removing custinfo() logging
- remove duplicate #defines
- move var declarations to the beginning of methods
commit bcd4abec7935ee9023ab72edfb02685dbeee243c
Author: Adam Feuer <adam@adamfeuer.com>
Date: Wed Jul 8 16:34:31 2020 -0700
handle SDMA Boundary Pause interrupt (DMAINT)
- SDMMC_INT_DINT
- add to waitints
- add handler to sam_interrupt
commit e9da026c1270e999df520ee2c60487195799f58c
Author: Adam Feuer <adam@adamfeuer.com>
Date: Tue Jul 7 16:07:34 2020 -0700
Kconfig setting for SDMMC bus speed
- 25 and 50 MHz
- 50 MHz is the default
commit 9edc636b7f18f981d653f85970c3af0b80801778
Author: Adam Feuer <adam@adamfeuer.com>
Date: Mon Jul 6 21:55:51 2020 -0700
added HSEN bit change for high speed mode
- above 26 MHz
commit b8e91c95b0f7b2f8220f02b1eb42b6134e0660d0
Author: Adam Feuer <adam@adamfeuer.com>
Date: Mon Jul 6 21:28:03 2020 -0700
added calloc to fix bug
- not sure why this works.
commit 1ceaf2f8487fe39d4d6fb21adecd57e4c4992e07
Author: Adam Feuer <adam@adamfeuer.com>
Date: Mon Jul 6 21:25:47 2020 -0700
removing spurious typo characters
commit 14ba51743bcca35686b07a76f5af17bcce078a5f
Author: Adam Feuer <adam@adamfeuer.com>
Date: Sat Jul 4 18:10:46 2020 -0700
nxstyle changes
commit d8af26df47b7840117de0d3a44ec548b3a72bc2b
Author: Adam Feuer <adam@adamfeuer.com>
Date: Sat Jul 4 17:01:11 2020 -0700
nxstyle changes
commit 0ae532bd62d02c5ac36aa2192f31fa1f7f1cde99
Author: Adam Feuer <adam@adamfeuer.com>
Date: Sat Jul 4 16:37:17 2020 -0700
remove long lines in comments - nxstyle
commit 3d025a84f8e9ddb7f7a4570504118d782dd5574c
Author: Adam Feuer <adam@adamfeuer.com>
Date: Sat Jul 4 16:36:52 2020 -0700
removed custinfo logging
commit 366b5d9d241a42d693583679cb49aa7bf25615aa
Author: Adam Feuer <adam@adamfeuer.com>
Date: Sat Jul 4 16:35:08 2020 -0700
removed custinfo logging
commit c74396e4a4943873c7de5b6ffee193787c39baef
Author: Adam Feuer <adam@adamfeuer.com>
Date: Sat Jul 4 16:34:36 2020 -0700
fixed typo
commit 7f51e99d7f4c1e5e0bf71a84fd0b2467157fea59
Merge: c40f8c1039 2481b1bfd5
Author: Adam Feuer <adam@adamfeuer.com>
Date: Sat Jul 4 15:33:06 2020 -0700
Merge remote-tracking branch 'upstream/master' into feature/sama5d27-sdmmc-support
commit c40f8c10390ecefeb3a113046edd6740b07ab31b
Author: Adam Feuer <adam@adamfeuer.com>
Date: Thu Jul 2 22:08:20 2020 -0700
SDMMC support for SAMA5D27
This commit is contained in:
Adam Feuer
Abdelatif Guettouche
parent
954ee9d5f3
commit
65a866fbe2
23 changed files with 5962 additions and 207 deletions
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@ -121,6 +121,10 @@ config SAMA5_HAVE_EMAC1
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bool
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default n
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config SAMA5_HAVE_SDMMC
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bool
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default n
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config SAMA5_HAVE_HSMCI2
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bool
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default n
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@ -285,6 +289,8 @@ config ARCH_CHIP_ATSAMA5D27
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select SAMA5_HAVE_CAN0
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select SAMA5_HAVE_CAN1
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select SAMA5_HAVE_DDR32
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select SAMA5_HAVE_SDMMC
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select SAMA5_HAVE_GMAC
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config ARCH_CHIP_ATSAMA5D28
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bool "Atmel ATSAMA5D28"
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@ -545,6 +551,12 @@ config SAMA5_TWI3
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default n
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depends on SAMA5_HAVE_TWI3
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config SAMA5_SDMMC
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bool "Secure Digital Multimedia Card Interface (SDMMC)"
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default n
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depends on SAMA5_HAVE_SDMMC
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select ARCH_HAVE_SDIO
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config SAMA5_HSMCI0
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bool "High Speed Multimedia Card Interface 0 (HSMCI0)"
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default n
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@ -5056,4 +5068,32 @@ config SAMA5_EBICS3_HEAP_SIZE
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endif #SAMA5_EBICS3_HEAP
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endmenu # Heap Configuration
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config SAMA5_SDMMC
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bool "enable SDMMC controller"
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default y if SAMA5_HAVE_SDMMC
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select SDIO_DMA
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select SCHED_WORKQUEUE
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select SCHED_HPWORK
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select MMCSD
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select MMCSD_SDIO
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select SDIO_BLOCKSETUP
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select ARCH_HAVE_SDIO
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select SAMA5_SDMMC_DMA
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---help---
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Enable SD Card interface SDMMC. Selects SAMA5_SDMMC SAMA5_SDMMC_DMA SDIO_DMA SCHED_WORKQUEUE SCHED_HPWORK SDIO_BLOCKSETUP
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choice
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prompt "SDMMC maximum bus speed"
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default SAMA5_SDMMC_50MHZ
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depends on SAMA5_SDMMC
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config SAMA5_SDMMC_25MHZ
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bool "SDMMC 25Mhz"
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config SAMA5_SDMMC_50MHZ
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bool "SDMMC 50Mhz"
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endchoice # SDMMC bus speed
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endif # ARCH_CHIP_SAMA5
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@ -213,6 +213,14 @@ endif
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endif
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endif
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ifeq ($(CONFIG_SAMA5_SDMMC0),y)
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CHIP_CSRCS += sam_sdmmc.c
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else
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ifeq ($(CONFIG_SAMA5_SDMMC1),y)
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CHIP_CSRCS += sam_sdmmc.c
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endif
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endif
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ifeq ($(CONFIG_SAMA5_HSMCI0),y)
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CHIP_CSRCS += sam_hsmci.c sam_hsmci_clkdiv.c
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else
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@ -317,6 +317,8 @@
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#define SAM_AXIMX_MMUFLAGS MMU_IOFLAGS
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#define SAM_DAP_MMUFLAGS MMU_IOFLAGS
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#define SAM_L2CC_MMUFLAGS MMU_IOFLAGS
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#define SAM_SDMMC0_MMUFLAGS MMU_IOFLAGS
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#define SAM_SDMMC1_MMUFLAGS MMU_IOFLAGS
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/* If the NFC is not being used, the NFC SRAM can be used as general purpose
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* SRAM (cached). If the NFC is used, then the NFC SRAM should be treated
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@ -429,8 +431,8 @@
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#define SAM_EBICS1_VSECTION 0x60000000 /* 0x60000000-0x6fffffff: EBI Chip Select 1 */
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#define SAM_EBICS2_VSECTION 0x70000000 /* 0x70000000-0x7fffffff: EBI Chip Select 2 */
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#define SAM_EBICS3_VSECTION 0x80000000 /* 0x80000000-0x8fffffff: EBI Chip Select 3 */
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#define SAM_QSPI0AES_VSECTION 0x90000000 /* 0x90000000-0x9fffffff: QSPI0 AES Memory */
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#define SAM_QSPI1AES_VSECTION 0xa0000000 /* 0xa0000000-0xafffffff: QSPI1 AES Memory */
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#define SAM_QSPI0AES_VSECTION 0x90000000 /* 0x90000000-0x97ffffff: QSPI0 AES Memory */
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#define SAM_QSPI1AES_VSECTION 0x98000000 /* 0x98000000-0x9fffffff: QSPI1 AES Memory */
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#define SAM_SDMMC0_VSECTION 0xa0000000 /* 0xa0000000-0xafffffff: SDMMC0 */
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#define SAM_SDMMC1_VSECTION 0xb0000000 /* 0xb0000000-0xbfffffff: SDMMC1 */
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#define SAM_NFCCR_VSECTION 0xc0000000 /* 0xc0000000-0xcfffffff: NFC Command Registers */
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@ -461,6 +463,8 @@
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/* Peripheral virtual base addresses */
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#define SAM_SDMMC0_VBASE (SAM_SDMMC0_VSECTION)
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#define SAM_SDMMC1_VBASE (SAM_SDMMC1_VSECTION)
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#define SAM_LCDC_VBASE (SAM_PERIPHA_VSECTION+SAM_LCDC_OFFSET)
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#define SAM_XDMAC1_VBASE (SAM_PERIPHA_VSECTION+SAM_XDMAC1_OFFSET)
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#define SAM_ISC_VBASE (SAM_PERIPHA_VSECTION+SAM_ISC_OFFSET)
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@ -640,7 +644,7 @@
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* 1) If CONFIG_ARCH_ROMPGTABLE, then the page table resides in ROM and we
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* will not use any page table in RAM.
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* 2) We are executing out of SRAM. In this case, vectors will reside at
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* the bottom of SRAM, following by .text, .data, .bss, and heep. The
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* the bottom of SRAM, following by .text, .data, .bss, and heap. The
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* page table will be squeezed into the end of internal SRAM in this
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* case.
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*
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@ -1,4 +1,4 @@
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/************************************************************************************************************
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/****************************************************************************
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* arch/arm/src/sama5/hardware/_sama5d2x_pinmap.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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@ -31,40 +31,42 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PINMAP_H
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#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PINMAP_H
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/************************************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "sam_pio.h"
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/************************************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************************************/
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****************************************************************************/
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/* PIO pin definitions **************************************************************************************/
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/* Alternate Pin Functions.
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/* PIO pin definitions ******************************************************
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* Alternate Pin Functions.
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*
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* Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers, however, will
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* use the pin selection without the numeric suffix. Additional definitions are required in the board.h
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* file. For example, if we wanted the PCK0 on PB26, then the following definition should appear in the
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* board.h header file for that board:
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* Alternative pin selections are provided with a numeric suffix like _1, _2,
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* etc. Drivers, however, will use the pin selection without the numeric
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* suffix. Additional definitions are required in the board.h file. For
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* example, if we wanted the PCK0 on PB26, then the following definition
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* should appear in the board.h header file for that board:
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*
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* #define PIO_PMC_PCK0 PIO_PMC_PCK0_1
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*
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* The PCK logic will then automatically configure PB26 as the PCK0 pin.
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*/
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/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
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* Additional effort is required to select specific PIO options such as frequency, open-drain/push-pull,
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* and pull-up/down! Just the basics are defined for most pins in this file at the present time.
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/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
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* Additional effort is required to select specific PIO options such as
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* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
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* defined for most pins in this file at the present time.
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*/
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/* Analog-to-Digital Converter - ADC */
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@ -537,7 +539,6 @@
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#define PIO_PDMIC_DAT_1 (PIO_PERIPHD | PIO_CFG_DEFAULT | PIO_PORT_PIOB | PIO_PIN11)
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#define PIO_PDMIC_DAT_2 (PIO_PERIPHD | PIO_CFG_DEFAULT | PIO_PORT_PIOB | PIO_PIN26)
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/* Pulse Width Modulation Controller - PWM */
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#define PIO_PWM0_EXTRG0 (PIO_PERIPHD | PIO_CFG_DEFAULT | PIO_PORT_PIOB | PIO_PIN3)
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@ -601,28 +602,28 @@
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/* Secure Data Memory Card - SDMMC */
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#define PIO_SDMMC0_CD (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN13)
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#define PIO_SDMMC0_CD (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN13 | PIO_CFG_DEGLITCH | PIO_INT_BOTHEDGES | PIO_INPUT )
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#define PIO_SDMMC0_CK (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN0)
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#define PIO_SDMMC0_CMD (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN1)
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#define PIO_SDMMC0_DAT0 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN2)
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#define PIO_SDMMC0_DAT1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN3)
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#define PIO_SDMMC0_DAT2 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN4)
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#define PIO_SDMMC0_DAT3 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN5)
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#define PIO_SDMMC0_DAT4 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN6)
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#define PIO_SDMMC0_DAT5 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN7)
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#define PIO_SDMMC0_DAT6 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN8)
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#define PIO_SDMMC0_DAT7 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN9)
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#define PIO_SDMMC0_CMD (PIO_PERIPHA | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN1)
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#define PIO_SDMMC0_DAT0 (PIO_PERIPHA | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN2)
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#define PIO_SDMMC0_DAT1 (PIO_PERIPHA | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN3)
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#define PIO_SDMMC0_DAT2 (PIO_PERIPHA | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN4)
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#define PIO_SDMMC0_DAT3 (PIO_PERIPHA | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN5)
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#define PIO_SDMMC0_DAT4 (PIO_PERIPHA | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN6)
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#define PIO_SDMMC0_DAT5 (PIO_PERIPHA | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN7)
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#define PIO_SDMMC0_DAT6 (PIO_PERIPHA | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN8)
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#define PIO_SDMMC0_DAT7 (PIO_PERIPHA | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN9)
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#define PIO_SDMMC0_RSTN (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN10)
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#define PIO_SDMMC0_VDDSEL (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN11)
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#define PIO_SDMMC0_WP (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN12)
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#define PIO_SDMMC1_CD (PIO_PERIPHE | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN30)
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#define PIO_SDMMC1_CK (PIO_PERIPHE | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN22)
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#define PIO_SDMMC1_CMD (PIO_PERIPHE | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN28)
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#define PIO_SDMMC1_DAT0 (PIO_PERIPHE | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN18)
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#define PIO_SDMMC1_DAT1 (PIO_PERIPHE | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN19)
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#define PIO_SDMMC1_DAT2 (PIO_PERIPHE | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN20)
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#define PIO_SDMMC1_DAT3 (PIO_PERIPHE | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN21)
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#define PIO_SDMMC1_CMD (PIO_PERIPHE | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN28)
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#define PIO_SDMMC1_DAT0 (PIO_PERIPHE | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN18)
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#define PIO_SDMMC1_DAT1 (PIO_PERIPHE | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN19)
|
||||
#define PIO_SDMMC1_DAT2 (PIO_PERIPHE | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN20)
|
||||
#define PIO_SDMMC1_DAT3 (PIO_PERIPHE | PIO_CFG_PULLUP | PIO_PORT_PIOA | PIO_PIN21)
|
||||
#define PIO_SDMMC1_RSTN (PIO_PERIPHE | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN27)
|
||||
#define PIO_SDMMC1_WP (PIO_PERIPHE | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN29)
|
||||
|
||||
|
|
|
|||
603
arch/arm/src/sama5/hardware/sam_sdmmc.h
Normal file
603
arch/arm/src/sama5/hardware/sam_sdmmc.h
Normal file
|
|
@ -0,0 +1,603 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/sama5/hardware/sam_sdmmc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAMA5_SDMMC_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAMA5_SDMMC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define SAMA5_SDMMC_DSADDR_OFFSET 0x0000 /* DMA System Address Register */
|
||||
#define SAMA5_SDMMC_BLKATTR_OFFSET 0x0004 /* Block Size Register */
|
||||
#define SAMA5_SDMMC_BSR_OFFSET 0x0004 /* Block Size Register */
|
||||
#define SAMA5_SDMMC_BCR_OFFSET 0x0006 /* Block Count Register */
|
||||
#define SAMA5_SDMMC_CMDARG_OFFSET 0x0008 /* Command Argument Register */
|
||||
#define SAMA5_SDMMC_XFERTYP_OFFSET 0x000c /* Transfer Type Register SAMA5: Transfer Mode Register */
|
||||
#define SAMA5_SDMMC_CMDRSP0_OFFSET 0x0010 /* Command Response 0 */
|
||||
#define SAMA5_SDMMC_CMDRSP1_OFFSET 0x0014 /* Command Response 1 */
|
||||
#define SAMA5_SDMMC_CMDRSP2_OFFSET 0x0018 /* Command Response 2 */
|
||||
#define SAMA5_SDMMC_CMDRSP3_OFFSET 0x001c /* Command Response 3 */
|
||||
#define SAMA5_SDMMC_DATAPORT_OFFSET 0x0020 /* Buffer Data Port Register */
|
||||
#define SAMA5_SDMMC_PRSSTAT_OFFSET 0x0024 /* Present State Register */
|
||||
#define SAMA5_SDMMC_PROCTL_OFFSET 0x0028 /* Protocol Control Register */
|
||||
#define SAMA5_SDMMC_PWRCTL_OFFSET 0x0029 /* Power Control Control Register */
|
||||
#define SAMA5_SDMMC_SYSCTL_OFFSET 0x002c /* System Control Register, or Clock Control Register/Timout Control Register */
|
||||
#define SAMA5_SDMMC_TCR_OFFSET 0x002e /* Timout Control Register (8 bit) */
|
||||
#define SAMA5_SDMMC_SRR_OFFSET 0x002f /* Software Reset Register (8 bit) */
|
||||
#define SAMA5_SDMMC_IRQSTAT_OFFSET 0x0030 /* Interrupt Status Register */
|
||||
#define SAMA5_SDMMC_IRQSTATEN_OFFSET 0x0034 /* Interrupt Status Enable Register */
|
||||
#define SAMA5_SDMMC_EISTER_OFFSET 0x0036 /* SAMA5: Error Interrupt Status Register */
|
||||
#define SAMA5_SDMMC_IRQSIGEN_OFFSET 0x0038 /* Interrupt Signal Enable Register */
|
||||
#define SAMA5_SDMMC_AC12ERR_OFFSET 0x003c /* Auto CMD12 Error Status Register */
|
||||
#define SAMA5_SDMMC_H2CR_OFFSET 0x003e /* Host Control 2 Register */
|
||||
#define SAMA5_SDMMC_HTCAPBLT0_OFFSET 0x0040 /* Host Controller Capabilities 0 Register */
|
||||
#define SAMA5_SDMMC_HTCAPBLT1_OFFSET 0x0044 /* Host Controller Capabilities 1 Register */
|
||||
#define SAMA5_SDMMC_MIX_OFFSET 0x0048 /* Mixer Control Register SAMA5: Maximum Current Capabililities Register */
|
||||
#define SAMA5_SDMMC_FEVT_OFFSET 0x0050 /* Force Event Register */
|
||||
#define SAMA5_SDMMC_ADMAES_OFFSET 0x0054 /* ADMA Error Status Register */
|
||||
#define SAMA5_SDMMC_ADSADDR_OFFSET 0x0058 /* ADMA System Address Register */
|
||||
#define SAMA5_SDMMC_DLL_CONTROL_OFFSET 0x0060 /* DLL Control Register */
|
||||
#define SAMA5_SDMMC_DLL_STATUS_OFFSET 0x0064 /* DLL Status Register */
|
||||
#define SAMA5_SDMMC_CLK_TUNE_CTRL_OFFSET 0x0068 /* Clock tuning control Register */
|
||||
/* 0x0070 – 0x00f8: reserved */
|
||||
#define SAMA5_SDMMC_HOST_VERSION_OFFSET 0x00fe /* Host Controller Version Register */
|
||||
#define SAMA5_SDMMC_APSR_OFFSET 0x0200 /* Additional Present State Register */
|
||||
#define SAMA5_SDMMC_MC1R_OFFSET 0x0204 /* e.MMC Control 1 Register */
|
||||
#define SAMA5_SDMMC_MC2R_OFFSET 0x0205 /* e.MMC Control 2 Register */
|
||||
#define SAMA5_SDMMC_ACR_OFFSET 0x0208 /* AHB Control Register */
|
||||
#define SAMA5_SDMMC_CC2R_OFFSET 0x020C /* Clock Control 2 Register */
|
||||
#define SAMA5_SDMMC_RTC1R_OFFSET 0x0210 /* Retuning Timer Control 1 Register */
|
||||
#define SAMA5_SDMMC_RTC2R_OFFSET 0x0211 /* Retuning Timer Control 2 Register */
|
||||
#define SAMA5_SDMMC_RTCVR_OFFSET 0x0214 /* Retuning Timer Counter Value Register */
|
||||
#define SAMA5_SDMMC_RTISTER_OFFSET 0x0218 /* Retuning Timer Interrupt Status Enable Register */
|
||||
#define SAMA5_SDMMC_RTISIER_OFFSET 0x0219 /* Retuning Timer Interrupt Signal Enable Register */
|
||||
#define SAMA5_SDMMC_RTISTR_OFFSET 0x021C /* Retuning Timer Interrupt Status Register */
|
||||
#define SAMA5_SDMMC_RTSSR_OFFSET 0x021D /* Retuning Timer Status Slots Register */
|
||||
#define SAMA5_SDMMC_TUNCR_OFFSET 0x0220 /* Tuning Control Register */
|
||||
/* 0x0224 – 0x022C Reserved */
|
||||
#define SAMA5_SDMMC_CACR_OFFSET 0x0230 /* Capabilities Control Register */
|
||||
/* 0x0234 – 0x023C Reserved */
|
||||
#define SAMA5_SDMMC_CALCR_OFFSET 0x0240 /* Calibration Control Register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* For SDMMC0... */
|
||||
|
||||
#define SAMA5_SDMMC0_DSADDR (SAM_SDMMC0_VBASE + SAMA5_SDMMC_DSADDR_OFFSET)
|
||||
#define SAMA5_SDMMC0_BLKATTR (SAM_SDMMC0_VBASE + SAMA5_SDMMC_BLKATTR_OFFSET)
|
||||
#define SAMA5_SDMMC0_CMDARG (SAM_SDMMC0_VBASE + SAMA5_SDMMC_CMDARG_OFFSET)
|
||||
#define SAMA5_SDMMC0_XFERTYP (SAM_SDMMC0_VBASE + SAMA5_SDMMC_XFERTYP_OFFSET)
|
||||
#define SAMA5_SDMMC0_CMDRSP0 (SAM_SDMMC0_VBASE + SAMA5_SDMMC_CMDRSP0_OFFSET)
|
||||
#define SAMA5_SDMMC0_CMDRSP1 (SAM_SDMMC0_VBASE + SAMA5_SDMMC_CMDRSP1_OFFSET)
|
||||
#define SAMA5_SDMMC0_CMDRSP2 (SAM_SDMMC0_VBASE + SAMA5_SDMMC_CMDRSP2_OFFSET)
|
||||
#define SAMA5_SDMMC0_CMDRSP3 (SAM_SDMMC0_VBASE + SAMA5_SDMMC_CMDRSP3_OFFSET)
|
||||
#define SAMA5_SDMMC0_DATAPORT (SAM_SDMMC0_VBASE + SAMA5_SDMMC_DATAPORT_OFFSET)
|
||||
#define SAMA5_SDMMC0_PRSSTAT (SAM_SDMMC0_VBASE + SAMA5_SDMMC_PRSSTAT_OFFSET)
|
||||
#define SAMA5_SDMMC0_PROCTL (SAM_SDMMC0_VBASE + SAMA5_SDMMC_PROCTL_OFFSET)
|
||||
#define SAMA5_SDMMC0_PWRCTL (SAM_SDMMC0_VBASE + SAMA5_SDMMC_PWRCTL_OFFSET)
|
||||
#define SAMA5_SDMMC0_SYSCTL (SAM_SDMMC0_VBASE + SAMA5_SDMMC_SYSCTL_OFFSET)
|
||||
#define SAMA5_SDMMC0_IRQSTAT (SAM_SDMMC0_VBASE + SAMA5_SDMMC_IRQSTAT_OFFSET)
|
||||
#define SAMA5_SDMMC0_IRQSTATEN (SAM_SDMMC0_VBASE + SAMA5_SDMMC_IRQSTATEN_OFFSET)
|
||||
#define SAMA5_SDMMC0_IRQSIGEN (SAM_SDMMC0_VBASE + SAMA5_SDMMC_IRQSIGEN_OFFSET)
|
||||
#define SAMA5_SDMMC0_AC12ERR (SAM_SDMMC0_VBASE + SAMA5_SDMMC_AC12ERR_OFFSET)
|
||||
#define SAMA5_SDMMC0_HTCAPBLT0 (SAM_SDMMC0_VBASE + SAMA5_SDMMC_HTCAPBLT0_OFFSET)
|
||||
#define SAMA5_SDMMC0_HTCAPBLT1 (SAM_SDMMC0_VBASE + SAMA5_SDMMC_HTCAPBLT1_OFFSET)
|
||||
#define SAMA5_SDMMC0_MIX (SAM_SDMMC0_VBASE + SAMA5_SDMMC_MIX_OFFSET)
|
||||
#define SAMA5_SDMMC0_FEVT (SAM_SDMMC0_VBASE + SAMA5_SDMMC_FEVT_OFFSET)
|
||||
#define SAMA5_SDMMC0_ADMAES (SAM_SDMMC0_VBASE + SAMA5_SDMMC_ADMAES_OFFSET)
|
||||
#define SAMA5_SDMMC0_ADSADDR (SAM_SDMMC0_VBASE + SAMA5_SDMMC_ADSADDR_OFFSET)
|
||||
#define SAMA5_SDMMC_DLL_CONTROL (SAM_SDMMC0_VBASE + SAMA5_SDMMC_DLL_CONTROL_OFFSET)
|
||||
#define SAMA5_SDMMC_DLL_STATUS (SAM_SDMMC0_VBASE + SAMA5_SDMMC_DLL_STATUS)
|
||||
#define SAMA5_SDMMC_CLK_TUNE_CTRL (SAM_SDMMC0_VBASE + SAMA5_SDMMC_CLK_TUNE_CTRL)
|
||||
#define SAMA5_SDMMC0_VENDOR (SAM_SDMMC0_VBASE + SAMA5_SDMMC_VENDOR_OFFSET)
|
||||
#define SAMA5_SDMMC0_MMCBOOT (SAM_SDMMC0_VBASE + SAMA5_SDMMC_MMCBOOT_OFFSET)
|
||||
#define SAMA5_SDMMC0_VENDOR2 (SAM_SDMMC0_VBASE + SAMA5_SDMMC_VENDOR2_OFFSET)
|
||||
#define SAMA5_SDMMC0_TC (SAM_SDMMC0_VBASE + SAMA5_SDMMC_TC_OFFSET)
|
||||
|
||||
/* For SDMMC1... */
|
||||
|
||||
#define SAMA5_SDMMC1_DSADDR (SAM_SDMMC1_VBASE + SAMA5_SDMMC_DSADDR_OFFSET)
|
||||
#define SAMA5_SDMMC1_BLKATTR (SAM_SDMMC1_VBASE + SAMA5_SDMMC_BLKATTR_OFFSET)
|
||||
#define SAMA5_SDMMC1_CMDARG (SAM_SDMMC1_VBASE + SAMA5_SDMMC_CMDARG_OFFSET)
|
||||
#define SAMA5_SDMMC1_XFERTYP (SAM_SDMMC1_VBASE + SAMA5_SDMMC_XFERTYP_OFFSET)
|
||||
#define SAMA5_SDMMC1_CMDRSP0 (SAM_SDMMC1_VBASE + SAMA5_SDMMC_CMDRSP0_OFFSET)
|
||||
#define SAMA5_SDMMC1_CMDRSP1 (SAM_SDMMC1_VBASE + SAMA5_SDMMC_CMDRSP1_OFFSET)
|
||||
#define SAMA5_SDMMC1_CMDRSP2 (SAM_SDMMC1_VBASE + SAMA5_SDMMC_CMDRSP2_OFFSET)
|
||||
#define SAMA5_SDMMC1_CMDRSP3 (SAM_SDMMC1_VBASE + SAMA5_SDMMC_CMDRSP3_OFFSET)
|
||||
#define SAMA5_SDMMC1_DATAPORT (SAM_SDMMC1_VBASE + SAMA5_SDMMC_DATPORT_OFFSET)
|
||||
#define SAMA5_SDMMC1_PRSSTAT (SAM_SDMMC1_VBASE + SAMA5_SDMMC_PRSSTAT_OFFSET)
|
||||
#define SAMA5_SDMMC1_PROCTL (SAM_SDMMC1_VBASE + SAMA5_SDMMC_PROCTL_OFFSET)
|
||||
#define SAMA5_SDMMC1_PWRCTL (SAM_SDMMC1_VBASE + SAMA5_SDMMC_PWRCTL_OFFSET)
|
||||
#define SAMA5_SDMMC1_SYSCTL (SAM_SDMMC1_VBASE + SAMA5_SDMMC_SYSCTL_OFFSET)
|
||||
#define SAMA5_SDMMC1_IRQSTAT (SAM_SDMMC1_VBASE + SAMA5_SDMMC_IRQSTAT_OFFSET)
|
||||
#define SAMA5_SDMMC1_IRQSTATEN (SAM_SDMMC1_VBASE + SAMA5_SDMMC_IRQSTATEN_OFFSET)
|
||||
#define SAMA5_SDMMC1_IRQSIGEN (SAM_SDMMC1_VBASE + SAMA5_SDMMC_IRQSIGEN_OFFSET)
|
||||
#define SAMA5_SDMMC1_AC12ERR (SAM_SDMMC1_VBASE + SAMA5_SDMMC_AC12ERR_OFFSET)
|
||||
#define SAMA5_SDMMC1_HTCAPBLT0 (SAM_SDMMC1_VBASE + SAMA5_SDMMC_HTCAPBLT0_OFFSET)
|
||||
#define SAMA5_SDMMC1_HTCAPBLT1 (SAM_SDMMC1_VBASE + SAMA5_SDMMC_HTCAPBLT1_OFFSET)
|
||||
#define SAMA5_SDMMC1_FEVT (SAM_SDMMC1_VBASE + SAMA5_SDMMC_FEVT_OFFSET)
|
||||
#define SAMA5_SDMMC1_ADMAES (SAM_SDMMC1_VBASE + SAMA5_SDMMC_ADMAES_OFFSET)
|
||||
#define SAMA5_SDMMC1_ADSADDR (SAM_SDMMC1_VBASE + SAMA5_SDMMC_ADSADDR_OFFSET)
|
||||
#define SAMA5_SDMMC1_DLL_CONTROL (SAM_SDMMC1_VBASE + SAMA5_SDMMC_DLL_CONTROL_OFFSET)
|
||||
#define SAMA5_SDMMC1_DLL_STATUS (SAM_SDMMC1_VBASE + SAMA5_SDMMC_DLL_STATUS)
|
||||
#define SAMA5_USSDHC_CLK_TUNE_CTRL (SAM_SDMMC1_VBASE + SAMA5_SDMMC_CLK_TUNE_CTRL)
|
||||
#define SAMA5_SDMMC1_VENDOR (SAM_SDMMC1_VBASE + SAMA5_SDMMC_VENDOR_OFFSET)
|
||||
#define SAMA5_SDMMC1_MMCBOOT (SAM_SDMMC1_VBASE + SAMA5_SDMMC_MMCBOOT_OFFSET)
|
||||
#define SAMA5_SDMMC1_VENDOR2 (SAM_SDMMC1_VBASE + SAMA5_SDMMC_VENDOR2_OFFSET)
|
||||
#define SAMA5_SDMMC1_TC (SAM_SDMMC1_VBASE + SAMA5_SDMMC_TC_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *************************************************/
|
||||
|
||||
/* DMA System Address Register */
|
||||
|
||||
#define SDMMC_DSADDR_SHIFT (0) /* Bits 2-31: DMA System Address */
|
||||
#define SDMMC_DSADDR_MASK (0xfffffffc) /* Bits 0-1: 32 bit aligned, low bits Reserved */
|
||||
|
||||
/* Block Attributes Register */
|
||||
|
||||
#define SDMMC_BSR_BLKSIZE_SHIFT (0) /* Bits 0-9: Transfer Block Size */
|
||||
/* Bits 10-11: Reserved */
|
||||
#define SDMMC_BSR_BOUNDARY_SHIFT (12) /* Bits 12-14: Boundary */
|
||||
/* Bit 15: Reserved */
|
||||
|
||||
/* Block Count Register (16-bit block count) */
|
||||
|
||||
/* Command Argument Register (32-bit cmd/arg data) */
|
||||
|
||||
/* Transfer Type Register */
|
||||
|
||||
#define SDMMC_XFERTYP_DMAEN (1 << 0) /* Bit 0: DMA Enable */
|
||||
#define SDMMC_XFERTYP_BCEN (1 << 1) /* Bit 1: Block Count Enable */
|
||||
#define SDMMC_XFERTYP_AC12EN (1 << 2) /* Bit 2: Auto CMD12 Enable */
|
||||
/* Bit 3: Reserved */
|
||||
|
||||
#define SDMMC_XFERTYP_DTDSEL (1 << 4) /* Bit 4: Data Transfer Direction Select */
|
||||
#define SDMMC_XFERTYP_MSBSEL (1 << 5) /* Bit 5: Multi/Single Block Select */
|
||||
/* Bits 6-15: Reserved */
|
||||
|
||||
#define SDMMC_XFERTYP_RSPTYP_SHIFT (16) /* Bits 16-17: Response Type Select */
|
||||
#define SDMMC_XFERTYP_RSPTYP_MASK (3 << SDMMC_XFERTYP_RSPTYP_SHIFT)
|
||||
# define SDMMC_XFERTYP_RSPTYP_NONE (0 << SDMMC_XFERTYP_RSPTYP_SHIFT) /* No response */
|
||||
# define SDMMC_XFERTYP_RSPTYP_LEN136 (1 << SDMMC_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */
|
||||
# define SDMMC_XFERTYP_RSPTYP_LEN48 (2 << SDMMC_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */
|
||||
# define SDMMC_XFERTYP_RSPTYP_LEN48BSY (3 << SDMMC_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */
|
||||
/* Bit 18: Reserved */
|
||||
#define SDMMC_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */
|
||||
#define SDMMC_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */
|
||||
#define SDMMC_XFERTYP_DPSEL (1 << 21) /* Bit 21: Data Present Select */
|
||||
#define SDMMC_XFERTYP_CMDTYP_SHIFT (22) /* Bits 22-23: Command Type */
|
||||
#define SDMMC_XFERTYP_CMDTYP_MASK (3 << SDMMC_XFERTYP_CMDTYP_SHIFT)
|
||||
# define SDMMC_XFERTYP_CMDTYP_NORMAL (0 << SDMMC_XFERTYP_CMDTYP_SHIFT) /* Normal other commands */
|
||||
# define SDMMC_XFERTYP_CMDTYP_SUSPEND (1 << SDMMC_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */
|
||||
# define SDMMC_XFERTYP_CMDTYP_RESUME (2 << SDMMC_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */
|
||||
# define SDMMC_XFERTYP_CMDTYP_ABORT (3 << SDMMC_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */
|
||||
#define SDMMC_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */
|
||||
#define SDMMC_XFERTYP_CMDINX_MASK (0x3f << SDMMC_XFERTYP_CMDINX_SHIFT)
|
||||
/* Bits 30-31: Reserved */
|
||||
|
||||
/* Command Response 0-3 (32-bit response data) */
|
||||
|
||||
/* Buffer Data Port Register (32-bit data content) */
|
||||
|
||||
/* Present State Register */
|
||||
|
||||
#define SDMMC_PRSSTAT_CIHB (1 << 0) /* Bit 0: Command Inhibit (CMD) */
|
||||
#define SDMMC_PRSSTAT_CDIHB (1 << 1) /* Bit 1: Command Inhibit (DAT) */
|
||||
#define SDMMC_PRSSTAT_DLA (1 << 2) /* Bit 2: Data Line Active */
|
||||
#define SDMMC_PRSSTAT_SDSTB (1 << 3) /* Bit 3: Unused in SAMA5 */
|
||||
#define SDMMC_PRSSTAT_IPGOFF (1 << 4) /* Bit 4: Unused */
|
||||
#define SDMMC_PRSSTAT_HCKOFF (1 << 5) /* Bit 5: Unused */
|
||||
#define SDMMC_PRSSTAT_PEROFF (1 << 6) /* Bit 6: Unused */
|
||||
#define SDMMC_PRSSTAT_SDOFF (1 << 7) /* Bit 7: Unused */
|
||||
#define SDMMC_PRSSTAT_WTA (1 << 8) /* Bit 8: Write Transfer Active */
|
||||
#define SDMMC_PRSSTAT_RTA (1 << 9) /* Bit 9: Read Transfer Active */
|
||||
#define SDMMC_PRSSTAT_BWEN (1 << 10) /* Bit 10: Buffer Write Enable */
|
||||
#define SDMMC_PRSSTAT_BREN (1 << 11) /* Bit 11: Buffer Read Enable */
|
||||
#define SDMMC_PRSSTAT_RTR (1 << 12) /* Bit 12: Retuning request */
|
||||
/* Bits 13-14: Reserved */
|
||||
#define SDMMC_PRSSTAT_TSCD (1 << 15) /* Bit 15: Tape Select Change Done */
|
||||
#define SDMMC_PRSSTAT_CINS (1 << 16) /* Bit 16: Card Inserted */
|
||||
/* Bit 17: Reserved */
|
||||
#define SDMMC_PRSSTAT_CDPL (1 << 18) /* Bit 18: Card Detect Pin Level */
|
||||
#define SDMMC_PRSSTAT_WPSPL (1 << 19) /* Bit 19: Write Protect Switch Pin Level */
|
||||
#define SDMMC_PRSSTAT_CLSL (1 << 24) /* Bit 24: CMD Line Signal Level */
|
||||
/* Bits 25-31: Reserved */
|
||||
#define SDMMC_PRSSTAT_DLSL_SHIFT (20) /* Bits 20-23: DAT Line Signal Level */
|
||||
#define SDMMC_PRSSTAT_DLSL_MASK (0x0f << SDMMC_PRSSTAT_DLSL_SHIFT)
|
||||
# define SDMMC_PRSSTAT_DLSL_DAT0 (0x01 << SDMMC_PRSSTAT_DLSL_SHIFT)
|
||||
# define SDMMC_PRSSTAT_DLSL_DAT1 (0x02 << SDMMC_PRSSTAT_DLSL_SHIFT)
|
||||
# define SDMMC_PRSSTAT_DLSL_DAT2 (0x04 << SDMMC_PRSSTAT_DLSL_SHIFT)
|
||||
# define SDMMC_PRSSTAT_DLSL_DAT3 (0x08 << SDMMC_PRSSTAT_DLSL_SHIFT)
|
||||
|
||||
/* Protocol Control Register */
|
||||
|
||||
#define SDMMC_PROCTL_LCTL (1 << 0) /* Bit 0: LED Control */
|
||||
#define SDMMC_PROCTL_DTW_SHIFT (1) /* Bit 1: Data Transfer Width */
|
||||
#define SDMMC_PROCTL_DTW_MASK (1 << SDMMC_PROCTL_DTW_SHIFT)
|
||||
# define SDMMC_PROCTL_DTW_1BIT (0 << SDMMC_PROCTL_DTW_SHIFT) /* 1-bit mode */
|
||||
# define SDMMC_PROCTL_DTW_4BIT (1 << SDMMC_PROCTL_DTW_SHIFT) /* 4-bit mode */
|
||||
#define SDMMC_PROCTL_HSEN (1 << 2) /* Bit 2: High Speed Enable */
|
||||
#define SDMMC_PROCTL_DMAS_SHIFT (3) /* Bits 3-4: DMA Select */
|
||||
#define SDMMC_PROCTL_DMAS_MASK (3 << SDMMC_PROCTL_DMAS_SHIFT)
|
||||
# define SDMMC_PROCTL_DMAS_SDMA (0 << SDMMC_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */
|
||||
# define SDMMC_PROCTL_DMAS_RES1 (1 << SDMMC_PROCTL_DMAS_SHIFT) /* Reserved */
|
||||
# define SDMMC_PROCTL_DMAS_ADMA (2 << SDMMC_PROCTL_DMAS_SHIFT) /* ADMA is selected */
|
||||
# define SDMMC_PROCTL_DMAS_RES2 (1 << SDMMC_PROCTL_DMAS_SHIFT) /* Reserved */
|
||||
#define SDMMC_PROCTL_EXTDW_SHIFT (5) /* Bits 3-4: DMA Select */
|
||||
#define SDMMC_PROCTL_EXTDW_MASK (1 << SDMMC_PROCTL_EXTDW_SHIFT)
|
||||
/* Bits 6-7: Reserved */
|
||||
#define SDMMC_PROCTL_SDBPWR_SHIFT (9) /* Bits 3-4: SD Bus Power */
|
||||
#define SDMMC_PROCTL_SDBPWR_MASK (1 << SDMMC_PROCTL_SDBPWR_SHIFT)
|
||||
/* Bits 10-15: Reserved */
|
||||
#define SDMMC_PROCTL_SABGREQ (1 << 16) /* Bit 16: Stop At Block Gap Request */
|
||||
#define SDMMC_PROCTL_CREQ (1 << 17) /* Bit 17: Continue Request */
|
||||
#define SDMMC_PROCTL_RWCTL (1 << 18) /* Bit 18: Read Wait Control */
|
||||
#define SDMMC_PROCTL_IABG (1 << 19) /* Bit 19: Interrupt At Block Gap */
|
||||
#define SDMMC_PROCTL_RDDONENO8CLK (1 << 20) /* Bit 20: Read done to 8 clock */
|
||||
#define SDMMC_PROCTL_RESV2023 (4 << 21) /* Bits 21-23: Reserved, write as 0x100 */
|
||||
#define SDMMC_PROCTL_WECINT (1 << 24) /* Bit 24: Wakeup Event Enable On Card Interrupt */
|
||||
#define SDMMC_PROCTL_WECINS (1 << 25) /* Bit 25: Wakeup Event Enable On SD Card Insertion */
|
||||
#define SDMMC_PROCTL_WECRM (1 << 26) /* Bit 26: Wakeup Event Enable On SD Card Removal */
|
||||
#define SDMMC_PROCTL_BURST_SHIFT (27) /* Bits 27-29: Burst Length */
|
||||
#define SDMMC_PROCTL_BURST_MASK (7 << SDMMC_PROCTL_BUSRT_SHIFT)
|
||||
# define SDMMC_PROCTL_BURST_INCR (1 << SDMMC_PROCTL_BURST_SHIFT) /* Burst for Incr */
|
||||
# define SDMMC_PROCTL_BURST_4816 (2 << SDMMC_PROCTL_BURST_SHIFT) /* Burst for 4/8/16 */
|
||||
# define SDMMC_PROCTL_BURST_4W8W16W (4 << SDMMC_PROCTL_BURST_SHIFT) /* Burst for 4w/8w/16w */
|
||||
#define SDMMC_PROTCTL_NEBLKRD (1 << 30) /* Bit 30: Non-exect block read */
|
||||
/* Bit 31: Reserved */
|
||||
|
||||
/* Power Control Register */
|
||||
|
||||
#define SDMMC_POWER_ON (0x01)
|
||||
#define SDMMC_POWER_180 (0x0a)
|
||||
#define SDMMC_POWER_300 (0x0c)
|
||||
#define SDMMC_POWER_330 (0x0e)
|
||||
|
||||
/* System Control Register */
|
||||
|
||||
#define SDMMC_SYSCTL_INTCLKEN (1 << 0) /* Bit 0: Internal Clock Enable */
|
||||
#define SDMMC_SYSCTL_INTCLKS (1 << 1) /* Bit 1: Internal Clock Stable */
|
||||
#define SDMMC_SYSCTL_SDCLKEN (1 << 2) /* Bit 2: SD Clock Enable */
|
||||
#define SDMMC_SYSCTL_CLKGSEL (1 << 5) /* Bit 5: Clock Generator Select */
|
||||
#define SDMMC_SYSCTL_USDCLKFSEL (3 << 6) /* Bit 0: Upper bits of SDCLK Frequency Select */
|
||||
#define SDMMC_SYSCTL_CLKFSEL (0xf0) /* Bit 0: SDCLK Frequency Select */
|
||||
#define SDMMC_CLOCK_MUL_MASK (0x00ff0000)
|
||||
#define SDMMC_CLOCK_MUL_SHIFT (16)
|
||||
|
||||
#define SDMMC_SYSCTL_DVS_SHIFT (4) /* Bits 4-7: Divisor */
|
||||
#define SDMMC_SYSCTL_DVS_MASK (0x0f << SDMMC_SYSCTL_DVS_SHIFT)
|
||||
# define SDMMC_SYSCTL_DVS_DIV(n) (((n) - 1) << SDMMC_SYSCTL_DVS_SHIFT) /* Divide by n, n=1..16 */
|
||||
#define SDMMC_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */
|
||||
#define SDMMC_SYSCTL_SDCLKFS_MASK (0xff << SDMMC_SYSCTL_SDCLKFS_SHIFT)
|
||||
# define SDMMC_SYSCTL_SDCLKFS_BYPASS (0x00 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Bypass the prescaler */
|
||||
# define SDMMC_SYSCTL_SDCLKFS_DIV2 (0x01 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 2 */
|
||||
# define SDMMC_SYSCTL_SDCLKFS_DIV4 (0x02 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 4 */
|
||||
# define SDMMC_SYSCTL_SDCLKFS_DIV8 (0x04 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 8 */
|
||||
# define SDMMC_SYSCTL_SDCLKFS_DIV16 (0x08 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 16 */
|
||||
# define SDMMC_SYSCTL_SDCLKFS_DIV32 (0x10 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 32 */
|
||||
# define SDMMC_SYSCTL_SDCLKFS_DIV64 (0x20 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 64 */
|
||||
# define SDMMC_SYSCTL_SDCLKFS_DIV128 (0x40 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 128 */
|
||||
# define SDMMC_SYSCTL_SDCLKFS_DIV256 (0x80 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 256 */
|
||||
#define SDMMC_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */
|
||||
#define SDMMC_SYSCTL_DTOCV_MASK (0x0f << SDMMC_SYSCTL_DTOCV_SHIFT)
|
||||
# define SDMMC_SYSCTL_DTOCV_MUL(n) (((n) - 213) << SDMMC_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */
|
||||
/* Bits 20-22: Reserved */
|
||||
#define SDMMC_SYSCTL_IPPRSTN (1 << 23) /* Bit 23: Card /reset (default 1) */
|
||||
#define SDMMC_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */
|
||||
#define SDMMC_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */
|
||||
#define SDMMC_SYSCTL_RSTD (1 << 26) /* Bit 26: Software Reset For DAT Line */
|
||||
#define SDMMC_SYSCTL_INITA (1 << 27) /* Bit 27: Initialization Active (SAMA5: unused) */
|
||||
#define SDMMC_SYSCTL_RSTT (1 << 28) /* Bit 28: Reset tuning (SAMA5: unused) */
|
||||
/* Bits 29-31: Reserved */
|
||||
#define SDMMC_DIVIDER_SHIFT (8)
|
||||
#define SDMMC_DIV_MASK (0xff)
|
||||
#define SDMMC_DIVIDER_HI_SHIFT (6)
|
||||
#define SDMMC_DIV_MASK_LEN (8)
|
||||
#define SDMMC_DIV_HI_MASK (0x300)
|
||||
#define SDMMC_CLOCK_BASE_MASK (0x00003f00)
|
||||
#define SDMMC_CLOCK_V3_BASE_MASK (0x0000ff00)
|
||||
#define SDMMC_CLOCK_BASE_SHIFT (8)
|
||||
|
||||
/* Timeout Control Register */
|
||||
|
||||
#define SDMMC_TCR_MASK (0x0f) /* Bits 0-3 */
|
||||
|
||||
/* Interrupt Status Register, Interrupt Status Enable Register and Interrupt
|
||||
* Signal Enable Register Common interrupt bit definitions
|
||||
*/
|
||||
|
||||
#define SDMMC_INT_CC (1 << 0) /* Bit 0: Command Complete */
|
||||
#define SDMMC_INT_TC (1 << 1) /* Bit 1: Transfer Complete */
|
||||
#define SDMMC_INT_BGE (1 << 2) /* Bit 2: Block Gap Event */
|
||||
#define SDMMC_INT_DINT (1 << 3) /* Bit 3: DMA Interrupt - indicates SDMA Boundary Pause */
|
||||
#define SDMMC_INT_BWR (1 << 4) /* Bit 4: Buffer Write Ready */
|
||||
#define SDMMC_INT_BRR (1 << 5) /* Bit 5: Buffer Read Ready */
|
||||
#define SDMMC_INT_CINS (1 << 6) /* Bit 6: Card Insertion */
|
||||
#define SDMMC_INT_CRM (1 << 7) /* Bit 7: Card Removal */
|
||||
#define SDMMC_INT_CINT (1 << 8) /* Bit 8: Card Interrupt */
|
||||
/* Bits 9-11: Reserved */
|
||||
#define SDMMC_INT_RTR (1 << 12) /* Bit 12: Re-tuning event */
|
||||
/* Bit 13: Reserved */
|
||||
#define SDMMC_INT_TP (1 << 14) /* Bit 14: Tuning pass */
|
||||
/* Bit 15: Reserved */
|
||||
#define SDMMC_INT_CTOE (1 << 16) /* Bit 16: Command Timeout Error */
|
||||
#define SDMMC_INT_CCE (1 << 17) /* Bit 17: Command CRC Error */
|
||||
#define SDMMC_INT_CEBE (1 << 18) /* Bit 18: Command End Bit Error */
|
||||
#define SDMMC_INT_CIE (1 << 19) /* Bit 19: Command Index Error */
|
||||
#define SDMMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error */
|
||||
#define SDMMC_INT_DCE (1 << 21) /* Bit 21: Data CRC Error */
|
||||
#define SDMMC_INT_DEBE (1 << 22) /* Bit 22: Data End Bit Error */
|
||||
#define SDMMC_INT_CURLIM (1 << 23) /* Bit 23: Current Limit Error */
|
||||
#define SDMMC_INT_AC12E (1 << 24) /* Bit 24: Auto CMD12 Error */
|
||||
#define SDMMC_INT_ADMAE (1 << 25) /* Bit 25: ADMA error */
|
||||
/* Bits 26-31: Reserved */
|
||||
#define SDMMC_INT_ALL 0x117f01ff
|
||||
|
||||
/* Auto CMD12 Error Status Register */
|
||||
|
||||
#define SDMMC_AC12ERR_NE (1 << 0) /* Bit 0: Auto CMD12 Not Executed */
|
||||
#define SDMMC_AC12ERR_TOE (1 << 1) /* Bit 1: Auto CMD12 Timeout Error */
|
||||
#define SDMMC_AC12ERR_EBE (1 << 2) /* Bit 2: Auto CMD12 End Bit Error */
|
||||
#define SDMMC_AC12ERR_CE (1 << 3) /* Bit 3: Auto CMD12 CRC Error */
|
||||
#define SDMMC_AC12ERR_IE (1 << 4) /* Bit 4: Auto CMD12 Index Error */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define SDMMC_AC12ERR_CNI (1 << 7) /* Bit 7: Command Not Issued By Auto CMD12 Error */
|
||||
/* Bits 8-21: Reserved */
|
||||
#define SDMMC_AC12ERR_EXECUTE_TUNING (1 << 22) /* Bit 22: Execute Tuning */
|
||||
#define SDMMC_AC12ERR_SMP_CLK_SEL (1 << 23) /* Bit 23: Sample clock sel */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* Host Controller Capabilities */
|
||||
|
||||
#define SDMMC_HTCAPBLT_SDR50 (1 << 0) /* Bit 0: SDR50 support indication */
|
||||
#define SDMMC_HTCAPBLT_SDR104 (1 << 1) /* Bit 1: SDR104 support indication */
|
||||
#define SDMMC_HTCAPBLT_DDR50 (1 << 2) /* Bit 2: DDR50 support indication */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define SDMMC_HTCAPBLT_TCR_SHIFT (8) /* Bits 8-11: Time count retuning */
|
||||
#define SDMMC_HTCAPBLT_TCR_MASK (0xF << SDMMC_HTCAPBLT_TCR_SHIFT)
|
||||
# define SDMMC_HTCAPBLT_TCR(n) ((n) << SDMMC_HTCAPBLT_TCR_SHIFT)
|
||||
#define SDMMC_HTCAPBLT_USE_TUNING_SDR50 (1 << 13) /* Bit 13: Use tuning for SDR50 */
|
||||
#define SDMMC_HTCAPBLT_RET_MODE_SHIFT (14) /* bit 14-15: Retuning mode */
|
||||
#define SDMMC_HTCAPBLT_RET_MODE_MASK (3<<SDHC_HTCAPBLT_RET_MODE_SHIFT)
|
||||
#define SDMMC_HTCAPBLT_RET_MODE_1 (0<<SDHC_HTCAPBLT_RET_MODE_SHIFT)
|
||||
#define SDMMC_HTCAPBLT_RET_MODE_2 (1<<SDHC_HTCAPBLT_RET_MODE_SHIFT)
|
||||
#define SDMMC_HTCAPBLT_RET_MODE_3 (2<<SDHC_HTCAPBLT_RET_MODE_SHIFT)
|
||||
#define SDMMC_HTCAPBLT_MBL_SHIFT (16) /* Bits 16-18: Max Block Length */
|
||||
#define SDMMC_HTCAPBLT_MBL_MASK (7 << SDMMC_HTCAPBLT_MBL_SHIFT)
|
||||
# define SDMMC_HTCAPBLT_MBL_512BYTES (0 << SDMMC_HTCAPBLT_MBL_SHIFT)
|
||||
# define SDMMC_HTCAPBLT_MBL_1KB (1 << SDMMC_HTCAPBLT_MBL_SHIFT)
|
||||
# define SDMMC_HTCAPBLT_MBL_2KB (2 << SDMMC_HTCAPBLT_MBL_SHIFT)
|
||||
# define SDMMC_HTCAPBLT_MBL_4KB (3 << SDMMC_HTCAPBLT_MBL_SHIFT)
|
||||
/* Bit 19: Reserved */
|
||||
#define SDMMC_HTCAPBLT_ADMAS (1 << 20) /* Bit 20: ADMA Support */
|
||||
#define SDMMC_HTCAPBLT_HSS (1 << 21) /* Bit 21: High Speed Support */
|
||||
#define SDMMC_HTCAPBLT_DMAS (1 << 22) /* Bit 22: DMA Support */
|
||||
#define SDMMC_HTCAPBLT_SRS (1 << 23) /* Bit 23: Suspend/Resume Support */
|
||||
#define SDMMC_HTCAPBLT_VS33 (1 << 24) /* Bit 24: Voltage Support 3.3 V */
|
||||
#define SDMMC_HTCAPBLT_VS30 (1 << 25) /* Bit 25: Voltage Support 3.0 V */
|
||||
#define SDMMC_HTCAPBLT_VS18 (1 << 26) /* Bit 26: Voltage Support 1.8 */
|
||||
/* Bits 27-31: Reserved */
|
||||
|
||||
/* Capabilities 0 Register */
|
||||
|
||||
/* Capabilities 1 Register */
|
||||
|
||||
/* Force Event Register */
|
||||
|
||||
#define SDMMC_FEVT_AC12NE (1 << 0) /* Bit 0: Force Event Auto Command 12 Not Executed */
|
||||
#define SDMMC_FEVT_AC12TOE (1 << 1) /* Bit 1: Force Event Auto Command 12 Time Out Error */
|
||||
#define SDMMC_FEVT_AC12CE (1 << 2) /* Bit 2: Force Event Auto Command 12 CRC Error */
|
||||
#define SDMMC_FEVT_AC12EBE (1 << 3) /* Bit 3: Force Event Auto Command 12 End Bit Error */
|
||||
#define SDMMC_FEVT_AC12IE (1 << 4) /* Bit 4: Force Event Auto Command 12 Index Error */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define SDMMC_FEVT_CNIBAC12E (1 << 7) /* Bit 7: Force Event Command Not Executed By Auto Command 12 Error */
|
||||
/* Bits 8-15: Reserved */
|
||||
#define SDMMC_FEVT_CTOE (1 << 16) /* Bit 16: Force Event Command Time Out Error */
|
||||
#define SDMMC_FEVT_CCE (1 << 17) /* Bit 17: Force Event Command CRC Error */
|
||||
#define SDMMC_FEVT_CEBE (1 << 18) /* Bit 18: Force Event Command End Bit Error */
|
||||
#define SDMMC_FEVT_CIE (1 << 19) /* Bit 19: Force Event Command Index Error */
|
||||
#define SDMMC_FEVT_DTOE (1 << 20) /* Bit 20: Force Event Data Time Out Error */
|
||||
#define SDMMC_FEVT_DCE (1 << 21) /* Bit 21: Force Event Data CRC Error */
|
||||
#define SDMMC_FEVT_DEBE (1 << 22) /* Bit 22: Force Event Data End Bit Error */
|
||||
/* Bit 23: Reserved */
|
||||
#define SDMMC_FEVT_AC12E (1 << 24) /* Bit 24: Force Event Auto Command 12 Error */
|
||||
/* Bit 25: Reserved */
|
||||
#define SDMMC_FEVT_TTNE (1 << 26) /* Bit 26: Force tuning error */
|
||||
/* Bit 27: reserved */
|
||||
#define SDMMC_FEVT_DMAE (1 << 28) /* Bit 28: Force Event DMA Error */
|
||||
/* Bits 29-30: Reserved */
|
||||
#define SDMMC_FEVT_CINT (1 << 31) /* Bit 31: Force Event Card Interrupt */
|
||||
|
||||
/* ADMA Error Status Register */
|
||||
|
||||
#define SDMMC_ADMAES_SHIFT (0) /* Bits 0-1: ADMA Error State (when ADMA Error is occurred) */
|
||||
#define SDMMC_ADMAES_MASK (3 << SDMMC_ADMAES_ADMAES_SHIFT)
|
||||
# define SDMMC_ADMAES_STOP (0 << SDMMC_ADMAES_ADMAES_SHIFT) /* Stop DMA */
|
||||
# define SDMMC_ADMAES_FDS (1 << SDMMC_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */
|
||||
# define SDMMC_ADMAES_CADR (2 << SDMMC_ADMAES_ADMAES_SHIFT) /* Change address */
|
||||
# define SDMMC_ADMAES_TFR (3 << SDMMC_ADMAES_ADMAES_SHIFT) /* Transfer data */
|
||||
#define SDMMC_ADMAES_LME (1 << 2) /* Bit 2: ADMA Length Mismatch Error */
|
||||
#define SDMMC_ADMAES_DCE (1 << 3) /* Bit 3: ADMA Descriptor Error */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* ADMA System Address Register */
|
||||
|
||||
#define SDMMC_ADSADDR_SHIFT (0) /* Bits 1-31: ADMA System Address */
|
||||
#define SDMMC_ADSADDR_MASK (0xfffffffc) /* Bits 0-1: Reserved */
|
||||
|
||||
/* Delay Line Control */
|
||||
|
||||
#define SDMMC_DL_CTRL_EN (1 << 0) /* Bit 0: Delay Line enable */
|
||||
#define SDMMC_DL_CTRL_RST (1 << 1) /* Bit 1: Delay line reset */
|
||||
#define SDMMC_DL_CTRL_SLV_FORCE_UP (1 << 2) /* Bit 2: SLV Force update */
|
||||
#define SDMMC_DL_SLV_DLY_TGT0_SHIFT (3) /* Bits 3-6: Delay Target 0 */
|
||||
#define SDMMC_DL_SLV_DLY_TGT0_MASK (0xf << SDMMC_DL_SLV_DLY_TGT0_SHIFT)
|
||||
# define SDMMC_DL_SLV_DLY_TGT0(n) ((n) << SDMMC_DL_SLV_DLY_TGT0_SHIFT)
|
||||
#define SDMMC_DL_CTRL_SLV_UPD (1 << 7) /* Bit 7: Delay Control Gate update */
|
||||
#define SDMMC_DL_CTRL_SLV_OVR (1 << 8) /* Bit 8: Delay Control Gate override */
|
||||
#define SDMMC_DL_CTRL_OVR_VAL_SHIFT (9) /* Bits 9-15: Override Value */
|
||||
#define SDMMC_DL_CTRL_OVR_VAL_MASK (0x7f << SDMMC_DL_CTRL_OVR_VAL_SHIFT)
|
||||
# define SDMMC_DL_CTRL_OVR_VAL(n) ((n) << SDMMC_DL_CTRL_OVR_VAL_SHIFT)
|
||||
#define SDMMC_DL_SLV_DLY_TGT1_SHIFT (16) /* Bits 16-18: Delay Target 1 */
|
||||
#define SDMMC_DL_SLV_DLY_TGT1_MASK (0x7 << SDMMC_DL_SLV_DLY_TGT1_SHIFT)
|
||||
# define SDMMC_DL_SLV_DLY_TGT1(n) ((n) << SDMMC_DL_SLV_DLY_TGT1_SHIFT)
|
||||
/* Bit 19: Reserved */
|
||||
#define SDMMC_DL_CTRL_SLV_UPDINT_SHIFT (20) /* Bits 20-27: DLL Control SLV Update Interval */
|
||||
#define SDMMC_DL_CTRL_SLV_UPDINT_MASK (0xff << SDMMC_DL_CTRL_SLV_UPDINT_SHIFT)
|
||||
# define SDMMC_DL_CTRL_SLV_UPDINT(n) ((n) << SDMMC_DL_CTRL_SLV_UPDINT_SHIFT)
|
||||
#define SDMMC_DL_CTRL_REF_UPDINT_SHIFT (28) /* Bits 28-31: DLL Control Reference Update Interval */
|
||||
#define SDMMC_DL_CTRL_REF_UPDINT_MASK (0xf << SDMMC_DL_CTRL_REF_UPDINT_SHIFT)
|
||||
# define SDMMC_DL_CTRL_REF_UPDINT(n) ((n)<< SDMMC_DL_CTRL_REF_UPDINT_SHIFT)
|
||||
|
||||
/* Delay Line Status */
|
||||
|
||||
#define SDMMC_DL_STAT_SLV_LOCK (1 << 0) /* Bit 0: Slave delay-line lock status */
|
||||
#define SDMMC_DL_STAT_REF_LOCK (1 << 1) /* Bit 1: Reference delay-line lock status */
|
||||
#define SDMMC_DL_STAT_SLV_SEL_SHIFT (2) /* Bits 2-8: Slave delay line select status */
|
||||
#define SDMMC_DL_STAT_SLV_SEL_MASK (0x7f << SDMMC_DL_STAT_SLV_SEL_SHIFT)
|
||||
# define SDMMC_DL_STAT_SLV_SEL(n) ((n) << SDMMC_DL_STAT_SLV_SEL_SHIFT)
|
||||
#define SDMMC_DL_STAT_REF_SEL_SHIFT (9) /* Bits 9-15: Reference delay line select taps */
|
||||
#define SDMMC_DL_STAT_REF_SEL_MASK (0x7f << SDMMC_DL_STAT_REF_SEL_SHIFT)
|
||||
# define SDMMC_DL_STAT_REF_SEL(n) ((n) << SDMMC_DL_STAT_REF_SEL_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Tuning Control Register */
|
||||
|
||||
#define SDMMC_TC_SMPLPT_MASK (1 << 0) /* Bit 0: Sampling Point */
|
||||
#define SDMMC_TC_SMPLPT_50_PCT (0 << 0) /* Sampling Point at 50% of window */
|
||||
#define SDMMC_TC_SMPLPT_75_PCT (1 << 0) /* Sampling Point at 75% of window */
|
||||
|
||||
/* Host Version Register */
|
||||
|
||||
#define SDMMC_SPEC_1 0
|
||||
#define SDMMC_SPEC_2 1
|
||||
#define SDMMC_SPEC_3 2
|
||||
#define SDMMC_MAX_DIV_SPEC_2 256
|
||||
#define SDMMC_MAX_DIV_SPEC_3 2046
|
||||
|
||||
/* Software Reset Register */
|
||||
#define SDMMC_RESET_ALL 0x01
|
||||
#define SDMMC_RESET_CMD 0x02
|
||||
#define SDMMC_RESET_DATA 0x04
|
||||
|
||||
/* Host Control 2 Register */
|
||||
#define SDMMC_UHSMS_MASK (7) /* Bits 0-2: UHS Mode Select */
|
||||
#define SDMMC_VS18EN (1 << 3) /* Bit 3: 1.8V Signaling Enable */
|
||||
#define SDMMC_DRVSEL_MASK (0x3 << 4) /* Driver Strength Select */
|
||||
#define SDMMC_EXTUN (1 << 6) /* Bit 6: Execute Tuning */
|
||||
#define SDMMC_SCLKSEL (1 << 7) /* Bit 7: Sampling Clock Select */
|
||||
#define SDMMC_ASINTEN (1 << 14) /* Bit 14: Asynchronous Interrupt Enable*/
|
||||
#define SDMMC_PVALEN (1 << 15) /* Bit 15: Preset Value Enable */
|
||||
|
||||
/* Host Control 2 Register */
|
||||
#define SDMMC_H2CR_UHS_MASK (0x0007)
|
||||
#define SDMMC_H2CR_UHS_SDR12 (0x0000)
|
||||
#define SDMMC_H2CR_UHS_SDR25 (0x0001)
|
||||
#define SDMMC_H2CR_UHS_SDR50 (0x0002)
|
||||
#define SDMMC_H2CR_UHS_SDR104 (0x0003)
|
||||
#define SDMMC_H2CR_UHS_DDR50 (0x0004)
|
||||
#define SDMMC_H2CR_HS400 (0x0005) /* Non-standard */
|
||||
#define SDMMC_H2CR_VDD_180 (0x0008)
|
||||
#define SDMMC_H2CR_DRV_TYPE_MASK (0x0030)
|
||||
#define SDMMC_H2CR_DRV_TYPE_B (0x0000)
|
||||
#define SDMMC_H2CR_DRV_TYPE_A (0x0010)
|
||||
#define SDMMC_H2CR_DRV_TYPE_C (0x0020)
|
||||
#define SDMMC_H2CR_DRV_TYPE_D (0x0030)
|
||||
#define SDMMC_H2CR_EXEC_TUNING (0x0040)
|
||||
#define SDMMC_H2CR_TUNED_CLK (0x0080)
|
||||
#define SDMMC_H2CR_PRESET_VAL_ENABLE (0x8000)
|
||||
|
||||
/* SDMMC bus modes */
|
||||
|
||||
enum bus_mode
|
||||
{
|
||||
MMC_LEGACY,
|
||||
SD_LEGACY,
|
||||
MMC_HS,
|
||||
SD_HS,
|
||||
MMC_HS_52,
|
||||
MMC_DDR_52,
|
||||
UHS_SDR12, /* Single data rate, 12Mhz - default */
|
||||
UHS_SDR25, /* Single data rate, 25Mhz */
|
||||
UHS_SDR50, /* Single data rate, 50Mhz */
|
||||
UHS_DDR50, /* Double data rate, 50Mhz */
|
||||
UHS_SDR104, /* Single data rate, 100Mhz */
|
||||
MMC_HS_200,
|
||||
MMC_HS_400,
|
||||
MMC_HS_400_ES,
|
||||
MMC_MODES_END
|
||||
};
|
||||
|
||||
/* MMC Power */
|
||||
|
||||
#define MMCSD_VDD_19_20 ((uint32_t)1 << 7) /* VDD voltage 1.9 - 2.0 */
|
||||
#define MMCSD_VDD_29_30 ((uint32_t)1 << 17) /* VDD voltage 2.9-3.0 */
|
||||
#define MMCSD_VDD_30_31 ((uint32_t)1 << 18) /* VDD voltage 3.0-3.1 */
|
||||
#define MMCSD_VDD_32_33 ((uint32_t)1 << 20) /* VDD voltage 3.2-3.3 */
|
||||
#define MMCSD_VDD_33_34 ((uint32_t)1 << 21) /* VDD voltage 3.3-3.4 */
|
||||
|
||||
/* SDMMC bus speed for IDMODE transfers */
|
||||
|
||||
#define SAMA5_SDMMC_BUS_SPEED_IDMODE 400000
|
||||
|
||||
/* SDMMC bus speed threshold for high-speed mode transfers-
|
||||
* above this we need to set SDMMC_PROCTL_HSEN bit
|
||||
*/
|
||||
|
||||
#define SAMA5_SDMMC_BUS_HIGH_SPEED_THRESHOLD 26000000
|
||||
|
||||
/* SDMMC maximum bus speed - only used if SD Card supports this speed;
|
||||
* DDR (double data rate) signaling on rising and falling edges of the clock
|
||||
* will also be used if card supports it.
|
||||
*
|
||||
* DDR50 in widebus mode = 400 megabits/s
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SAMA5_SDMMC_50MHZ
|
||||
# define SAMA5_SDMMC_BUS_SPEED 50000000
|
||||
#else
|
||||
# define SAMA5_SDMMC_BUS_SPEED 25000000
|
||||
#endif
|
||||
|
||||
/* SDMA default buffer size - needed to reset the start address after an SDMA
|
||||
* Buffer Boundary pause event.
|
||||
*/
|
||||
|
||||
#define SDMMC_DEFAULT_BOUNDARY_SIZE (512 * 1024)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAMA5_SDMMC_H */
|
||||
619
arch/arm/src/sama5/hardware/sama5d2_sdmmc.h
Normal file
619
arch/arm/src/sama5/hardware/sama5d2_sdmmc.h
Normal file
|
|
@ -0,0 +1,619 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/sama5/hardware/sama5d2_sdmmc.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org> & Contributors
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAMA5D2_SDMMC_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAMA5D2_SDMMC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define SAMA5D2_SDMMC_SSAR_OFFSET 0x0000 /* SDMA System Address / Argument 2 Register */
|
||||
#define SAMA5D2_SDMMC_BSR_OFFSET 0x0004 /* Block Size Register */
|
||||
#define SAMA5D2_SDMMC_BCR_OFFSET 0x0006 /* Block Count Register */
|
||||
#define SAMA5D2_SDMMC_ARG1R_OFFSET 0x0008 /* Argument 1 Register */
|
||||
#define SAMA5D2_SDMMC_TMR_OFFSET 0x000c /* Transfer Mode Register */
|
||||
#define SAMA5D2_SDMMC_CR_OFFSET 0x000e /* Command Register */
|
||||
#define SAMA5D2_SDMMC_RR0_OFFSET 0x0010 /* Response Register 0 */
|
||||
#define SAMA5D2_SDMMC_RR1_OFFSET 0x0014 /* Response Register 1 */
|
||||
#define SAMA5D2_SDMMC_RR2_OFFSET 0x0018 /* Response Register 2 */
|
||||
#define SAMA5D2_SDMMC_RR3_OFFSET 0x001c /* Response Register 3 */
|
||||
#define SAMA5D2_SDMMC_BDPR_OFFSET 0x0020 /* Buffer Data Port Register */
|
||||
#define SAMA5D2_SDMMC_PSR_OFFSET 0x0024 /* Present State Register */
|
||||
#define SAMA5D2_SDMMC_HCR1_OFFSET 0x0028 /* Host Control 1 Register */
|
||||
#define SAMA5D2_SDMMC_PR_OFFSET 0x0029 /* Power Control Register */
|
||||
#define SAMA5D2_SDMMC_BGCR_OFFSET 0x002a /* Block Gap Control Register */
|
||||
#define SAMA5D2_SDMMC_WCR_OFFSET 0x002b /* Wakeup Control Register */
|
||||
#define SAMA5D2_SDMMC_CCR_OFFSET 0x002c /* Clock Control Register */
|
||||
#define SAMA5D2_SDMMC_TCR_OFFSET 0x002e /* Timeout Control Register */
|
||||
#define SAMA5D2_SDMMC_SRR_OFFSET 0x002f /* Software Reset Register */
|
||||
#define SAMA5D2_SDMMC_NISTR_OFFSET 0x0030 /* Normal Interrupt Status Register */
|
||||
#define SAMA5D2_SDMMC_EISTR_OFFSET 0x0032 /* Error Interrupt Status Register */
|
||||
#define SAMA5D2_SDMMC_NISTER_OFFSET 0x0034 /* Normal Interrupt Status Enable Register */
|
||||
#define SAMA5D2_SDMMC_EISTER_OFFSET 0x0036 /* Error Interrupt Status Enable Register */
|
||||
#define SAMA5D2_SDMMC_NISIER_OFFSET 0x0038 /* Normal Interrupt Signal Enable Register */
|
||||
#define SAMA5D2_SDMMC_EISIER_OFFSET 0x003a /* Error Interrupt Signal Enable Register */
|
||||
#define SAMA5D2_SDMMC_ACESR_OFFSET 0x003c /* Auto CMD Error Status Register */
|
||||
#define SAMA5D2_SDMMC_HC2R_OFFSET 0x003e /* Host Control 2 Register */
|
||||
#define SAMA5D2_SDMMC_CA0R_OFFSET 0x0040 /* Capabilities 0 Register */
|
||||
#define SAMA5D2_SDMMC_CA1R_OFFSET 0x0044 /* Capabilities 1 Register */
|
||||
#define SAMA5D2_SDMMC_MCCAR_OFFSET 0x0048 /* Maximum Current Capabilities Register */
|
||||
#define SAMA5D2_SDMMC_FERACES_OFFSET 0x0050 /* Force Event Register for Auto CMD Error Status */
|
||||
#define SAMA5D2_SDMMC_FEREIS_OFFSET 0x0052 /* Force Event Register for Error Interrupt Status */
|
||||
#define SAMA5D2_SDMMC_AESR_OFFSET 0x0054 /* ADMA Error Status Register */
|
||||
#define SAMA5D2_SDMMC_ASAR0_OFFSET 0x0054 /* ADMA System Address Register 0 */
|
||||
#define SAMA5D2_SDMMC_PVRX_OFFSET(x) (0x60 + x * 0x02) /* Preset Value Register */
|
||||
#define SAMA5D2_SDMMC_PVR0_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(0) /* Initialization */
|
||||
#define SAMA5D2_SDMMC_PVR1_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(1) /* Default Speed */
|
||||
#define SAMA5D2_SDMMC_PVR2_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(2) /* High Speed */
|
||||
#define SAMA5D2_SDMMC_PVR3_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(3) /* SDR12 */
|
||||
#define SAMA5D2_SDMMC_PVR4_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(4) /* SDR25 */
|
||||
#define SAMA5D2_SDMMC_PVR5_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(5) /* SDR50 */
|
||||
#define SAMA5D2_SDMMC_PVR6_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(6) /* SDR104/HS200 */
|
||||
#define SAMA5D2_SDMMC_PVR7_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(7) /* DDR50 */
|
||||
#define SAMA5D2_SDMMC_SISR_OFFSET 0x00fc /* Slot Interrupt Status Register */
|
||||
#define SAMA5D2_SDMMC_HCVR_OFFSET 0x00fe /* Host Controller Version Register */
|
||||
#define SAMA5D2_SDMMC_APSR_OFFSET 0x0200 /* Additional Present State Register */
|
||||
#define SAMA5D2_SDMMC_MC1R_OFFSET 0x0204 /* e.MMC Control 1 Register */
|
||||
#define SAMA5D2_SDMMC_MC2R_OFFSET 0x0204 /* e.MMC Control 2 Register */
|
||||
#define SAMA5D2_SDMMC_ACR_OFFSET 0x0208 /* AHB Control Register */
|
||||
#define SAMA5D2_SDMMC_CC2R_OFFSET 0x020c /* Clock Control 2 Register */
|
||||
#define SAMA5D2_SDMMC_RTC1R_OFFSET 0x0210 /* Retuning Control 1 Register */
|
||||
#define SAMA5D2_SDMMC_RTC2R_OFFSET 0x0211 /* Retuning Control 2 Register */
|
||||
#define SAMA5D2_SDMMC_RTCVR_OFFSET 0x0214 /* Retuning Counter Value Register */
|
||||
#define SAMA5D2_SDMMC_RTISTER_OFFSET 0x0218 /* Retuning Interrupt Status Enable Register */
|
||||
#define SAMA5D2_SDMMC_RTISIER_OFFSET 0x0219 /* Retuning Interrupt Signal Enable Register */
|
||||
#define SAMA5D2_SDMMC_RTISTR_OFFSET 0x021c /* Retuning Interrupt Status Register */
|
||||
#define SAMA5D2_SDMMC_RTSSR_OFFSET 0x021d /* Retuning Status Slots Register */
|
||||
#define SAMA5D2_SDMMC_TUNCR_OFFSET 0x0220 /* Tuning Control Register */
|
||||
#define SAMA5D2_SDMMC_CACR_OFFSET 0x0230 /* Capabilities Control Register */
|
||||
#define SAMA5D2_SDMMC_CALCR_OFFSET 0x0240 /* Calibration Control Register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
/* For SDMMC0 ... */
|
||||
|
||||
#define SAMA5D2_SDMMC0_SSAR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_SSAR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_BSR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_BSR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_BCR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_BCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_ARG1R (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_ARG1R_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_TMR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_TMR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_CR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_CR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RR0 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RR0_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RR1 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RR1_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RR2 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RR2_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RR3 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RR3_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_BDPR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_BDPR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PSR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PSR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_HCR1 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_HCR1_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_BGCR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_BGCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_WCR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_WCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_CCR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_CCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_TCR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_TCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_SRR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_SRR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_NISTR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_NISTR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_EISTR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_EISTR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_NISTER (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_NISTER_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_EISTER (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_EISTER_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_NISIER (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_NISIER_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_EISIER (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_EISIER_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_ACESR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_ACESR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_HC2R (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_HC2R_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_CA0R (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_CA0R_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_CA1R (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_CA1R_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_MCCAR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_MCCAR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_FERACES (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_FERACES_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_FEREIS (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_FEREIS_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_AESR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_AESR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_ASAR0 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_ASAR0_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PVRX(x) (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PVRX_OFFSET(x))
|
||||
#define SAMA5D2_SDMMC0_PVR0 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PVR0_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PVR1 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PVR1_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PVR2 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PVR2_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PVR3 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PVR3_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PVR4 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PVR4_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PVR5 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PVR5_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PVR6 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PVR6_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_PVR7 (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_PVR7_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_SISR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_SISR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_HCVR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_HCVR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_APSR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_APSR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_MC1R (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_MC1R_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_MC2R (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_MC2R_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_ACR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_ACR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_CC2R (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_CC2R_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RTC1R (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RTC1R_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RTC2R (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RTC2R_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RTCVR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RTCVR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RTISTER (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RTISTER_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RTISIER (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RTISIER_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RTISTR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RTISTR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_RTSSR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_RTSSR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_TUNCR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_TUNCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_CACR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_CACR_OFFSET)
|
||||
#define SAMA5D2_SDMMC0_CALCR (SAM_SDMMC0_VBASE + SAMA5D2_SDMMC_CALCR_OFFSET)
|
||||
|
||||
/* For SDMMC1 ... */
|
||||
|
||||
#define SAMA5D2_SDMMC1_SSAR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_SSAR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_BSR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_BSR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_BCR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_BCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_ARG1R (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_ARG1R_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_TMR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_TMR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_CR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_CR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RR0 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RR0_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RR1 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RR1_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RR2 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RR2_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RR3 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RR3_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_BDPR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_BDPR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PSR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PSR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_HCR1 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_HCR1_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_BGCR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_BGCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_WCR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_WCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_CCR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_CCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_TCR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_TCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_SRR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_SRR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_NISTR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_NISTR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_EISTR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_EISTR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_NISTER (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_NISTER_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_EISTER (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_EISTER_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_NISIER (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_NISIER_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_EISIER (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_EISIER_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_ACESR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_ACESR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_HC2R (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_HC2R_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_CA0R (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_CA0R_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_CA1R (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_CA1R_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_MCCAR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_MCCAR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_FERACES (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_FERACES_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_FEREIS (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_FEREIS_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_AESR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_AESR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_ASAR0 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_ASAR0_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PVRX(x) (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PVRX_OFFSET(x))
|
||||
#define SAMA5D2_SDMMC1_PVR0 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PVR0_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PVR1 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PVR1_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PVR2 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PVR2_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PVR3 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PVR3_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PVR4 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PVR4_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PVR5 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PVR5_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PVR6 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PVR6_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_PVR7 (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_PVR7_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_SISR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_SISR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_HCVR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_HCVR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_APSR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_APSR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_MC1R (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_MC1R_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_MC2R (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_MC2R_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_ACR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_ACR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_CC2R (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_CC2R_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RTC1R (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RTC1R_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RTC2R (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RTC2R_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RTCVR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RTCVR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RTISTER (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RTISTER_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RTISIER (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RTISIER_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RTISTR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RTISTR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_RTSSR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_RTSSR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_TUNCR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_TUNCR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_CACR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_CACR_OFFSET)
|
||||
#define SAMA5D2_SDMMC1_CALCR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_CALCR_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *********************************************************/
|
||||
|
||||
/* Block Size Register (0x04) */
|
||||
|
||||
#define SDMMC_BSR_BLKSIZE_SHIFT (0) /* Bits 0-9: Transfer Block Size */
|
||||
#define SDMMC_BSR_BLKSIZE_MASK (0x3ff << SDMMC_BSR_SIZE_SHIFT)
|
||||
# define SDMMC_BSR_BLKSIZE(n) ((n & SDMMC_BSR_BLKSIZE_MASK) << SDMMC_BSR_BLKSIZE_SHIFT)
|
||||
|
||||
#define SDMMC_BSR_BOUNDARY_SHIFT (12) /* Bits 12-14: Buffer Boundary */
|
||||
# define SDMMC_BSR_BOUNDARY_4K (0 << SDMMC_BSR_BOUNDARY_SHIFT)
|
||||
# define SDMMC_BSR_BOUNDARY_8K (1 << SDMMC_BSR_BOUNDARY_SHIFT)
|
||||
# define SDMMC_BSR_BOUNDARY_16K (2 << SDMMC_BSR_BOUNDARY_SHIFT)
|
||||
# define SDMMC_BSR_BOUNDARY_32K (3 << SDMMC_BSR_BOUNDARY_SHIFT)
|
||||
# define SDMMC_BSR_BOUNDARY_64K (4 << SDMMC_BSR_BOUNDARY_SHIFT)
|
||||
# define SDMMC_BSR_BOUNDARY_128K (5 << SDMMC_BSR_BOUNDARY_SHIFT)
|
||||
# define SDMMC_BSR_BOUNDARY_256K (6 << SDMMC_BSR_BOUNDARY_SHIFT)
|
||||
# define SDMMC_BSR_BOUNDARY_512K (7 << SDMMC_BSR_BOUNDARY_SHIFT)
|
||||
|
||||
/* Block Count Register (0x06) */
|
||||
|
||||
#define SDMMC_BCR_BLKCNT_SHIFT (0) /* Bits 0-15: Blocks Count For Current Transfer */
|
||||
#define SDMMC_BCR_BLKCNT_MASK (0xffff << SDMMC_BCR_BLKCNT_SHIFT)
|
||||
# define SDMMC_BCR_BLKCNT(n) ((n) << SDMMC_BCR_BLKCNT_SHIFT)
|
||||
|
||||
/* Transfer Mode Register (0x0c) */
|
||||
|
||||
#define SDMMC_TMR_MSBSEL (1 << 5) /* Bit 5: Multi/Single Block Selection */
|
||||
#define SDMMC_TMR_DTDSEL (1 << 4) /* Bit 4: Data Transfer Direction Selection */
|
||||
#define SDMMC_TMR_ACMDEN_SHIFT (2)
|
||||
# define SDMMC_TMR_ACMDEN_DISABLED (0 << SDMMC_TMR_ACMDEN_SHIFT)
|
||||
# define SDMMC_TMR_ACMDEN_CMD12 (1 << SDMMC_TMR_ACMDEN_SHIFT)
|
||||
# define SDMMC_TMR_ACMDEN_CMD23 (2 << SDMMC_TMR_ACMDEN_SHIFT)
|
||||
#define SDMMC_TMR_BCEN (1 << 1) /* Bit 1: Block Count Enable */
|
||||
#define SDMMC_TMR_DMAEN (1 << 0) /* Bit 0: DMA Enable */
|
||||
#define SDMMC_TMR_SINGLE (0)
|
||||
#define SDMMC_TMR_INFINITE (SDMMC_TMR_MSBSEL)
|
||||
#define SDMMC_TMR_MULTIPLE (SDMMC_TMR_MSBSEL | SDMMC_TMR_BCEN)
|
||||
|
||||
/* Command Register (0x0e) */
|
||||
|
||||
#define SDMMC_CR_RSPTYP_SHIFT (0) /* Bits 0-1: Response Type Select */
|
||||
#define SDMMC_CR_RSPTYP_MASK (3 << SDMMC_CR_RSPTYP_SHIFT)
|
||||
# define SDMMC_CR_RSPTYP_NORESP (0 << SDMMC_CR_RSPTYP_SHIFT) /* No response */
|
||||
# define SDMMC_CR_RSPTYP_RL136 (1 << SDMMC_CR_RSPTYP_SHIFT) /* Response length 136 */
|
||||
# define SDMMC_CR_RSPTYP_RL48 (2 << SDMMC_CR_RSPTYP_SHIFT) /* Response length 48 */
|
||||
# define SDMMC_CR_RSPTYP_RL48BUSY (3 << SDMMC_CR_RSPTYP_SHIFT) /* Response length 48 with Busy */
|
||||
|
||||
#define SDMMC_CR_CMDCCCEN (1 << 3) /* Bit 3: Command CRC Check Enable */
|
||||
#define SDMMC_CR_CMDCICEN (1 << 4) /* Bit 4: Command Index Check Enable */
|
||||
#define SDMMC_CR_DPSEL (1 << 5) /* Bit 5: Data Present Select */
|
||||
#define SDMMC_CR_CMDTYP_SHIFT (6) /* Bits 6-7: Command Type */
|
||||
#define SDMMC_CR_CMDTYP_MASK (3 << SDMMC_CR_CMDTYP_SHIFT)
|
||||
# define SDMMC_CR_CMDTYP_NORMAL (0 << SDMMC_CR_CMDTYP_SHIFT) /* Other commands */
|
||||
# define SDMMC_CR_CMDTYP_SUSPEND (1 << SDMMC_CR_CMDTYP_SHIFT) /* CMD52 to write "Bus Suspend" in CCCR */
|
||||
# define SDMMC_CR_CMDTYP_RESUME (2 << SDMMC_CR_CMDTYP_SHIFT) /* CMD52 to write "Function Select" in CCCR */
|
||||
# define SDMMC_CR_CMDTYP_ABORT (3 << SDMMC_CR_CMDTYP_SHIFT) /* CMD12, CMD52 to write "I/O Abort" in CCCR */
|
||||
#define SDMMC_CR_CMDINX_SHIFT (8) /* Bits 8-13: Command Index */
|
||||
#define SDMMC_CR_CMDINX_MASK (0x3f << SDMMC_CR_CMDINX_SHIFT)
|
||||
|
||||
/* Present State Register (0x24) */
|
||||
|
||||
#define SDMMC_PSR_CMDINHC (1 << 0) /* Bit 0: Command Inhibit (CMD) */
|
||||
#define SDMMC_PSR_CMDINHD (1 << 1) /* Bit 1: Command Inhibit (DAT) */
|
||||
#define SDMMC_PSR_DLACT (1 << 2) /* Bit 2: Data Line Active */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define SDMMC_PSR_WTACT (1 << 8) /* Bit 8: Write Transfer Active */
|
||||
#define SDMMC_PSR_RTACT (1 << 9) /* Bit 9: Read Transfer Active */
|
||||
#define SDMMC_PSR_BUFWREN (1 << 10) /* Bit 10: Buffer Write Enable */
|
||||
#define SDMMC_PSR_BUFRDEN (1 << 11) /* Bit 11: Buffer Read Enable */
|
||||
/* Bits 12-15: Reserved */
|
||||
#define SDMMC_PSR_CARDINS (1 << 16) /* Bit 16: Card Inserted */
|
||||
#define SDMMC_PSR_CARDSS (1 << 17) /* Bit 17: Card State Stable */
|
||||
#define SDMMC_PSR_CARDDPL (1 << 18) /* Bit 18: Card Detect Pin Level */
|
||||
#define SDMMC_PSR_WRPPL (1 << 19) /* Bit 19: Write Protect Pin Level */
|
||||
#define SDMMC_PSR_DATLL_SHIFT (20)
|
||||
#define SDMMC_PSR_DATLL_MASK (0x0f << SDMMC_PSR_DATLL_SHIFT)
|
||||
# define SDMMC_PSR_DATLL_DAT0 (0x01 << SDMMC_PSR_DATLL_SHIFT)
|
||||
# define SDMMC_PSR_DATLL_DAT1 (0x02 << SDMMC_PSR_DATLL_SHIFT)
|
||||
# define SDMMC_PSR_DATLL_DAT2 (0x04 << SDMMC_PSR_DATLL_SHIFT)
|
||||
# define SDMMC_PSR_DATLL_DAT3 (0x08 << SDMMC_PSR_DATLL_SHIFT)
|
||||
#define SDMMC_PSR_CMDLL (1 << 24) /* Bit 24: CMD Line Level */
|
||||
|
||||
/* Host Control 1 Register (0x28) */
|
||||
|
||||
#define SDMMC_HC1R_LEDCTRL (1 << 0) /* Bit 0: LED Control */
|
||||
#define SDMMC_HC1R_DW_SHIFT (1) /* Bit 1: Data Width */
|
||||
#define SDMMC_HC1R_DW_MASK (1 << SDMMC_HC1R_DW_SHIFT)
|
||||
# define SDMMC_HC1R_DW_1BIT (0 << SDMMC_HC1R_DW_SHIFT) /* 1-bit mode */
|
||||
# define SDMMC_HC1R_DW_4BIT (1 << SDMMC_HC1R_DW_SHIFT) /* 4-bit mode */
|
||||
#define SDMMC_H1CR_HSEN (1 << 2) /* Bit 2: High Speed Enable */
|
||||
#define SDMMC_H1CR_DMASEL_SHIFT (3) /* Bits 3-4: DMA Select */
|
||||
#define SDMMC_H1CR_DMASEL_MASK (3 << SDMMC_DMASEL_SHIFT)
|
||||
# define SDMMC_H1CR_DMASEL_SDMA (0 << SDMMC_DMASEL_SHIFT) /* SDMA is selected */
|
||||
# define SDMMC_H1CR_DMASEL_ADMA32 (2 << SDMMC_DMASEL_SHIFT) /* 32-bit Address ADMA2 is selected */
|
||||
#define SDMMC_H1CR_EXTDW (1 << 5) /* Bit 5: Extended Data Width (e.MMC) */
|
||||
#define SDMMC_H1CR_CARDDTL (1 << 6) /* Bit 6: Card Detect Test Level */
|
||||
#define SDMMC_H1CR_CARDDSEL (1 << 7) /* Bit 7: Card Detect Signal Selection */
|
||||
|
||||
/* Power Control Register (0x29) */
|
||||
|
||||
#define SDMMC_PCR_SDBPWR (1 << 0) /* Bit 0: SD Bus Power */
|
||||
|
||||
/* Block Gap Control Register (0x2a) */
|
||||
|
||||
#define SDMMC_BGCR_STPBGR (1 << 0) /* Bit 0: Stop At Block Gap Request */
|
||||
#define SDMMC_BGCR_CONTR (1 << 1) /* Bit 1: Continue Request */
|
||||
#define SDMMC_BGCR_RWCTRL (1 << 2) /* Bit 2: Read Wait Control */
|
||||
#define SDMMC_BGCR_INTBG (1 << 3) /* Bit 3: Interrupt at Block Gap */
|
||||
|
||||
/* Wakeup Control Register (0x2b) */
|
||||
|
||||
#define SDMMC_WCR_WKENCINT (1 << 0) /* Bit 0: Wakeup Event Enable on Card Interrupt */
|
||||
#define SDMMC_WCR_WKENCINS (1 << 1) /* Bit 1: Wakeup Event Enable on Card Insertion */
|
||||
#define SDMMC_WCR_WKENCREM (1 << 2) /* Bit 2: Wakeup Event Enable on Card Removal */
|
||||
|
||||
/* Clock Control Register (0x2c) */
|
||||
|
||||
#define SDMMC_CCR_INTCLKEN (1 << 0) /* Bit 0: Internal Clock Enable */
|
||||
#define SDMMC_CCR_INTCLKS (1 << 1) /* Bit 1: Internal Clock Stable */
|
||||
#define SDMMC_CCR_SDCLKEN (1 << 2) /* Bit 2: SD Clock Enable */
|
||||
#define SDMMC_CCR_CLKGSEL (1 << 5) /* Bit 5: Clock Generator Select */
|
||||
#define SDMMC_CCR_USDCLKFSEL_SHIFT (6) /* Bits 6-7: Upper Bits of SDCLK Frequency Select */
|
||||
#define SDMMC_CCR_USDCLKFSEL_MASK (3 << SDMMC_CCR_USDCLKFSEL_SHIFT)
|
||||
#define SDMMC_CCR_SDCLKFSEL_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */
|
||||
#define SDMMC_CCR_SDCLKFSEL_MASK (0xff << SDMMC_CCR_SDCLKFSEL_SHIFT)
|
||||
# define SDMMC_CCR_SDCLKFSEL(n) (((n & 0xff) << SDMMC_CCR_SDCLKFSEL_SHIFT) | \
|
||||
((n & 0x300) >> 2))
|
||||
# define SDMMC_CCR_SDCLKFSEL_VAL(reg) (((reg & 0xff00) >> SDMMC_CCR_SDCLKFSEL_SHIFT) | \
|
||||
((reg & 0x0030) << 2))
|
||||
|
||||
/* Timeout Control Register (0x2e) */
|
||||
|
||||
#define SDMMC_TCR_DTCVAL_SHIFT (0) /* Bits 0-3: Data Timeout Counter Value */
|
||||
#define SDMMC_TCR_DTCVAL_MASK (0x0f << SDMMC_TCR_DTCVAL_SHIFT)
|
||||
# define SDMMC_TCR_DTCVAL(n) ((n & SDMMC_TCR_DTCVAL_MASK) << SDMMC_TCR_DTCVAL_SHIFT)
|
||||
|
||||
/* Software Reset Register (0x2f) */
|
||||
|
||||
#define SDMMC_SRR_SWRSTALL (1 << 0) /* Bit 0: Software Reset for All */
|
||||
#define SDMMC_SRR_SWRSTCMD (1 << 1) /* Bit 1: Software Reset for CMD Line */
|
||||
#define SDMMC_SRR_SWRSTDAT (1 << 2) /* Bit 2: Software Reset for DAT Line */
|
||||
|
||||
/* Normal Interrupt Status Register (0x30) */
|
||||
|
||||
#define SDMMC_NISTR_CMDC (1 << 0) /* Bit 0: Command Complete */
|
||||
#define SDMMC_NISTR_TRFC (1 << 1) /* Bit 1: Transfer Complete */
|
||||
#define SDMMC_NISTR_BLKGE (1 << 2) /* Bit 2: Block Gap Event */
|
||||
#define SDMMC_NISTR_DMAINT (1 << 3) /* Bit 3: DMA Interrupt */
|
||||
#define SDMMC_NISTR_BWRRDY (1 << 4) /* Bit 4: Buffer Write Ready */
|
||||
#define SDMMC_NISTR_BRDRDY (1 << 5) /* Bit 5: Buffer Read Ready */
|
||||
#define SDMMC_NISTR_CINS (1 << 6) /* Bit 6: Card Insertion */
|
||||
#define SDMMC_NISTR_CREM (1 << 7) /* Bit 7: Card Removal */
|
||||
#define SDMMC_NISTR_CINT (1 << 8) /* Bit 8: Card Interrupt */
|
||||
#define SDMMC_NISTR_BOOTAR (1 << 14) /* Bit 14: Boot Acknowledge Received (e.MMC) */
|
||||
#define SDMMC_NISTR_ERRINT (1 << 15) /* Bit 15: Error Interrupt */
|
||||
|
||||
/* Error Interrupt Status Register (0x32) */
|
||||
|
||||
#define SDMMC_EISTR_CMDTEO (1 << 0) /* Bit 0: Command TImeout Error */
|
||||
#define SDMMC_EISTR_CMDCRC (1 << 1) /* Bit 1: Command CRC Error */
|
||||
#define SDMMC_EISTR_CMDEND (1 << 2) /* Bit 2: Command End Bit Error */
|
||||
#define SDMMC_EISTR_CMDIDX (1 << 3) /* Bit 3: Command Index Error */
|
||||
#define SDMMC_EISTR_DATTEO (1 << 4) /* Bit 4: Data Timeout Error */
|
||||
#define SDMMC_EISTR_DATCRC (1 << 5) /* Bit 5: Data CRC Error */
|
||||
#define SDMMC_EISTR_DATEND (1 << 6) /* Bit 6: Data End Bit Error */
|
||||
#define SDMMC_EISTR_CURLIM (1 << 7) /* Bit 7: Current Limit Error */
|
||||
#define SDMMC_EISTR_ACMD (1 << 8) /* Bit 8: Auto CMD Error */
|
||||
#define SDMMC_EISTR_ADMA (1 << 9) /* Bit 9: ADMA Error */
|
||||
#define SDMMC_EISTR_BOOTAE (1 << 12) /* Bit 12: Boot Acknowledge Error (e.MMC) */
|
||||
|
||||
/* Normal Interrupt Status Enable Register (0x34) */
|
||||
|
||||
#define SDMMC_NISTER_CMDC (1 << 0) /* Bit 0: Command Complete Status Enable */
|
||||
#define SDMMC_NISTER_TRFC (1 << 1) /* Bit 1: Transfer Complete Status Enable */
|
||||
#define SDMMC_NISTER_BLKGE (1 << 2) /* Bit 2: Block Gap Event Status Enable */
|
||||
#define SDMMC_NISTER_DMAINT (1 << 3) /* Bit 3: DMA Interrupt Status Enable */
|
||||
#define SDMMC_NISTER_BWRRDY (1 << 4) /* Bit 4: Buffer Write Ready Status Enable */
|
||||
#define SDMMC_NISTER_BRDRDY (1 << 5) /* Bit 5: Buffer Read Ready Status Enable */
|
||||
#define SDMMC_NISTER_CINS (1 << 6) /* Bit 6: Card Insertion Status Enable */
|
||||
#define SDMMC_NISTER_CREM (1 << 7) /* Bit 7: Card Removal Status Enable */
|
||||
#define SDMMC_NISTER_CINT (1 << 8) /* Bit 8: Card Interrupt Status Enable */
|
||||
#define SDMMC_NISTER_BOOTAR (1 << 14) /* Bit 14: Boot Acknowledge Received Status Enable (e.MMC) */
|
||||
|
||||
/* Error Interrupt Status Enable Register (0x36) */
|
||||
|
||||
#define SDMMC_EISTER_CMDTEO (1 << 0) /* Bit 0: Command TImeout Error Status Enable */
|
||||
#define SDMMC_EISTER_CMDCRC (1 << 1) /* Bit 1: Command CRC Error Status Enable */
|
||||
#define SDMMC_EISTER_CMDEND (1 << 2) /* Bit 2: Command End Bit Error Status Enable */
|
||||
#define SDMMC_EISTER_CMDIDX (1 << 3) /* Bit 3: Command Index Error Status Enable */
|
||||
#define SDMMC_EISTER_DATTEO (1 << 4) /* Bit 4: Data Timeout Error Status Enable */
|
||||
#define SDMMC_EISTER_DATCRC (1 << 5) /* Bit 5: Data CRC Error Status Enable */
|
||||
#define SDMMC_EISTER_DATEND (1 << 6) /* Bit 6: Data End Bit Error Status Enable */
|
||||
#define SDMMC_EISTER_CURLIM (1 << 7) /* Bit 7: Current Limit Error Status Enable */
|
||||
#define SDMMC_EISTER_ACMD (1 << 8) /* Bit 8: Auto CMD Error Status Enable */
|
||||
#define SDMMC_EISTER_ADMA (1 << 9) /* Bit 9: ADMA Error Status Enable */
|
||||
#define SDMMC_EISTER_BOOTAE (1 << 12) /* Bit 12: Boot Acknowledge Error Status Enable (e.MMC) */
|
||||
|
||||
/* Normal Interrupt Signal Enable Register (0x38) */
|
||||
|
||||
#define SDMMC_NISIER_CMDC (1 << 0) /* Bit 0: Command Complete Signal Enable */
|
||||
#define SDMMC_NISIER_TRFC (1 << 1) /* Bit 1: Transfer Complete Signal Enable */
|
||||
#define SDMMC_NISIER_BLKGE (1 << 2) /* Bit 2: Block Gap Event Signal Enable */
|
||||
#define SDMMC_NISIER_DMAINT (1 << 3) /* Bit 3: DMA Interrupt Signal Enable */
|
||||
#define SDMMC_NISIER_BWRRDY (1 << 4) /* Bit 4: Buffer Write Ready Signal Enable */
|
||||
#define SDMMC_NISIER_BRDRDY (1 << 5) /* Bit 5: Buffer Read Ready Signal Enable */
|
||||
#define SDMMC_NISIER_CINS (1 << 6) /* Bit 6: Card Insertion Signal Enable */
|
||||
#define SDMMC_NISIER_CREM (1 << 7) /* Bit 7: Card Removal Signal Enable */
|
||||
#define SDMMC_NISIER_CINT (1 << 8) /* Bit 8: Card Interrupt Signal Enable */
|
||||
#define SDMMC_NISIER_BOOTAR (1 << 14) /* Bit 14: Boot Acknowledge Received Signal Enable (e.MMC) */
|
||||
|
||||
/* Error Interrupt Signal Enable Register (0x3a) */
|
||||
|
||||
#define SDMMC_EISIER_CMDTEO (1 << 0) /* Bit 0: Command TImeout Error Signal Enable */
|
||||
#define SDMMC_EISIER_CMDCRC (1 << 1) /* Bit 1: Command CRC Error Signal Enable */
|
||||
#define SDMMC_EISIER_CMDEND (1 << 2) /* Bit 2: Command End Bit Error Signal Enable */
|
||||
#define SDMMC_EISIER_CMDIDX (1 << 3) /* Bit 3: Command Index Error Signal Enable */
|
||||
#define SDMMC_EISIER_DATTEO (1 << 4) /* Bit 4: Data Timeout Error Signal Enable */
|
||||
#define SDMMC_EISIER_DATCRC (1 << 5) /* Bit 5: Data CRC Error Signal Enable */
|
||||
#define SDMMC_EISIER_DATEND (1 << 6) /* Bit 6: Data End Bit Error Signal Enable */
|
||||
#define SDMMC_EISIER_CURLIM (1 << 7) /* Bit 7: Current Limit Error Signal Enable */
|
||||
#define SDMMC_EISIER_ACMD (1 << 8) /* Bit 8: Auto CMD Error Signal Enable */
|
||||
#define SDMMC_EISIER_ADMA (1 << 9) /* Bit 9: ADMA Error Signal Enable */
|
||||
#define SDMMC_EISIER_BOOTAE (1 << 12) /* Bit 12: Boot Acknowledge Error Signal Enable (e.MMC) */
|
||||
|
||||
/* Auto CMD Error Status Register (0x3c) */
|
||||
#define SDMMC_ACESR_ACMD12NE (1 << 0) /* Bit 0: Auto CMD12 Not Executed */
|
||||
#define SDMMC_ACESR_ACMDTER (1 << 1) /* Bit 1: Auto Command Timeout Error */
|
||||
#define SDMMC_ACESR_ACMDCRC (1 << 2) /* Bit 2: Auto CMD CRC Error */
|
||||
#define SDMMC_ACESR_ACMDEND (1 << 3) /* Bit 3: Auto CMD End Bit Error */
|
||||
#define SDMMC_ACESR_ACMDIDX (1 << 4) /* Bit 4: Auto CMD Index Error */
|
||||
#define SDMMC_ACESR_CMDNI (1 << 7) /* Bit 7: Command Not Issued by Auto CMD12 Error */
|
||||
|
||||
/* Host Control 2 Register (0x3e) */
|
||||
#define SDMMC_HC2R_UHSMS_SHIFT (0) /* Bits 0-2: UHS Mode Select */
|
||||
#define SDMMC_HC2R_UHSMS_MASK (0x07 << SDMMC_HC2R_UHSMS_SHIFT)
|
||||
# define SDMMC_HC2R_UHSMS_SDR12 (0 << SDMMC_HC2R_UHSMS_SHIFT) /* UHS SDR12 Mode */
|
||||
# define SDMMC_HC2R_UHSMS_SDR25 (1 << SDMMC_HC2R_UHSMS_SHIFT) /* UHS SDR25 Mode */
|
||||
# define SDMMC_HC2R_UHSMS_SDR50 (2 << SDMMC_HC2R_UHSMS_SHIFT) /* UHS SDR50 Mode */
|
||||
# define SDMMC_HC2R_UHSMS_SDR104 (3 << SDMMC_HC2R_UHSMS_SHIFT) /* UHS SDR104 Mode */
|
||||
# define SDMMC_HC2R_UHSMS_DDR50 (4 << SDMMC_HC2R_UHSMS_SHIFT) /* UHS DDR50 Mode */
|
||||
#define SDMMC_HC2R_HS200EN_SHIFT (0) /* Bits 0-3: HS200 Mode Enable (e.MMC) */
|
||||
#define SDMMC_HC2R_HS200EN_MASK (0x0f << SDMMC_HC2R_HS200EN_SHIFT)
|
||||
# define SDMMC_HC2R_HS200EN_ENABLE (0x0b << SDMMC_HC2R_HS200EN_SHIFT) /* HS200 mode is enabled */
|
||||
#define SDMMC_HC2R_VS18EN (1 << 3) /* Bit 3: 1.8V Signaling Enable */
|
||||
#define SDMMC_HC2R_DRVSEL_SHIFT (4) /* Bits 4-5: Driver Strength Select */
|
||||
#define SDMMC_HC2R_DRVSEL_MASK (3 << SDMMC_HC2R_DRVSEL_SHIFT)
|
||||
# define SDMMC_HC2R_DRVSEL_TYPEB (0 << SDMMC_HC2R_DRVSEL_SHIFT) /* Driver Type B is selected (Default) */
|
||||
# define SDMMC_HC2R_DRVSEL_TYPEA (1 << SDMMC_HC2R_DRVSEL_SHIFT) /* Driver Type A is selected */
|
||||
# define SDMMC_HC2R_DRVSEL_TYPEC (2 << SDMMC_HC2R_DRVSEL_SHIFT) /* Driver Type C is selected */
|
||||
# define SDMMC_HC2R_DRVSEL_TYPED (3 << SDMMC_HC2R_DRVSEL_SHIFT) /* Driver Type D is selected */
|
||||
#define SDMMC_HC2R_EXTUN (1 << 6) /* Bit 6: Execute Tuning */
|
||||
#define SDMMC_HC2R_SCLKSEL (1 << 7) /* Bit 7: Sampling Clock Select */
|
||||
#define SDMMC_HC2R_ASINTEN (1 << 14) /* Bit 14: Asynchronous Interrupt Enable */
|
||||
#define SDMMC_HC2R_PVALEN (1 << 15) /* Bit 15: Preset Value Enable */
|
||||
|
||||
/* Capabilities 0 Register (0x40) */
|
||||
|
||||
#define SDMMC_CA0R_TEOCLKF_SHIFT (0) /* Bits 0-5: Timeout Clock Frequency */
|
||||
#define SDMMC_CA0R_TEOCLKF_MASK (0x3f << SDMMC_CA0R_TEOCLKF_SHIFT)
|
||||
#define SDMMC_CA0R_TEOCLKF(n) ((n &0x3f) << SDMMC_CA0R_TEOCLKF_SHIFT)
|
||||
#define SDMMC_CA0R_TEOCLKU (1 << 7) /* Bit 7: Timeout Clock Unit */
|
||||
#define SDMMC_CA0R_TEOCLKU_KHz (0 << 7) /* KHz */
|
||||
#define SDMMC_CA0R_TEOCLKU_MHz (1 << 7) /* MHz */
|
||||
#define SDMMC_CA0R_BASECLKF_SHIFT (8) /* Bits 8-15: Base Clock Frequency */
|
||||
#define SDMMC_CA0R_BASECLKF_MASK (0xf << SDMMC_BASECLKF_SHIFT)
|
||||
#define SDMMC_CA0R_BASECLKF(n) ((n & 0xf) << SDMMC_BASECLKF_SHIFT)
|
||||
#define SDMMC_CA0R_MAXBLKL_SHIFT (16) /* Bits 16-17: Max Block Length */
|
||||
#define SDMMC_CA0R_MAXBLKL_MASK (3 << SDMMC_CA0R_MAXBLKL_SHIFT)
|
||||
#define SDMMC_CA0R_MAXBLKL_512 (0 << SDMMC_CA0R_MAXBLKL_SHIFT) /* 512 bytes */
|
||||
#define SDMMC_CA0R_MAXBLKL_1024 (1 << SDMMC_CA0R_MAXBLKL_SHIFT) /* 1024 bytes */
|
||||
#define SDMMC_CA0R_MAXBLKL_2048 (2 << SDMMC_CA0R_MAXBLKL_SHIFT) /* 2048 bytes */
|
||||
#define SDMMC_CA0R_MAXBLKL_NONE (3 << SDMMC_CA0R_MAXBLKL_SHIFT) /* Reserved */
|
||||
#define SDMMC_CA0R_ED8SUP (1 << 18) /* Bit 18: 8-Bit Support for Embedded Device */
|
||||
#define SDMMC_CA0R_ADMA2SUP (1 << 19) /* Bit 19: ADMA2 Support */
|
||||
#define SDMMC_CA0R_HSSUP (1 << 21) /* Bit 21: High Speed Support */
|
||||
#define SDMMC_CA0R_SDMASUP (1 << 22) /* Bit 22: SDMA Support */
|
||||
#define SDMMC_CA0R_SRSUP (1 << 23) /* Bit 23: Suspend/Resume Support */
|
||||
#define SDMMC_CA0R_V33VSUP (1 << 24) /* Bit 24: Voltable Support 3.3V */
|
||||
#define SDMMC_CA0R_V30VSUP (1 << 25) /* Bit 25: Voltable Support 3.0V */
|
||||
#define SDMMC_CA0R_V18VSUP (1 << 26) /* Bit 26: Voltable Support 1.8V */
|
||||
#define SDMMC_CA0R_SB64SUP (1 << 28) /* Bit 28: 64-Bit System Bus Support */
|
||||
#define SDMMC_CA0R_ASINTSUP (1 << 29) /* Bit 29: Asynchronous Interrupt Support */
|
||||
#define SDMMC_CA0R_SLTYPE_SHIFT (30) /* Bits 30-31: Slot Type */
|
||||
#define SDMMC_CA0R_SLTYPE_MASK (3 << SDMMC_CA0R_SLTYPE_SHIFT)
|
||||
#define SDMMC_CA0R_SLTYPE_REMOVABLE (0 << SDMMC_CA0R_SLTYPE_SHIFT) /* Removable Card Slot */
|
||||
#define SDMMC_CA0R_SLTYPE_EMBEDDED (1 << SDMMC_CA0R_SLTYPE_SHIFT) /* Embedded Slot for One Device */
|
||||
|
||||
/* Capabilities 1 Register (0x44) */
|
||||
|
||||
#define SDMMC_CA1R_SDR50SUP (1 << 0) /* Bit 0: SDR50 Support */
|
||||
#define SDMMC_CA1R_SDR104SUP (1 << 1) /* Bit 1: SDR104 Support */
|
||||
#define SDMMC_CA1R_DDR50SUP (1 << 2) /* Bit 2: DDR50 Support */
|
||||
#define SDMMC_CA1R_DRVASUP (1 << 4) /* Bit 4: Driver Type A Support */
|
||||
#define SDMMC_CA1R_DRVCSUP (1 << 5) /* Bit 5: Driver Type C Support */
|
||||
#define SDMMC_CA1R_DRVDSUP (1 << 6) /* Bit 6: Driver Type D Support */
|
||||
#define SDMMC_CA1R_TCNTRT_SHIFT (8) /* Bits 8-11: Timer Count For Retuning */
|
||||
#define SDMMC_CA1R_TCNTRT_MASK (0x0f << SDMMC_CA1R_TCNTRT_SHIFT)
|
||||
#define SDMMC_CA1R_TCNTRT(n) ((n & 0x0f) << SDMMC_CA1R_TCNTRT_SHIFT)
|
||||
#define SDMMC_CA1R_TSDR50 (1 << 13) /* Bit 13: Use Tuning for SDR50 */
|
||||
#define SDMMC_CA1R_RTMOD_SHIFT (14) /* Bits 14-15: Retuning Modes */
|
||||
#define SDMMC_CA1R_RTMOD_MASK (3 << SDMMC_CA1R_RTMOD_SHIFT)
|
||||
#define SDMMC_CA1R_RTMOD_MODE1 (0 << SDMMC_CA1R_RTMOD_SHIFT) /* MODE1: Timer */
|
||||
#define SDMMC_CA1R_RTMOD_MODE2 (1 << SDMMC_CA1R_RTMOD_SHIFT) /* MODE2: Timer and Retuning Request */
|
||||
#define SDMMC_CA1R_RTMOD_MODE3 (2 << SDMMC_CA1R_RTMOD_SHIFT) /* MODE3: Auto Retuning Timer and Retuning Request */
|
||||
#define SDMMC_CA1R_CLKMULT_SHIFT (16) /* Bits 16-23: Clock Multiplier */
|
||||
#define SDMMC_CA1R_CLKMULT_MASK (0xf << SDMMC_CA1R_CLKMULT_SHIFT)
|
||||
#define SDMMC_CA1R_CLKMULT(n) ((n & 0xf) << SDMMC_CA1R_CLKMULT_SHIFT)
|
||||
|
||||
/* Preset Value Register (0x60 + x * 0x02 [x=0..7]) */
|
||||
|
||||
#define SDMMC_PVRx_SDCLKFSEL_SHIFT (0) /* Bits 0-9: SDCLK Frequency Select */
|
||||
#define SDMMC_PVRx_SDCLKFSEL_MASK (0x3f << SDMMC_PVRx_SDCLKFSEL_SHIFT)
|
||||
#define SDMMC_PVRx_SDCLKFSEL(n) ((n & 0x3f) << SDMMC_PVRx_SDCLKFSEL_SHIFT)
|
||||
#define SDMMC_PVRx_CLKGSEL (1 << 10) /* Bit 10: Clock Generator Select */
|
||||
#define SDMMC_PVRx_DRVSEL_SHIFT (14) /* Bits 14-15: Driver Strength Select */
|
||||
#define SDMMC_PVRx_DRVSEL_MASK (3 << SDMMC_PVRx_DRVSEL_SHIFT)
|
||||
#define SDMMC_PVRx_DRVSEL(n) ((n & 3) << SDMMC_PVRx_DRVSEL_SHIFT)
|
||||
|
||||
/* Slot Interrupt Status Register (0xfc) */
|
||||
|
||||
#define SDMMC_SISR_INTSSL0 (1 << 0) /* Bit 0: Interrupt Signal for Slot 0 */
|
||||
#define SDMMC_SISR_INTSSL1 (1 << 1) /* Bit 1: Interrupt Signal for Slot 1 */
|
||||
|
||||
/* Host Controller Version Register (0xfe) */
|
||||
|
||||
#define SDMMC_HCVR_SVER_SHIFT (0) /* Bits 0-7: Specification Version Number */
|
||||
#define SDMMC_HCVR_SVER_MASK (0xf << SDMMC_HCVR_SVER_SHIFT)
|
||||
#define SDMMC_HCVR_SVER(reg) ((reg & SDMMC_HCVR_SVER_MASK) >> SDMMC_HCVR_SVER_SHIFT)
|
||||
#define SDMMC_HCVR_VVER_SHIFT (8) /* Bits 8-15: Vendor Version Number */
|
||||
#define SDMMC_HCVR_VVER_MASK (0xf << SDMMC_HCVR_VVER_SHIFT)
|
||||
#define SDMMC_HCVR_VVER(reg) ((reg & SDMMC_HCVR_VVER_MASK) >> SDMMC_HCVR_VVER_SHIFT)
|
||||
|
||||
/* Additional Present State Register (0x200) */
|
||||
|
||||
#define SDMMC_APSR_HDATLL_SHIFT (0) /* Bits 0-3: DAT[7:4] High Line Level */
|
||||
#define SDMMC_APSR_HDATLL_MASK (0xf << SDMMC_APSR_HDATLL_SHIFT)
|
||||
#define SDMMC_APSR_HDATLL(reg) ((reg & SDMMC_APSR_HDATLL_MASK) >> SDMMC_APSR_HDATLL_SHIFT)
|
||||
|
||||
/* e.MMC Control 1 Register (0x204) */
|
||||
|
||||
#define SDMMC_MC1R_CMDTYPE_SHIFT (0) /* Bits 0-1: e.MMC Command Type */
|
||||
#define SDMMC_MC1R_CMDTYPE_MASK (3 << SDMMC_MC1R_CMDTYPE_SHIFT)
|
||||
#define SDMMC_MC1R_CMDTYPE_NORMAL (0 << SDMMC_MC1R_CMDTYPE_SHIFT)
|
||||
#define SDMMC_MC1R_CMDTYPE_WAITIRQ (1 << SDMMC_MC1R_CMDTYPE_SHIFT)
|
||||
#define SDMMC_MC1R_CMDTYPE_STREAM (2 << SDMMC_MC1R_CMDTYPE_SHIFT)
|
||||
#define SDMMC_MC1R_CMDTYPE_BOOT (3 << SDMMC_MC1R_CMDTYPE_SHIFT)
|
||||
#define SDMMC_MC1R_DDR (1 << 3) /* Bit 3: e.MMC HSDDR Mode */
|
||||
#define SDMMC_MC1R_OPD (1 << 4) /* Bit 4: e.MMC Open Drain Mode */
|
||||
#define SDMMC_MC1R_BOOTA (1 << 5) /* Bit 5: e.MMC Boot Acknowledge Mode */
|
||||
#define SDMMC_MC1R_RSTN (1 << 6) /* Bit 6: e.MMC Reset Signal */
|
||||
#define SDMMC_MC1R_FCD (1 << 7) /* Bit 7: e.MMC Force Card Detect */
|
||||
|
||||
/* e.MMC Control 2 Register (0x205) */
|
||||
|
||||
#define SDMMC_MC2R_SRESP (1 << 0) /* Bit 0: e.MMC Abort Wait IRQ */
|
||||
#define SDMMC_MC2R_ABOOT (1 << 1) /* Bit 1: e.MMC Abort Boot */
|
||||
|
||||
/* Capabilities Control Register (0x230) */
|
||||
|
||||
#define SDMMC_CACR_CAPWREN (1 << 0) /* Bit 0: Capabilities Write Enable */
|
||||
#define SDMMC_CACR_KEY_SHIFT (8) /* Bits 8-15: Key */
|
||||
#define SDMMC_CACR_KEY_MASK (0xff << SDMMC_CACR_KEY_SHIFT)
|
||||
#define SDMMC_CACR_KEY_ENABLE (0x46 << SDMMC_CACR_KEY_SHIFT)
|
||||
#define SDMMC_CACR_KEY_DISABLE (0x00 << SDMMC_CACR_KEY_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAMA5D2_SDMMC_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/sama5/sam_pmc.c
|
||||
* arch/arm/src/sama5/sam_hsmci_clkdiv.c
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
|
|
|
|||
|
|
@ -386,8 +386,10 @@ void sam_pioirq(pio_pinset_t pinset)
|
|||
#if defined(SAM_PIO_ISLR_OFFSET)
|
||||
uint32_t regval;
|
||||
#endif
|
||||
#if defined(SAM_PIO_ISLR_OFFSET) || defined(_PIO_INT_AIM)
|
||||
uint32_t base = sam_piobase(pinset);
|
||||
int pin = sam_piopin(pinset);
|
||||
#endif
|
||||
|
||||
#if defined(SAM_PIO_ISLR_OFFSET)
|
||||
/* Enable writing to PIO registers. The following registers are protected:
|
||||
|
|
|
|||
3859
arch/arm/src/sama5/sam_sdmmc.c
Normal file
3859
arch/arm/src/sama5/sam_sdmmc.c
Normal file
File diff suppressed because it is too large
Load diff
142
arch/arm/src/sama5/sam_sdmmc.h
Normal file
142
arch/arm/src/sama5/sam_sdmmc.h
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/sama5/sam_sdmmc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_SDMMC_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_SDMMC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/sam_sdmmc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_sdmmc_set_sdio_card_isr
|
||||
*
|
||||
* Description:
|
||||
* SDIO card generates interrupt via SDIO_DATA_1 pin.
|
||||
* Called by board-specific logic to register an ISR for SDIO card.
|
||||
*
|
||||
* Input Parameters:
|
||||
* func - callback function.
|
||||
* arg - arg to be passed to the function.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_sdmmc_set_sdio_card_isr(FAR struct sdio_dev_s *dev,
|
||||
int (*func)(void *), void *arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_sdmmc_sdio_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SDMMC for operation.
|
||||
*
|
||||
* Input Parameters:
|
||||
* slotno - Not used.
|
||||
*
|
||||
* Returned Value:
|
||||
* A reference to a SDIO interface structure. NULL is returned on
|
||||
* failures.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct sdio_dev_s *sam_sdmmc_sdio_initialize(int slotno);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_mediachange
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic -- possibly from an interrupt handler --
|
||||
* in order to signal to the driver that a card has been inserted or
|
||||
* removed from the slot
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* cardinslot - true is a card has been detected in the slot; false if a
|
||||
* card has been removed from the slot. Only transitions
|
||||
* (inserted->removed or removed->inserted should be reported)
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_wrprotect
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic to report if the card in the slot is
|
||||
* mechanically write protected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* wrprotect - true is a card is writeprotected.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SDMMC_H */
|
||||
|
|
@ -85,6 +85,7 @@
|
|||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/* An opaque handle used to represent a timer channel */
|
||||
|
||||
typedef void *TC_HANDLE;
|
||||
|
|
@ -216,7 +217,7 @@ tc_handler_t sam_tc_attach(TC_HANDLE handle, tc_handler_t handler,
|
|||
* Name: sam_tc_getpending
|
||||
*
|
||||
* Description:
|
||||
* Return the current contents of the interrutp status register, clearing
|
||||
* Return the current contents of the interrupt status register, clearing
|
||||
* all pending interrupts.
|
||||
*
|
||||
* Input Parameters:
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
|
|
@ -110,6 +110,7 @@ const uintptr_t g_spiobase[SAM_NPIO] =
|
|||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* Maps a port number to the standard port character */
|
||||
|
||||
#if defined(CONFIG_DEBUG_GPIO_INFO) && SAM_NPIO > 0
|
||||
|
|
@ -131,6 +132,7 @@ static const char g_portchar[SAM_NPIO] =
|
|||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_issecure
|
||||
*
|
||||
|
|
@ -411,7 +413,9 @@ int sam_configpio(pio_pinset_t cfgset)
|
|||
irqstate_t flags;
|
||||
int ret;
|
||||
|
||||
/* Get the base address and pin mask associated with this pin configuration */
|
||||
/* Get the base address and pin mask associated with this pin
|
||||
* configuration
|
||||
*/
|
||||
|
||||
base = sam_piobase(cfgset);
|
||||
if (base == 0)
|
||||
|
|
@ -464,7 +468,10 @@ int sam_configpio(pio_pinset_t cfgset)
|
|||
{
|
||||
putreg32(pin, base + SAM_SPIO_SIONR_OFFSET);
|
||||
}
|
||||
/* Set the mask register to modify only the specific pin being configured. */
|
||||
|
||||
/* Set the mask register to modify only the specific pin being
|
||||
* configured.
|
||||
*/
|
||||
|
||||
putreg32(pin, base + SAM_PIO_MSKR_OFFSET);
|
||||
|
||||
|
|
@ -485,7 +492,9 @@ int sam_configpio(pio_pinset_t cfgset)
|
|||
break;
|
||||
|
||||
case PIO_ANALOG:
|
||||
|
||||
/* REVISIT */
|
||||
|
||||
ret = OK;
|
||||
break;
|
||||
|
||||
|
|
@ -581,26 +590,28 @@ bool sam_pioread(pio_pinset_t pinset)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: sam_pio_forceclk
|
||||
*
|
||||
* Description:
|
||||
* Enable PIO clocking. Needed only for SAMA5D3/D4 compatibility. For the SAMA5D2,
|
||||
* there is a common clock for all PIO ports and that clock is always enabled.
|
||||
* Enable PIO clocking. Needed only for SAMA5D3/D4 compatibility. For the
|
||||
* SAMA5D2, there is a common clock for all PIO ports and that clock is
|
||||
* always enabled.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
void sam_pio_forceclk(pio_pinset_t pinset, bool enable)
|
||||
{
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Function: sam_dumppio
|
||||
*
|
||||
* Description:
|
||||
* Dump all PIO registers associated with the base address of the provided pinset.
|
||||
* Dump all PIO registers associated with the base address of the provided
|
||||
* pinset.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO_INFO
|
||||
int sam_dumppio(uint32_t pinset, const char *msg)
|
||||
|
|
@ -632,17 +643,22 @@ int sam_dumppio(uint32_t pinset, const char *msg)
|
|||
}
|
||||
|
||||
gpioinfo(" MSKR: %08x CFGR: %08x PDSR: %08x LOCKSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_MSKR_OFFSET), getreg32(base + SAM_PIO_CFGR_OFFSET),
|
||||
getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET));
|
||||
getreg32(base + SAM_PIO_MSKR_OFFSET),
|
||||
getreg32(base + SAM_PIO_CFGR_OFFSET),
|
||||
getreg32(base + SAM_PIO_PDSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_LOCKSR_OFFSET));
|
||||
gpioinfo(" ODSR: %08x IMR: %08x ISR: %08x\n",
|
||||
getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
|
||||
getreg32(base + SAM_PIO_ODSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_IMR_OFFSET),
|
||||
getreg32(base + SAM_PIO_ISR_OFFSET));
|
||||
|
||||
if (secure)
|
||||
{
|
||||
gpioinfo(" SCDR: %08x WPMR: %08x WPSR: %08x IOSSR: %08x\n",
|
||||
getreg32(SAM_SPIO_SCDR), getreg32(SAM_SPIO_WPMR),
|
||||
getreg32(SAM_SPIO_WPSR), getreg32(base + SAM_SPIO_IOSSR_OFFSET));
|
||||
getreg32(SAM_SPIO_SCDR),
|
||||
getreg32(SAM_SPIO_WPMR),
|
||||
getreg32(SAM_SPIO_WPSR),
|
||||
getreg32(base + SAM_SPIO_IOSSR_OFFSET));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
|||
|
|
@ -34,4 +34,98 @@ config SAMA5D2XULT_USBHOST_PRIO
|
|||
default 100
|
||||
depends on USBHOST
|
||||
|
||||
config SAMA5_SDMMC
|
||||
bool "enable SDMMC controller"
|
||||
default y if SAMA5_HAVE_SDMMC
|
||||
select SDIO_DMA
|
||||
select SCHED_WORKQUEUE
|
||||
select SCHED_HPWORK
|
||||
select MMCSD
|
||||
select MMCSD_SDIO
|
||||
select SDIO_BLOCKSETUP
|
||||
select ARCH_HAVE_SDIO
|
||||
select SAMA5_SDMMC_DMA
|
||||
---help---
|
||||
Enable SD Card interface SDMMC0. Selects SAMA5_SDMMC SAMA5_SDMMC0 SAMA5_SDMMC_DMA SDIO_DMA SCHED_WORKQUEUE SCHED_HPWORK SDIO_BLOCKSETUP
|
||||
|
||||
config SAMA5_SDMMC0
|
||||
bool "Enable SDMMC0 (built-in eMMC)"
|
||||
default n if SAMA5_SDMMC
|
||||
depends on SAMA5_SDMMC
|
||||
|
||||
config SAMA5_SDMMC0_SIZE
|
||||
int "SDMMC0 size in bytes"
|
||||
default 4294967296
|
||||
depends on SAMA5_SDMMC0
|
||||
---help---
|
||||
Size of eMMC flash in bytes. Default: 4GB
|
||||
|
||||
config SAMA5D27_SDMMC0_MOUNT
|
||||
bool "Mount SDMMC0 at startup"
|
||||
default n
|
||||
depends on SAMA5_SDMMC0
|
||||
|
||||
config SAMA5D27_SDMMC0_MOUNT_BLKDEV
|
||||
string "SDMMC0 block device name"
|
||||
default mmc0
|
||||
depends on SAMA5_SDMMC0
|
||||
|
||||
config SAMA5D27_SDMMC0_MOUNT_MOUNTPOINT
|
||||
string "SDMMC0 mountpoint"
|
||||
default "/mnt/sdmmc0"
|
||||
depends on SAMA5_SDMMC0
|
||||
|
||||
config SAMA5D27_SDMMC0_MOUNT_FSTYPE
|
||||
string "SDMMC0 file system type"
|
||||
default "vfat"
|
||||
depends on SAMA5_SDMMC0
|
||||
|
||||
config CONFIG_SAMA5_SDMMC1_WIDTH_D1_D8
|
||||
bool "SDMMC0 data bus width 8 bits"
|
||||
default y
|
||||
depends on SAMA5_SDMMC0
|
||||
|
||||
config SAMA5_SDMMC1
|
||||
bool "Enable SDMMC1"
|
||||
default y if SAMA5_SDMMC
|
||||
select SAMA5_SDMMC1_WIDTH_D1_D4
|
||||
depends on SAMA5_SDMMC
|
||||
|
||||
config SAMA5_SDMMC1_SIZE
|
||||
int "SDMMC1 size in bytes"
|
||||
default 1073741824
|
||||
depends on SAMA5_SDMMC1
|
||||
---help---
|
||||
Size of SD Card in bytes. Default: 16GB
|
||||
|
||||
config SAMA5D27_SDMMC1_MOUNT
|
||||
bool "Mount SDMMC1 at startup"
|
||||
default n
|
||||
depends on SAMA5_SDMMC1
|
||||
|
||||
config SAMA5D27_SDMMC1_MOUNT_BLKDEV
|
||||
string "SDMMC1 block device name"
|
||||
default mmc1
|
||||
depends on SAMA5_SDMMC1
|
||||
|
||||
config SAMA5D27_SDMMC1_MOUNT_MOUNTPOINT
|
||||
string "SDMMC1 mountpoint"
|
||||
default "/mnt/sdmmc1"
|
||||
depends on SAMA5_SDMMC1
|
||||
|
||||
config SAMA5D27_SDMMC1_MOUNT_FSTYPE
|
||||
string "SDMMC1 file system type"
|
||||
default "vfat"
|
||||
depends on SAMA5_SDMMC1
|
||||
|
||||
config MMCSD_HAVE_CARDDETECT
|
||||
bool "SDMMC1 card detect"
|
||||
default y
|
||||
depends on SAMA5_SDMMC1
|
||||
|
||||
config SAMA5_SDMMC1_WIDTH_D1_D4
|
||||
bool "SDMMC1 data bus width 4 bits"
|
||||
default y
|
||||
depends on SAMA5_SDMMC1
|
||||
|
||||
endif # ARCH_BOARD_SAMA5D2_XULT
|
||||
|
|
|
|||
|
|
@ -780,8 +780,10 @@ Configurations
|
|||
|
||||
netnsh:
|
||||
|
||||
This is a network enabled configuration based on the NuttShell (NSH)
|
||||
REVISIT: More to be provided.
|
||||
This is a network enabled configuration based on the NuttShell (NSH).
|
||||
The CDC-ECM driver is enabled, so you can plug a USB cable into the
|
||||
USB-Micro port (USB-A) and the board will appear as an CDC-ECM
|
||||
ethernet adapter.
|
||||
|
||||
nsh:
|
||||
|
||||
|
|
@ -952,3 +954,10 @@ Configurations
|
|||
NOTE: If you want the RTC to preserve time over power cycles, you
|
||||
will need to install a battery in the battery holder (J12) and close
|
||||
the jumper, JP13.
|
||||
|
||||
sdmmcnsh:
|
||||
|
||||
This is a configuration based on the NuttShell (NSH). The SDMMC
|
||||
peripheral is enabled, and can read and write to a VFAT filesystem
|
||||
on the SD Card.
|
||||
|
||||
|
|
|
|||
147
boards/arm/sama5/sama5d2-xult/configs/sdmmcnsh/defconfig
Normal file
147
boards/arm/sama5/sama5d2-xult/configs/sdmmcnsh/defconfig
Normal file
|
|
@ -0,0 +1,147 @@
|
|||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_AUDIO_FORMAT_MP3 is not set
|
||||
# CONFIG_DISABLE_OS_API is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
# CONFIG_NSH_CMDPARMS is not set
|
||||
# CONFIG_SAMA5_UART0 is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="sama5d2-xult"
|
||||
CONFIG_ARCH_BOARD_SAMA5D2_XULT=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="sama5"
|
||||
CONFIG_ARCH_CHIP_ATSAMA5D27=y
|
||||
CONFIG_ARCH_CHIP_SAMA5=y
|
||||
CONFIG_ARCH_CHIP_SAMA5D2=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=2048
|
||||
CONFIG_ARCH_IRQBUTTONS=y
|
||||
CONFIG_ARCH_LOWVECTORS=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_AUDIO=y
|
||||
CONFIG_AUDIO_NUM_BUFFERS=8
|
||||
CONFIG_BOARDCTL_ROMDISK=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=65775
|
||||
CONFIG_BOOT_RUNFROMSDRAM=y
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_CONSOLE_SYSLOG=y
|
||||
CONFIG_DEBUG_FULLOPT=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_DEV_LOOP=y
|
||||
CONFIG_DEV_ZERO=y
|
||||
CONFIG_EXAMPLES_HELLO=y
|
||||
CONFIG_EXAMPLES_TCPBLASTER=y
|
||||
CONFIG_EXAMPLES_TCPECHO=y
|
||||
CONFIG_EXAMPLES_WGET=y
|
||||
CONFIG_EXAMPLES_WGET_URL="http://10.0.0.1/"
|
||||
CONFIG_FAT_LCNAMES=y
|
||||
CONFIG_FAT_LFN=y
|
||||
CONFIG_FS_AUTOMOUNTER=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_EXCLUDE_VERSION=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_HIDKBD_POLLUSEC=80000
|
||||
CONFIG_I2S=y
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_IOB_NBUFFERS=72
|
||||
CONFIG_IOB_THROTTLE=16
|
||||
CONFIG_MAX_TASKS=16
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
CONFIG_NETDB_BUFSIZE=128
|
||||
CONFIG_NETINIT_NETLOCAL=y
|
||||
CONFIG_NETINIT_NOMAC=y
|
||||
CONFIG_NETUTILS_TELNETC=y
|
||||
CONFIG_NETUTILS_WEBCLIENT=y
|
||||
CONFIG_NET_ARP_IPIN=y
|
||||
CONFIG_NET_ARP_SEND=y
|
||||
CONFIG_NET_BROADCAST=y
|
||||
CONFIG_NET_CDCECM=y
|
||||
CONFIG_NET_ETH_PKTSIZE=1514
|
||||
CONFIG_NET_ICMP=y
|
||||
CONFIG_NET_ICMP_SOCKET=y
|
||||
CONFIG_NET_ROUTE=y
|
||||
CONFIG_NET_STATISTICS=y
|
||||
CONFIG_NET_TCP=y
|
||||
CONFIG_NET_TCPBACKLOG=y
|
||||
CONFIG_NET_TCP_NOTIFIER=y
|
||||
CONFIG_NET_TCP_WRITE_BUFFERS=y
|
||||
CONFIG_NET_UDP=y
|
||||
CONFIG_NFILE_DESCRIPTORS=8
|
||||
CONFIG_NFILE_STREAMS=8
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_PROMPT_STRING="nsh> "
|
||||
CONFIG_NSH_QUOTE=y
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PREALLOC_MQ_MSGS=4
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_PREALLOC_WDOGS=16
|
||||
CONFIG_RAM_SIZE=268435456
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAM_VSTART=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_READLINE_CMD_HISTORY=y
|
||||
CONFIG_READLINE_CMD_HISTORY_LEN=100
|
||||
CONFIG_READLINE_CMD_HISTORY_LINELEN=120
|
||||
CONFIG_READLINE_TABCOMPLETION=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SAMA5D27_SDMMC0_MOUNT_BLKDEV="/dev/mmcsd0"
|
||||
CONFIG_SAMA5D27_SDMMC0_MOUNT_MOUNTPOINT="/mnt/mmcsd0"
|
||||
CONFIG_SAMA5D27_SDMMC1_MOUNT=y
|
||||
CONFIG_SAMA5D27_SDMMC1_MOUNT_BLKDEV="/dev/mmcsd1"
|
||||
CONFIG_SAMA5D27_SDMMC1_MOUNT_MOUNTPOINT="/mnt/mmcsd1"
|
||||
CONFIG_SAMA5D2XULT_528MHZ=y
|
||||
CONFIG_SAMA5D2XULT_USBHOST_STACKSIZE=2048
|
||||
CONFIG_SAMA5_BOOT_SDRAM=y
|
||||
CONFIG_SAMA5_DDRCS_HEAP_END=0x2fa00000
|
||||
CONFIG_SAMA5_DDRCS_RESERVE=y
|
||||
CONFIG_SAMA5_EHCI=y
|
||||
CONFIG_SAMA5_HSMC=y
|
||||
CONFIG_SAMA5_OHCI=y
|
||||
CONFIG_SAMA5_PIOA_IRQ=y
|
||||
CONFIG_SAMA5_PIOB_IRQ=y
|
||||
CONFIG_SAMA5_PIOC_IRQ=y
|
||||
CONFIG_SAMA5_PIO_IRQ=y
|
||||
CONFIG_SAMA5_RTC=y
|
||||
CONFIG_SAMA5_SDMMC0=y
|
||||
CONFIG_SAMA5_SDMMC0_SIZE=1073741824
|
||||
CONFIG_SAMA5_SDMMC=y
|
||||
CONFIG_SAMA5_TRNG=y
|
||||
CONFIG_SAMA5_UART1=y
|
||||
CONFIG_SAMA5_UDPHS=y
|
||||
CONFIG_SAMA5_UHPHS=y
|
||||
CONFIG_SCHED_HPWORKPRIORITY=192
|
||||
CONFIG_SCHED_LPNTHREADS=2
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_SERIAL_TERMIOS=y
|
||||
CONFIG_SIG_DEFAULT=y
|
||||
CONFIG_SIG_EVTHREAD=y
|
||||
CONFIG_START_DAY=31
|
||||
CONFIG_START_MONTH=7
|
||||
CONFIG_START_YEAR=2014
|
||||
CONFIG_SYMTAB_ORDEREDBYNAME=y
|
||||
CONFIG_SYSLOG_TIMESTAMP=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_SYSTEM_PING=y
|
||||
CONFIG_SYSTEM_VI=y
|
||||
CONFIG_TTY_SIGINT=y
|
||||
CONFIG_TTY_SIGSTP=y
|
||||
CONFIG_UART1_SERIAL_CONSOLE=y
|
||||
CONFIG_USBDEV=y
|
||||
CONFIG_USBDEV_DMA=y
|
||||
CONFIG_USBDEV_DUALSPEED=y
|
||||
CONFIG_USBDEV_TRACE=y
|
||||
CONFIG_USBDEV_TRACE_NRECORDS=512
|
||||
CONFIG_USBHOST_HIDKBD=y
|
||||
CONFIG_USBHOST_MSC=y
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_WDOG_INTRESERVE=2
|
||||
|
|
@ -65,8 +65,8 @@
|
|||
#if defined(CONFIG_SAMA5_BOOT_SDRAM)
|
||||
/* When booting from SDRAM, NuttX is loaded in SDRAM by an intermediate
|
||||
* bootloader.
|
||||
* That bootloader had to have already configured the PLL and SDRAM for proper
|
||||
* operation.
|
||||
* That bootloader had to have already configured the PLL and SDRAM for
|
||||
* proper operation.
|
||||
*
|
||||
* In this case, we don not reconfigure the clocking.
|
||||
* Rather, we need to query the register settings to determine the clock
|
||||
|
|
@ -317,6 +317,24 @@
|
|||
* ---- ------- ---- --------
|
||||
*/
|
||||
|
||||
/* SDIO - Used for both Port 0 & 1 ******************************************/
|
||||
|
||||
/* 386 KHz for initial inquiry stuff */
|
||||
|
||||
#define BOARD_SDMMC_IDMODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV256
|
||||
#define BOARD_SDMMC_IDMODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(2)
|
||||
|
||||
/* 24.8MHz for other modes */
|
||||
|
||||
#define BOARD_SDMMC_MMCMODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV8
|
||||
#define BOARD_SDMMC_MMCMODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(1)
|
||||
|
||||
#define BOARD_SDMMC_SD1MODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV8
|
||||
#define BOARD_SDMMC_SD1MODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(1)
|
||||
|
||||
#define BOARD_SDMMC_SD4MODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV8
|
||||
#define BOARD_SDMMC_SD4MODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(1)
|
||||
|
||||
/****************************************************************************
|
||||
* Assembly Language Macros
|
||||
****************************************************************************/
|
||||
|
|
|
|||
|
|
@ -59,6 +59,14 @@ CSRCS += sam_at25.c
|
|||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SAMA5_SDMMC0),y)
|
||||
CSRCS += sam_sdmmc.c
|
||||
else
|
||||
ifeq ($(CONFIG_SAMA5_SDMMC1),y)
|
||||
CSRCS += sam_sdmmc.c
|
||||
endif
|
||||
|
||||
endif
|
||||
ifeq ($(CONFIG_SAMA5_HSMCI0),y)
|
||||
CSRCS += sam_hsmci.c
|
||||
else
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <syslog.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
|
|
@ -68,6 +70,7 @@ int board_app_initialize(uintptr_t arg)
|
|||
#ifndef CONFIG_BOARD_LATE_INITIALIZE
|
||||
/* Perform board initialization */
|
||||
|
||||
mcinfo("Entry\n");
|
||||
return sam_bringup();
|
||||
#else
|
||||
return OK;
|
||||
|
|
|
|||
|
|
@ -25,8 +25,10 @@
|
|||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/mount.h>
|
||||
#include <stdlib.h>
|
||||
#include <syslog.h>
|
||||
#include <debug.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/kthread.h>
|
||||
|
|
@ -34,6 +36,8 @@
|
|||
#include <nuttx/usb/usbhost.h>
|
||||
#include <nuttx/usb/usbdev_trace.h>
|
||||
|
||||
#include "sama5d2-xult.h"
|
||||
|
||||
#ifdef CONFIG_CDCACM
|
||||
# include <nuttx/usb/cdcacm.h>
|
||||
#endif
|
||||
|
|
@ -51,7 +55,10 @@
|
|||
# include <nuttx/usb/rndis.h>
|
||||
#endif
|
||||
|
||||
#include "sama5d2-xult.h"
|
||||
#ifdef CONFIG_MMCSD
|
||||
# include <nuttx/mmcsd.h>
|
||||
# include "sam_sdmmc.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -124,6 +131,102 @@ static void sam_i2ctool(void)
|
|||
# define sam_i2ctool()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nsh_sdmmc_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SDMMC drivers
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA5_SDMMC
|
||||
|
||||
static int nsh_sdmmc_initialize(void)
|
||||
{
|
||||
struct sdio_dev_s *sdmmc0;
|
||||
struct sdio_dev_s *sdmmc1;
|
||||
int ret = 0;
|
||||
|
||||
/* Get an instance of the SDIO interface */
|
||||
|
||||
#ifdef CONFIG_SAMA5_SDMMC0
|
||||
sdmmc0 = sam_sdmmc_sdio_initialize(SDMMC0_SLOTNO);
|
||||
if (!sdmmc0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to initialize SD/MMC\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Bind the SDIO interface to the MMC/SD driver */
|
||||
|
||||
ret = mmcsd_slotinitialize(SDMMC0_MINOR, sdmmc0);
|
||||
if (ret != OK)
|
||||
{
|
||||
syslog(LOG_ERR,
|
||||
"ERROR: Failed to bind SDIO to the MMC/SD driver (slot 0): "
|
||||
"%d\n",
|
||||
ret);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SAMA5D27_SDMMC0_MOUNT
|
||||
/* Mount the volume on SDMMC0 */
|
||||
|
||||
ret = mount(CONFIG_SAMA5D27_SDMMC0_MOUNT_BLKDEV,
|
||||
CONFIG_SAMA5D27_SDMMC0_MOUNT_MOUNTPOINT,
|
||||
CONFIG_SAMA5D27_SDMMC0_MOUNT_FSTYPE,
|
||||
0, NULL);
|
||||
|
||||
if (ret < 0)
|
||||
{
|
||||
_err("ERROR: Failed to mount %s: %d\n",
|
||||
CONFIG_SAMA5D27_SDMMC0_MOUNT_MOUNTPOINT, errno);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_SDMMC1
|
||||
sdmmc1 = sam_sdmmc_sdio_initialize(SDMMC1_SLOTNO);
|
||||
if (!sdmmc1)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to initialize SD/MMC\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Bind the SDIO interface to the MMC/SD driver */
|
||||
|
||||
ret = mmcsd_slotinitialize(SDMMC1_MINOR, sdmmc1);
|
||||
if (ret != OK)
|
||||
{
|
||||
syslog(LOG_ERR,
|
||||
"ERROR: Failed to bind SDIO to the MMC/SD driver (slot 0): "
|
||||
"%d\n",
|
||||
ret);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SAMA5D27_SDMMC1_MOUNT
|
||||
/* Mount the volume on SDMMC1 */
|
||||
|
||||
ret = mount(CONFIG_SAMA5D27_SDMMC1_MOUNT_BLKDEV,
|
||||
CONFIG_SAMA5D27_SDMMC1_MOUNT_MOUNTPOINT,
|
||||
CONFIG_SAMA5D27_SDMMC1_MOUNT_FSTYPE,
|
||||
0, NULL);
|
||||
|
||||
if (ret < 0)
|
||||
{
|
||||
_err("ERROR: Failed to mount %s: %d\n",
|
||||
CONFIG_SAMA5D27_SDMMC1_MOUNT_MOUNTPOINT, errno);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
#else
|
||||
# define nsh_sdmmc_initialize() (OK)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
@ -144,6 +247,14 @@ int sam_bringup(void)
|
|||
|
||||
sam_i2ctool();
|
||||
|
||||
#ifdef HAVE_SDMMC
|
||||
#ifdef CONFIG_SAMA5_SDMMC
|
||||
/* Initialize SDMCC-based MMC/SD card support */
|
||||
|
||||
nsh_sdmmc_initialize();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_HSMCI
|
||||
#ifdef CONFIG_SAMA5_HSMCI0
|
||||
/* Initialize the HSMCI0 driver */
|
||||
|
|
@ -191,7 +302,7 @@ int sam_bringup(void)
|
|||
#ifdef CONFIG_SAMA5D4EK_HSMCI1_MOUNT
|
||||
else
|
||||
{
|
||||
/* REVISIT: A delay seems to be required here or the mount will fail. */
|
||||
/* REVISIT: A delay seems required here or the mount will fail. */
|
||||
|
||||
/* Mount the volume on HSMCI1 */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* boards/arm/sama5/sama5d2-xult/src/sam_hsmci.c
|
||||
* boards/arm/sama5/sama5d2-xult/src/sam_sdmmc.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
|
|
@ -18,38 +18,37 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* The SAMA5D3-Xplained provides a two SD memory card slots:
|
||||
* (1) a full size SD card slot (J10), and
|
||||
* (2) a microSD memory card slot (J11).
|
||||
/* The SAMA5D2-XULT provides a built-in 4GB eMMC (SDMMC0), and one SD
|
||||
* full-size memory card slot at J19 (SDMMC1).
|
||||
*
|
||||
* The full size SD card slot connects via HSMCI0. The card detect discrete
|
||||
* is available on PB17 (pulled high). The write protect descrete is tied to
|
||||
* ground (via PP6) and not available to software. The slot supports 8-bit
|
||||
* wide transfer mode, but the NuttX driver currently uses only the 4-bit
|
||||
* wide transfer mode
|
||||
* SDMMC0: There is a Micron 4Gx8 eMMC managed NAND Flash (MTFC4GLDEA-0M WT)
|
||||
* connected to SDMMC0.
|
||||
*
|
||||
* PD17 MCI0_CD
|
||||
* PD1 MCI0_DA0
|
||||
* PD2 MCI0_DA1
|
||||
* PD3 MCI0_DA2
|
||||
* PD4 MCI0_DA3
|
||||
* PD5 MCI0_DA4
|
||||
* PD6 MCI0_DA5
|
||||
* PD7 MCI0_DA6
|
||||
* PD8 MCI0_DA7
|
||||
* PD9 MCI0_CK
|
||||
* PD0 MCI0_CDA
|
||||
* PA1 SDMMC0_CMD
|
||||
* PA2 SDMMC0_DAT0
|
||||
* PA3 SDMMC0_DAT1
|
||||
* PA4 SDMMC0_DAT2
|
||||
* PA5 SDMMC0_DAT3
|
||||
* PA6 SDMMC0_DAT4
|
||||
* PA7 SDMMC0_DAT5
|
||||
* PA8 SDMMC0_DAT6
|
||||
* PA9 SDMMC0_DAT7
|
||||
* PA0 SDMMC0_CK
|
||||
* PA10 SDMMC0_RSTN
|
||||
*
|
||||
* The microSD connects vi HSMCI1. The card detect discrete is available on
|
||||
* PB18 (pulled high):
|
||||
* SDMMC1: The full size SD card slot connects via SDMMC1. The card detect
|
||||
* discrete is available on PA30 (pulled high). The write protect discrete
|
||||
* is tied to ground and not available to software. The slot only supports
|
||||
* 4-bit wide transfer mode.
|
||||
*
|
||||
* PA30 SDMMC1_CD
|
||||
* PA18 SDMMC1_DAT0
|
||||
* PA19 SDMMC1_DAT1
|
||||
* PA20 SDMMC1_DAT2
|
||||
* PA21 SDMMC1_DAT3
|
||||
* PD22 SDMMC1_CK
|
||||
* PA28 SDMMC1_CDA
|
||||
*
|
||||
* PD18 MCI1_CD
|
||||
* PB20 MCI1_DA0
|
||||
* PB21 MCI1_DA1
|
||||
* PB22 MCI1_DA2
|
||||
* PB23 MCI1_DA3
|
||||
* PB24 MCI1_CK
|
||||
* PB19 MCI1_CDA
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -66,22 +65,26 @@
|
|||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "arm_internal.h"
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "sam_pio.h"
|
||||
#include "sam_hsmci.h"
|
||||
#include "sam_sdmmc.h"
|
||||
|
||||
#include "sama5d3-xplained.h"
|
||||
#include "sama5d2-xult.h"
|
||||
|
||||
#ifdef HAVE_HSMCI
|
||||
#ifdef HAVE_SDMMC
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/* This structure holds static information unique to one HSMCI peripheral */
|
||||
/* This structure holds static information unique to one SDMMC peripheral */
|
||||
|
||||
struct sam_hsmci_state_s
|
||||
struct sam_sdmmc_state_s
|
||||
{
|
||||
struct sdio_dev_s *hsmci; /* R/W device handle */
|
||||
struct sdio_dev_s *sdmmc; /* R/W device handle */
|
||||
pio_pinset_t pincfg; /* Card detect PIO pin configuration */
|
||||
uint8_t irq; /* Interrupt number (same as pid) */
|
||||
uint8_t slotno; /* Slot number */
|
||||
|
|
@ -93,29 +96,29 @@ struct sam_hsmci_state_s
|
|||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* HSCMI device state */
|
||||
/* SDMMC device state */
|
||||
|
||||
#ifdef CONFIG_SAMA5_HSMCI0
|
||||
static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg);
|
||||
#ifdef CONFIG_SAMA5_SDMMC0
|
||||
static int sam_sdmmc0_cardetect(int irq, void *regs, FAR void *arg);
|
||||
|
||||
static struct sam_hsmci_state_s g_hsmci0 =
|
||||
static struct sam_sdmmc_state_s g_sdmmc0 =
|
||||
{
|
||||
.pincfg = PIO_MCI0_CD,
|
||||
.irq = IRQ_MCI0_CD,
|
||||
.pincfg = PIO_SDMMC0_CD,
|
||||
.irq = -1,
|
||||
.slotno = 0,
|
||||
.handler = sam_hsmci0_cardetect,
|
||||
.handler = sam_sdmmc0_cardetect,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_HSMCI1
|
||||
static int sam_hsmci1_cardetect(int irq, void *regs, FAR void *arg);
|
||||
#ifdef CONFIG_SAMA5_SDMMC1
|
||||
static int sam_sdmmc1_cardetect(int irq, void *regs, FAR void *arg);
|
||||
|
||||
static struct sam_hsmci_state_s g_hsmci1 =
|
||||
static struct sam_sdmmc_state_s g_sdmmc1 =
|
||||
{
|
||||
.pincfg = PIO_MCI1_CD,
|
||||
.irq = IRQ_MCI1_CD,
|
||||
.pincfg = PIO_SDMMC1_CD,
|
||||
.irq = IRQ_SDMMC1_CD,
|
||||
.slotno = 1,
|
||||
.handler = sam_hsmci1_cardetect,
|
||||
.handler = sam_sdmmc1_cardetect,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -127,11 +130,11 @@ static struct sam_hsmci_state_s g_hsmci1 =
|
|||
* Name: sam_cardinserted_internal
|
||||
*
|
||||
* Description:
|
||||
* Check if a card is inserted into the selected HSMCI slot
|
||||
* Check if a card is inserted into the selected SDMMC slot
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool sam_cardinserted_internal(struct sam_hsmci_state_s *state)
|
||||
bool sam_cardinserted_internal(struct sam_sdmmc_state_s *state)
|
||||
{
|
||||
bool inserted;
|
||||
|
||||
|
|
@ -143,14 +146,14 @@ bool sam_cardinserted_internal(struct sam_hsmci_state_s *state)
|
|||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_hsmci_cardetect, sam_hsmci0_cardetect, and sam_hsmci1_cardetect
|
||||
* Name: sam_sdmmc_cardetect, sam_sdmmc0_cardetect, and sam_sdmmc1_cardetect
|
||||
*
|
||||
* Description:
|
||||
* Card detect interrupt handlers
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int sam_hsmci_cardetect(struct sam_hsmci_state_s *state)
|
||||
static int sam_sdmmc_cardetect(struct sam_sdmmc_state_s *state)
|
||||
{
|
||||
/* Get the current card insertion state */
|
||||
|
||||
|
|
@ -160,59 +163,59 @@ static int sam_hsmci_cardetect(struct sam_hsmci_state_s *state)
|
|||
|
||||
if (cd != state->cd)
|
||||
{
|
||||
/* Yes... remember that new state and inform the HSMCI driver */
|
||||
/* Yes... remember that new state and inform the SDMMC driver */
|
||||
|
||||
state->cd = cd;
|
||||
|
||||
/* Report the new state to the SDIO driver */
|
||||
|
||||
sdio_mediachange(state->hsmci, cd);
|
||||
sdio_mediachange(state->sdmmc, cd);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SAMA5_HSMCI0
|
||||
static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg)
|
||||
#ifdef CONFIG_SAMA5_SDMMC0
|
||||
static int sam_sdmmc0_cardetect(int irq, void *regs, FAR void *arg)
|
||||
{
|
||||
return sam_hsmci_cardetect(&g_hsmci0);
|
||||
return sam_sdmmc_cardetect(&g_sdmmc0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_HSMCI1
|
||||
static int sam_hsmci1_cardetect(int irq, void *regs, FAR void *arg)
|
||||
#ifdef CONFIG_SAMA5_SDMMC1
|
||||
static int sam_sdmmc1_cardetect(int irq, void *regs, FAR void *arg)
|
||||
{
|
||||
return sam_hsmci_cardetect(&g_hsmci1);
|
||||
return sam_sdmmc_cardetect(&g_sdmmc1);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_hsmci_state
|
||||
* Name: sam_sdmmc_state
|
||||
*
|
||||
* Description:
|
||||
* Initialize HSMCI PIOs.
|
||||
* Initialize SDMMC PIOs.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static struct sam_hsmci_state_s *sam_hsmci_state(int slotno)
|
||||
static struct sam_sdmmc_state_s *sam_sdmmc_state(int slotno)
|
||||
{
|
||||
struct sam_hsmci_state_s *state = NULL;
|
||||
struct sam_sdmmc_state_s *state = NULL;
|
||||
|
||||
#ifdef CONFIG_SAMA5_HSMCI0
|
||||
#ifdef CONFIG_SAMA5_HSMCI1
|
||||
#ifdef CONFIG_SAMA5_SDMMC0
|
||||
#ifdef CONFIG_SAMA5_SDMMC1
|
||||
if (slotno == 0)
|
||||
#endif
|
||||
{
|
||||
state = &g_hsmci0;
|
||||
state = &g_sdmmc0;
|
||||
}
|
||||
#ifdef CONFIG_SAMA5_HSMCI1
|
||||
#ifdef CONFIG_SAMA5_SDMMC1
|
||||
else
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_HSMCI1
|
||||
#ifdef CONFIG_SAMA5_SDMMC1
|
||||
{
|
||||
state = &g_hsmci1;
|
||||
state = &g_sdmmc1;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -224,21 +227,24 @@ static struct sam_hsmci_state_s *sam_hsmci_state(int slotno)
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_hsmci_initialize
|
||||
* Name: sam_sdmmc_initialize
|
||||
*
|
||||
* Description:
|
||||
* Perform architecture specific initialization
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int sam_hsmci_initialize(int slotno, int minor)
|
||||
int sam_sdmmc_initialize(int slotno, int minor)
|
||||
{
|
||||
struct sam_hsmci_state_s *state;
|
||||
struct sam_sdmmc_state_s *state;
|
||||
int ret;
|
||||
|
||||
/* Get the static HSMI description */
|
||||
mcinfo("Entry.\n");
|
||||
mcinfo("slotno: %d\n", slotno);
|
||||
|
||||
state = sam_hsmci_state(slotno);
|
||||
/* Get the static SDMMC description */
|
||||
|
||||
state = sam_sdmmc_state(slotno);
|
||||
if (!state)
|
||||
{
|
||||
ferr("ERROR: No state for slotno %d\n", slotno);
|
||||
|
|
@ -253,8 +259,8 @@ int sam_hsmci_initialize(int slotno, int minor)
|
|||
|
||||
/* First, get an instance of the SDIO interface */
|
||||
|
||||
state->hsmci = sdio_initialize(slotno);
|
||||
if (!state->hsmci)
|
||||
state->sdmmc = sam_sdmmc_sdio_initialize(slotno);
|
||||
if (!state->sdmmc)
|
||||
{
|
||||
ferr("ERROR: Failed to initialize SDIO slot %d\n", slotno);
|
||||
return -ENODEV;
|
||||
|
|
@ -262,7 +268,7 @@ int sam_hsmci_initialize(int slotno, int minor)
|
|||
|
||||
/* Now bind the SDIO interface to the MMC/SD driver */
|
||||
|
||||
ret = mmcsd_slotinitialize(minor, state->hsmci);
|
||||
ret = mmcsd_slotinitialize(minor, state->sdmmc);
|
||||
if (ret != OK)
|
||||
{
|
||||
ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
|
||||
|
|
@ -274,10 +280,10 @@ int sam_hsmci_initialize(int slotno, int minor)
|
|||
sam_pioirq(state->pincfg);
|
||||
irq_attach(state->irq, state->handler, NULL);
|
||||
|
||||
/* Then inform the HSMCI driver if there is or is not a card in the slot. */
|
||||
/* Then inform the SDMMC driver if there is or is not a card in the slot. */
|
||||
|
||||
state->cd = sam_cardinserted_internal(state);
|
||||
sdio_mediachange(state->hsmci, state->cd);
|
||||
sdio_mediachange(state->sdmmc, state->cd);
|
||||
|
||||
/* Enable card detect interrupts */
|
||||
|
||||
|
|
@ -289,17 +295,17 @@ int sam_hsmci_initialize(int slotno, int minor)
|
|||
* Name: sam_cardinserted
|
||||
*
|
||||
* Description:
|
||||
* Check if a card is inserted into the selected HSMCI slot
|
||||
* Check if a card is inserted into the selected SDMMC slot
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool sam_cardinserted(int slotno)
|
||||
{
|
||||
struct sam_hsmci_state_s *state;
|
||||
struct sam_sdmmc_state_s *state;
|
||||
|
||||
/* Get the HSMI description */
|
||||
/* Get the SDMMC description */
|
||||
|
||||
state = sam_hsmci_state(slotno);
|
||||
state = sam_sdmmc_state(slotno);
|
||||
if (!state)
|
||||
{
|
||||
ferr("ERROR: No state for slotno %d\n", slotno);
|
||||
|
|
@ -315,7 +321,7 @@ bool sam_cardinserted(int slotno)
|
|||
* Name: sam_writeprotected
|
||||
*
|
||||
* Description:
|
||||
* Check if a card is inserted into the selected HSMCI slot
|
||||
* Check if a card is inserted into the selected SDMMC slot
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
|
@ -326,4 +332,5 @@ bool sam_writeprotected(int slotno)
|
|||
return false;
|
||||
}
|
||||
|
||||
#endif /* HAVE_HSMCI */
|
||||
#endif /* HAVE_SDMMC */
|
||||
|
||||
|
|
@ -42,7 +42,7 @@
|
|||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#define HAVE_HSMCI 1
|
||||
#define HAVE_SDMMC 1
|
||||
#define HAVE_AT25 1
|
||||
#define HAVE_NAND 1
|
||||
#define HAVE_USBHOST 1
|
||||
|
|
@ -50,26 +50,26 @@
|
|||
#define HAVE_USBMONITOR 1
|
||||
#define HAVE_NETWORK 1
|
||||
|
||||
/* HSMCI */
|
||||
/* SDMMC */
|
||||
|
||||
/* Can't support MMC/SD if the card interface(s) are not enable */
|
||||
|
||||
#if !defined(CONFIG_SAMA5_HSMCI0) && !defined(CONFIG_SAMA5_HSMCI1)
|
||||
# undef HAVE_HSMCI
|
||||
#if !defined(CONFIG_SAMA5_SDMMC) && !defined(CONFIG_SAMA5_SDMMC0)
|
||||
# undef HAVE_SDMMC
|
||||
#endif
|
||||
|
||||
/* Can't support MMC/SD features if mountpoints are disabled */
|
||||
|
||||
#if defined(HAVE_HSMCI) && defined(CONFIG_DISABLE_MOUNTPOINT)
|
||||
#if defined(HAVE_SDMMC) && defined(CONFIG_DISABLE_MOUNTPOINT)
|
||||
# warning Mountpoints disabled. No MMC/SD support
|
||||
# undef HAVE_HSMCI
|
||||
# undef HAVE_SDMCC
|
||||
#endif
|
||||
|
||||
/* We need PIO interrupts on PIOD to support card detect interrupts */
|
||||
|
||||
#if defined(HAVE_HSMCI) && !defined(CONFIG_SAMA5_PIOD_IRQ)
|
||||
# warning PIOD interrupts not enabled. No MMC/SD support.
|
||||
# undef HAVE_HSMCI
|
||||
#if defined(HAVE_SDMMC) && !defined(CONFIG_SAMA5_PIOA_IRQ)
|
||||
# warning PIOA interrupts not enabled. No MMC/SD support.
|
||||
# undef HAVE_SDMMC
|
||||
#endif
|
||||
|
||||
/* NAND FLASH */
|
||||
|
|
@ -95,27 +95,27 @@
|
|||
#endif
|
||||
|
||||
/* If we are going to mount the NAND, then they user must also have told
|
||||
* us what to do with it by setting one of CONFIG_SAMA5D3XPLAINED_NAND_FTL or
|
||||
* CONFIG_SAMA5D3XPLAINED_NAND_NXFFS.
|
||||
* us what to do with it by setting one of CONFIG_SAMA5D2XULT_NAND_FTL or
|
||||
* CONFIG_SAMA5D2XULT_NAND_NXFFS.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_MTD
|
||||
# undef CONFIG_SAMA5D3XPLAINED_NAND_NXFFS
|
||||
# undef CONFIG_SAMA5D3XPLAINED_NAND_FTL
|
||||
# undef CONFIG_SAMA5D2XULT_NAND_NXFFS
|
||||
# undef CONFIG_SAMA5D2XULT_NAND_FTL
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_FS_NXFFS) || !defined(CONFIG_NXFFS_NAND)
|
||||
# undef CONFIG_SAMA5D3XPLAINED_NAND_NXFFS
|
||||
# undef CONFIG_SAMA5D2XULT_NAND_NXFFS
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SAMA5D3XPLAINED_NAND_FTL) && !defined(CONFIG_SAMA5D3XPLAINED_NAND_NXFFS)
|
||||
#if !defined(CONFIG_SAMA5D2XULT_NAND_FTL) && !defined(CONFIG_SAMA5D2XULT_NAND_NXFFS)
|
||||
# undef HAVE_NAND
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SAMA5D3XPLAINED_NAND_FTL) && defined(CONFIG_SAMA5D3XPLAINED_NAND_NXFFS)
|
||||
# warning Both CONFIG_SAMA5D3XPLAINED_NAND_FTL and CONFIG_SAMA5D3XPLAINED_NAND_NXFFS are set
|
||||
# warning Ignoring CONFIG_SAMA5D3XPLAINED_NAND_NXFFS
|
||||
# undef CONFIG_SAMA5D3XPLAINED_NAND_NXFFS
|
||||
#if defined(CONFIG_SAMA5D2XULT_NAND_FTL) && defined(CONFIG_SAMA5D2XULT_NAND_NXFFS)
|
||||
# warning Both CONFIG_SAMA5D2XULT_NAND_FTL and CONFIG_SAMA5D2XULT_NAND_NXFFS are set
|
||||
# warning Ignoring CONFIG_SAMA5D2XULT_NAND_NXFFS
|
||||
# undef CONFIG_SAMA5DXULT_NAND_NXFFS
|
||||
#endif
|
||||
|
||||
/* AT25 Serial FLASH */
|
||||
|
|
@ -142,14 +142,14 @@
|
|||
# undef CONFIG_SAMA5D3XPLAINED_AT25_NXFFS
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SAMA5D3XPLAINED_AT25_FTL) && !defined(CONFIG_SAMA5D3XPLAINED_AT25_NXFFS)
|
||||
#if !defined(CONFIG_SAMA5D2XULT_AT25_FTL) && !defined(CONFIG_SAMA5D2XULT_AT25_NXFFS)
|
||||
# undef HAVE_AT25
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SAMA5D3XPLAINED_AT25_FTL) && defined(CONFIG_SAMA5D3XPLAINED_AT25_NXFFS)
|
||||
# warning Both CONFIG_SAMA5D3XPLAINED_AT25_FTL and CONFIG_SAMA5D3XPLAINED_AT25_NXFFS are set
|
||||
# warning Ignoring CONFIG_SAMA5D3XPLAINED_AT25_NXFFS
|
||||
# undef CONFIG_SAMA5D3XPLAINED_AT25_NXFFS
|
||||
#if defined(CONFIG_SAMA5D2XULT_AT25_FTL) && defined(CONFIG_SAMA5D2XULT_AT25_NXFFS)
|
||||
# warning Both CONFIG_SAMA5D2XULT_AT25_FTL and CONFIG_SAMA5D2XULT_AT25_NXFFS are set
|
||||
# warning Ignoring CONFIG_SAMA5D2XULT_AT25_NXFFS
|
||||
# undef CONFIG_SAMA5D2XULT_AT25_NXFFS
|
||||
#endif
|
||||
|
||||
/* Assign minor device numbers. For example, if we also use MINOR number 0
|
||||
|
|
@ -178,16 +178,25 @@
|
|||
# define CONFIG_NSH_MMCSDMINOR 0
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_HSMCI
|
||||
#ifdef HAVE_SDMMC
|
||||
|
||||
# define HSMCI0_SLOTNO 0
|
||||
# define HSMCI1_SLOTNO 1
|
||||
|
||||
# ifdef CONFIG_SAMA5_HSMCI0
|
||||
# define HSMCI0_MINOR CONFIG_NSH_MMCSDMINOR
|
||||
# define HSMCI1_MINOR (CONFIG_NSH_MMCSDMINOR+1)
|
||||
# if ( defined(CONFIG_SAMA5_SDMMC0) && defined(CONFIG_SAMA5_SDMMC1) )
|
||||
# define SDMMC0_SLOTNO 0
|
||||
# define SDMMC1_SLOTNO 1
|
||||
# else
|
||||
# define HSMCI1_MINOR CONFIG_NSH_MMCSDMINOR
|
||||
# if ( defined(CONFIG_SAMA5_SDMMC0) )
|
||||
# define SDMMC0_SLOTNO 0
|
||||
# endif
|
||||
# if ( defined(CONFIG_SAMA5_SDMMC1) )
|
||||
# define SDMMC1_SLOTNO 0
|
||||
# endif
|
||||
# endif
|
||||
|
||||
# ifdef CONFIG_SAMA5_SDMMC0
|
||||
# define SDMMC0_MINOR CONFIG_NSH_MMCSDMINOR
|
||||
# define SDMMC1_MINOR (CONFIG_NSH_MMCSDMINOR+1)
|
||||
# else
|
||||
# define SDMMC1_MINOR CONFIG_NSH_MMCSDMINOR
|
||||
# endif
|
||||
#else
|
||||
#endif
|
||||
|
|
@ -300,33 +309,51 @@
|
|||
PIO_INT_BOTHEDGES | PIO_PORT_PIOB | PIO_PIN6)
|
||||
#define IRQ_BTN_USER SAM_IRQ_PB6
|
||||
|
||||
/* HSMCI Card Slots *********************************************************/
|
||||
|
||||
/* The SAMA5D2-XULT provides a SD memory card slots:
|
||||
* a full size SD card slot (J19)
|
||||
/* SDMMC clocking
|
||||
*
|
||||
* The full size SD card slot connects via HSMCI0. The card detect discrete
|
||||
* is available on PD17 (pulled high). The write protect discrete is tied to
|
||||
* ground (via PP6) and not available to software. The slot supports 8-bit
|
||||
* wide transfer mode, but the NuttX driver currently uses only the 4-bit
|
||||
* wide transfer mode
|
||||
* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
|
||||
* divided by (2*(CLKDIV+1)).
|
||||
*
|
||||
* PD17 MCI0_CD
|
||||
* PD1 MCI0_DA0
|
||||
* PD2 MCI0_DA1
|
||||
* PD3 MCI0_DA2
|
||||
* PD4 MCI0_DA3
|
||||
* PD5 MCI0_DA4
|
||||
* PD6 MCI0_DA5
|
||||
* PD7 MCI0_DA6
|
||||
* PD8 MCI0_DA7
|
||||
* PD9 MCI0_CK
|
||||
* PD0 MCI0_CDA
|
||||
* MCI_SPEED = MCK / (2*(CLKDIV+1))
|
||||
* CLKDIV = MCI / MCI_SPEED / 2 - 1
|
||||
*
|
||||
* Where CLKDIV has a range of 0-255.
|
||||
*/
|
||||
|
||||
#define PIO_MCI0_CD (PIO_INPUT | PIO_CFG_DEFAULT | PIO_CFG_DEGLITCH | \
|
||||
PIO_INT_BOTHEDGES | PIO_PORT_PIOA | PIO_PIN11)
|
||||
#define IRQ_MCI0_CD SAM_IRQ_PA11
|
||||
/* MCK = 96MHz, CLKDIV = 119, MCI_SPEED = 96MHz / 2 * (119+1) = 400 KHz */
|
||||
|
||||
#define SDMMC_INIT_CLKDIV (119 << SDMMC_MR_CLKDIV_SHIFT)
|
||||
|
||||
/* MCK = 96MHz, CLKDIV = 3, MCI_SPEED = 96MHz / 2 * (3+1) = 12 MHz */
|
||||
|
||||
#define SDMMC_MMCXFR_CLKDIV (3 << SDMMC_MR_CLKDIV_SHIFT)
|
||||
|
||||
/* MCK = 96MHz, CLKDIV = 1, MCI_SPEED = 96MHz / 2 * (1+1) = 24 MHz */
|
||||
|
||||
#define SDMMC_SDXFR_CLKDIV (1 << SDMMC_MR_CLKDIV_SHIFT)
|
||||
#define SDMMC_SDWIDEXFR_CLKDIV SDMMC_SDXFR_CLKDIV
|
||||
|
||||
/* SDMMC Card Slots *********************************************************/
|
||||
|
||||
/* The SAMA5D2-XULT provides a SD memory card slot:
|
||||
* a full size SD card slot (J19)
|
||||
*
|
||||
* The full size SD card slot connects via SDMMC1. The card detect discrete
|
||||
* is available on PA30 (pulled high). The write protect discrete is tied to
|
||||
* ground and not available to software. The slot only supports 4-bit
|
||||
* wide transfer mode, and the NuttX driver currently uses only the 4-bit
|
||||
* wide transfer mode.
|
||||
*
|
||||
* PA30 SDMMC1_CD
|
||||
* PA18 SDMMC1_DAT0
|
||||
* PA19 SDMMC1_DAT1
|
||||
* PA20 SDMMC1_DAT2
|
||||
* PA21 SDMMC1_DAT3
|
||||
* PA22 SDMMC1_CK
|
||||
* PA28 SDMMC1_CDA
|
||||
*/
|
||||
|
||||
#define IRQ_SDMMC1_CD SAM_IRQ_PA30
|
||||
|
||||
/* USB Ports ****************************************************************/
|
||||
|
||||
|
|
@ -414,6 +441,42 @@
|
|||
|
||||
int sam_bringup(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_sdmmc_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize and configure one SDMMC slot
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_SDMMC
|
||||
int sam_sdmmc_initialize(int slotno, int minor);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_cardinserted
|
||||
*
|
||||
* Description:
|
||||
* Check if a card is inserted into the selected SDMMC slot
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_SDMMC
|
||||
bool sam_cardinserted(int slotno);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_writeprotected
|
||||
*
|
||||
* Description:
|
||||
* Check if the card in the MMCSD slot is write protected
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_HSMCI
|
||||
bool sam_writeprotected(int slotno);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_usbinitialize
|
||||
*
|
||||
|
|
|
|||
|
|
@ -171,8 +171,8 @@
|
|||
|
||||
/* AT24 Serial EEPROM
|
||||
*
|
||||
* A AT24C512 Serial EEPPROM was used for tested I2C. There are other I2C/TWI
|
||||
* devices on-board, but the serial EEPROM is the simplest test.
|
||||
* A AT24C512 Serial EEPPROM was used for tested I2C. There are other
|
||||
* I2C/TWI devices on-board, but the serial EEPROM is the simplest test.
|
||||
*
|
||||
* There is, however, no AT24 EEPROM on board the SAMA5D3x-EK: The Serial
|
||||
* EEPROM was mounted on an external adaptor board and connected to the
|
||||
|
|
@ -243,9 +243,9 @@
|
|||
# define AT24_MINOR _AT24_MINOR
|
||||
#endif
|
||||
|
||||
/* MMC/SD minor numbers: The NSH device minor extended is extended to support
|
||||
* two devices. If CONFIG_NSH_MMCSDMINOR is zero, these will be: /dev/mmcsd0
|
||||
* and /dev/mmcsd1.
|
||||
/* MMC/SD minor numbers: The NSH device minor extended is extended to
|
||||
* support two devices. If CONFIG_NSH_MMCSDMINOR is zero, these will be:
|
||||
* /dev/mmcsd0 and /dev/mmcsd1.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_NSH_MMCSDMINOR
|
||||
|
|
@ -450,7 +450,7 @@
|
|||
* (2) a microSD memory card slot (J6 labeled MCI1).
|
||||
*
|
||||
* The full size SD card slot connects via HSMCI0. The card detect discrete
|
||||
* is available on PB17 (pulled high). The write protect descrete is tied to
|
||||
* is available on PB17 (pulled high). The write protect discrete is tied to
|
||||
* ground (via PP6) and not available to software. The slot supports 8-bit
|
||||
* wide transfer mode, but the NuttX driver currently uses only the 4-bit
|
||||
* wide transfer mode
|
||||
|
|
@ -602,7 +602,7 @@
|
|||
* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
|
||||
* The board supports RGMII interface mode. The Ethernet interface
|
||||
* consists of 4 pairs of low voltage differential pair signals
|
||||
* designated from GRX± and GTx± plus control signals for link
|
||||
* designated from GRX and GTx plus control signals for link
|
||||
* activity indicators. These signals can be used to connect to a
|
||||
* 10/100/1000 BaseT RJ45 connector integrated on the main board.
|
||||
*
|
||||
|
|
@ -688,7 +688,7 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ Files in this directory
|
|||
|
||||
dev_null.c and dev_zero.c
|
||||
These files provide the standard /dev/null and /dev/zero devices. See
|
||||
include/nuttx/drivers/driers.h for prototypes of functions that should
|
||||
include/nuttx/drivers/drivers.h for prototypes of functions that should
|
||||
be called if you want to register these devices (devnull_register()
|
||||
and devzero_register()).
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue