diff --git a/Documentation/components/drivers/character/timers/capture.rst b/Documentation/components/drivers/character/timers/capture.rst index 026174e83a1..50208b54f37 100644 --- a/Documentation/components/drivers/character/timers/capture.rst +++ b/Documentation/components/drivers/character/timers/capture.rst @@ -109,7 +109,7 @@ To enable the capture driver, enable the following configuration options: * ``CONFIG_CAPTURE`` - Enable the capture driver framework * ``CONFIG_CAPTURE_NOTIFY`` - Enable signal notification support for edge events * ``CONFIG_FAKE_CAPTURE`` - Enable fake capture driver for testing (generates 10Hz signal with 50% duty cycle) -* ``CONFIG_STM32H7_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific) +* ``CONFIG_STM32_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific) The ``CONFIG_CAPTURE`` option enables the lower-half driver and registers the ``/dev/capture`` device. diff --git a/Documentation/guides/renode.rst b/Documentation/guides/renode.rst index b3918d2e8ca..ccafddf944f 100644 --- a/Documentation/guides/renode.rst +++ b/Documentation/guides/renode.rst @@ -119,7 +119,7 @@ nucleo-h743zi ============= Renode doesn't support ``PWR_CSR1_ACTVOSRDY`` bit so we have to disable -it with ``CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY=y``. +it with ``CONFIG_STM32_PWR_IGNORE_ACTVOSRDY=y``. Renode script:: diff --git a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst index bcba3e81df6..0adfaf55625 100644 --- a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst +++ b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst @@ -721,7 +721,7 @@ After that check if your PC recognized the usb driver:: [27221.266103] sd 0:0:0:0: [sda] Attached SCSI removable disk [27228.147377] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. -**OBS:** This example disable the macro CONFIG_STM32H7_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c +**OBS:** This example disable the macro CONFIG_STM32_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c netnsh ------ diff --git a/Documentation/platforms/arm/stm32h7/index.rst b/Documentation/platforms/arm/stm32h7/index.rst index b042e33c30c..61e1f4387be 100644 --- a/Documentation/platforms/arm/stm32h7/index.rst +++ b/Documentation/platforms/arm/stm32h7/index.rst @@ -114,7 +114,7 @@ The selection of the core for which the image is build is made using options: - ``CONFIG_ARCH_CHIP_STM32H7_CORTEXM4`` - selects Cortex-M4 core Support for the CM7 core is always enabled, support for the CM4 core is controlled -with the ``CONFIG_STM32H7_CORTEXM4_ENABLED`` option. +with the ``CONFIG_STM32_CORTEXM4_ENABLED`` option. Interprocessor communication between cores is realized with the NuttX RPTUN device based on the OpenAMP framework. ``HSEM`` is used for synchronization and diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ea411453337..b4c6ffbadf3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -639,6 +639,7 @@ config ARCH_CHIP_STM32F7 config ARCH_CHIP_STM32H7 bool "STMicro STM32 H7" + select ARCH_CHIP_STM32 select ARCH_HAVE_MPU select ARCH_HAVE_I2CRESET select ARCH_HAVE_PROGMEM diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index 2aa62e17e93..aab8d553109 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -91,10 +91,10 @@ /* Size SRAM */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || defined(CONFIG_STM32_STM32H7X3XX) || defined(CONFIG_STM32_STM32H7X5XX) /* Memory */ -# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX # define STM32_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ # define STM32_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ # define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ @@ -152,7 +152,7 @@ # define STM32_NSAI (4) /* (4) SAI1-4*/ # define STM32_NCAN (2) /* (2) CAN1-2 */ # define STM32_NSDIO (2) /* (2) SDIO */ -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) /* Memory */ # define STM32_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ @@ -206,7 +206,7 @@ # define STM32_NSAI (4) /* (4) SAI1-4*/ # define STM32_NCAN (2) /* (2) CAN1-2 */ # define STM32_NSDIO (2) /* (2) SDIO */ -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) /* Memory */ # define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ @@ -259,13 +259,13 @@ /* Diversification based on Family and package */ -#if defined(CONFIG_STM32H7_HAVE_ETHERNET) +#if defined(CONFIG_STM32_HAVE_ETHERNET) # define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else # define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif -#if defined(CONFIG_STM32H7_HAVE_FMC) +#if defined(CONFIG_STM32_HAVE_FMC) # define STM32_NFMC 1 /* Have FMC memory controller */ #else # define STM32_NFMC 0 /* No FMC memory controller */ diff --git a/arch/arm/include/stm32h7/irq.h b/arch/arm/include/stm32h7/irq.h index 427d6b8c1f2..24cfc5f4add 100644 --- a/arch/arm/include/stm32h7/irq.h +++ b/arch/arm/include/stm32h7/irq.h @@ -69,19 +69,19 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # if CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # include # else # include # endif -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include #else # error "Unsupported STM32 H7 chip" diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index e1636a3fb8d..b226502c093 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -35,7 +35,7 @@ list( stm32_serial.c stm32_uid.c) -if(CONFIG_STM32H7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -43,7 +43,7 @@ if(CONFIG_ARCH_STM32H7_DUALCORE) list(APPEND SRCS stm32_dualcore.c) endif() -if(CONFIG_STM32H7_HSEM) +if(CONFIG_STM32_HSEM) list(APPEND SRCS stm32_hsem.c) endif() @@ -57,7 +57,7 @@ else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32H7_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) endif() @@ -73,47 +73,51 @@ if(CONFIG_ARMV7M_DTCM) list(APPEND SRCS stm32_dtcm.c) endif() -if(CONFIG_STM32H7_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H7_FDCAN) +if(CONFIG_STM32_FDCAN) list(APPEND SRCS stm32_fdcan_sock.c) endif() -if(CONFIG_STM32H7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_STM32H7_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() -if(CONFIG_STM32H7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_fmc.c) endif() -if(CONFIG_STM32H7_IWDG OR CONFIG_STM32H7_RTC_LSICLOCK) +if(CONFIG_STM32_RNG) + list(APPEND SRCS stm32_rng.c) +endif() + +if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) list(APPEND SRCS stm32_lsi.c) endif() -if(CONFIG_STM32H7_RTC_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32H7_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32H7_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() -if(CONFIG_STM32H7_QSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32H7_RTC) +if(CONFIG_STM32_RTC) list(APPEND SRCS stm32_rtc.c) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) @@ -126,7 +130,7 @@ if(CONFIG_STM32H7_RTC) endif() endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() @@ -134,7 +138,7 @@ if(CONFIG_SPI_SLAVE) list(APPEND SRCS stm32_spi_slave.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -142,7 +146,7 @@ if(CONFIG_TIMER) list(APPEND SRCS stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32H7_TIMX_CAP) +if(CONFIG_STM32_TIMX_CAP) list(APPEND SRCS stm32_capture.c) endif() @@ -150,7 +154,7 @@ if(CONFIG_CAPTURE) list(APPEND SRCS stm32_capture_lowerhalf.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_ltdc.c) endif() @@ -169,15 +173,15 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32H7_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() -if(CONFIG_STM32H7_LPTIM) +if(CONFIG_STM32_LPTIM) list(APPEND SRCS stm32_lptim.c) endif() -if(CONFIG_STM32H7_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -185,7 +189,7 @@ if(CONFIG_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32H7_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() @@ -204,12 +208,20 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32H7_IWDG) +if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32_iwdg.c) endif() -if(CONFIG_STM32H7_WWDG) +if(CONFIG_STM32_WWDG) list(APPEND SRCS stm32_wwdg.c) endif() +if(CONFIG_STM32_CRYP AND CONFIG_STM32_HAVE_IP_CRYPTO_H7) + list(APPEND SRCS stm32_aes.c) +endif() + +if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_H7) + list(APPEND SRCS stm32_crypto.c) +endif() + target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index bc7c0670d88..90ec8b7febf 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -7,6 +7,51 @@ if ARCH_CHIP_STM32H7 comment "STM32 H7 Configuration Options" +config STM32_H7_PERIPHERALS + bool + default ARCH_CHIP_STM32H7 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM3 + select STM32_HAVE_LPTIM4 + select STM32_HAVE_OTGFS + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKPSRAM + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART6 + select STM32_HAVE_HSEM + select STM32_HAVE_CSI + select STM32_HAVE_HSI48 + select STM32_HAVE_MDMA + select STM32_HAVE_BDMA + select STM32_HAVE_OTG_H7 + select STM32_HAVE_OTGHS + select STM32_HAVE_USART_RXFIFO_THRESHOLD + select STM32_HAVE_FDCAN_H7 + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 H7 Chip Selection" default ARCH_CHIP_STM32H743ZI @@ -14,34 +59,34 @@ choice config ARCH_CHIP_STM32H723VG bool "STM32H723VG" - select STM32H7_STM32H7X3XX - select STM32H7_STM32H72XXX_OR_STM32H73XXX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_FDCAN3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_FDCAN3 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM, LQFP144 config ARCH_CHIP_STM32H723ZG bool "STM32H723ZG" - select STM32H7_STM32H7X3XX - select STM32H7_STM32H72XXX_OR_STM32H73XXX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_FDCAN3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_FDCAN3 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM, LQFP144 config ARCH_CHIP_STM32H743AG bool "STM32H743AG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_A ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -49,8 +94,8 @@ config ARCH_CHIP_STM32H743AG config ARCH_CHIP_STM32H743AI bool "STM32H743AI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -58,8 +103,8 @@ config ARCH_CHIP_STM32H743AI config ARCH_CHIP_STM32H743BG bool "STM32H743BG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -67,8 +112,8 @@ config ARCH_CHIP_STM32H743BG config ARCH_CHIP_STM32H743BI bool "STM32H743BI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -76,8 +121,8 @@ config ARCH_CHIP_STM32H743BI config ARCH_CHIP_STM32H743IG bool "STM32H743IG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -85,8 +130,8 @@ config ARCH_CHIP_STM32H743IG config ARCH_CHIP_STM32H743II bool "STM32H743II" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -94,8 +139,8 @@ config ARCH_CHIP_STM32H743II config ARCH_CHIP_STM32H743VG bool "STM32H743VG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -103,8 +148,8 @@ config ARCH_CHIP_STM32H743VG config ARCH_CHIP_STM32H743VI bool "STM32H743VI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -112,8 +157,8 @@ config ARCH_CHIP_STM32H743VI config ARCH_CHIP_STM32H743XG bool "STM32H743XG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -121,8 +166,8 @@ config ARCH_CHIP_STM32H743XG config ARCH_CHIP_STM32H743XI bool "STM32H743XI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -130,8 +175,8 @@ config ARCH_CHIP_STM32H743XI config ARCH_CHIP_STM32H743ZG bool "STM32H743ZG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -139,8 +184,8 @@ config ARCH_CHIP_STM32H743ZG config ARCH_CHIP_STM32H743ZI bool "STM32H743ZI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -148,8 +193,8 @@ config ARCH_CHIP_STM32H743ZI config ARCH_CHIP_STM32H745BG bool "STM32H745BG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -157,8 +202,8 @@ config ARCH_CHIP_STM32H745BG config ARCH_CHIP_STM32H745BI bool "STM32H745BI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -166,8 +211,8 @@ config ARCH_CHIP_STM32H745BI config ARCH_CHIP_STM32H745IG bool "STM32H745IG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -175,8 +220,8 @@ config ARCH_CHIP_STM32H745IG config ARCH_CHIP_STM32H745II bool "STM32H745II" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -184,8 +229,8 @@ config ARCH_CHIP_STM32H745II config ARCH_CHIP_STM32H745XG bool "STM32H745XG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -193,8 +238,8 @@ config ARCH_CHIP_STM32H745XG config ARCH_CHIP_STM32H745XI bool "STM32H745XI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -202,8 +247,8 @@ config ARCH_CHIP_STM32H745XI config ARCH_CHIP_STM32H745ZG bool "STM32H745ZG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -211,8 +256,8 @@ config ARCH_CHIP_STM32H745ZG config ARCH_CHIP_STM32H745ZI bool "STM32H745ZI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -220,165 +265,170 @@ config ARCH_CHIP_STM32H745ZI config ARCH_CHIP_STM32H747XI bool "STM32H747XI" - select STM32H7_STM32H7X7XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X7XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_SMPS + select STM32_HAVE_SMPS ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM TFBGA240 config ARCH_CHIP_STM32H750VB bool "STM32H750VB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100 config ARCH_CHIP_STM32H750ZB bool "STM32H750ZB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 config ARCH_CHIP_STM32H750IB bool "STM32H750IB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176 or UFBGA176+25 config ARCH_CHIP_STM32H750XB bool "STM32H750XB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240+25 config ARCH_CHIP_STM32H753AI bool "STM32H753AI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, UFBGA169 config ARCH_CHIP_STM32H753BI bool "STM32H753BI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP208 config ARCH_CHIP_STM32H753II bool "STM32H753II" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 config ARCH_CHIP_STM32H753VI bool "STM32H753VI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100/TFBGA100 config ARCH_CHIP_STM32H753XI bool "STM32H753XI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240 config ARCH_CHIP_STM32H753ZI bool "STM32H753ZI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 config ARCH_CHIP_STM32H7B3LI bool "STM32H7B3LI" - select STM32H7_STM32H7B3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7B3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_L - select STM32H7_HAVE_SMPS - select STM32H7_HAVE_CRYP + select STM32_HAVE_SMPS + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1376 Kb SRAM, with cryptographic accelerator, TFBGA225 config ARCH_CHIP_STM32H755II bool "STM32H755II" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_CRYP + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 config ARCH_CHIP_STM32H755XI bool "STM32H755XI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_CRYP + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240 endchoice # STM32 H7 Chip Selection -config STM32H7_HAVE_SMPS - bool - default n - -config STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY - bool - default n - -config STM32H7_PWR_DIRECT_SMPS_SUPPLY +config STM32_PWR_DIRECT_SMPS_SUPPLY bool "Use direct SMPS supply mode" - depends on STM32H7_HAVE_SMPS + depends on STM32_HAVE_SMPS default n -config STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY +config STM32_PWR_EXTERNAL_SOURCE_SUPPLY bool "Use external source as power supply" default n ---help--- @@ -386,8 +436,8 @@ config STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY choice prompt "STM32 H7 Power Supply Selection" - default STM32H7_PWR_DEFAULT_SUPPLY - depends on STM32H7_HAVE_SMPS && !STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY + default STM32_PWR_DEFAULT_SUPPLY + depends on STM32_HAVE_SMPS && !STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY ---help--- The STM32H7x5 and STM32H7x7 support power supply configurations for the VCORE core domain and an external supply, by configuring the SMPS step-down converter and voltage regulator. @@ -395,15 +445,15 @@ choice Currently the only supported modes are Direct SMPS supply and LDO supply. -config STM32H7_PWR_DEFAULT_SUPPLY +config STM32_PWR_DEFAULT_SUPPLY bool "Default" -config STM32H7_PWR_LDO_SUPPLY +config STM32_PWR_LDO_SUPPLY bool "Use LDO supply mode" endchoice # "STM32 H7 Power Supply Selection" -config STM32H7_PWR_IGNORE_ACTVOSRDY +config STM32_PWR_IGNORE_ACTVOSRDY bool "Ignore PWR_CSR1_ACTVOSRDY bit" default n ---help--- @@ -411,38 +461,45 @@ config STM32H7_PWR_IGNORE_ACTVOSRDY This is workaround for Renode simulation that doesn't implement this feature. config STM32H7_IO_CONFIG_A + # Package designator A bool default n config STM32H7_IO_CONFIG_B + # Package designator B bool default n config STM32H7_IO_CONFIG_I + # Package designator I bool default n config STM32H7_IO_CONFIG_L + # Package designator L bool default n config STM32H7_IO_CONFIG_V + # Package designator V bool default n config STM32H7_IO_CONFIG_X + # Package designator X bool default n config STM32H7_IO_CONFIG_Z + # Package designator Z bool default n config ARCH_STM32H7_DUALCORE bool default n - select STM32H7_HSEM if !STM32H7_CORTEXM4_DISABLED - select STM32H7_HAVE_CM4 + select STM32_HSEM if !STM32_CORTEXM4_DISABLED + select STM32_HAVE_CM4 choice prompt "STM32 H7 Core selection" @@ -463,141 +520,165 @@ config ARCH_CHIP_STM32H7_CORTEXM4 endchoice # STM32 H7 Core selection -config STM32H7_STM32H7X0XX +config STM32_STM32H7X0XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG -config STM32H7_STM32H7X3XX +config STM32_STM32H7X3XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG -config STM32H7_STM32H7B3XX +config STM32_STM32H7B3XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG -config STM32H7_STM32H7X5XX +config STM32_STM32H7X5XX bool default n select ARCH_STM32H7_DUALCORE select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_SMPS - select STM32H7_HAVE_RNG + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_SMPS + select STM32_HAVE_RNG -config STM32H7_STM32H7X7XX +config STM32_STM32H7X7XX bool default n select ARCH_STM32H7_DUALCORE select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF - select STM32H7_HAVE_GPIOG - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF + select STM32_HAVE_GPIOG + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG # The reduced SRAM configuration STM32H72X and STM32H73X -config STM32H7_STM32H72XXX_OR_STM32H73XXX +config STM32_STM32H72XXX_OR_STM32H73XXX bool default n -config STM32H7_FLASH_CONFIG_B - bool - default n - -config STM32H7_FLASH_CONFIG_G - bool - default n - -config STM32H7_FLASH_CONFIG_I - bool - default n - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32H7 - default STM32H7_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32H7 series parts numbering (sans the package type) ends with a - letter that designates the FLASH size. - - Designator Size in KiB - B 128 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based - on that designator or the default smaller size if there is no last - character designator is present in the STM32 Chip Selection. - - Examples: - - If the STM32H743ZI is chosen, the Flash configuration would be - 'I', if a variant of the part is released in the future one - could simply select another designator here. - - If an STM32H7xxx Series parts is chosen the default Flash - configuration will be set herein and can be changed. - -config STM32H7_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32H7_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32H7_FLASH_OVERRIDE_G - bool "G 1048KiB" - -config STM32H7_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # "Override Flash Size Designator" - -config STM32H7_FLASH_CR_PSIZE +config STM32_FLASH_CR_PSIZE int "Flash program size width" depends on ARCH_CHIP_STM32H7 default 3 @@ -611,7 +692,7 @@ config STM32H7_FLASH_CR_PSIZE 2: 32 bits 3: 64 bits (default) -config STM32H7_AXI_SRAM_CORRUPTION_WAR +config STM32_AXI_SRAM_CORRUPTION_WAR bool "Errata 2.2.9 Reading from AXI SRAM data read corruption Workaround" default y ---help--- @@ -631,47 +712,36 @@ if ARCH_STM32H7_DUALCORE if ARCH_CHIP_STM32H7_CORTEXM7 -config STM32H7_CORTEXM4_ENABLED +config STM32_CORTEXM4_ENABLED bool "Enable support for M4 core" default y -config STM32H7_CORTEXM7_BOOTM4 +config STM32_CORTEXM7_BOOTM4 bool "Boot M4 core" - select STM32H7_SYSCFG - default y if STM32H7_CORTEXM4_ENABLED + select STM32_SYSCFG + default y if STM32_CORTEXM4_ENABLED default n endif # ARCH_CHIP_STM32H7_CORTEXM7 -config STM32H7_CORTEXM7_FLASH_SIZE +config STM32_CORTEXM7_FLASH_SIZE int "Flash reserved for M7 core" - default 1048576 if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 + default 1048576 if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 default 2097152 -config STM32H7_CORTEXM7_SHMEM +config STM32_CORTEXM7_SHMEM bool select ARM_MPU if ARCH_CHIP_STM32H7_CORTEXM7 - default y if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 + default y if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 default n -config STM32H7_SHMEM_SRAM3 +config STM32_SHMEM_SRAM3 bool "Use SRAM3 as shared memory" - depends on STM32H7_CORTEXM7_SHMEM + depends on STM32_CORTEXM7_SHMEM default y endif # ARCH_STM32H7_DUALCORE -config STM32_HAVE_OTA_PARTITION - bool - default n - -config STM32H7_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain an uniform flash memory mapping. - menu "Application Image Configuration" choice prompt "Application Image Format" @@ -711,1650 +781,7 @@ endchoice # Application Image Format endmenu # Application Image Configuration -menu "STM32H7 Peripheral Selection" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32H7_HAVE_CM4 - bool - default n - -config STM32H7_HAVE_LTDC - bool - default n - -config STM32H7_HAVE_ETHERNET - bool - default n - -config STM32H7_HAVE_PHY_POLLED - bool - default n - -config STM32H7_HAVE_FMC - bool - default n - -config STM32H7_HAVE_GPIOF - bool - default n - -config STM32H7_HAVE_GPIOG - bool - default n - -config STM32H7_HAVE_SPI4 - bool - default n - -config STM32H7_HAVE_SPI5 - bool - default n - -config STM32H7_HAVE_SPI6 - bool - default n - -config STM32H7_HAVE_FDCAN1 - bool - default n - -config STM32H7_HAVE_FDCAN2 - bool - default n - -config STM32H7_HAVE_FDCAN3 - bool - default n - -config STM32H7_HAVE_RNG - bool - default n - -config STM32H7_HAVE_CRYP - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32H7_ADC - bool - default n - -config STM32H7_FDCAN - bool - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - select NET_CAN_EXTID - select NET_CAN_HAVE_TX_DEADLINE - default n - -config STM32H7_DAC - bool - default n - -config STM32H7_DMA - bool - default n - -config STM32H7_I2C - bool - default n - -config STM32H7_SAI - bool - default n - -config STM32H7_SDMMC - bool - default n - -config STM32H7_SPI - bool - default n - -config STM32H7_SPI_DMA - bool - default n - -config STM32H7_TIM - bool - default n - -config STM32H7_LPTIM - bool - default n - -config STM32H7_HSEM - bool "Hardware semaphore" - default n - -config STM32H7_RTC - bool "RTC" - default n - select RTC - -config STM32H7_CSI - bool "CSI Low-speed internal oscillator (4MHz)" - default n - -config STM32H7_HSI48 - bool "HSI48 High-speed 48MHz internal oscillator" - default n - -config STM32H7_PWR - bool "PWR" - default n - -config STM32H7_PWM - bool - default n - -config STM32H7_USART - bool - default n - -# These are the peripheral selections proper -config STM32H7_ADC1 - bool "ADC1" - default n - select STM32H7_ADC - -config STM32H7_ADC2 - bool "ADC2" - default n - select STM32H7_ADC - -config STM32H7_ADC3 - bool "ADC3" - default n - select STM32H7_ADC - -config STM32H7_RNG - bool "RNG" - default n - depends on STM32H7_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32H7_CRC - bool "CRC" - default n - -config STM32H7_CRYP - bool "CRYP" - default n - depends on STM32H7_HAVE_CRYP - -config STM32H7_BKPSRAM - bool "Enable BKP RAM Domain" - select STM32H7_PWR - default n - -config STM32H7_DMA1 - bool "DMA1" - default n - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_DMA2 - bool "DMA2" - default n - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_MDMA - bool "MDMA" - default n - depends on EXPERIMENTAL - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_BDMA - bool "BDMA" - default n - depends on EXPERIMENTAL - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32H7_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32H7_HAVE_PHY_POLLED - -config STM32H7_FMC - bool "FMC" - default n - depends on STM32H7_HAVE_FMC - ---help--- - Enable Flexible Memory Controller. - To correctly configure FMC for your hardware, you will have to define - a number of macros in your board.h file. See stm32_fmc.c for directions. - -config STM32H7_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32H7_OTGHS - bool "OTG FS/HS" - default n - depends on EXPERIMENTAL - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32H7_OTG_SOFOUTPUT - bool "OTG SOF output" - default n - -config STM32H7_OTG_USBREGEN - bool "Enable USB voltage regulator" - default n - -config STM32H7_QSPI - bool "QuadSPI" - default n - -config STM32H7_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - default n - depends on USBDEV - -config STM32H7_USBHOST_REGDEBUG - bool "OTG USBHOST REGDEBUG" - default n - depends on USBHOST - -config STM32H7_USBHOST_PKTDUMP - bool "OTG USBHOST PKTDUMP" - default n - depends on USBHOST - -config STM32H7_SDMMC1 - bool "SDMMC1" - default n - select STM32H7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32H7_SDMMC2 - bool "SDMMC2" - default n - select STM32H7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32H7_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32H7_WWDG - bool "WWDG" - default n - select WATCHDOG - -menu "STM32H7 FDCAN Selection" - -config STM32H7_FDCAN1 - bool "FDCAN1" - default n - select STM32H7_FDCAN - -config STM32H7_FDCAN2 - bool "FDCAN2" - default n - select STM32H7_FDCAN - -config STM32H7_FDCAN3 - bool "FDCAN3" - default n - select STM32H7_FDCAN - -endmenu # STM32H7 FDCAN Selection - -menu "STM32H7 I2C Selection" - -config STM32H7_I2C1 - bool "I2C1" - default n - select STM32H7_I2C - -config STM32H7_I2C2 - bool "I2C2" - default n - select STM32H7_I2C - -config STM32H7_I2C3 - bool "I2C3" - default n - select STM32H7_I2C - -config STM32H7_I2C4 - bool "I2C4" - default n - select STM32H7_I2C - -endmenu # STM32H7 I2C Selection - -config STM32H7_LTDC - bool "LTDC" - default n - select FB - depends on STM32H7_HAVE_LTDC - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32H7 devices. - It features a standard RGB888 parallel video interface (along - with HSYNC, VSYNC, etc.) for controlling TFT LCD displays. - In some STM32H7 devices the graphics signals can optionally - be output via DSI instead of the parallel interface: - See config options STM32H7_DSIHOST and STM32H7_LTDC_USE_DSI. - -menu "STM32H7 SPI Selection" - -config STM32H7_SPI1 - bool "SPI1" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI2 - bool "SPI2" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI3 - bool "SPI3" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI4 - bool "SPI4" - default n - depends on STM32H7_HAVE_SPI4 - select SPI - select STM32H7_SPI - -config STM32H7_SPI5 - bool "SPI5" - default n - depends on STM32H7_HAVE_SPI5 - select SPI - select STM32H7_SPI - -config STM32H7_SPI6 - bool "SPI6" - default n - depends on STM32H7_HAVE_SPI6 - select SPI - select STM32H7_SPI - -endmenu # STM32H7 SPI Selection - -config STM32H7_SYSCFG - bool "SYSCFG" - default y - -menu "STM32H7 Timer Selection" - -config STM32H7_TIM1 - bool "TIM1" - default n - select STM32H7_TIM - -config STM32H7_TIM2 - bool "TIM2" - default n - select STM32H7_TIM - -config STM32H7_TIM3 - bool "TIM3" - default n - select STM32H7_TIM - -config STM32H7_TIM4 - bool "TIM4" - default n - select STM32H7_TIM - -config STM32H7_TIM5 - bool "TIM5" - default n - select STM32H7_TIM - -config STM32H7_TIM6 - bool "TIM6" - default n - select STM32H7_TIM - -config STM32H7_TIM7 - bool "TIM7" - default n - select STM32H7_TIM - -config STM32H7_TIM8 - bool "TIM8" - default n - select STM32H7_TIM - -config STM32H7_TIM12 - bool "TIM12" - default n - select STM32H7_TIM - -config STM32H7_TIM13 - bool "TIM13" - default n - select STM32H7_TIM - -config STM32H7_TIM14 - bool "TIM14" - default n - select STM32H7_TIM - -config STM32H7_TIM15 - bool "TIM15" - default n - select STM32H7_TIM - -config STM32H7_TIM16 - bool "TIM16" - default n - select STM32H7_TIM - -config STM32H7_TIM17 - bool "TIM17" - default n - select STM32H7_TIM - -endmenu # STM32H7 Timer Selection - -menu "STM32H7 Low-power Timer Selection" - -config STM32H7_LPTIM1 - bool "LPTIM1" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM2 - bool "LPTIM2" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM3 - bool "LPTIM3" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM4 - bool "LPTIM4" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM5 - bool "LPTIM5" - default n - select STM32H7_LPTIM - -endmenu # STM32H7 Low-power Timer Selection - -menu "STM32H7 U[S]ART Selection" - -config STM32H7_USART1 - bool "USART1" - default n - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H7_USART - -config STM32H7_USART2 - bool "USART2" - default n - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H7_USART - -config STM32H7_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART3_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART4_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART5_SERIALDRIVER - select STM32H7_USART - -config STM32H7_USART6 - bool "USART6" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART6_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART7 - bool "UART7" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART7_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART8 - bool "UART8" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART8_SERIALDRIVER - select STM32H7_USART - -endmenu # STM32H7 U[S]ART Selection -endmenu # STM32H7 Peripheral Selection - -config STM32H7_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - select STM32H7_CSI - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V - -menu "OTG_HS Configuration" - depends on STM32H7_OTGHS - -config STM32H7_OTGHS_FS - bool "OTGHS in FS mode" - default n - -choice - prompt "ULPI Selection" - default STM32H7_OTGHS_NO_ULPI - -config STM32H7_OTGHS_NO_ULPI - bool "No External ULPI on board." - ---help--- - Select to indicate that there is no external ULPI PHY. This means the OTG_HS - peripheral must use the internal full-speed PHY and will be limited to - full-speed mode. - -config STM32H7_OTGHS_EXTERNAL_ULPI - bool "External ULPI" - ---help--- - Select to indicate the presence of an external ULPI PHY and use it. - -endchoice #"ULPI Selection" - -endmenu # OTG_HS Config - -menu "I2C Configuration" - depends on STM32H7_I2C - -config STM32H7_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32H7_I2C - -config STM32H7_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32H7_I2C_DYNTIMEO - -config STM32H7_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32H7_I2C_DYNTIMEO - -config STM32H7_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32H7_I2C - -config STM32H7_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32H7_I2C && !STM32H7_I2C_DYNTIMEO - -config STM32H7_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32H7_I2C && !STM32H7_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "OTG Configuration" - depends on STM32H7_OTGFS || STM32H7_OTGHS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -choice - prompt "STM32H7 OTGFS role" - depends on STM32H7_OTGFS - default STM32H7_OTGFS_USBDEV if USBDEV - default STM32H7_OTGFS_HOST if !USBDEV && USBHOST - -config STM32H7_OTGFS_USBDEV - bool "OTGFS as USBDEV" - depends on USBDEV - -config STM32H7_OTGFS_HOST - bool "OTGFS as HOST" - depends on USBHOST - -endchoice # "STM32H7 OTGFS role" - -choice - prompt "STM32H7 OTGHS role (only USBDEV supported for now)" - depends on STM32H7_OTGHS - default STM32H7_OTGHS_USBDEV if USBDEV - -config STM32H7_OTGHS_USBDEV - bool "OTGHS as USBDEV" - depends on USBDEV - -endchoice # "STM32H7 OTGHS role" - -endmenu # OTG Configuration - -menu "SPI Configuration" - depends on STM32H7_SPI - -config STM32H7_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32H7_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32H7_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32H7_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32H7_SPI1 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32H7_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32H7_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32H7_SPI2 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32H7_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32H7_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32H7_SPI3 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32H7_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32H7_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32H7_SPI4 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32H7_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32H7_SPI4_COMMTYPE - int "SPI4 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI4 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32H7_SPI5 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32H7_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32H7_SPI5_COMMTYPE - int "SPI5 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI5 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32H7_SPI6 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32H7_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -config STM32H7_SPI6_COMMTYPE - int "SPI6 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI6 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # "SPI Configuration" - -menu "U[S]ART Configuration" - depends on STM32H7_USART - -if STM32H7_USART1 - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART1 - -if STM32H7_USART2 - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART2 - -if STM32H7_USART3 - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXFIFO_THRES - int "USART3 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART3 - -if STM32H7_UART4 - -config UART4_RS485 - bool "RS-485 on UART4" - default n - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXFIFO_THRES - int "UART4 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART4 - -if STM32H7_UART5 - -config UART5_RS485 - bool "RS-485 on UART5" - default n - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXFIFO_THRES - int "UART5 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART5 - -if STM32H7_USART6 - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXFIFO_THRES - int "USART6 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART - -if STM32H7_UART7 - -config UART7_RS485 - bool "RS-485 on UART7" - default n - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXFIFO_THRES - int "UART7 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART7 - -if STM32H7_UART8 - -config UART8_RS485 - bool "RS-485 on UART8" - default n - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXFIFO_THRES - int "UART8 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART8 - -config STM32H7_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32H7_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32H7_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on SERIAL_IFLOWCONTROL_WATERMARKS - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32H7_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32H7_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32H7_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32H7 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32H7_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32H7_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32H7 serial driver. - -config STM32H7_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32H7_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32H7 serial driver. - -config STM32H7_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32H7_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32H7 serial driver. - -if PM - -config STM32H7_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # PM -endmenu # U[S]ART Configuration - -menu "ADC Configuration" - depends on STM32H7_ADC - -config STM32H7_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32H7_ADC1_DMA - bool "ADC1 DMA (not supported yet)" - depends on STM32H7_ADC1 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32H7_ADC1 && STM32H7_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H7_ADC2_DMA - bool "ADC2 DMA (not supported yet)" - depends on STM32H7_ADC2 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32H7_ADC2 && STM32H7_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H7_ADC3_DMA - bool "ADC3 DMA (not supported yet)" - depends on STM32H7_ADC3 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32H7_ADC3 && STM32H7_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -endmenu # ADC Configuration - -menu "SD/MMC Configuration" - depends on STM32H7_SDMMC - -config STM32H7_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32H7_SDMMC_IDMA - bool "Support IDMA data transfers" - default y - select SDIO_DMA - ---help--- - Support IDMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32H7_SDMMC1 - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC1 Configuration" - -menu "SDMMC2 Configuration" - depends on STM32H7_SDMMC2 - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC2 Configuration" -endmenu # "SD/MMC Configuration" - -if STM32H7_BKPSRAM - -config STM32H7_BBSRAM - bool "BBSRAM File Support" - default n - select ARM_MPU - -config STM32H7_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - depends on STM32H7_BBSRAM - -config STM32H7_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - depends on STM32H7_BBSRAM - -endif # STM32H7_BKPSRAM - -config STM32H7_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32H7_RTC - -config STM32H7_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32H7_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32H7_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32H7_RTC_LSECLOCK - -config STM32H7_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -config STM32H7_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32H7_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -endchoice #"RTC clock source" - -if STM32H7_RTC_LSECLOCK - -config STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the correct* values from low to high. To - avoid damaging the crystal, we want to use the lowest setting that - gets the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - *It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - -config STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - -config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - depends on !STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - - WARNING this RUN setting does not appear to work! It appears - that the LSEDRV bits cannot be changed once the OSC is running. - -endif # STM32H7_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "QuadSPI Configuration" - depends on STM32H7_QSPI - -config STM32H7_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32H7 QSPI peripheral requires the size of the Flash be specified - -config STM32H7_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32H7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32H7_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32H7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32H7_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H7_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32H7_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32H7_QSPI_DMA - bool "DMA" - depends on STM32H7_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice # Transfer technique - -choice - prompt "Bank selection" - default STM32H7_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H7_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32H7_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32H7_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice # Bank selection - -choice - prompt "DMA Priority" - default STM32H7_QSPI_DMAPRIORITY_MEDIUM - depends on STM32H7_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32H7_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32H7_DMA - ---help--- - 'Highest' priority. - -config STM32H7_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32H7_DMA - ---help--- - 'High' priority. - -config STM32H7_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32H7_DMA - ---help--- - 'Medium' priority. - -config STM32H7_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32H7_DMA - ---help--- - 'Low' priority. - -endchoice # DMA Priority - -config STM32H7_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32H7_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32H7_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32H7_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32H7_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu # QuadSPI Configuration - -config STM32H7_BYPASS_CLOCKCONFIG +config STM32_BYPASS_CLOCKCONFIG bool "Bypass clock configuration" depends on ARCH_STM32H7_DUALCORE default n if ARCH_CHIP_STM32H7_CORTEXM7 @@ -2363,13 +790,7 @@ config STM32H7_BYPASS_CLOCKCONFIG Bypass clock configuration. For dual core chips only one core should configure clocks -config STM32H7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32H7_SRAM4EXCLUDE +config STM32_SRAM4EXCLUDE bool "Exclude SRAM4 from the heap" default y if RPTUN default n @@ -2377,4280 +798,6 @@ config STM32H7_SRAM4EXCLUDE Exclude SRAM4 from the HEAP in order to use this 64 KB region for other uses, such as DMA buffers, etc. -config STM32H7_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - default LIBC_ARCH_ELF - depends on ARMV7M_HAVE_DTCM - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32H7_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - default n - depends on ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32H7_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default n - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32H7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - default n - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32H7_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32H7_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32H7_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32H7_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32H7_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32H7_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32H7_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32H7_TIM1 - select STM32H7_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM1_PWM - -config STM32H7_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H7_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32H7_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM1_CHANNEL1 - -config STM32H7_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL1 - -config STM32H7_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM1_CHANNEL2 - -config STM32H7_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL2 - -config STM32H7_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM1_CHANNEL3 - -config STM32H7_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL3 - -config STM32H7_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM1_CHANNEL4 - -config STM32H7_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM1_CHANNEL4 - -config STM32H7_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H7_TIM1_CHANNEL5 - -config STM32H7_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H7_TIM1_CHANNEL5 - -config STM32H7_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H7_TIM1_CHANNEL6 - -config STM32H7_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H7_TIM1_CHANNEL6 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM1_CHANNEL = 1 - -config STM32H7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 1 - -if STM32H7_TIM1_CHANNEL = 2 - -config STM32H7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 2 - -if STM32H7_TIM1_CHANNEL = 3 - -config STM32H7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 3 - -if STM32H7_TIM1_CHANNEL = 4 - -config STM32H7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM1_CHANNEL = 4 - -config STM32H7_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM1_PWM - -config STM32H7_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32H7_TIM2 - select STM32H7_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM2_PWM - -config STM32H7_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM2_CHANNEL1 - -config STM32H7_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM2_CHANNEL1 - -config STM32H7_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM2_CHANNEL2 - -config STM32H7_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM2_CHANNEL2 - -config STM32H7_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM2_CHANNEL3 - -config STM32H7_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM2_CHANNEL3 - -config STM32H7_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM2_CHANNEL4 - -config STM32H7_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM2_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM2_CHANNEL = 1 - -config STM32H7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM2_CHANNEL = 1 - -if STM32H7_TIM2_CHANNEL = 2 - -config STM32H7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM2_CHANNEL = 2 - -if STM32H7_TIM2_CHANNEL = 3 - -config STM32H7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM2_CHANNEL = 3 - -if STM32H7_TIM2_CHANNEL = 4 - -config STM32H7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM2_CHANNEL = 4 - -config STM32H7_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM2_PWM - -config STM32H7_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32H7_TIM3 - select STM32H7_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM3_PWM - -config STM32H7_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM3_CHANNEL1 - -config STM32H7_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM3_CHANNEL1 - -config STM32H7_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM3_CHANNEL2 - -config STM32H7_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM3_CHANNEL2 - -config STM32H7_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM3_CHANNEL3 - -config STM32H7_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM3_CHANNEL3 - -config STM32H7_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM3_CHANNEL4 - -config STM32H7_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM3_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM3_CHANNEL = 1 - -config STM32H7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM3_CHANNEL = 1 - -if STM32H7_TIM3_CHANNEL = 2 - -config STM32H7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM3_CHANNEL = 2 - -if STM32H7_TIM3_CHANNEL = 3 - -config STM32H7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM3_CHANNEL = 3 - -if STM32H7_TIM3_CHANNEL = 4 - -config STM32H7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM3_CHANNEL = 4 - -config STM32H7_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM3_PWM - -config STM32H7_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32H7_TIM4 - select STM32H7_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM4_PWM - -config STM32H7_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM4_CHANNEL1 - -config STM32H7_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM4_CHANNEL1 - -config STM32H7_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM4_CHANNEL2 - -config STM32H7_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM4_CHANNEL2 - -config STM32H7_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM4_CHANNEL3 - -config STM32H7_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM4_CHANNEL3 - -config STM32H7_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM4_CHANNEL4 - -config STM32H7_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM4_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM4_CHANNEL = 1 - -config STM32H7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM4_CHANNEL = 1 - -if STM32H7_TIM4_CHANNEL = 2 - -config STM32H7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM4_CHANNEL = 2 - -if STM32H7_TIM4_CHANNEL = 3 - -config STM32H7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM4_CHANNEL = 3 - -if STM32H7_TIM4_CHANNEL = 4 - -config STM32H7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM4_CHANNEL = 4 - -config STM32H7_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM4_PWM - -config STM32H7_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32H7_TIM5 - select STM32H7_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM5_PWM - -config STM32H7_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM5_CHANNEL1 - -config STM32H7_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM5_CHANNEL1 - -config STM32H7_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM5_CHANNEL2 - -config STM32H7_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM5_CHANNEL2 - -config STM32H7_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM5_CHANNEL3 - -config STM32H7_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM5_CHANNEL3 - -config STM32H7_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM5_CHANNEL4 - -config STM32H7_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM5_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM5_CHANNEL = 1 - -config STM32H7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM5_CHANNEL = 1 - -if STM32H7_TIM5_CHANNEL = 2 - -config STM32H7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM5_CHANNEL = 2 - -if STM32H7_TIM5_CHANNEL = 3 - -config STM32H7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM5_CHANNEL = 3 - -if STM32H7_TIM5_CHANNEL = 4 - -config STM32H7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM5_CHANNEL = 4 - -config STM32H7_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM5_PWM - -config STM32H7_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32H7_TIM8 - select STM32H7_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM8_PWM - -config STM32H7_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H7_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32H7_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32H7_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM8_CHANNEL1 - -config STM32H7_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL1 - -config STM32H7_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM8_CHANNEL2 - -config STM32H7_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL2 - -config STM32H7_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM8_CHANNEL3 - -config STM32H7_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL3 - -config STM32H7_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM8_CHANNEL4 - -config STM32H7_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM8_CHANNEL4 - -config STM32H7_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H7_TIM8_CHANNEL5 - -config STM32H7_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H7_TIM8_CHANNEL5 - -config STM32H7_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H7_TIM8_CHANNEL6 - -config STM32H7_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H7_TIM8_CHANNEL6 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM8_CHANNEL = 1 - -config STM32H7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 1 - -if STM32H7_TIM8_CHANNEL = 2 - -config STM32H7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 2 - -if STM32H7_TIM8_CHANNEL = 3 - -config STM32H7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 3 - -if STM32H7_TIM8_CHANNEL = 4 - -config STM32H7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM8_CHANNEL = 4 - -config STM32H7_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM8_PWM - -config STM32H7_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32H7_TIM12 - select STM32H7_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM12_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM12_CHANNEL1 - -config STM32H7_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM12_CHANNEL1 - -config STM32H7_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM12_CHANNEL2 - -config STM32H7_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM12_CHANNEL2 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H7_TIM12_CHANNEL = 1 - -config STM32H7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM12_CHANNEL = 1 - -if STM32H7_TIM12_CHANNEL = 2 - -config STM32H7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM12_CHANNEL = 2 - -config STM32H7_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM12_PWM - -config STM32H7_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32H7_TIM13 - select STM32H7_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM13_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM13_CHANNEL1 - -config STM32H7_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM13_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM13_CHANNEL = 1 - -config STM32H7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM13_CHANNEL = 1 - -config STM32H7_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM13_PWM - -config STM32H7_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32H7_TIM14 - select STM32H7_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM14_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM14_CHANNEL1 - -config STM32H7_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM14_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM14_CHANNEL = 1 - -config STM32H7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM14_CHANNEL = 1 - -config STM32H7_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM14_PWM - -config STM32H7_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32H7_TIM15 - select STM32H7_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM15_PWM - -config STM32H7_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32H7_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM15_CHANNEL1 - -config STM32H7_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL1 - -config STM32H7_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM15_CHANNEL2 - -config STM32H7_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM15_CHANNEL2 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H7_TIM15_CHANNEL = 1 - -config STM32H7_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL = 1 - -if STM32H7_TIM15_CHANNEL = 2 - -config STM32H7_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL = 2 - -config STM32H7_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM15_PWM - -config STM32H7_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32H7_TIM16 - select STM32H7_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM16_PWM - -config STM32H7_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32H7_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM16_CHANNEL1 - -config STM32H7_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM16_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM16_CHANNEL = 1 - -config STM32H7_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM16_CHANNEL = 1 - -config STM32H7_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM16_PWM - -config STM32H7_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32H7_TIM17 - select STM32H7_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM17_PWM - -config STM32H7_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32H7_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM17_CHANNEL1 - -config STM32H7_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM17_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM17_CHANNEL = 1 - -config STM32H7_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM17_CHANNEL = 1 - -config STM32H7_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM17_PWM - -config STM32H7_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32H7_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32H7_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32H7_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32H7_TIM1 - select STM32H7_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32H7_TIM1_PULSECOUNT - -config STM32H7_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32H7_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H7_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32H7_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H7_TIM1_PULSECOUNT - -config STM32H7_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32H7_TIM8 - select STM32H7_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32H7_TIM8_PULSECOUNT - -config STM32H7_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32H7_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H7_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32H7_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H7_TIM8_PULSECOUNT -config STM32H7_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32H7_TIM1 && STM32H7_ADC - ---help--- - Reserve timer 1 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM1" - default STM32H7_TIM1_ADC1 - depends on STM32H7_TIM1_ADC - -config STM32H7_TIM1_ADC1 - bool "Use TIM1 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32H7_TIM1_ADC2 - bool "Use TIM1 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32H7_TIM1_ADC3 - bool "Use TIM1 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice # Select ADC for use with TIM1 - -config STM32H7_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32H7_TIM2 && STM32H7_ADC - ---help--- - Reserve timer 2 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM2" - default STM32H7_TIM2_ADC1 - depends on STM32H7_TIM2_ADC - -config STM32H7_TIM2_ADC1 - bool "Use TIM2 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32H7_TIM2_ADC2 - bool "Use TIM2 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32H7_TIM2_ADC3 - bool "Use TIM2 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice # Select ADC for use with TIM2 - -config STM32H7_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32H7_TIM3 && STM32H7_ADC - ---help--- - Reserve timer 3 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM3" - default STM32H7_TIM3_ADC1 - depends on STM32H7_TIM3_ADC - -config STM32H7_TIM3_ADC1 - bool "Use TIM3 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32H7_TIM3_ADC2 - bool "Use TIM3 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32H7_TIM3_ADC3 - bool "Use TIM3 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice # Select ADC for use with TIM3 - -config STM32H7_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32H7_TIM4 && STM32H7_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM4" - default STM32H7_TIM4_ADC1 - depends on STM32H7_TIM4_ADC - -config STM32H7_TIM4_ADC1 - bool "Use TIM4 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32H7_TIM4_ADC2 - bool "Use TIM4 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32H7_TIM4_ADC3 - bool "Use TIM4 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice # Select ADC for use with TIM4 - -config STM32H7_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32H7_TIM6 && STM32H7_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM6" - default STM32H7_TIM6_ADC1 - depends on STM32H7_TIM6_ADC - -config STM32H7_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32H7_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32H7_TIM6_ADC3 - bool "Use TIM6 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice # Select ADC for use with TIM6 - -config STM32H7_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32H7_TIM8 && STM32H7_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM8" - default STM32H7_TIM8_ADC1 - depends on STM32H7_TIM8_ADC - -config STM32H7_TIM8_ADC1 - bool "Use TIM8 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32H7_TIM8_ADC2 - bool "Use TIM8 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32H7_TIM8_ADC3 - bool "Use TIM8 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice # Select ADC for use with TIM8 - -config STM32H7_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32H7_TIM15 && STM32H7_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM15" - default STM32H7_TIM15_ADC1 - depends on STM32H7_TIM15_ADC - -config STM32H7_TIM15_ADC1 - bool "Use TIM15 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32H7_TIM15_ADC2 - bool "Use TIM15 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32H7_TIM15_ADC3 - bool "Use TIM15 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice # Select ADC for use with TIM15 - -config STM32H7_HAVE_ADC1_TIMER - bool - -config STM32H7_HAVE_ADC2_TIMER - bool - -config STM32H7_HAVE_ADC3_TIMER - bool - -config STM32H7_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32H7_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32H7_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32H7_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_TIMX_CAP - default n - bool "Helpers for Capture Drivers" - -config STM32H7_TIM1_CAP - bool "TIM1 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM1 - ---help--- - Reserve timer 1 for use by the capture driver. - -if STM32H7_TIM1_CAP - -config STM32H7_TIM1_CHANNEL - int "TIM1 Capture Input Channel" - default 1 - range 1 6 - ---help--- - Specifies the timer input channel {1..6} for TIM1. - -config STM32H7_TIM1_CLOCK - int "TIM1 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM1_CAP - -config STM32H7_TIM8_CAP - bool "TIM8 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM8 - ---help--- - Reserve timer 8 for use by the capture driver. - -if STM32H7_TIM8_CAP - -config STM32H7_TIM8_CHANNEL - int "TIM8 Capture Input Channel" - default 1 - range 1 6 - ---help--- - Specifies the timer input channel {1..6} for TIM8. - -config STM32H7_TIM8_CLOCK - int "TIM8 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM8_CAP - -# -# General-Purpose Timers (4 Channels) -# - -config STM32H7_TIM2_CAP - bool "TIM2 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM2 - ---help--- - Reserve timer 2 for use by the capture driver. - -if STM32H7_TIM2_CAP - -config STM32H7_TIM2_CHANNEL - int "TIM2 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM2. - -config STM32H7_TIM2_CLOCK - int "TIM2 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM2_CAP - -config STM32H7_TIM3_CAP - bool "TIM3 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM3 - ---help--- - Reserve timer 3 for use by the capture driver. - -if STM32H7_TIM3_CAP - -config STM32H7_TIM3_CHANNEL - int "TIM3 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM3. - -config STM32H7_TIM3_CLOCK - int "TIM3 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM3_CAP - -config STM32H7_TIM4_CAP - bool "TIM4 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM4 - ---help--- - Reserve timer 4 for use by the capture driver. - -if STM32H7_TIM4_CAP - -config STM32H7_TIM4_CHANNEL - int "TIM4 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM4. - -config STM32H7_TIM4_CLOCK - int "TIM4 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM4_CAP - -config STM32H7_TIM5_CAP - bool "TIM5 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM5 - ---help--- - Reserve timer 5 for use by the capture driver. - -if STM32H7_TIM5_CAP - -config STM32H7_TIM5_CHANNEL - int "TIM5 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM5. - -config STM32H7_TIM5_CLOCK - int "TIM5 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM5_CAP - -# -# General-Purpose Timers (2 Channels) -# - -config STM32H7_TIM12_CAP - bool "TIM12 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM12 - ---help--- - Reserve timer 12 for use by the capture driver. - -if STM32H7_TIM12_CAP - -config STM32H7_TIM12_CHANNEL - int "TIM12 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1..2} for TIM12. - -config STM32H7_TIM12_CLOCK - int "TIM12 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM12_CAP - -config STM32H7_TIM15_CAP - bool "TIM15 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM15 - ---help--- - Reserve timer 15 for use by the capture driver. - -if STM32H7_TIM15_CAP - -config STM32H7_TIM15_CHANNEL - int "TIM15 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1..2} for TIM15. - -config STM32H7_TIM15_CLOCK - int "TIM15 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM15_CAP - -# -# General-Purpose Timers (1 Channel) -# - -config STM32H7_TIM13_CAP - bool "TIM13 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM13 - ---help--- - Reserve timer 13 for use by the capture driver. - -if STM32H7_TIM13_CAP - -config STM32H7_TIM13_CHANNEL - int "TIM13 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM13. - -config STM32H7_TIM13_CLOCK - int "TIM13 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM13_CAP - -config STM32H7_TIM14_CAP - bool "TIM14 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM14 - ---help--- - Reserve timer 14 for use by the capture driver. - -if STM32H7_TIM14_CAP - -config STM32H7_TIM14_CHANNEL - int "TIM14 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM14. - -config STM32H7_TIM14_CLOCK - int "TIM14 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM14_CAP - -config STM32H7_TIM16_CAP - bool "TIM16 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM16 - ---help--- - Reserve timer 16 for use by the capture driver. - -if STM32H7_TIM16_CAP - -config STM32H7_TIM16_CHANNEL - int "TIM16 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM16. - -config STM32H7_TIM16_CLOCK - int "TIM16 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM16_CAP - -config STM32H7_TIM17_CAP - bool "TIM17 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM17 - ---help--- - Reserve timer 17 for use by the capture driver. - -if STM32H7_TIM17_CAP - -config STM32H7_TIM17_CHANNEL - int "TIM17 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM17. - -config STM32H7_TIM17_CLOCK - int "TIM17 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM17_CAP - -# -# Low-Power Timers -# - -config STM32H7_LPTIM1_CAP - bool "LPTIM1 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM1 - ---help--- - Reserve low-power timer 1 for use by the capture driver. - -if STM32H7_LPTIM1_CAP - -config STM32H7LPTIM1_CHANNEL - int "LPTIM1 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM1. - -config STM32H7LPTIM1_CLOCK - int "LPTIM1 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM1_CAP - -config STM32H7_LPTIM2_CAP - bool "LPTIM2 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM2 - ---help--- - Reserve low-power timer 2 for use by the capture driver. - -if STM32H7_LPTIM2_CAP - -config STM32H7LPTIM2_CHANNEL - int "LPTIM2 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM2. - -config STM32H7LPTIM2_CLOCK - int "LPTIM2 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM2_CAP - -config STM32H7_LPTIM3_CAP - bool "LPTIM3 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM3 - ---help--- - Reserve low-power timer 3 for use by the capture driver. - -if STM32H7_LPTIM3_CAP - -config STM32H7LPTIM3_CHANNEL - int "LPTIM3 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM3. - -config STM32H7LPTIM3_CLOCK - int "LPTIM3 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM3_CAP - -config STM32H7_LPTIM4_CAP - bool "LPTIM4 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM4 - ---help--- - Reserve low-power timer 4 for use by the capture driver. - -if STM32H7_LPTIM4_CAP - -config STM32H7LPTIM4_CHANNEL - int "LPTIM4 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM4. - -config STM32H7LPTIM4_CLOCK - int "LPTIM4 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM4_CAP - -config STM32H7_LPTIM5_CAP - bool "LPTIM5 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM5 - ---help--- - Reserve low-power timer 5 for use by the capture driver. - -if STM32H7_LPTIM5_CAP - -config STM32H7LPTIM5_CHANNEL - int "LPTIM5 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM5. - -config STM32H7LPTIM5_CLOCK - int "LPTIM5 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM5_CAP - -menu "STM32 TIMx Outputs Configuration" - -config STM32H7_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32H7_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32H7_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32H7_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32H7_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32H7_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32H7_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32H7_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32H7_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32H7_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32H7_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32H7_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32H7_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32H7_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32H7_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32H7_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32H7_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32H7_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32H7_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32H7_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32H7_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32H7_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32H7_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32H7_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32H7_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32H7_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32H7_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32H7_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32H7_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32H7_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32H7_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32H7_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32H7_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32H7_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32H7_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32H7_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32H7_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32H7_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32H7_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32H7_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32H7_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32H7_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32H7_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32H7_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32H7_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32H7_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32H7_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32H7_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32H7_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32H7_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32H7_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32H7_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32H7_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32H7_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32H7_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32H7_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32H7_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32H7_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32H7_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32H7_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32H7_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32H7_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32H7_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32H7_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32H7_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32H7_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32H7_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32H7_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32H7_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32H7_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32H7_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32H7_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32H7_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32H7_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32H7_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32H7_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32H7_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32H7_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32H7_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32H7_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32H7_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32H7_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32H7_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32H7_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32H7_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32H7_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32H7_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32H7_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "Ethernet MAC configuration" - depends on STM32H7_ETHMAC - -config STM32H7_PHYADDR - int "PHY address" - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32H7_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32H7_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32H7_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32H7_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32H7_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32H7_MII_EXTCLK - depends on STM32H7_MII - -config STM32H7_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MCO1 to clock the MII interface. - -config STM32H7_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MCO2 to clock the MII interface. - -config STM32H7_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # MII clock configuration - -config STM32H7_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32H7_ETH_NRXDESC - int "Number of RX descriptors" - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32H7_ETH_NTXDESC - int "Number of TX descriptors" - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32H7_ETHFD - bool "Full duplex" - default n - depends on !STM32H7_AUTONEG - ---help--- - If STM32H7_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32H7_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32H7_AUTONEG - ---help--- - If STM32H7_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32H7_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32H7_AUTONEG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32H7_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32H7_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32H7_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32H7_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32H7_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32H7_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32H7_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32H7_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32H7_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32H7_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32H7_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32H7_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32H7_RMII - bool - default !STM32H7_MII - -choice - prompt "RMII clock configuration" - default STM32H7_RMII_EXTCLK - depends on STM32H7_RMII - -config STM32H7_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32H7_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32H7_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32H7_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -config STM32H7_NO_PHY - bool "MAC has no PHY" - default n - -endmenu # Ethernet MAC configuration - -if STM32H7_LTDC - -menu "LTDC Configuration" - -config STM32H7_LTDC_USE_DSI - bool "Use DSI as display connection" - default n - depends on STM32H7_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32H7_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32H7_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32H7_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value, - which gets written unmodified to register LTDC_BCCR. - -config STM32H7_LTDC_DITHER - bool "Dither support" - default n - -config STM32H7_LTDC_DITHER_RED - depends on STM32H7_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32H7_LTDC_DITHER_GREEN - depends on STM32H7_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32H7_LTDC_DITHER_BLUE - depends on STM32H7_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32H7_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FMC. - -config STM32H7_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32H7_LTDC_FB_DOUBLE_BUFFER - bool "Enable double buffering" - default n - ---help--- - Enable double buffering to allow updates to the framebuffer while the display is being refreshed. - This configuration requires two framebuffers: one active and one inactive. - When the display refreshes, the active and inactive framebuffers are swapped, - enabling smooth and flicker-free updates. - -config STM32H7_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32H7_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32H7_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -choice - prompt "Layer 1 color format" - default STM32H7_LTDC_L1_RGB565 - -config STM32H7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32H7_FB_CMAP - -endchoice # Layer 1 color format - -config STM32H7_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32H7_LTDC_L2 - -config STM32H7_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32H7_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32H7_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -choice - prompt "Layer 2 (top layer) color format" - default STM32H7_LTDC_L2_RGB565 - -config STM32H7_LTDC_L2_L8 - depends on STM32H7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32H7_LTDC_L2_AL44 - depends on STM32H7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32H7_LTDC_L2_AL88 - depends on STM32H7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32H7_LTDC_L2_RGB565 - depends on STM32H7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32H7_LTDC_L2_ARGB4444 - depends on STM32H7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32H7_LTDC_L2_ARGB1555 - depends on STM32H7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32H7_LTDC_L2_RGB888 - depends on STM32H7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32H7_LTDC_L2_ARGB8888 - depends on STM32H7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - -endif # STM32H7_LTDC_L2 - -config STM32H7_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - EnablingEnablescolor map support is necessary for ltdc L8 format. - -config STM32H7_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32H7_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enables transparency color map support is necessary for ltdc L8 format. - -config STM32H7_LTDC_REGDEBUG - bool "Enable LTDC register value debug messages" - default n - ---help--- - This gives additional messages for LTDC related register values. - Additionally, you have to select "Low-level LCD Debug Features" - to enable the debug messages. - -endmenu # LTDC Configuration - -endif # STM32H7_LTDC - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32H7_TIM1 || STM32H7_TIM2 || STM32H7_TIM3 || STM32H7_TIM4 || STM32H7_TIM5 || STM32H7_TIM8 - -config STM32H7_TIM1_QE - bool "TIM1" - default n - depends on STM32H7_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32H7_TIM1_QE - -config STM32H7_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM1_QE - -config STM32H7_TIM2_QE - bool "TIM2" - default n - depends on STM32H7_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32H7_TIM2_QE - -config STM32H7_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM2_QE - -config STM32H7_TIM3_QE - bool "TIM3" - default n - depends on STM32H7_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32H7_TIM3_QE - -config STM32H7_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM3_QE - -config STM32H7_TIM4_QE - bool "TIM4" - default n - depends on STM32H7_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32H7_TIM4_QE - -config STM32H7_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM4_QE - -config STM32H7_TIM5_QE - bool "TIM5" - default n - depends on STM32H7_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32H7_TIM5_QE - -config STM32H7_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM5_QE - -config STM32H7_TIM8_QE - bool "TIM8" - default n - depends on STM32H7_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32H7_TIM8_QE - -config STM32H7_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM8_QE - -config STM32H7_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32H7_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32H7_QENCODER_SAMPLE_FDTS_4 - -config STM32H7_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32H7_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32H7_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32H7_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32H7_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32H7_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32H7_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice # Input channel sampling frequency - -choice - depends on STM32H7_QENCODER_FILTER - prompt "Input channel event count" - default STM32H7_QENCODER_SAMPLE_EVENT_6 - -config STM32H7_QENCODER_SAMPLE_EVENT_1 - depends on STM32H7_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32H7_QENCODER_SAMPLE_EVENT_2 - depends on STM32H7_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32H7_QENCODER_SAMPLE_EVENT_4 - depends on STM32H7_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32H7_QENCODER_SAMPLE_EVENT_5 - depends on STM32H7_QENCODER_SAMPLE_FDTS_16 || STM32H7_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32H7_QENCODER_SAMPLE_EVENT_6 - depends on !STM32H7_QENCODER_SAMPLE_FDTS && !STM32H7_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32H7_QENCODER_SAMPLE_EVENT_8 - depends on !STM32H7_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice # Input channel event count - -endmenu # QEncoder Driver - -menu "FDCAN Driver Configuration" - depends on STM32H7_FDCAN1 || STM32H7_FDCAN2 || STM32H7_FDCAN3 - -menu "FDCAN1 Configuration" - depends on STM32H7_FDCAN1 - -config FDCAN1_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 100000 - -config FDCAN1_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 100000 - -config FDCAN1_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN1 - -menu "FDCAN2 Configuration" - depends on STM32H7_FDCAN2 - -config FDCAN2_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 100000 - -config FDCAN2_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 100000 - -config FDCAN2_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN2 - -menu "FDCAN3 Configuration" - depends on STM32H7_FDCAN3 - -config FDCAN3_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 1000000 - -config FDCAN3_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 1000000 - -config FDCAN3_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN3 - -config STM32H7_FDCAN_REGDEBUG - bool "Enable register dump debugging" - depends on DEBUG_NET_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO and CONFIG_DEBUG_NET_INFO. - -config STM32H7_FDCAN_LOOPBACK - bool "Enable FDCAN loopback mode" - default n - ---help--- - Enable the FDCAN local loopback mode for testing purposes. - Requires a further choice of internal or external loopback mode. - - TODO: Enable separately for FDCAN1 and FDCAN2 - -choice - prompt "FDCAN Loopback Mode" - depends on STM32H7_FDCAN_LOOPBACK - default STM32H7_FDCAN_LOOPBACK_INTERNAL - -config STM32H7_FDCAN_LOOPBACK_INTERNAL - bool "Internal loopback mode" - ---help--- - Enable internal loopback mode, where both Tx and Rx are - disconnected from the CAN bus. This can be used for a "Hot Selftest", - meaning the FDCAN can be used without affecting a running CAN bus. - - All transmitted frames are treated as received frames and processed - accordingly. - -config STM32H7_FDCAN_LOOPBACK_EXTERNAL - bool "External loopback mode" - ---help--- - Enable external loopback mode, where the Rx pin is disconnected from - the CAN bus but the Tx pin remains connected. - - All transmitted frames are treated as received frames and processed - accordingly. - -endchoice # FDCAN Loopback Mode - -choice - prompt "FDCAN WorkQueue Selection" - default STM32H7_FDCAN_LPWORK - -config STM32H7_FDCAN_LPWORK - bool "Use LP work queue" - ---help--- - Use the low-priority (LP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -config STM32H7_FDCAN_HPWORK - bool "Use HP work queue" - ---help--- - Use the high-priority (HP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -endchoice # FDCAN WorkQueue Selection - -endmenu # FDCAN Driver - menu "Progmem MTD configuration" if STM32_HAVE_OTA_PARTITION @@ -6665,7 +812,7 @@ config STM32_PROGMEM_OTA_PARTITION select MTD_BYTE_WRITE select MTD_PARTITION select MTD_PROGMEM - select STM32H7_PROGMEM + select STM32_PROGMEM ---help--- Initialize an MTD driver for the Flash, which will add an entry at /dev for application access from userspace. diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 005c695adc8..e8fb7d38e3a 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -27,7 +27,7 @@ include armv7-m/Make.defs -ifeq ($(CONFIG_STM32H7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -35,7 +35,7 @@ ifeq ($(CONFIG_ARCH_STM32H7_DUALCORE),y) CHIP_CSRCS += stm32_dualcore.c endif -ifeq ($(CONFIG_STM32H7_HSEM),y) +ifeq ($(CONFIG_STM32_HSEM),y) CHIP_CSRCS += stm32_hsem.c endif @@ -55,7 +55,7 @@ else CHIP_CSRCS += stm32_timerisr.c endif -ifeq ($(CONFIG_STM32H7_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c endif @@ -71,51 +71,51 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y) CHIP_CSRCS += stm32_dtcm.c endif -ifeq ($(CONFIG_STM32H7_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32H7_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN),y) CHIP_CSRCS += stm32_fdcan_sock.c endif -ifeq ($(CONFIG_STM32H7_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32H7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CHIP_CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_STM32H7_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32H7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif -ifeq ($(filter y,$(CONFIG_STM32H7_IWDG) $(CONFIG_STM32H7_RTC_LSICLOCK)),y) +ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) CHIP_CSRCS += stm32_lsi.c endif -ifeq ($(CONFIG_STM32H7_RTC_LSECLOCK),y) +ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32H7_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32H7_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif -ifeq ($(CONFIG_STM32H7_QSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32H7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) CHIP_CSRCS += stm32_rtc.c ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c @@ -128,7 +128,7 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif @@ -136,7 +136,7 @@ ifeq ($(CONFIG_SPI_SLAVE),y) CHIP_CSRCS += stm32_spi_slave.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif @@ -144,7 +144,7 @@ ifeq ($(CONFIG_TIMER),y) CHIP_CSRCS += stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32H7_TIMX_CAP),y) +ifeq ($(CONFIG_STM32_TIMX_CAP),y) CHIP_CSRCS += stm32_capture.c endif @@ -152,7 +152,7 @@ ifeq ($(CONFIG_CAPTURE),y) CHIP_CSRCS += stm32_capture_lowerhalf.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CHIP_CSRCS += stm32_ltdc.c endif @@ -171,23 +171,23 @@ endif endif endif -ifeq ($(CONFIG_STM32H7_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif -ifeq ($(CONFIG_STM32H7_LPTIM),y) +ifeq ($(CONFIG_STM32_LPTIM),y) CHIP_CSRCS += stm32_lptim.c endif -ifeq ($(CONFIG_STM32H7_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32H7_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif -ifeq ($(CONFIG_STM32H7_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif @@ -206,22 +206,22 @@ CHIP_CSRCS += stm32_pminitialize.c endif endif -ifeq ($(CONFIG_STM32H7_IWDG),y) +ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32_iwdg.c endif -ifeq ($(CONFIG_STM32H7_WWDG),y) +ifeq ($(CONFIG_STM32_WWDG),y) CHIP_CSRCS += stm32_wwdg.c endif -#ifeq ($(CONFIG_STM32H7_HASH),y) -#CHIP_CSRCS += stm32_hash.c -#endif - -ifeq ($(CONFIG_STM32H7_CRYP),y) +ifeq ($(CONFIG_STM32_CRYP),y) +ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y) CHIP_CSRCS += stm32_aes.c endif +endif ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) +ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y) CHIP_CSRCS += stm32_crypto.c endif +endif diff --git a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h index 74973a4004a..5ac1b4a0481 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h @@ -203,15 +203,15 @@ /* Import DMAMUX map */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_dmamux.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h index f22c76cd156..a65c2430761 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h @@ -33,11 +33,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -680,5 +680,5 @@ struct eth_desc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_exti.h b/arch/arm/src/stm32h7/hardware/stm32_exti.h index e197f4b6c42..bd5bf31c73e 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_exti.h +++ b/arch/arm/src/stm32h7/hardware/stm32_exti.h @@ -35,11 +35,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -243,5 +243,5 @@ #define EXTI_EVENT_ETHWKUP 86 /* Ethernet wakeup */ #define EXTI_EVENT_HSECSS 87 /* HSECSS interrupt */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_flash.h b/arch/arm/src/stm32h7/hardware/stm32_flash.h index 399694f63f7..b24ccc58f70 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_flash.h +++ b/arch/arm/src/stm32h7/hardware/stm32_flash.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7b3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_flash.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_gpio.h b/arch/arm/src/stm32h7/hardware/stm32_gpio.h index 83c989afaa2..68f682e41c9 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32_gpio.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_gpio.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_i2c.h b/arch/arm/src/stm32h7/hardware/stm32_i2c.h index 7b7efcd8549..e9b47c45689 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32_i2c.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_i2c.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h index 18c199495ab..85b3d880ebd 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_memorymap.h" #else # error "Unsupported STM32 H7 memory map" diff --git a/arch/arm/src/stm32h7/hardware/stm32_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h index db27991f33d..409bca78983 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_pinmap.h" #else # error "Unsupported STM32 H7 Pin map" diff --git a/arch/arm/src/stm32h7/hardware/stm32_pwr.h b/arch/arm/src/stm32h7/hardware/stm32_pwr.h index 88f257e9a58..a3fe24507b8 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32_pwr.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_pwr.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_rcc.h b/arch/arm/src/stm32h7/hardware/stm32_rcc.h index 984f782d612..67ef3c5d180 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_rcc.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_rcc.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h index 28bcba80b9a..b5d9bd01944 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h7x3xx_sdmmc.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_spi.h b/arch/arm/src/stm32h7/hardware/stm32_spi.h index 44bae2e58fa..f342cc3ea35 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_spi.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_spi.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h index a48b13ff5d2..3403a0f6fd0 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_syscfg.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_uart.h b/arch/arm/src/stm32h7/hardware/stm32_uart.h index 9bc1408a9b4..0e6820748e3 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32_uart.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_uart.h" #else # error "Unsupported STM32 H7 memory map" diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h index c38ff4666e2..310899214c3 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h @@ -30,11 +30,11 @@ #include #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -120,7 +120,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -390,5 +390,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_GPIO_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h index 215c7be0ed8..1e3737d13e3 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h @@ -65,7 +65,7 @@ #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x30003fff: System SRAM1 */ -# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX # define STM32_SRAM2_BASE 0x30004000 /* 0x30004000-0x30007fff: System SRAM2 */ # else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */ # define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h index 46b114c3e67..3974629f516 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h @@ -31,11 +31,11 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -1538,5 +1538,5 @@ #define GPIO_UART8_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN1) #define GPIO_UART8_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTJ|GPIO_PIN8) -#endif /* CONFIG_STM32H7_STM32H7X0XX CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X0XX CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PINMAP_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h index 977f1c41350..6643ce2452f 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h @@ -131,10 +131,10 @@ #define STM32_PWR_CR3_BYPASS (1 << 0) /* Bit 0: Power management unit bypass */ #define STM32_PWR_CR3_LDOEN (1 << 1) /* Bit 1: Low drop-out regulator enable */ -#ifndef CONFIG_STM32H7_HAVE_SMPS +#ifndef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_SCUEN (1 << 2) /* Bit 2: Supply configuration update enable */ #endif -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_SDEN (1 << 2) /* Bit 2: SMPS step-down converter enable */ # define STM32_PWR_CR3_SMPSEXTHP (1 << 3) /* Bit 3: SMPS step-down converter external power delivery selection */ # define STM32_PWR_CR3_SMPSLEVEL_SHIFT (4) /* BitS 4-5: SMPS step-down converter voltage output level selection */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h index 8124fbd9c7b..308dc30f621 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h @@ -827,10 +827,10 @@ /* RCC Global Control register */ #define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */ #endif -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */ # define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */ #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h index fa7c71d92bf..2cfb71ca647 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h @@ -29,11 +29,11 @@ #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -466,5 +466,5 @@ /* TODO: SPI/I2S configuration register */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SPI_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h index e259beff596..e5c6fe8e3ce 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h @@ -56,7 +56,7 @@ #define STM32_SYSCFG_UR_OFFSET(n) (0x0300 + ((n) << 2)) #define STM32_SYSCFG_UR0_OFFSET 0x0300 /* User register 0 */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define STM32_SYSCFG_UR1_OFFSET 0x0304 /* User register 2 */ #endif #define STM32_SYSCFG_UR2_OFFSET 0x0308 /* User register 2 */ @@ -92,7 +92,7 @@ #define STM32_SYSCFG_PWRCR (STM32_SYSCFG_BASE + STM32_SYSCFG_PWRCR_OFFSET) #define STM32_SYSCFG_UR0 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR0_OFFSET) -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define STM32_SYSCFG_UR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR1_OFFSET) #endif #define STM32_SYSCFG_UR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR2_OFFSET) @@ -220,7 +220,7 @@ /* User register 1 */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define SYSCFG_UR1_BCM4 (1 << 0) /* Bit 0: Boot Cortex-M4 */ # define SYSCFG_UR1_BCM7 (1 << 16) /* Bit 16: Boot Cortex-M7 */ #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h index 7bab6c142c4..84a46958e43 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h @@ -31,11 +31,11 @@ #include "chip.h" #include "hardware/stm32_memorymap.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -415,5 +415,5 @@ # define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ # define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ # define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H */ diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index 1db742bb688..da606d9df3e 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -77,8 +77,8 @@ /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /**************************************************************************** * Pre-processor Definitions @@ -92,9 +92,9 @@ /* ADC Channels/DMA *********************************************************/ #ifdef ADC_HAVE_DMA -# if !defined(CONFIG_STM32H7_DMA1) && !defined(CONFIG_STM32H7_DMA2) +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # /* REVISIT: check accordingly to which one is configured in board.h */ -# error "STM32H7 ADC DMA support requires CONFIG_STM32H7_DMA1 or CONFIG_STM32H7_DMA2" +# error "STM32H7 ADC DMA support requires CONFIG_STM32_DMA1 or CONFIG_STM32_DMA2" # endif #endif @@ -191,7 +191,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t chanlist[CONFIG_STM32H7_ADC_MAX_SAMPLES]; + uint8_t chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; }; /**************************************************************************** @@ -254,10 +254,10 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, /* ADC Interrupt Handler */ static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) static int adc3_interrupt(int irq, void *context, void *arg); #endif @@ -289,11 +289,11 @@ static const struct adc_ops_s g_adcops = /* ADC1 state */ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = @@ -305,19 +305,19 @@ static struct stm32_dev_s g_adcpriv1 = .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .trcc_enr = ADC1_TIMER_RCC_ENR, .trcc_en = ADC1_TIMER_RCC_EN, .extsel = ADC1_EXTSEL_VALUE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC1_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, #endif #ifdef ADC1_HAVE_DFSDM .hasdfsdm = true, @@ -339,11 +339,11 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = @@ -355,19 +355,19 @@ static struct stm32_dev_s g_adcpriv2 = .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .trcc_enr = ADC2_TIMER_RCC_ENR, .trcc_en = ADC2_TIMER_RCC_EN, .extsel = ADC2_EXTSEL_VALUE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC2_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, #endif #ifdef ADC2_HAVE_DFSDM .hasdfsdm = true, @@ -389,11 +389,11 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = @@ -405,19 +405,19 @@ static struct stm32_dev_s g_adcpriv3 = .mbase = STM32_ADC3_BASE, .initialized = false, #ifdef ADC3_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC3_TIMTRIG, + .trigger = CONFIG_STM32_ADC3_TIMTRIG, .tbase = ADC3_TIMER_BASE, .trcc_enr = ADC3_TIMER_RCC_ENR, .trcc_en = ADC3_TIMER_RCC_EN, .extsel = ADC3_EXTSEL_VALUE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC3_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, #endif #ifdef ADC3_HAVE_DFSDM .hasdfsdm = true, @@ -1381,7 +1381,7 @@ static int adc_setup(struct adc_dev_s *dev) * ADC1 and ADC2 are enabled.) */ -#if defined(CONFIG_STM32H7_ADC1) && defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2) if ((dev == &g_adcdev1 && !((struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) || (dev == &g_adcdev2 && @@ -1880,7 +1880,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); @@ -2163,13 +2163,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2178,7 +2178,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) } #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2203,7 +2203,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 static int adc3_interrupt(int irq, void *context, void *arg) { uint32_t regval; @@ -2312,19 +2312,19 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, switch (intf) { -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: ainfo("ADC1 selected\n"); dev = &g_adcdev1; break; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: ainfo("ADC2 selected\n"); dev = &g_adcdev2; break; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: ainfo("ADC3 selected\n"); dev = &g_adcdev3; @@ -2340,10 +2340,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, priv = (struct stm32_dev_s *)dev->ad_priv; priv->cb = NULL; - DEBUGASSERT(cchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES); - if (cchannels > CONFIG_STM32H7_ADC_MAX_SAMPLES) + DEBUGASSERT(cchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cchannels = CONFIG_STM32H7_ADC_MAX_SAMPLES; + cchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = cchannels; @@ -2360,5 +2360,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32h7/stm32_adc.h b/arch/arm/src/stm32h7/stm32_adc.h index ce6a460ca92..174d6739e00 100644 --- a/arch/arm/src/stm32h7/stm32_adc.h +++ b/arch/arm/src/stm32h7/stm32_adc.h @@ -46,80 +46,80 @@ * well. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_ADC -# undef CONFIG_STM32H7_TIM1_ADC1 -# undef CONFIG_STM32H7_TIM1_ADC2 -# undef CONFIG_STM32H7_TIM1_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_ADC -# undef CONFIG_STM32H7_TIM2_ADC1 -# undef CONFIG_STM32H7_TIM2_ADC2 -# undef CONFIG_STM32H7_TIM2_ADC3 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_ADC -# undef CONFIG_STM32H7_TIM3_ADC1 -# undef CONFIG_STM32H7_TIM3_ADC2 -# undef CONFIG_STM32H7_TIM3_ADC3 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_ADC -# undef CONFIG_STM32H7_TIM4_ADC1 -# undef CONFIG_STM32H7_TIM4_ADC2 -# undef CONFIG_STM32H7_TIM4_ADC3 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM6 -# undef CONFIG_STM32H7_TIM6_ADC -# undef CONFIG_STM32H7_TIM6_ADC1 -# undef CONFIG_STM32H7_TIM6_ADC2 -# undef CONFIG_STM32H7_TIM6_ADC3 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_ADC -# undef CONFIG_STM32H7_TIM8_ADC1 -# undef CONFIG_STM32H7_TIM8_ADC2 -# undef CONFIG_STM32H7_TIM8_ADC3 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM15 -# undef CONFIG_STM32H7_TIM15_ADC -# undef CONFIG_STM32H7_TIM15_ADC1 -# undef CONFIG_STM32H7_TIM15_ADC2 -# undef CONFIG_STM32H7_TIM15_ADC3 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* ADC output to DFSDM support. Note that DFSDM and DMA are * mutually exclusive. */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32H7_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32H7_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32H7_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC1_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) # define ADC1_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC1_DMA +# undef CONFIG_STM32_ADC1_DMA #else # undef ADC1_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC2_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) # define ADC2_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC2_DMA +# undef CONFIG_STM32_ADC2_DMA #else # undef ADC2_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC3_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC3_DMA +# undef CONFIG_STM32_ADC3_DMA #else # undef ADC3_HAVE_DFSDM #endif @@ -127,24 +127,24 @@ /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32H7_ADC1_DMA) || defined(CONFIG_STM32H7_ADC2_DMA) || \ - defined(CONFIG_STM32H7_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32H7_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32H7_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32H7_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -154,43 +154,43 @@ * information about the timer. */ -#if defined(CONFIG_STM32H7_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC1) +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -201,52 +201,52 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC1_TIMTRIG -# error "CONFIG_STM32H7_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC2) +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -257,52 +257,52 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC2_TIMTRIG -# error "CONFIG_STM32H7_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC3) +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC3) +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC3) +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC3) +#elif defined(CONFIG_STM32_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM6_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC3) +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC3) +#elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM15_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -313,11 +313,11 @@ #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC3_TIMTRIG -# error "CONFIG_STM32H7_ADC3_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC3_TIMTRIG +# error "CONFIG_STM32_ADC3_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif @@ -455,315 +455,315 @@ #define ADC3_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4 #define ADC3_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO -#if defined(CONFIG_STM32H7_TIM1_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #endif @@ -809,5 +809,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ADC_H */ diff --git a/arch/arm/src/stm32h7/stm32_aes.h b/arch/arm/src/stm32h7/stm32_aes.h index ad9595d946a..207bcad7262 100644 --- a/arch/arm/src/stm32h7/stm32_aes.h +++ b/arch/arm/src/stm32h7/stm32_aes.h @@ -37,7 +37,7 @@ * variants include CRYP */ -#ifdef CONFIG_STM32H7_HAVE_CRYP +#ifdef CONFIG_STM32_HAVE_CRYP # include "hardware/stm32h7xxxx_cryp.h" #else # error "Unknown chip for AES" diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index 3b64acba794..ab77f78604d 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -57,7 +57,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - !defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + !defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support disabled */ @@ -84,7 +84,7 @@ * - Tightly Coupled Memory (TCM RAM), we can use Data TCM (DTCM) for system * heap. Note that DTCM has a number of limitations, for example DMA * transfers to/from DTCM are limited. - * Define CONFIG_STM32H7_DTCMEXCLUDE to exclude the DTCM from heap. + * Define CONFIG_STM32_DTCMEXCLUDE to exclude the DTCM from heap. * +1 to CONFIG_MM_REGIONS if you want to use DTCM. * * - External SDRAM can be connected to the FMC peripheral. Initialization @@ -117,7 +117,7 @@ # define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) #elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support enabled */ @@ -139,7 +139,7 @@ #endif #undef HAVE_SRAM4 -#if !defined(CONFIG_STM32H7_SRAM4EXCLUDE) +#if !defined(CONFIG_STM32_SRAM4EXCLUDE) # define HAVE_SRAM4 1 # define SRAM4_START ((uint32_t)(STM32_SRAM4_BASE)) @@ -158,7 +158,7 @@ /* DTCM to be excluded from the main heap. */ -#ifdef CONFIG_STM32H7_DTCMEXCLUDE +#ifdef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM #endif @@ -410,7 +410,7 @@ void arm_addregion(void) } #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC stm32_fmc_init(); #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c index 8f27740c1aa..37dc0b741b2 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.c +++ b/arch/arm/src/stm32h7/stm32_bbsram.c @@ -50,14 +50,14 @@ #include "mpu.h" #include "stm32_pwr.h" -#ifdef CONFIG_STM32H7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32H7_BKPSRAM) -#error Driver Requires CONFIG_STM32H7_BKPSRAM to be enabled +#if !defined(CONFIG_STM32_BKPSRAM) +#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled #endif #define MAX_OPENCNT (255) /* Limit of uint8_t */ @@ -168,7 +168,7 @@ static const struct file_operations g_stm32_bbsram_fops = #endif }; -static struct stm32_bbsram_s g_bbsram[CONFIG_STM32H7_BBSRAM_FILES]; +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; /**************************************************************************** * Private Functions @@ -690,7 +690,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) avail = STM32_BBSRAM_SIZE; - for (i = 0; (i < CONFIG_STM32H7_BBSRAM_FILES) && ent[i] && (avail > 0); + for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) { /* Validate the actual allocations against what is in the BBSRAM */ @@ -855,7 +855,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { struct bbsramfh_s *bbf; @@ -873,7 +873,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { once = true; - DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32H7_BBSRAM_FILES); + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); bbf = g_bbsram[fileno].bbf; diff --git a/arch/arm/src/stm32h7/stm32_bbsram.h b/arch/arm/src/stm32h7/stm32_bbsram.h index 08421e22571..cecff041fa7 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.h +++ b/arch/arm/src/stm32h7/stm32_bbsram.h @@ -48,8 +48,8 @@ #define STM32_BBSRAM_SIZE 4096 -#if !defined(CONFIG_STM32H7_BBSRAM_FILES) -# define CONFIG_STM32H7_BBSRAM_FILES 4 +#if !defined(CONFIG_STM32_BBSRAM_FILES) +# define CONFIG_STM32_BBSRAM_FILES 4 #endif /* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique @@ -107,8 +107,8 @@ extern "C" * the last entry should be 0 * A size of -1 will use all the remaining spaces * - * If the length of sizes is greater then CONFIG_STM32H7_BBSRAM_FILES - * CONFIG_STM32H7_BBSRAM_FILES will be returned. + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. * * Returned Value: * Number of files created on success; Negated errno on failure. @@ -137,7 +137,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * *****************************************************************************/ -#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); #endif diff --git a/arch/arm/src/stm32h7/stm32_capture.c b/arch/arm/src/stm32h7/stm32_capture.c index ec1c3e0dfd7..32ef41e9d9c 100644 --- a/arch/arm/src/stm32h7/stm32_capture.c +++ b/arch/arm/src/stm32h7/stm32_capture.c @@ -49,7 +49,7 @@ /* Sanity checks ************************************************************/ -#if !defined(CONFIG_STM32H7_STM32H7X3XX) +#if !defined(CONFIG_STM32_STM32H7X3XX) # warning "This driver is for STM32H7X3XX devices" #endif @@ -59,7 +59,7 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H7_TIMX_CAP) +#if defined(CONFIG_STM32_TIMX_CAP) /* Check if any channel is enabled. * This is done to simplify the logic below. @@ -102,25 +102,25 @@ /* Check if we have any advanced timers */ -#if defined(CONFIG_STM32H7_TIM1_CAP) || defined(CONFIG_STM32H7_TIM8_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM8_CAP) # define USE_ADVANCED_TIM 1 #endif /* Check if we have any general purpose timers */ -#if defined(CONFIG_STM32H7_TIM2_CAP) || defined(CONFIG_STM32H7_TIM3_CAP) || \ - defined(CONFIG_STM32H7_TIM4_CAP) || defined(CONFIG_STM32H7_TIM5_CAP) || \ - defined(CONFIG_STM32H7_TIM12_CAP) || defined(CONFIG_STM32H7_TIM13_CAP) || \ - defined(CONFIG_STM32H7_TIM14_CAP) || defined(CONFIG_STM32H7_TIM15_CAP) || \ - defined(CONFIG_STM32H7_TIM16_CAP) || defined(CONFIG_STM32H7_TIM17_CAP) +#if defined(CONFIG_STM32_TIM2_CAP) || defined(CONFIG_STM32_TIM3_CAP) || \ + defined(CONFIG_STM32_TIM4_CAP) || defined(CONFIG_STM32_TIM5_CAP) || \ + defined(CONFIG_STM32_TIM12_CAP) || defined(CONFIG_STM32_TIM13_CAP) || \ + defined(CONFIG_STM32_TIM14_CAP) || defined(CONFIG_STM32_TIM15_CAP) || \ + defined(CONFIG_STM32_TIM16_CAP) || defined(CONFIG_STM32_TIM17_CAP) # define USE_GENERAL_TIM 1 #endif /* Check if we have any low-power timers */ -#if defined(CONFIG_STM32H7_LPTIM1_CAP) || defined(CONFIG_STM32H7_LPTIM2_CAP) || \ - defined(CONFIG_STM32H7_LPTIM3_CAP) || defined(CONFIG_STM32H7_LPTIM4_CAP) || \ - defined(CONFIG_STM32H7_LPTIM5_CAP) +#if defined(CONFIG_STM32_LPTIM1_CAP) || defined(CONFIG_STM32_LPTIM2_CAP) || \ + defined(CONFIG_STM32_LPTIM3_CAP) || defined(CONFIG_STM32_LPTIM4_CAP) || \ + defined(CONFIG_STM32_LPTIM5_CAP) # define USE_LOWPOWER_TIM 1 #endif @@ -237,7 +237,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, switch (priv->base) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: switch (channel) { @@ -265,7 +265,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: switch (channel) { @@ -293,7 +293,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: switch (channel) { @@ -321,7 +321,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: switch (channel) { @@ -349,7 +349,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: switch (channel) { @@ -379,7 +379,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: switch (channel) { @@ -407,7 +407,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: switch (channel) { @@ -435,7 +435,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: switch (channel) { @@ -463,7 +463,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: switch (channel) { @@ -491,7 +491,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: switch (channel) { @@ -519,7 +519,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: switch (channel) { @@ -547,7 +547,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: switch (channel) { @@ -589,31 +589,31 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, { /* APB2 Timers */ -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM8EN; break; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP case STM32_TIM15_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM15EN; break; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP case STM32_TIM16_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM16EN; break; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP case STM32_TIM17_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM17EN; @@ -622,50 +622,50 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* APB1L Timers */ -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM4EN; break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM5EN; break; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM12EN; break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM13EN; break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM14EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM1_CAP +#ifdef CONFIG_STM32_LPTIM1_CAP case STM32_LPTIM1_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_LPTIM1EN; @@ -674,25 +674,25 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* APB4 Timers */ -#ifdef CONFIG_STM32H7_LPTIM2_CAP +#ifdef CONFIG_STM32_LPTIM2_CAP case STM32_LPTIM2_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM2EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM3_CAP +#ifdef CONFIG_STM32_LPTIM3_CAP case STM32_LPTIM3_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM3EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM4_CAP +#ifdef CONFIG_STM32_LPTIM4_CAP case STM32_LPTIM4_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM4EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM5_CAP +#ifdef CONFIG_STM32_LPTIM5_CAP case STM32_LPTIM5_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM5EN; @@ -744,62 +744,62 @@ static int stm32_cap_setclock(struct stm32_cap_dev_s *dev, switch (priv->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: freqin = STM32_APB2_TIM9_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: freqin = STM32_APB2_TIM10_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: freqin = STM32_APB2_TIM11_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; @@ -1350,7 +1350,7 @@ struct stm32_cap_ops_s stm32_cap_ops = .getflags = &stm32_cap_getflags }; -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP const struct stm32_cap_priv_s stm32_tim1_priv = { .ops = &stm32_cap_ops, @@ -1362,7 +1362,7 @@ const struct stm32_cap_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP const struct stm32_cap_priv_s stm32_tim2_priv = { .ops = &stm32_cap_ops, @@ -1374,7 +1374,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP const struct stm32_cap_priv_s stm32_tim3_priv = { .ops = &stm32_cap_ops, @@ -1386,7 +1386,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP const struct stm32_cap_priv_s stm32_tim4_priv = { .ops = &stm32_cap_ops, @@ -1398,7 +1398,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP const struct stm32_cap_priv_s stm32_tim5_priv = { .ops = &stm32_cap_ops, @@ -1412,7 +1412,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv = /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP const struct stm32_cap_priv_s stm32_tim8_priv = { .ops = &stm32_cap_ops, @@ -1424,7 +1424,7 @@ const struct stm32_cap_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP const struct stm32_cap_priv_s stm32_tim9_priv = { .ops = &stm32_cap_ops, @@ -1436,7 +1436,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP const struct stm32_cap_priv_s stm32_tim10_priv = { .ops = &stm32_cap_ops, @@ -1448,7 +1448,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP const struct stm32_cap_priv_s stm32_tim11_priv = { .ops = &stm32_cap_ops, @@ -1460,7 +1460,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP const struct stm32_cap_priv_s stm32_tim12_priv = { .ops = &stm32_cap_ops, @@ -1472,7 +1472,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP const struct stm32_cap_priv_s stm32_tim13_priv = { .ops = &stm32_cap_ops, @@ -1484,7 +1484,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP const struct stm32_cap_priv_s stm32_tim14_priv = { .ops = &stm32_cap_ops, @@ -1496,7 +1496,7 @@ const struct stm32_cap_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP static const struct stm32_cap_priv_s stm32_tim15_priv = { .ops = &stm32_cap_ops, @@ -1508,7 +1508,7 @@ static const struct stm32_cap_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP static const struct stm32_cap_priv_s stm32_tim16_priv = { .ops = &stm32_cap_ops, @@ -1520,7 +1520,7 @@ static const struct stm32_cap_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP static const struct stm32_cap_priv_s stm32_tim17_priv = { .ops = &stm32_cap_ops, @@ -1536,54 +1536,54 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) { switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: return &stm32_tim1_priv; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: return &stm32_tim2_priv; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: return &stm32_tim3_priv; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: return &stm32_tim4_priv; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: return &stm32_tim5_priv; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: return &stm32_tim8_priv; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case 9: return &stm32_tim9_priv; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case 10: return &stm32_tim10_priv; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case 11: return &stm32_tim11_priv; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: return &stm32_tim12_priv; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: return &stm32_tim13_priv; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: return &stm32_tim14_priv; #endif @@ -1640,4 +1640,4 @@ int stm32_cap_deinit(struct stm32_cap_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_TIM1 || ... || TIM14) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c index c1a1e71517d..79ee35e3022 100644 --- a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c @@ -125,123 +125,123 @@ static const struct cap_ops_s g_cap_ops = .getfreq = stm32_getfreq, }; -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP static struct stm32_lowerhalf_s g_cap1_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM1_RES, - .channel = CONFIG_STM32H7_TIM1_CHANNEL, - .clock = CONFIG_STM32H7_TIM1_CLOCK, + .channel = CONFIG_STM32_TIM1_CHANNEL, + .clock = CONFIG_STM32_TIM1_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP static struct stm32_lowerhalf_s g_cap2_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM2_RES, - .channel = CONFIG_STM32H7_TIM2_CHANNEL, - .clock = CONFIG_STM32H7_TIM2_CLOCK, + .channel = CONFIG_STM32_TIM2_CHANNEL, + .clock = CONFIG_STM32_TIM2_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP static struct stm32_lowerhalf_s g_cap3_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM3_RES, - .channel = CONFIG_STM32H7_TIM3_CHANNEL, - .clock = CONFIG_STM32H7_TIM3_CLOCK, + .channel = CONFIG_STM32_TIM3_CHANNEL, + .clock = CONFIG_STM32_TIM3_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP static struct stm32_lowerhalf_s g_cap4_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM4_RES, - .channel = CONFIG_STM32H7_TIM4_CHANNEL, - .clock = CONFIG_STM32H7_TIM4_CLOCK, + .channel = CONFIG_STM32_TIM4_CHANNEL, + .clock = CONFIG_STM32_TIM4_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP static struct stm32_lowerhalf_s g_cap5_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM5_RES, - .channel = CONFIG_STM32H7_TIM5_CHANNEL, - .clock = CONFIG_STM32H7_TIM5_CLOCK, + .channel = CONFIG_STM32_TIM5_CHANNEL, + .clock = CONFIG_STM32_TIM5_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP static struct stm32_lowerhalf_s g_cap8_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM8_RES, - .channel = CONFIG_STM32H7_TIM8_CHANNEL, - .clock = CONFIG_STM32H7_TIM8_CLOCK, + .channel = CONFIG_STM32_TIM8_CHANNEL, + .clock = CONFIG_STM32_TIM8_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP static struct stm32_lowerhalf_s g_cap12_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM12_RES, - .channel = CONFIG_STM32H7_TIM12_CHANNEL, - .clock = CONFIG_STM32H7_TIM12_CLOCK, + .channel = CONFIG_STM32_TIM12_CHANNEL, + .clock = CONFIG_STM32_TIM12_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP static struct stm32_lowerhalf_s g_cap13_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM13_RES, - .channel = CONFIG_STM32H7_TIM13_CHANNEL, - .clock = CONFIG_STM32H7_TIM13_CLOCK, + .channel = CONFIG_STM32_TIM13_CHANNEL, + .clock = CONFIG_STM32_TIM13_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP static struct stm32_lowerhalf_s g_cap14_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM14_RES, - .channel = CONFIG_STM32H7_TIM14_CHANNEL, - .clock = CONFIG_STM32H7_TIM14_CLOCK, + .channel = CONFIG_STM32_TIM14_CHANNEL, + .clock = CONFIG_STM32_TIM14_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP static struct stm32_lowerhalf_s g_cap15_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM15_RES, - .channel = CONFIG_STM32H7_TIM15_CHANNEL, - .clock = CONFIG_STM32H7_TIM15_CLOCK, + .channel = CONFIG_STM32_TIM15_CHANNEL, + .clock = CONFIG_STM32_TIM15_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP static struct stm32_lowerhalf_s g_cap16_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM16_RES, - .channel = CONFIG_STM32H7_TIM16_CHANNEL, - .clock = CONFIG_STM32H7_TIM16_CLOCK, + .channel = CONFIG_STM32_TIM16_CHANNEL, + .clock = CONFIG_STM32_TIM16_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP static struct stm32_lowerhalf_s g_cap17_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM17_RES, - .channel = CONFIG_STM32H7_TIM17_CHANNEL, - .clock = CONFIG_STM32H7_TIM17_CLOCK, + .channel = CONFIG_STM32_TIM17_CHANNEL, + .clock = CONFIG_STM32_TIM17_CLOCK, }; #endif @@ -504,62 +504,62 @@ struct cap_lowerhalf_s *stm32_cap_initialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: lower = &g_cap1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: lower = &g_cap2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: lower = &g_cap3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: lower = &g_cap4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: lower = &g_cap5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: lower = &g_cap8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: lower = &g_cap12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: lower = &g_cap13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: lower = &g_cap14_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP case 15: lower = &g_cap15_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP case 16: lower = &g_cap16_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP case 17: lower = &g_cap17_lowerhalf; break; diff --git a/arch/arm/src/stm32h7/stm32_dma.c b/arch/arm/src/stm32h7/stm32_dma.c index adbecb87cea..5ea0a3f87e7 100644 --- a/arch/arm/src/stm32h7/stm32_dma.c +++ b/arch/arm/src/stm32h7/stm32_dma.c @@ -51,22 +51,22 @@ #define DMAMUX_NUM 2 #define DMA_CONTROLLERS 4 -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA # define MDMA_NCHAN 16 #else # define MDMA_NCHAN 0 #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NSTREAMS 8 #else # define DMA1_NSTREAMS 0 #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NSTREAMS 8 #else # define DMA2_NSTREAMS 0 #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA # define BDMA_NCHAN 8 #else # define BDMA_NCHAN 0 @@ -185,7 +185,7 @@ struct stm32_dma_ops_s * Private Functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA static void stm32_mdma_disable(DMA_CHANNEL dmachan); static int stm32_mdma_interrupt(int irq, void *context, void *arg); static void stm32_mdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -193,7 +193,7 @@ static void stm32_mdma_free(DMA_HANDLE handle); static void stm32_mdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_mdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_mdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -201,7 +201,7 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg); #endif #endif -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32_sdma_disable(DMA_CHANNEL dmachan); static int stm32_sdma_interrupt(int irq, void *context, void *arg); static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -209,7 +209,7 @@ static void stm32_sdma_free(DMA_HANDLE handle); static void stm32_sdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_sdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_sdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -217,7 +217,7 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg); #endif #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA static void stm32_bdma_disable(DMA_CHANNEL dmachan); static int stm32_bdma_interrupt(int irq, void *context, void *arg); static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -225,7 +225,7 @@ static void stm32_bdma_free(DMA_HANDLE handle); static void stm32_bdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_bdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_bdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -265,7 +265,7 @@ static inline void dmachan_modifyreg32(DMA_CHANNEL dmachan, struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* 0 - MDMA */ { @@ -275,7 +275,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_mdma_free, .dma_start = stm32_mdma_start, .dma_residual = stm32_mdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_mdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -288,7 +288,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 1 - DMA1 */ { @@ -298,7 +298,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_sdma_free, .dma_start = stm32_sdma_start, .dma_residual = stm32_sdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_sdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -311,7 +311,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 2 - DMA2 */ { @@ -321,7 +321,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_sdma_free, .dma_start = stm32_sdma_start, .dma_residual = stm32_sdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_sdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -334,7 +334,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* 3 - BDMA */ { @@ -344,7 +344,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_bdma_free, .dma_start = stm32_bdma_start, .dma_residual = stm32_bdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_bdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -427,7 +427,7 @@ struct stm32_dma_s g_dma[DMA_NCHANNELS] = static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA */ { @@ -559,7 +559,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { @@ -627,7 +627,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { @@ -695,7 +695,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA */ { @@ -920,7 +920,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, * Master DMA functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /**************************************************************************** * Name: stm32_mdma_disable @@ -1028,7 +1028,7 @@ static size_t stm32_mdma_residual(DMA_HANDLE handle) * Name: stm32_mdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_mdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -1084,13 +1084,13 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_MDMA */ +#endif /* CONFIG_STM32_MDMA */ /**************************************************************************** * Standard DMA functions ****************************************************************************/ -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32_sdma_disable @@ -1158,7 +1158,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg) /* Get the stream and the controller that generated the interrupt */ -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6) { stream = irq - STM32_IRQ_DMA1S0; @@ -1171,7 +1171,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg) } else #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) { stream = irq - STM32_IRQ_DMA2S0; @@ -1258,7 +1258,7 @@ static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg) "scr: %08" PRIx32 "\n", cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_sdma_capable(cfg)); #endif @@ -1530,7 +1530,7 @@ static size_t stm32_sdma_residual(DMA_HANDLE handle) * Name: stm32_sdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_sdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -1604,7 +1604,7 @@ static bool stm32_sdma_capable(stm32_dmacfg_t *cfg) dmainfo("stm32_dmacapable: dcache unaligned " "maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n", cfg->maddr, mend); -#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -1766,13 +1766,13 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_DMA1 || CONFIG_STM32H7_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Basic DMA functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /**************************************************************************** * Name: stm32_bdma_channel_disable @@ -1898,7 +1898,7 @@ static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg) "scr: %08" PRIx32 "\n", cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_bdma_capable(cfg)); #endif @@ -2106,7 +2106,7 @@ static size_t stm32_bdma_residual(DMA_HANDLE handle) * Name: stm32_bdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_bdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -2177,7 +2177,7 @@ static bool stm32_bdma_capable(stm32_dmacfg_t *cfg) dmainfo("stm32_dmacapable: dcache unaligned " "maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n", cfg->maddr, mend); -#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -2253,7 +2253,7 @@ static void stm32_bdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_BDMA */ +#endif /* CONFIG_STM32_BDMA */ /**************************************************************************** * Name: stm32_dmamux_dump @@ -2341,30 +2341,30 @@ void weak_function arm_dma_initialize(void) #ifdef CONFIG_ARCH_IRQPRIO switch (controller) { -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) case DMA1: case DMA2: { up_prioritize_irq(dmachan->irq, CONFIG_DMA_PRI); break; } -#endif /* CONFIG_STM32H7_DMA1 && CONFIG_STM32H7_DMA2 */ +#endif /* CONFIG_STM32_DMA1 && CONFIG_STM32_DMA2 */ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA case MDMA: { up_prioritize_irq(dmachan->irq, CONFIG_MDMA_PRI); break; } -#endif /* CONFIG_STM32H7_MDMA */ +#endif /* CONFIG_STM32_MDMA */ -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA case BDMA: { up_prioritize_irq(dmachan->irq, CONFIG_BDMA_PRI); break; } -#endif /* CONFIG_STM32H7_BDMA */ +#endif /* CONFIG_STM32_BDMA */ default: { @@ -2666,7 +2666,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32h7/stm32_dma.h b/arch/arm/src/stm32h7/stm32_dma.h index d8cfdc3524e..39b440be58e 100644 --- a/arch/arm/src/stm32h7/stm32_dma.h +++ b/arch/arm/src/stm32h7/stm32_dma.h @@ -194,7 +194,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * Name: stm32_dmacapable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg); #else # define stm32_dmacapable(handle, cfg) (true) diff --git a/arch/arm/src/stm32h7/stm32_dtcm.h b/arch/arm/src/stm32h7/stm32_dtcm.h index aba82326484..c55ded32e57 100644 --- a/arch/arm/src/stm32h7/stm32_dtcm.h +++ b/arch/arm/src/stm32h7/stm32_dtcm.h @@ -50,7 +50,7 @@ * heap. */ -#ifndef CONFIG_STM32H7_DTCMEXCLUDE +#ifndef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM_HEAP #endif diff --git a/arch/arm/src/stm32h7/stm32_dualcore.c b/arch/arm/src/stm32h7/stm32_dualcore.c index 85ab5e0ba3c..d0b3d84148f 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.c +++ b/arch/arm/src/stm32h7/stm32_dualcore.c @@ -52,7 +52,7 @@ ****************************************************************************/ #if (defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED)) || \ + defined(CONFIG_STM32_CORTEXM4_ENABLED)) || \ defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4) /**************************************************************************** @@ -105,7 +105,7 @@ static void stm32_cpu2sem_wait(void) #endif #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32_cm7_take_sem @@ -134,7 +134,7 @@ static void stm32_cpu2sem_take(void) ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32_start_cm4 @@ -162,7 +162,7 @@ void stm32_start_cm4(void) stm32_cpu2sem_take(); } -#ifdef CONFIG_STM32H7_CORTEXM7_BOOTM4 +#ifdef CONFIG_STM32_CORTEXM7_BOOTM4 else { /* CM4 not started at boot - force CM4 boot */ diff --git a/arch/arm/src/stm32h7/stm32_dualcore.h b/arch/arm/src/stm32h7/stm32_dualcore.h index 64f42ade6b3..9a8973b6ccb 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.h +++ b/arch/arm/src/stm32h7/stm32_dualcore.h @@ -51,7 +51,7 @@ extern "C" #endif #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32_start_cm4 diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 9cd6b485b88..abb490cf59f 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -69,11 +69,11 @@ #include /* STM32_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32H7_ETHMAC will defined if + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32H7 Ethernet support is enabled in the configuration. */ -#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -162,79 +162,79 @@ # warning "No PHY specified!" #endif -#ifndef CONFIG_STM32H7_PHYADDR -# error "CONFIG_STM32H7_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32H7_MII) && !defined(CONFIG_STM32H7_RMII) -# warning "Neither CONFIG_STM32H7_MII nor CONFIG_STM32H7_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32H7_MII) && defined(CONFIG_STM32H7_RMII) -# error "Both CONFIG_STM32H7_MII and CONFIG_STM32H7_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32H7_MII -# if !defined(CONFIG_STM32H7_MII_MCO1) && !defined(CONFIG_STM32H7_MII_MCO2) && \ - !defined(CONFIG_STM32H7_MII_EXTCLK) -# warning "Neither CONFIG_STM32H7_MII_MCO1, CONFIG_STM32H7_MII_MCO2, nor CONFIG_STM32H7_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H7_MII_MCO1) && defined(CONFIG_STM32H7_MII_MCO2) -# error "Both CONFIG_STM32H7_MII_MCO1 and CONFIG_STM32H7_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H7_RMII -# if !defined(CONFIG_STM32H7_RMII_MCO1) && !defined(CONFIG_STM32H7_RMII_MCO2) && \ - !defined(CONFIG_STM32H7_RMII_EXTCLK) -# warning "Neither CONFIG_STM32H7_RMII_MCO1, CONFIG_STM32H7_RMII_MCO2, nor CONFIG_STM32H7_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H7_RMII_MCO1) && defined(CONFIG_STM32H7_RMII_MCO2) -# error "Both CONFIG_STM32H7_RMII_MCO1 and CONFIG_STM32H7_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H7_AUTONEG -# ifndef CONFIG_STM32H7_PHYSR -# error "CONFIG_STM32H7_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32H7_PHYSR_ALTMODE -# error "CONFIG_STM32H7_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_10HD -# error "CONFIG_STM32H7_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100HD -# error "CONFIG_STM32H7_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_10FD -# error "CONFIG_STM32H7_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100FD -# error "CONFIG_STM32H7_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32H7_PHYSR_SPEED -# error "CONFIG_STM32H7_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100MBPS -# error "CONFIG_STM32H7_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_MODE -# error "CONFIG_STM32H7_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_FULLDUPLEX -# error "CONFIG_STM32H7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32H7_ETH_PTP -# warning "CONFIG_STM32H7_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif -#undef CONFIG_STM32H7_ETH_HWCHECKSUM +#undef CONFIG_STM32_ETH_HWCHECKSUM /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must @@ -262,16 +262,16 @@ # warning "You are using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32H7_ETH_NRXDESC -# define CONFIG_STM32H7_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32H7_ETH_NTXDESC -# define CONFIG_STM32H7_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H7_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers used for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -289,10 +289,10 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32H7_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) #define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) @@ -303,7 +303,7 @@ */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32H7_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -394,7 +394,7 @@ * ETH_MACCR_ACS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_DR Retry disable 1 (disabled) * ETH_MACCR_IPC IPv4 checksum offload - * Depends on CONFIG_STM32H7_ETH_HWCHECKSUM + * Depends on CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_DO Receive own disable 0 (enabled) * ETH_MACCR_DCRS Carrier sense disable 0 (enabled) @@ -409,7 +409,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPC | ETH_MACCR_IPG(96)) #else @@ -558,10 +558,10 @@ #define MTLRXQOMR_SET_MASK \ ((0x7 << ETH_MTLRXQOMR_RQS_SHIFT) | ETH_MTLRXQOMR_RTC_64) -#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM /* TODO */ -# error CONFIG_STM32H7_ETH_HWCHECKSUM not supported +# error CONFIG_STM32_ETH_HWCHECKSUM not supported #endif /* Clear the DMAMR bits that will be setup during MAC initialization (or that @@ -731,7 +731,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -803,7 +803,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, union stm32_desc_u *rxtable, uint8_t *rxbuffer); /* PHY Initialization */ -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int stm32_phyintenable(struct stm32_ethmac_s *priv); #endif @@ -812,17 +812,17 @@ static int stm32_phyintenable(struct stm32_ethmac_s *priv); static inline int stm32_dm9161(struct stm32_ethmac_s *priv); #endif static int stm32_phyinit(struct stm32_ethmac_s *priv); -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(struct stm32_ethmac_s *priv); #endif #endif /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32H7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -852,7 +852,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -924,7 +924,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -951,7 +951,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1093,10 +1093,10 @@ static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]; union stm32_desc_u *last = - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC + - CONFIG_STM32H7_ETH_NTXDESC - 1]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC + + CONFIG_STM32_ETH_NTXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1313,7 +1313,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32H7_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMACIER_RIE); } @@ -1379,7 +1379,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES3_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) != 0 || @@ -1452,7 +1452,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (des0) will be - * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 && @@ -1578,10 +1578,10 @@ static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC]; union stm32_desc_u *last = - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC + - CONFIG_STM32H7_ETH_NRXDESC - 1]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC + + CONFIG_STM32_ETH_NRXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1732,8 +1732,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 && - i < CONFIG_STM32H7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32H7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is a normal descriptor */ @@ -2831,7 +2831,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32H7_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].desc; @@ -2867,7 +2867,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCATXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H7_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); + stm32_putreg(CONFIG_STM32_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); /* Set Transmit Descriptor List Address Register */ @@ -2920,7 +2920,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32H7_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].desc; @@ -2953,7 +2953,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCARXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H7_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); + stm32_putreg(CONFIG_STM32_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); /* Set Receive Descriptor List Address Register */ @@ -2961,7 +2961,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Set Receive Descriptor Tail pointer Address */ - stm32_putreg((uint32_t)&rxtable[CONFIG_STM32H7_ETH_NRXDESC - 1].desc, + stm32_putreg((uint32_t)&rxtable[CONFIG_STM32_ETH_NRXDESC - 1].desc, STM32_ETH_DMACRXDTPR); } @@ -2997,7 +2997,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, #ifdef CONFIG_NETDEV_PHY_IOCTL static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #ifdef CONFIG_ARCH_PHY_INTERRUPT struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private; #endif @@ -3027,7 +3027,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32H7_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3062,7 +3062,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) } #endif /* CONFIG_NETDEV_PHY_IOCTL */ -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY /**************************************************************************** * Function: stm32_phyintenable * @@ -3119,7 +3119,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID1, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3142,7 +3142,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, 16, &phyval); + CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3176,7 +3176,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(struct stm32_ethmac_s *priv) { uint16_t phyval; @@ -3186,7 +3186,7 @@ static void stm32_phyregdump(struct stm32_ethmac_s *priv) for (i = 0; i < 0x20; i++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, i, &phyval); + CONFIG_STM32_PHYADDR, i, &phyval); if (ret < 0) { nerr("ERROR: Failed to read reg: 0%2x\n", i); @@ -3217,7 +3217,7 @@ static void stm32_phyregdump(struct stm32_ethmac_s *priv) static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32H7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3240,7 +3240,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ ret = mdio_write(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_RESET); + CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { nerr("ERROR: Failed to reset the PHY: %d\n", ret); @@ -3254,7 +3254,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) to -= 10; phyval = 0xffff; ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, &phyval); + CONFIG_STM32_PHYADDR, MII_MCR, &phyval); ninfo("MII_MCR: phyval: %u ret: %d\n", phyval, ret); } @@ -3271,7 +3271,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) } ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID1, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { @@ -3289,7 +3289,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) ninfo("MII_PHYID1: phyval: %u ret: %d\n", phyval, ret); ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID2, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID2, &phyval); if (ret < 0) { @@ -3306,7 +3306,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) ninfo("MII_PHYID2: phyval: %u ret: %d\n", phyval, ret); -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG stm32_phyregdump(priv); #endif @@ -3322,13 +3322,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32H7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval); + CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3352,7 +3352,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ ret = mdio_write(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); @@ -3364,7 +3364,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval); + CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3387,7 +3387,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, CONFIG_STM32H7_PHYSR, &phyval); + CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3396,38 +3396,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32H7_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. IF - * This CONFIG_STM32H7_PHYSR_ALTCONFIG is selected, this indicates that + * This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for * example, with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32H7_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32H7_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32H7_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32H7_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32H7_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3440,13 +3440,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32H7_PHYSR_MODE) == - CONFIG_STM32H7_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32H7_PHYSR_SPEED) == CONFIG_STM32H7_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3455,14 +3455,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32H7_PHYADDR, MII_MCR, phyval, 0xffff); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval, 0xffff); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3473,10 +3473,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3504,7 +3504,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void) { uint32_t regval; @@ -3530,7 +3530,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void) { uint32_t regval; @@ -3562,17 +3562,17 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32H7_MII) || defined(CONFIG_STM32H7_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ -# ifndef CONFIG_STM32H7_NO_PHY +# ifndef CONFIG_STM32_NO_PHY stm32_configgpio(GPIO_ETH_MDC); stm32_configgpio(GPIO_ETH_MDIO); # endif /* Set up the MII interface */ -# if defined(CONFIG_STM32H7_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3587,7 +3587,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3595,7 +3595,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3603,7 +3603,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3634,7 +3634,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32H7_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3649,7 +3649,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3657,7 +3657,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3665,7 +3665,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3688,7 +3688,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32H7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -4027,7 +4027,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * sequence in stm32_rcc.c. */ -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4050,24 +4050,24 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Initialize the PHY */ -#ifdef CONFIG_STM32H7_NO_PHY +#ifdef CONFIG_STM32_NO_PHY ninfo("MAC without PHY\n"); -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #else priv->fduplex = 0; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #else priv->mbps100 = 0; @@ -4190,7 +4190,7 @@ static inline int stm32_ethinitialize(int intf) return -EAGAIN; } -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4238,4 +4238,4 @@ void arm_netinitialize(void) } #endif -#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32h7/stm32_ethernet.h b/arch/arm/src/stm32h7/stm32_ethernet.h index 8faf17694ca..347beebab66 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/stm32_ethernet.h @@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32H7_PHYINIT is defined in the configuration + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration * then the board specific logic must provide stm32_phyinitialize(); The * STM32 Ethernet driver will call this function one time before it first * uses the PHY. @@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif diff --git a/arch/arm/src/stm32h7/stm32_exti_gpio.c b/arch/arm/src/stm32h7/stm32_exti_gpio.c index 4b27006a665..74c8e812fc4 100644 --- a/arch/arm/src/stm32h7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32h7/stm32_exti_gpio.c @@ -44,11 +44,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Private Types @@ -378,4 +378,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, return OK; } -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.c b/arch/arm/src/stm32h7/stm32_fdcan_sock.c index 459f0204a8b..15eecf55a7e 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.c +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.c @@ -90,9 +90,9 @@ * critical Rx/Tx transactions on the CAN bus. */ -# if defined(CONFIG_STM32H7_FDCAN_HPWORK) +# if defined(CONFIG_STM32_FDCAN_HPWORK) # define CANWORK HPWORK -# elif defined(CONFIG_STM32H7_FDCAN_LPWORK) +# elif defined(CONFIG_STM32_FDCAN_LPWORK) # define CANWORK LPWORK # else # define CANWORK LPWORK @@ -326,7 +326,7 @@ struct fdcan_message_ram /* FDCAN device structures **************************************************/ -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 static const struct fdcan_config_s stm32_fdcan0_config = { .tx_pin = GPIO_CAN1_TX, @@ -339,7 +339,7 @@ static const struct fdcan_config_s stm32_fdcan0_config = }; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 static const struct fdcan_config_s stm32_fdcan1_config = { .tx_pin = GPIO_CAN2_TX, @@ -352,7 +352,7 @@ static const struct fdcan_config_s stm32_fdcan1_config = }; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 static const struct fdcan_config_s stm32_fdcan2_config = { .tx_pin = GPIO_CAN3_TX, @@ -411,15 +411,15 @@ struct fdcan_driver_s * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 static struct fdcan_driver_s g_fdcan0; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 static struct fdcan_driver_s g_fdcan1; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 static struct fdcan_driver_s g_fdcan2; #endif @@ -437,7 +437,7 @@ static int fdcan_txpoll(struct net_driver_s *dev); /* Helper functions */ -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct fdcan_driver_s *priv); #endif @@ -511,7 +511,7 @@ static void fdcan_errint(struct fdcan_driver_s *priv, bool enable); * Dump common register values to the console for debugging purposes. ****************************************************************************/ -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct fdcan_driver_s *priv) { printf("-------------- FDCAN Reg Dump ----------------\n"); @@ -685,7 +685,7 @@ int32_t fdcan_bittiming(struct fdcan_bitseg *timing) return 3; /* Solution not found */ } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d" ", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1, bs2 - 1); @@ -1803,7 +1803,7 @@ static int fdcan_ifup(struct net_driver_s *dev) fdcan_setinit(priv->base, 0); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2092,7 +2092,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) return -EIO; } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG const struct fdcan_bitseg *tim = &priv->arbi_timing; ninfo("[fdcan][arbi] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); @@ -2116,7 +2116,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) return -EIO; } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG tim = &priv->data_timing; ninfo("[fdcan][data] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); @@ -2136,14 +2136,14 @@ int fdcan_initialize(struct fdcan_driver_s *priv) /* Operation Configuration */ -#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK +#ifdef CONFIG_STM32_FDCAN_LOOPBACK /* Enable External Loopback Mode (Rx pin disconnected) (RM0433 pg 2494) */ modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_TEST); modifyreg32(priv->base + STM32_FDCAN_TEST_OFFSET, 0, FDCAN_TEST_LBCK); #endif -#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK_INTERNAL +#ifdef CONFIG_STM32_FDCAN_LOOPBACK_INTERNAL /* Enable Bus Monitoring / Restricted Op Mode (RM0433 pg 2492, 2494) */ modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_MON); @@ -2331,7 +2331,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) regval &= ~FDCAN_GFC_ANFE; /* Accept non-matching extid frames into FIFO0 */ putreg32(regval, priv->base + STM32_FDCAN_GFC_OFFSET); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2339,7 +2339,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) fdcan_setinit(priv->base, 0); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2395,7 +2395,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv) { for (uint32_t i = 0; i < NUM_RX_FIFO0; i++) { - #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + #ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] MB RX %i %p\r\n", i, &priv->rx[i]); #endif priv->rx[i].header.w1 = 0x0; @@ -2411,7 +2411,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv) { for (uint32_t i = 0; i < NUM_TX_FIFO; i++) { - #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + #ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] MB TX %i %p\r\n", i, &priv->tx[i]); #endif priv->tx[i].header.w1 = 0x0; @@ -2458,7 +2458,7 @@ int stm32_fdcansockinitialize(int intf) switch (intf) { -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 case 0: priv = &g_fdcan0; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2477,7 +2477,7 @@ int stm32_fdcansockinitialize(int intf) break; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 case 1: priv = &g_fdcan1; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2496,7 +2496,7 @@ int stm32_fdcansockinitialize(int intf) break; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 case 2: priv = &g_fdcan2; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2579,7 +2579,7 @@ int stm32_fdcansockinitialize(int intf) netdev_register(&priv->dev, NET_LL_CAN); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2600,15 +2600,15 @@ int stm32_fdcansockinitialize(int intf) #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 stm32_fdcansockinitialize(2); #endif } diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.h b/arch/arm/src/stm32h7/stm32_fdcan_sock.h index 0c92ea109ae..f5f66c31090 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.h +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.h @@ -31,7 +31,7 @@ #include "hardware/stm32_fdcan.h" -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN /**************************************************************************** * Pre-processor Definitions @@ -105,5 +105,5 @@ int stm32_fdcansockinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_FDCAN */ +#endif /* CONFIG_STM32_FDCAN */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H */ diff --git a/arch/arm/src/stm32h7/stm32_flash.c b/arch/arm/src/stm32h7/stm32_flash.c index 3a963bbc22b..c9afb10a362 100644 --- a/arch/arm/src/stm32h7/stm32_flash.c +++ b/arch/arm/src/stm32h7/stm32_flash.c @@ -26,15 +26,15 @@ #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7b3xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h743xx_flash.c" #else # error "Unsupported STM32 H7 chip" diff --git a/arch/arm/src/stm32h7/stm32_fmc.c b/arch/arm/src/stm32h7/stm32_fmc.c index 841f2e64525..1b790354b18 100644 --- a/arch/arm/src/stm32h7/stm32_fmc.c +++ b/arch/arm/src/stm32h7/stm32_fmc.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32H7_FMC) +#if defined(CONFIG_STM32_FMC) #include "stm32.h" @@ -41,7 +41,7 @@ /**************************************************************************** * To use FMC, you must first enable it in configuration: * - * CONFIG_STM32H7_FMC=y + * CONFIG_STM32_FMC=y * * FMC is statically configured at startup. Its configuration is adjusted * using BOARD_XXX macros described below, which should be declared @@ -549,4 +549,4 @@ void stm32_fmc_sdram_command(uint32_t cmd) putreg32(cmd, STM32_FMC_SDCMR); } -#endif /* CONFIG_STM32H7_FMC */ +#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index 8723b1d4b5f..77bcccbc4ea 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -44,11 +44,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Private Data @@ -80,14 +80,14 @@ const uint32_t g_gpiobase[STM32_NGPIO] = STM32_GPIOE_BASE, #endif #if STM32_NGPIO > 5 -# if defined(CONFIG_STM32H7_HAVE_GPIOF) +# if defined(CONFIG_STM32_HAVE_GPIOF) STM32_GPIOF_BASE, # else 0, # endif #endif #if STM32_NGPIO > 6 -# if defined(CONFIG_STM32H7_HAVE_GPIOG) +# if defined(CONFIG_STM32_HAVE_GPIOG) STM32_GPIOG_BASE, # else 0, @@ -526,7 +526,7 @@ bool stm32_gpioread(uint32_t pinset) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION void stm32_iocompensation(void) { /* Enable I/O Compensation. Writing '1' to the CMPCR power-down bit @@ -543,4 +543,4 @@ void stm32_iocompensation(void) } #endif -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.h b/arch/arm/src/stm32h7/stm32_gpio.h index ab46e15a402..18ce28cc321 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.h +++ b/arch/arm/src/stm32h7/stm32_gpio.h @@ -199,10 +199,10 @@ #if STM32_NGPIO > 4 # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ #endif -#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) # define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ #endif -#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) # define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ #endif #if STM32_NGPIO > 7 @@ -350,7 +350,7 @@ bool stm32_gpioread(uint32_t pinset); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION void stm32_iocompensation(void); #endif diff --git a/arch/arm/src/stm32h7/stm32_i2c.c b/arch/arm/src/stm32h7/stm32_i2c.c index 9b7cdc9df2f..e01dd136a21 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.c +++ b/arch/arm/src/stm32h7/stm32_i2c.c @@ -156,28 +156,28 @@ * * One of: * - * CONFIG_STM32H7_STM32H7X3XX + * CONFIG_STM32_STM32H7X3XX * * and one or more interfaces: * - * CONFIG_STM32H7_I2C1 - * CONFIG_STM32H7_I2C2 - * CONFIG_STM32H7_I2C3 - * CONFIG_STM32H7_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32H7_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32H7_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32H7_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32H7_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32H7_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in msec) * * Debugging output enabled with: @@ -225,8 +225,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || \ - defined(CONFIG_STM32H7_I2C3) || defined(CONFIG_STM32H7_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -234,14 +234,14 @@ #undef INVALID_CLOCK_SOURCE -#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || \ - defined(CONFIG_STM32H7_I2C3) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) # if STM32_RCC_D2CCIP2R_I2C123SRC != RCC_D2CCIP2R_I2C123SEL_HSI # warning "Clock Source STM32_RCC_D2CCIP2R_I2C123SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 # if STM32_RCC_D3CCIPR_I2C4SRC != RCC_D3CCIPR_I2C4SEL_HSI # warning "Clock Source STM32_RCC_D3CCIPR_I2C4SRC must be HSI" # define INVALID_CLOCK_SOURCE @@ -258,25 +258,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32H7_I2CTIMEOSEC) && !defined(CONFIG_STM32H7_I2CTIMEOMS) -# define CONFIG_STM32H7_I2CTIMEOSEC 0 -# define CONFIG_STM32H7_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32H7_I2CTIMEOSEC) -# define CONFIG_STM32H7_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32H7_I2CTIMEOMS) -# define CONFIG_STM32H7_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32H7_I2CTIMEOTICKS -# define CONFIG_STM32H7_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32H7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32H7_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32H7_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -446,9 +446,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32H7_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -488,7 +488,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -524,7 +524,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -560,7 +560,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -596,7 +596,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -726,7 +726,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -743,7 +743,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -799,12 +799,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32H7_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -842,10 +842,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32H7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -983,10 +983,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32H7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2715,22 +2715,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2816,5 +2816,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32H7_I2C1 || CONFIG_STM32H7_I2C2 || \ - * CONFIG_STM32H7_I2C3 || CONFIG_STM32H7_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32h7/stm32_i2c.h b/arch/arm/src/stm32h7/stm32_i2c.h index ae507efe603..78dc96b1ba5 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.h +++ b/arch/arm/src/stm32h7/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO -# if CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32H7_I2C_DYNTIMEO because of CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32h7/stm32_iwdg.c b/arch/arm/src/stm32h7/stm32_iwdg.c index 13150c39431..39212b5a753 100644 --- a/arch/arm/src/stm32h7/stm32_iwdg.c +++ b/arch/arm/src/stm32h7/stm32_iwdg.c @@ -41,7 +41,7 @@ #include "stm32_rcc.h" #include "stm32_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32H7_IWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) /**************************************************************************** * Pre-processor Definitions @@ -681,9 +681,9 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) * on DBG_IWDG_STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32H7_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr = getreg32(STM32_DBGMCU_APB4_FZ1); cr |= DBGMCU_APB4_WDGLSD1; @@ -692,4 +692,4 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32H7_IWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32h7/stm32_lptim.c b/arch/arm/src/stm32h7/stm32_lptim.c index daa7bc8029f..958243f7631 100644 --- a/arch/arm/src/stm32h7/stm32_lptim.c +++ b/arch/arm/src/stm32h7/stm32_lptim.c @@ -43,9 +43,9 @@ #include "stm32_gpio.h" #include "stm32_lptim.h" -#if defined(CONFIG_STM32H7_LPTIM1) || defined(CONFIG_STM32H7_LPTIM2) || \ - defined(CONFIG_STM32H7_LPTIM3) || defined(CONFIG_STM32H7_LPTIM4) || \ - defined(CONFIG_STM32H7_LPTIM5) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) || \ + defined(CONFIG_STM32_LPTIM3) || defined(CONFIG_STM32_LPTIM4) || \ + defined(CONFIG_STM32_LPTIM5) /**************************************************************************** * Private Function prototypes @@ -103,35 +103,35 @@ static const struct stm32_lptim_ops_s stm32_lptim_ops = .ackint = &stm32_lptim_ackint }; -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 struct stm32_lptim_dev_s stm32_lptim1_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM1_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 struct stm32_lptim_dev_s stm32_lptim2_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM2_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 struct stm32_lptim_dev_s stm32_lptim3_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM3_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 struct stm32_lptim_dev_s stm32_lptim4_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM4_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 struct stm32_lptim_dev_s stm32_lptim5_priv = { .ops = &stm32_lptim_ops, @@ -205,7 +205,7 @@ static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, { switch (dev->base) { -#if defined(CONFIG_STM32H7_LPTIM1) || defined(CONFIG_STM32H7_LPTIM2) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) case STM32_LPTIM1_BASE: case STM32_LPTIM2_BASE: if (input == 0) @@ -221,7 +221,7 @@ static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: modifyreg32(dev->base + STM32_LPTIM_CFGR2_OFFSET, LPTIM_CFGR2_IN1SEL_MASK, mux); @@ -301,27 +301,27 @@ static int stm32_lptim_setisr(struct stm32_lptim_dev_s *dev, switch (dev->base) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: vectorno = STM32_IRQ_LPTIM1; break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: vectorno = STM32_IRQ_LPTIM2; break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: vectorno = STM32_IRQ_LPTIM3; break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case STM32_LPTIM4_BASE: vectorno = STM32_IRQ_LPTIM4; break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case STM32_LPTIM5_BASE: vectorno = STM32_IRQ_LPTIM5; break; @@ -391,31 +391,31 @@ struct stm32_lptim_dev_s *stm32_lptim_init(int lptimer) switch (lptimer) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case 1: dev = &stm32_lptim1_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_LPTIM1EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case 2: dev = &stm32_lptim2_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM2EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case 3: dev = &stm32_lptim3_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM3EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case 4: dev = &stm32_lptim4_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM4EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case 5: dev = &stm32_lptim5_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM5EN); @@ -436,27 +436,27 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) switch (dev->base) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: modifyreg32(STM32_RCC_APB1LLPENR, RCC_APB1LENR_LPTIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case STM32_LPTIM4_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case STM32_LPTIM5_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM5EN, 0); break; @@ -468,4 +468,4 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_LPTIM1 || ... || CONFIG_STM32H7_LPTIM5) */ +#endif /* defined(CONFIG_STM32_LPTIM1 || ... || CONFIG_STM32_LPTIM5) */ diff --git a/arch/arm/src/stm32h7/stm32_lse.c b/arch/arm/src/stm32h7/stm32_lse.c index e55b9936798..0fdfaf611c7 100644 --- a/arch/arm/src/stm32h7/stm32_lse.c +++ b/arch/arm/src/stm32h7/stm32_lse.c @@ -42,16 +42,16 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -96,7 +96,7 @@ void stm32_rcc_enablelse(void) { uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif const uint32_t *drives = drives_rev_y; @@ -131,18 +131,18 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. With the * enable off */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= drives[CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY]; + regval |= drives[CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY]; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -170,7 +170,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -179,13 +179,13 @@ void stm32_rcc_enablelse(void) while (drive < sizeof(drives_rev_y) / sizeof(drives_rev_y[0])); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= drives[CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY]; + regval |= drives[CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY]; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32h7/stm32_ltdc.c b/arch/arm/src/stm32h7/stm32_ltdc.c index 79f6ac0f0de..c946c889300 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.c +++ b/arch/arm/src/stm32h7/stm32_ltdc.c @@ -127,8 +127,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_LTDC_DEFBACKLIGHT -# define CONFIG_STM32H7_LTDC_DEFBACKLIGHT 0xf0 +#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT +# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 #endif #define STM32_LTDC_BACKLIGHT_OFF 0x00 @@ -136,23 +136,23 @@ /* Layer 1 format */ -#if defined(CONFIG_STM32H7_LTDC_L1_L8) +#if defined(CONFIG_STM32_LTDC_L1_L8) # define STM32_LTDC_L1_BPP 8 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L1CMAP -#elif defined(CONFIG_STM32H7_LTDC_L1_RGB565) +#elif defined(CONFIG_STM32_LTDC_L1_RGB565) # define STM32_LTDC_L1_BPP 16 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 -#elif defined(CONFIG_STM32H7_LTDC_L1_RGB888) +#elif defined(CONFIG_STM32_LTDC_L1_RGB888) # define STM32_LTDC_L1_BPP 24 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 -#elif defined(CONFIG_STM32H7_LTDC_L1_ARGB8888) +#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) # define STM32_LTDC_L1_BPP 32 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -163,24 +163,24 @@ /* Layer 2 format */ -#ifdef CONFIG_STM32H7_LTDC_L2 -# if defined(CONFIG_STM32H7_LTDC_L2_L8) +#ifdef CONFIG_STM32_LTDC_L2 +# if defined(CONFIG_STM32_LTDC_L2_L8) # define STM32_LTDC_L2_BPP 8 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L2CMAP -# elif defined(CONFIG_STM32H7_LTDC_L2_RGB565) +# elif defined(CONFIG_STM32_LTDC_L2_RGB565) # define STM32_LTDC_L2_BPP 16 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32H7_LTDC_L2_RGB888) +# elif defined(CONFIG_STM32_LTDC_L2_RGB888) # define STM32_LTDC_L2_BPP 24 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32H7_LTDC_L2_ARGB8888) +# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) # define STM32_LTDC_L2_BPP 32 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -188,7 +188,7 @@ # else # error "LTDC pixel format not supported" # endif -#endif /* CONFIG_STM32H7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ /* Framebuffer sizes in bytes */ @@ -208,13 +208,13 @@ #define STM32_LTDC_LX_BYPP(n) ((n) / 8) -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT * 2) #else #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) #endif -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # ifndef CONFIG_STM32H7_LTDC_L2_WIDTH # define CONFIG_STM32H7_LTDC_L2_WIDTH STM32_LTDC_WIDTH # endif @@ -258,7 +258,7 @@ /* Debug option */ -#ifdef CONFIG_STM32H7_LTDC_REGDEBUG +#ifdef CONFIG_STM32_LTDC_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -273,10 +273,10 @@ * against wild framebuffer writes. */ -#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32H7_LTDC_FB_SIZE +#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE #define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ STM32_LTDC_TOTAL_FBSIZE) -#define STM32_LTDC_BUFFER_START (CONFIG_STM32H7_LTDC_FB_BASE + \ +#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ STM32_LTDC_BUFFER_FREE/2) #if STM32_LTDC_BUFFER_FREE < 0 @@ -289,7 +289,7 @@ #define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ STM32_LTDC_L1_FBSIZE) -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 # define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ STM32_LTDC_L2_FBSIZE) @@ -299,7 +299,7 @@ /* LTDC layer */ -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_NLAYERS 2 #else # define LTDC_NLAYERS 1 @@ -307,27 +307,27 @@ /* DMA2D layer */ -#ifdef CONFIG_STM32H7_DMA2D -# define DMA2D_NLAYERS CONFIG_STM32H7_DMA2D_NLAYERS +#ifdef CONFIG_STM32_DMA2D +# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS # if DMA2D_NLAYERS < 1 # error "DMA2D must at least support 1 overlay" # endif -#define STM32_DMA2D_WIDTH CONFIG_STM32H7_DMA2D_LAYER_PPLINE +#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE -# if defined(CONFIG_STM32H7_DMA2D_L8) +# if defined(CONFIG_STM32_DMA2D_L8) # define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) # define STM32_DMA2D_BPP 8 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 -# elif defined(CONFIG_STM32H7_DMA2D_RGB565) +# elif defined(CONFIG_STM32_DMA2D_RGB565) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) # define STM32_DMA2D_BPP 16 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32H7_DMA2D_RGB888) +# elif defined(CONFIG_STM32_DMA2D_RGB888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) # define STM32_DMA2D_BPP 24 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32H7_DMA2D_ARGB8888) +# elif defined(CONFIG_STM32_DMA2D_ARGB8888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) # define STM32_DMA2D_BPP 32 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 @@ -335,63 +335,63 @@ # error "DMA2D pixel format not supported" # endif -# ifdef CONFIG_STM32H7_DMA2D_LAYER_SHARED -# define STM32_DMA2D_FBSIZE CONFIG_STM32H7_DMA2D_FB_SIZE +# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE # define STM32_DMA2D_LAYER_SIZE 0 # else -# define STM32_DMA2D_FBSIZE CONFIG_STM32H7_DMA2D_FB_SIZE / DMA2D_NLAYERS +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS # define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE -# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32H7_DMA2D_FB_SIZE +# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE # error "DMA2D framebuffer size to small for configured number of overlays" # endif -# endif /* CONFIG_STM32H7_DMA2D_LAYER_SHARED */ +# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ # define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE -# define STM32_DMA2D_BUFFER_START CONFIG_STM32H7_DMA2D_FB_BASE +# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE #else # define DMA2D_NLAYERS 0 -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS /* Dithering */ -#ifndef CONFIG_STM32H7_LTDC_DITHER_RED +#ifndef CONFIG_STM32_LTDC_DITHER_RED # define STM32_LTDC_DITHER_RED 0 #else -# define STM32_LTDC_DITHER_RED CONFIG_STM32H7_LTDC_DITHER_RED +# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED #endif -#ifndef CONFIG_STM32H7_LTDC_DITHER_GREEN +#ifndef CONFIG_STM32_LTDC_DITHER_GREEN # define STM32_LTDC_DITHER_GREEN 0 #else -# define STM32_LTDC_DITHER_GREEN CONFIG_STM32H7_LTDC_DITHER_GREEN +# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN #endif -#ifndef CONFIG_STM32H7_LTDC_DITHER_BLUE +#ifndef CONFIG_STM32_LTDC_DITHER_BLUE # define STM32_LTDC_DITHER_BLUE 0 #else -# define STM32_LTDC_DITHER_BLUE CONFIG_STM32H7_LTDC_DITHER_BLUE +# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE #endif /* Background color */ -#ifndef CONFIG_STM32H7_LTDC_BACKCOLOR +#ifndef CONFIG_STM32_LTDC_BACKCOLOR # define STM32_LTDC_BACKCOLOR 0 #else -# define STM32_LTDC_BACKCOLOR CONFIG_STM32H7_LTDC_BACKCOLOR +# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR #endif /* Layer default color */ -#ifdef CONFIG_STM32H7_LTDC_L1_COLOR -# define STM32_LTDC_L1_COLOR CONFIG_STM32H7_LTDC_L1_COLOR +#ifdef CONFIG_STM32_LTDC_L1_COLOR +# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR #else # define STM32_LTDC_L1_COLOR 0x000000 #endif -#ifdef CONFIG_STM32H7_LTDC_L2 -# ifdef CONFIG_STM32H7_LTDC_L2_COLOR -# define STM32_LTDC_L2_COLOR CONFIG_STM32H7_LTDC_L2_COLOR +#ifdef CONFIG_STM32_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2_COLOR +# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR # else # define STM32_LTDC_L2_COLOR 0x000000 # endif @@ -425,28 +425,28 @@ /* Check pixel format support by DMA2D driver */ -#ifdef CONFIG_STM32H7_DMA2D -# if defined(CONFIG_STM32H7_LTDC_L1_L8) || \ - defined(CONFIG_STM32H7_LTDC_L2_L8) -# if !defined(CONFIG_STM32H7_DMA2D_L8) +#ifdef CONFIG_STM32_DMA2D +# if defined(CONFIG_STM32_LTDC_L1_L8) || \ + defined(CONFIG_STM32_LTDC_L2_L8) +# if !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must support FB_FMT_RGB8 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_RGB565) || \ - defined(CONFIG_STM32H7_LTDC_L2_RGB565) -# if !defined(CONFIG_STM32H7_DMA2D_RGB565) +# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ + defined(CONFIG_STM32_LTDC_L2_RGB565) +# if !defined(CONFIG_STM32_DMA2D_RGB565) # error "DMA2D must support FB_FMT_RGB16_565 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_RGB888) || \ - defined(CONFIG_STM32H7_LTDC_L2_RGB888) -# if !defined(CONFIG_STM32H7_DMA2D_RGB888) +# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ + defined(CONFIG_STM32_LTDC_L2_RGB888) +# if !defined(CONFIG_STM32_DMA2D_RGB888) # error "DMA2D must support FB_FMT_RGB24 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_ARGB8888) || \ - defined(CONFIG_STM32H7_LTDC_L2_ARGB8888) -# if !defined(CONFIG_STM32H7_DMA2D_ARGB8888) +# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ + defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# if !defined(CONFIG_STM32_DMA2D_ARGB8888) # error "DMA2D must support FB_FMT_RGB32 pixel format" # endif # endif @@ -454,12 +454,12 @@ /* Calculate the size of the layers clut table */ -#ifdef CONFIG_STM32H7_FB_CMAP -# if defined(CONFIG_STM32H7_DMA2D) && !defined(CONFIG_STM32H7_DMA2D_L8) +#ifdef CONFIG_STM32_FB_CMAP +# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" # endif # ifdef STM32_LTDC_L1CMAP -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) @@ -467,7 +467,7 @@ # endif # ifdef STM32_LTDC_L2CMAP # undef STM32_LAYER_CLUT_SIZE -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 @@ -475,7 +475,7 @@ # endif #endif -#ifndef CONFIG_STM32H7_FB_CMAP +#ifndef CONFIG_STM32_FB_CMAP # if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) # undef STM32_LTDC_L1CMAP # undef STM32_LTDC_L2CMAP @@ -512,9 +512,9 @@ /* Acceleration support for LTDC overlays */ -#ifdef CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN # define STM32_LTDC_L1_CHROMAEN true -# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32H7_LTDC_L1_CHROMAKEY +# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L1_CHROMAEN false @@ -522,9 +522,9 @@ # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32H7_LTDC_L2_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN # define STM32_LTDC_L2_CHROMAEN true -# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32H7_LTDC_L2_CHROMAKEY +# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L2_CHROMAEN false @@ -532,34 +532,34 @@ # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D # ifdef CONFIG_FB_OVERLAY_BLIT -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_BLIT_ACCL FB_ACCL_BLIT # else # define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND -# endif /* CONFIG_STM32H7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ # else # define LTDC_BLIT_ACCL 0 # endif /* CONFIG_FB_OVERLAY_BLIT */ -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL # else # define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL -# endif /* CONFIG_STM32H7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ #else # define LTDC_DMA2D_ACCL 0 -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL #endif /* Acceleration support for DMA2D overlays */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP # ifdef CONFIG_FB_OVERLAY_BLIT # define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA # else @@ -585,7 +585,7 @@ /* Color normalization */ -#if defined(CONFIG_STM32H7_LTDC_L1_RGB565) +#if defined(CONFIG_STM32_LTDC_L1_RGB565) # define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) # define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) # define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) @@ -618,7 +618,7 @@ struct stm32_ltdc_s struct fb_overlayinfo_s oinfo; /* Overlay info */ #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ #endif @@ -643,7 +643,7 @@ struct stm32_ltdcdev_s /* Cmap information */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP struct fb_cmap_s cmap; #endif @@ -651,7 +651,7 @@ struct stm32_ltdcdev_s struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Interface to the dma2d controller */ struct dma2d_layer_s *dma2d; @@ -699,7 +699,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, bool enable); static void stm32_ltdc_linit(uint8_t lid); -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void); # ifdef CONFIG_FB_OVERLAY_BLIT @@ -708,7 +708,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, # endif #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, const struct fb_cmap_s *cmap); static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, @@ -731,7 +731,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, * mapping */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap); static int stm32_putcmap(struct fb_vtable_s *vtable, @@ -746,7 +746,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, static int stm32_waitforvsync(struct fb_vtable_s *vtable); #endif -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) static int stm32_pandisplay(struct fb_vtable_s *vtable, struct fb_planeinfo_s *pinfo); #endif @@ -806,16 +806,16 @@ static const uint32_t g_ltdcpins[] = #define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* The layers clut table entries */ static uint8_t g_redclut[STM32_LTDC_NCLUT]; static uint8_t g_greenclut[STM32_LTDC_NCLUT]; static uint8_t g_blueclut[STM32_LTDC_NCLUT]; -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY static uint8_t g_transpclut[STM32_LTDC_NCLUT]; # endif -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The LTDC semaphore that enforces mutually exclusive access */ @@ -847,12 +847,12 @@ static struct stm32_ltdcdev_s g_vtable = .waitforvsync = stm32_waitforvsync #endif -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) , .pandisplay = stm32_pandisplay #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP , .getcmap = stm32_getcmap, .putcmap = stm32_putcmap @@ -873,7 +873,7 @@ static struct stm32_ltdcdev_s g_vtable = # endif #endif /* CONFIG_FB_OVERLAY */ }, -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 .pinfo = { .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, @@ -901,7 +901,7 @@ static struct stm32_ltdcdev_s g_vtable = .display = 0, .bpp = STM32_LTDC_L1_BPP, .xres_virtual = STM32_LTDC_WIDTH, -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) .yres_virtual = STM32_LTDC_HEIGHT * 2, #else .yres_virtual = STM32_LTDC_HEIGHT, @@ -919,9 +919,9 @@ static struct stm32_ltdcdev_s g_vtable = .noverlays = LTDC_NOVERLAYS # endif } -#endif /* CONFIG_STM32H7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ , -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .cmap = { .first = 0, @@ -929,7 +929,7 @@ static struct stm32_ltdcdev_s g_vtable = .red = g_redclut, .green = g_greenclut, .blue = g_blueclut, -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY .transp = g_transpclut # endif } @@ -965,7 +965,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L1_DMA2D_PF, @@ -977,7 +977,7 @@ static struct stm32_ltdcdev_s g_vtable = #endif .lock = &g_lock } -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , .layer[LTDC_LAYER_L2] = { @@ -1009,7 +1009,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L2_DMA2D_PF, @@ -1031,7 +1031,7 @@ static struct stm32_ltdcdev_s g_vtable = static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = { STM32_LTDC_WIDTH -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_WIDTH #endif }; @@ -1041,7 +1041,7 @@ static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = { STM32_LTDC_HEIGHT -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_HEIGHT #endif }; @@ -1051,7 +1051,7 @@ static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_STRIDE -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_STRIDE #endif }; @@ -1061,7 +1061,7 @@ static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_BPP -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_BPP #endif }; @@ -1071,7 +1071,7 @@ static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_FBSIZE -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_FBSIZE #endif }; @@ -1081,7 +1081,7 @@ static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = { STM32_LTDC_BUFFER_L1 -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_BUFFER_L2 #endif }; @@ -1091,7 +1091,7 @@ static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_COLOR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_COLOR #endif }; @@ -1101,7 +1101,7 @@ static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAKEY -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAKEY #endif }; @@ -1111,7 +1111,7 @@ static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAEN -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAEN #endif }; @@ -1121,7 +1121,7 @@ static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR_PF -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR_PF #endif }; @@ -1133,7 +1133,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CR #endif }; @@ -1143,7 +1143,7 @@ static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WHPCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WHPCR #endif }; @@ -1153,7 +1153,7 @@ static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WVPCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WVPCR #endif }; @@ -1163,7 +1163,7 @@ static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR #endif }; @@ -1173,7 +1173,7 @@ static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1DCCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2DCCR #endif }; @@ -1183,7 +1183,7 @@ static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CKCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CKCR #endif }; @@ -1193,7 +1193,7 @@ static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CACR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CACR #endif }; @@ -1203,7 +1203,7 @@ static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1BFCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2BFCR #endif }; @@ -1213,7 +1213,7 @@ static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBAR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBAR #endif }; @@ -1223,7 +1223,7 @@ static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLR #endif }; @@ -1233,22 +1233,22 @@ static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLNR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLNR #endif }; /* LTDC_LxCLUTWR */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CLUTWR -# ifdef CONFIG_STM32H7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CLUTWR # endif }; -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The initialized state of the driver */ @@ -1501,7 +1501,7 @@ static int stm32_ltdcirq(int irq, void *context, void *arg) putreg32(LTDC_ICR_CRRIF, STM32_LTDC_ICR); priv->error = OK; -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) fb_remove_paninfo(&g_vtable.vtable, FB_NO_OVERLAY); #endif } @@ -1681,7 +1681,7 @@ static void stm32_ltdc_globalconfig(void) /* Configure dither */ stm32_ltdc_dither( -#ifdef CONFIG_STM32H7_LTDC_DITHER +#ifdef CONFIG_STM32_LTDC_DITHER true, #else false, @@ -1953,7 +1953,7 @@ static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, /* Set chromakey */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint8_t r = g_vtable.cmap.red[chroma]; uint8_t g = g_vtable.cmap.green[chroma]; uint8_t b = g_vtable.cmap.blue[chroma]; @@ -2023,7 +2023,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, bool enable) { uint32_t regval; @@ -2127,7 +2127,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) { -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n] = priv_cmap->transp[n]; # endif cmap->red[n] = priv_cmap->red[n]; @@ -2136,7 +2136,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", n, -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n], # endif cmap->red[n], @@ -2144,7 +2144,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, cmap->blue[n]); } } -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ltdc_lclear @@ -2176,7 +2176,7 @@ static void stm32_ltdc_lclear(uint8_t overlayno) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) +#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, const struct fb_area_s *area) { @@ -2187,7 +2187,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); } -#endif /* defined(CONFIG_STM32H7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ +#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ /**************************************************************************** * Name: stm32_ltdc_linit @@ -2247,7 +2247,7 @@ static void stm32_ltdc_linit(uint8_t overlay) stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Disable clut by default */ if (dev->vinfo.fmt == FB_FMT_RGB8) @@ -2287,7 +2287,7 @@ static void stm32_ltdc_linit(uint8_t overlay) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void) { int n; @@ -2323,7 +2323,7 @@ static void stm32_ltdc_dma2dlinit(void) layer->dma2dinfo.oinfo = &layer->oinfo; } } -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ /**************************************************************************** * Public Functions @@ -2410,7 +2410,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap) { @@ -2440,7 +2440,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, */ struct stm32_ltdc_s *layer; -# ifdef CONFIG_STM32H7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 layer = &priv->layer[LTDC_LAYER_L2]; # else layer = &priv->layer[LTDC_LAYER_L1]; @@ -2510,7 +2510,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, priv_cmap->red[n] = cmap->red[n]; priv_cmap->green[n] = cmap->green[n]; priv_cmap->blue[n] = cmap->blue[n]; -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY /* Not supported by LTDC */ priv_cmap->transp[n] = cmap->transp[n]; @@ -2530,7 +2530,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, stm32_ltdc_lputclut(layer, priv_cmap); } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Update dma2d cmap */ priv->dma2d->setclut(cmap); @@ -2542,7 +2542,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, return ret; } -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ioctl_waitforvsync @@ -2570,7 +2570,7 @@ static int stm32_waitforvsync(struct fb_vtable_s *vtable) * Description: * Entrypoint ioctl FBIOPAN_DISPLAY ****************************************************************************/ -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) static int stm32_pandisplay(struct fb_vtable_s *vtable, struct fb_planeinfo_s *pinfo) { @@ -2647,7 +2647,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable, layer->oinfo.transp.transp = oinfo->transp.transp; layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (layer->oinfo.transp.transp_mode == 0) { layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; @@ -2694,14 +2694,14 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, int ret; struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; -# ifndef CONFIG_STM32H7_LTDC_L1_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L1) { return -ENOSYS; } # endif -# ifndef CONFIG_STM32H7_LTDC_L2_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L2) { return -ENOSYS; @@ -2709,7 +2709,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, # endif nxsem_wait(layer->lock); -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP if (oinfo->chromakey >= g_vtable.cmap.len) { lcderr("ERROR: Clut index %d is out of range\n", oinfo->chromakey); @@ -2729,7 +2729,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, nxsem_post(layer->lock); return ret; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* Chromakey not supported by DMA2D */ @@ -2757,7 +2757,7 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, if (oinfo->overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Set color within the active overlay is not supported by LTDC. So use * DMA2D controller instead when configured. @@ -2817,7 +2817,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable, return OK; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* DMA2D overlays are non visible */ @@ -2851,7 +2851,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable, return -ENOSYS; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (oinfo->overlay < LTDC_NOVERLAYS) { struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; @@ -2885,7 +2885,7 @@ static int stm32_blit(struct fb_vtable_s *vtable, if (blit->dest.overlay < LTDC_NOVERLAYS && blit->src.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s sarea; const struct fb_area_s *darea = &blit->dest.area; @@ -2944,7 +2944,7 @@ static int stm32_blend(struct fb_vtable_s *vtable, blend->foreground.overlay < LTDC_NOVERLAYS && blend->background.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s barea; const struct fb_area_s *darea = &blend->dest.area; @@ -3055,7 +3055,7 @@ int stm32_ltdcinitialize(void) lcdinfo("Configure global register\n"); stm32_ltdc_globalconfig(); -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Initialize the dma2d controller */ ret = stm32_dma2dinitialize(); @@ -3071,26 +3071,26 @@ int stm32_ltdcinitialize(void) DEBUGASSERT(g_vtable.dma2d != NULL); #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Cleanup clut */ memset(&g_redclut, 0, STM32_LTDC_NCLUT); memset(&g_blueclut, 0, STM32_LTDC_NCLUT); memset(&g_greenclut, 0, STM32_LTDC_NCLUT); -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY memset(&g_transpclut, 0, STM32_LTDC_NCLUT); # endif -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Initialize ltdc layer */ lcdinfo("Initialize ltdc layer\n"); stm32_ltdc_linit(LTDC_LAYER_L1); -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 stm32_ltdc_linit(LTDC_LAYER_L2); #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D stm32_ltdc_dma2dlinit(); #endif /* Enable the backlight */ @@ -3184,7 +3184,7 @@ void stm32_ltdcuninitialize(void) #ifdef CONFIG_STM32H7_LCD_BACKLIGHT void stm32_backlight(bool blon) { - /* Set default backlight level CONFIG_STM32H7_LTDC_DEFBACKLIGHT */ + /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ lcderr("ERROR: Not supported\n"); } diff --git a/arch/arm/src/stm32h7/stm32_ltdc.h b/arch/arm/src/stm32h7/stm32_ltdc.h index 53a73da7d08..da7d21b7ed7 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.h +++ b/arch/arm/src/stm32h7/stm32_ltdc.h @@ -91,12 +91,12 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); * Name: stm32_lcd_backlight * * Description: - * If CONFIG_STM32F7_LCD_BACKLIGHT is defined, then the board-specific + * If CONFIG_STM32_LCD_BACKLIGHT is defined, then the board-specific * logic must provide this interface to turn the backlight on and off. * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif #endif /* __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32h7/stm32_mdio.c b/arch/arm/src/stm32h7/stm32_mdio.c index d524b27ce1f..412aedcb915 100644 --- a/arch/arm/src/stm32h7/stm32_mdio.c +++ b/arch/arm/src/stm32h7/stm32_mdio.c @@ -30,7 +30,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); diff --git a/arch/arm/src/stm32h7/stm32_mpuinit.c b/arch/arm/src/stm32h7/stm32_mpuinit.c index 625e7eb2a5f..a141895b210 100644 --- a/arch/arm/src/stm32h7/stm32_mpuinit.c +++ b/arch/arm/src/stm32h7/stm32_mpuinit.c @@ -44,7 +44,7 @@ ****************************************************************************/ #ifdef CONFIG_RPTUN -# ifdef CONFIG_STM32H7_SHMEM_SRAM3 +# ifdef CONFIG_STM32_SHMEM_SRAM3 # define STM32_SHMEM_BASE STM32_SRAM3_BASE # define STM32_SHMEM_SIZE STM32_SRAM3_SIZE # else diff --git a/arch/arm/src/stm32h7/stm32_oneshot.c b/arch/arm/src/stm32h7/stm32_oneshot.c index 078d6efe502..e1fc56718ec 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.c +++ b/arch/arm/src/stm32h7/stm32_oneshot.c @@ -39,7 +39,7 @@ #include "stm32_oneshot.h" -#ifdef CONFIG_STM32H7_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes @@ -51,7 +51,7 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg); * Private Data ****************************************************************************/ -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32H7_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions @@ -117,19 +117,19 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32H7_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32H7_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -401,4 +401,4 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32H7_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32h7/stm32_oneshot.h b/arch/arm/src/stm32h7/stm32_oneshot.h index 412f901e16b..f16523985ff 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.h +++ b/arch/arm/src/stm32h7/stm32_oneshot.h @@ -36,22 +36,22 @@ #include "stm32_tim.h" -#ifdef CONFIG_STM32H7_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32H7_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32H7_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32H7_ONESHOT_MAXTIMERS -# define CONFIG_STM32H7_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32H7_ONESHOT_MAXTIMERS -# define CONFIG_STM32H7_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -75,7 +75,7 @@ typedef void (*oneshot_handler_t)(void *arg); struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ @@ -193,5 +193,5 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32H7_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h index 43208d091f9..a847ccf74c0 100644 --- a/arch/arm/src/stm32h7/stm32_otg.h +++ b/arch/arm/src/stm32h7/stm32_otg.h @@ -37,21 +37,21 @@ #include "stm32_rcc.h" #include "hardware/stm32_otg.h" -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) #if (STM32_RCC_D2CCIP2R_USBSRC == RCC_D2CCIP2R_USBSEL_HSI48) && \ - !defined(CONFIG_STM32H7_HSI48) + !defined(CONFIG_STM32_HSI48) # error board.h selected HSI48 as USB clock source, but HSI48 is not \ enabled. Enable STM32_HSI48 #endif -#if defined(CONFIG_STM32H7_OTGHS) && !defined(CONFIG_STM32H7_OTGHS_FS) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI) +#if defined(CONFIG_STM32_OTGHS) && !defined(CONFIG_STM32_OTGHS_FS) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI) # error OTG HS selected but no ULPI enabled #endif -#if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) && \ - !defined(CONFIG_STM32H7_SYSCFG_IOCOMPENSATION) +#if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) && \ + !defined(CONFIG_STM32_SYSCFG_IOCOMPENSATION) # error External ULPI needs IOCOMPENSATION enabled #endif @@ -126,7 +126,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller); struct usbdev_s; void stm32_usbsuspend(struct usbdev_s *dev, bool resume); -#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /**************************************************************************** * Name: stm32_usbulpireset * @@ -145,5 +145,5 @@ void stm32_usbulpireset(struct usbdev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32h7/stm32_otgdev.c b/arch/arm/src/stm32h7/stm32_otgdev.c index 22e1774b527..ed564555d03 100644 --- a/arch/arm/src/stm32h7/stm32_otgdev.c +++ b/arch/arm/src/stm32h7/stm32_otgdev.c @@ -53,8 +53,8 @@ #include "stm32_otg.h" #include "arm_internal.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32H7_OTGFS) || \ - defined(CONFIG_STM32H7_OTGHS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || \ + defined(CONFIG_STM32_OTGHS)) /**************************************************************************** * Pre-processor Definitions @@ -62,7 +62,7 @@ /* OTG device selection *****************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_USBDEV) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_OTGFS_BASE # define GPIO_OTG_DM GPIO_OTGFS_DM @@ -70,7 +70,7 @@ # define GPIO_OTG_ID GPIO_OTGFS_ID # define GPIO_OTG_SOF GPIO_OTGFS_SOF # define STM32_OTG_FIFO_SIZE 4096 -#elif defined(CONFIG_STM32H7_OTGHS_USBDEV) +#elif defined(CONFIG_STM32_OTGHS_USBDEV) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_OTGHS_BASE # define GPIO_OTG_DM GPIO_OTGHS_DM @@ -82,7 +82,7 @@ # error Not selected USBDEV peripheral #endif -#if defined(CONFIG_STM32H7_OTGFS_USBDEV) && defined(CONFIG_STM32H7_OTGHS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_USBDEV) && defined(CONFIG_STM32_OTGHS_USBDEV) # error Only one USBDEV role supported #endif @@ -552,7 +552,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else @@ -879,7 +879,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -942,7 +942,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -2138,8 +2138,8 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; #else priv->usbdev.speed = USB_SPEED_FULL; @@ -3447,7 +3447,7 @@ static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_TRDT_MASK; -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= OTG_GUSBCFG_TRDT(9); #else regval |= OTG_GUSBCFG_TRDT(6); @@ -5289,9 +5289,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \ - defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if (defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI)) || \ + defined(CONFIG_STM32_OTGFS_USBDEV) /* Full speed serial transceiver select */ regval = stm32_getreg(STM32_OTG_GUSBCFG); @@ -5299,9 +5299,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTG_GUSBCFG); #endif -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_FS) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_FS) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* ULPI Full speed mode */ regval = stm32_getreg(STM32_OTG_GUSBCFG); @@ -5343,9 +5343,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GCCFG); -#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \ - defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if (defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI)) || \ + defined(CONFIG_STM32_OTGFS_USBDEV) /* Enable USB FS transceiver */ regval |= OTG_GCCFG_PWRDWN; @@ -5360,8 +5360,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTG_GCCFG); up_mdelay(20); -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* Enable delay to default timing, necessary for some ULPI PHYs such * as such as USB334x */ @@ -5404,10 +5404,10 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DSPD_MASK; -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_FS) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_FS) regval |= OTG_DCFG_DSPD_FSHS; -#elif defined(CONFIG_STM32H7_OTGHS_USBDEV) +#elif defined(CONFIG_STM32_OTGHS_USBDEV) regval |= OTG_DCFG_DSPD_HS; #else regval |= OTG_DCFG_DSPD_FS; @@ -5550,8 +5550,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= OTG_GINT_RESERVED; stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS); -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must * be done because if both the ULPI and the FS PHY clock enable bits * are set at the same time, the ARM never awakens from WFI due to @@ -5636,7 +5636,7 @@ void arm_usbinitialize(void) /* Enable USB regulator if configured */ -#ifdef CONFIG_STM32H7_OTG_USBREGEN +#ifdef CONFIG_STM32_OTG_USBREGEN regval |= STM32_PWR_CR3_USBREGEN; #else regval &= ~STM32_PWR_CR3_USBREGEN; @@ -5660,8 +5660,8 @@ void arm_usbinitialize(void) * current detection. */ -#if !(defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI)) +#if !(defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI)) /* Configure OTG alternate function pins */ stm32_configgpio(GPIO_OTG_DM); @@ -5674,7 +5674,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -# ifdef CONFIG_STM32H7_OTG_SOFOUTPUT +# ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); # endif @@ -5866,7 +5866,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) stm32_pullup(&priv->usbdev, true); -#if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; #else priv->usbdev.speed = USB_SPEED_FULL; diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c index 095f2204183..1e34a411832 100644 --- a/arch/arm/src/stm32h7/stm32_otghost.c +++ b/arch/arm/src/stm32h7/stm32_otghost.c @@ -60,7 +60,7 @@ #include "stm32_otg.h" #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H7_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ /* OTG host selection *******************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_OTGFS_BASE # define GPIO_OTG_DM GPIO_OTGFS_DM @@ -89,7 +89,7 @@ # error Not selected USBDEV peripheral #endif -#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_HOST) # error Only one HOST role supported #endif @@ -100,8 +100,8 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32H7_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * @@ -114,16 +114,16 @@ * CONFIG_STM32H7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 * CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32H7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG_FEATURES. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32H7_SYSCFG -# error "CONFIG_STM32H7_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif /* Default RxFIFO size */ @@ -153,8 +153,8 @@ /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ #ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_STM32H7_USBHOST_REGDEBUG -# undef CONFIG_STM32H7_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ @@ -299,7 +299,7 @@ struct stm32_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -312,7 +312,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32H7_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -523,7 +523,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -538,7 +538,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -602,7 +602,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -624,7 +624,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -5414,7 +5414,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* Enable USB regulator if configured */ -#ifdef CONFIG_STM32H7_OTG_USBREGEN +#ifdef CONFIG_STM32_OTG_USBREGEN regval |= STM32_PWR_CR3_USBREGEN; #else regval &= ~STM32_PWR_CR3_USBREGEN; @@ -5458,7 +5458,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32H7_OTG_SOFOUTPUT +#ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5484,4 +5484,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32H7_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32h7/stm32_pulsecount.c b/arch/arm/src/stm32h7/stm32_pulsecount.c index f0a5189aba0..b963fbf02cd 100644 --- a/arch/arm/src/stm32h7/stm32_pulsecount.c +++ b/arch/arm/src/stm32h7/stm32_pulsecount.c @@ -83,7 +83,7 @@ /* Advanced timer support */ -# if defined(CONFIG_STM32H7_TIM1_PULSECOUNT) || defined(CONFIG_STM32H7_TIM8_PULSECOUNT) +# if defined(CONFIG_STM32_TIM1_PULSECOUNT) || defined(CONFIG_STM32_TIM8_PULSECOUNT) # endif /* Synchronisation support */ @@ -191,10 +191,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -221,107 +221,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32H7_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32H7_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -332,7 +332,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -340,7 +340,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1332,21 +1332,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32H7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32H7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1419,7 +1419,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1428,7 +1428,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1611,7 +1611,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCRST_TIM1; @@ -1620,7 +1620,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCRST_TIM8; @@ -1782,7 +1782,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1792,7 +1792,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index d2dc3b4f06e..103b8d72785 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -49,7 +49,7 @@ * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ */ -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM /**************************************************************************** * Pre-processor Definitions @@ -171,7 +171,7 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32H7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif @@ -243,7 +243,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -316,10 +316,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_sync_configure(struct stm32_pwmtimer_s *priv, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -356,7 +356,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -379,16 +379,16 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -403,114 +403,114 @@ static struct stm32_pwmchan_s g_pwm1channels[] = #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH1POL, - .idle = CONFIG_STM32H7_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH1NPOL, - .idle = CONFIG_STM32H7_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM1_CH2MODE, -#ifdef CONFIG_STM32H7_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH2POL, - .idle = CONFIG_STM32H7_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH2NPOL, - .idle = CONFIG_STM32H7_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM1_CH3MODE, -#ifdef CONFIG_STM32H7_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH3POL, - .idle = CONFIG_STM32H7_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH3NPOL, - .idle = CONFIG_STM32H7_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM1_CH4MODE, -#ifdef CONFIG_STM32H7_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH4POL, - .idle = CONFIG_STM32H7_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H7_TIM1_CH5MODE, -#ifdef CONFIG_STM32H7_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH5POL, - .idle = CONFIG_STM32H7_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H7_TIM1_CH6MODE, -#ifdef CONFIG_STM32H7_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH6POL, - .idle = CONFIG_STM32H7_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -521,18 +521,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32H7_TIM1_MODE, - .lock = CONFIG_STM32H7_TIM1_LOCK, - .t_dts = CONFIG_STM32H7_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -540,72 +540,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H7_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM2_CH1MODE, -#ifdef CONFIG_STM32H7_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH1POL, - .idle = CONFIG_STM32H7_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM2_CH2MODE, -#ifdef CONFIG_STM32H7_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH2POL, - .idle = CONFIG_STM32H7_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM2_CH3MODE, -#ifdef CONFIG_STM32H7_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH3POL, - .idle = CONFIG_STM32H7_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM2_CH4MODE, -#ifdef CONFIG_STM32H7_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH4POL, - .idle = CONFIG_STM32H7_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -617,14 +617,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32H7_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -636,72 +636,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32H7_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM3_CH1MODE, -#ifdef CONFIG_STM32H7_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH1POL, - .idle = CONFIG_STM32H7_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM3_CH2MODE, -#ifdef CONFIG_STM32H7_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH2POL, - .idle = CONFIG_STM32H7_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM3_CH3MODE, -#ifdef CONFIG_STM32H7_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH3POL, - .idle = CONFIG_STM32H7_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM3_CH4MODE, -#ifdef CONFIG_STM32H7_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH4POL, - .idle = CONFIG_STM32H7_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -713,14 +713,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32H7_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -732,72 +732,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32H7_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM4_CH1MODE, -#ifdef CONFIG_STM32H7_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH1POL, - .idle = CONFIG_STM32H7_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM4_CH2MODE, -#ifdef CONFIG_STM32H7_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH2POL, - .idle = CONFIG_STM32H7_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM4_CH3MODE, -#ifdef CONFIG_STM32H7_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH3POL, - .idle = CONFIG_STM32H7_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM4_CH4MODE, -#ifdef CONFIG_STM32H7_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH4POL, - .idle = CONFIG_STM32H7_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -809,14 +809,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32H7_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -828,71 +828,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32H7_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM5_CH1MODE, -#ifdef CONFIG_STM32H7_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH1POL, - .idle = CONFIG_STM32H7_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM5_CH2MODE, -#ifdef CONFIG_STM32H7_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH2POL, - .idle = CONFIG_STM32H7_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM5_CH3MODE, -#ifdef CONFIG_STM32H7_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH3POL, - .idle = CONFIG_STM32H7_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM5_CH4MODE, -#ifdef CONFIG_STM32H7_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH4POL, - .idle = CONFIG_STM32H7_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -903,14 +903,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32H7_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -922,18 +922,18 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32H7_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -948,114 +948,114 @@ static struct stm32_pwmchan_s g_pwm8channels[] = #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH1POL, - .idle = CONFIG_STM32H7_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH1NPOL, - .idle = CONFIG_STM32H7_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM8_CH2MODE, -#ifdef CONFIG_STM32H7_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH2POL, - .idle = CONFIG_STM32H7_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH2NPOL, - .idle = CONFIG_STM32H7_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM8_CH3MODE, -#ifdef CONFIG_STM32H7_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH3POL, - .idle = CONFIG_STM32H7_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH3NPOL, - .idle = CONFIG_STM32H7_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM8_CH4MODE, -#ifdef CONFIG_STM32H7_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH4POL, - .idle = CONFIG_STM32H7_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H7_TIM8_CH5MODE, -#ifdef CONFIG_STM32H7_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH5POL, - .idle = CONFIG_STM32H7_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H7_TIM8_CH6MODE, -#ifdef CONFIG_STM32H7_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH6POL, - .idle = CONFIG_STM32H7_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1066,18 +1066,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32H7_TIM8_MODE, - .lock = CONFIG_STM32H7_TIM8_LOCK, - .t_dts = CONFIG_STM32H7_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1085,40 +1085,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H7_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM12_CH1MODE, -#ifdef CONFIG_STM32H7_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM12_CH1POL, - .idle = CONFIG_STM32H7_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM12_CH2MODE, -#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM12_CH2POL, - .idle = CONFIG_STM32H7_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1130,7 +1130,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1149,24 +1149,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32H7_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM13_CH1MODE, -#ifdef CONFIG_STM32H7_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM13_CH1POL, - .idle = CONFIG_STM32H7_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1178,7 +1178,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1197,24 +1197,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32H7_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM14_CH1MODE, -#ifdef CONFIG_STM32H7_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM14_CH1POL, - .idle = CONFIG_STM32H7_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1226,7 +1226,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1245,18 +1245,18 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32H7_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1267,36 +1267,36 @@ static struct stm32_pwmchan_s g_pwm15channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH1POL, - .idle = CONFIG_STM32H7_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH1NPOL, - .idle = CONFIG_STM32H7_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM15_CH2MODE, -#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH2POL, - .idle = CONFIG_STM32H7_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1308,7 +1308,7 @@ static struct stm32_pwmchan_s g_pwm15channels[] = static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, @@ -1316,10 +1316,10 @@ static struct stm32_pwmtimer_s g_pwm15dev = .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM15_LOCK, - .t_dts = CONFIG_STM32H7_TIM15_TDTS, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) .trgo = STM32_TIM15_TRGO, @@ -1327,18 +1327,18 @@ static struct stm32_pwmtimer_s g_pwm15dev = .base = STM32_TIM15_BASE, .pclk = TIMCLK_TIM15, }; -#endif /* CONFIG_STM32H7_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1349,16 +1349,16 @@ static struct stm32_pwmchan_s g_pwm16channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM16_CH1POL, - .idle = CONFIG_STM32H7_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, @@ -1374,7 +1374,7 @@ static struct stm32_pwmchan_s g_pwm16channels[] = static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, @@ -1382,10 +1382,10 @@ static struct stm32_pwmtimer_s g_pwm16dev = .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM16_LOCK, - .t_dts = CONFIG_STM32H7_TIM16_TDTS, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ @@ -1393,18 +1393,18 @@ static struct stm32_pwmtimer_s g_pwm16dev = .base = STM32_TIM16_BASE, .pclk = TIMCLK_TIM16, }; -#endif /* CONFIG_STM32H7_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1415,16 +1415,16 @@ static struct stm32_pwmchan_s g_pwm17channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM17_CH1POL, - .idle = CONFIG_STM32H7_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, @@ -1440,7 +1440,7 @@ static struct stm32_pwmchan_s g_pwm17channels[] = static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, @@ -1448,10 +1448,10 @@ static struct stm32_pwmtimer_s g_pwm17dev = .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM17_LOCK, - .t_dts = CONFIG_STM32H7_TIM17_TDTS, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ @@ -1459,7 +1459,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .base = STM32_TIM17_BASE, .pclk = TIMCLK_TIM17, }; -#endif /* CONFIG_STM32H7_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ /* TODO: support for TIM19,20,21,22 */ @@ -1796,7 +1796,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1853,7 +1853,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32H7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -2581,7 +2581,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3134,7 +3134,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3143,7 +3143,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3152,7 +3152,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3161,7 +3161,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3170,7 +3170,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3179,7 +3179,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3188,7 +3188,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3197,7 +3197,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3206,7 +3206,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3215,7 +3215,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCEN_TIM15; @@ -3224,7 +3224,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCEN_TIM16; @@ -3233,7 +3233,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCEN_TIM17; @@ -3531,7 +3531,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCRST_TIM1; @@ -3540,7 +3540,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCRST_TIM2; @@ -3549,7 +3549,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCRST_TIM3; @@ -3558,7 +3558,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCRST_TIM4; @@ -3567,7 +3567,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCRST_TIM5; @@ -3576,7 +3576,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCRST_TIM8; @@ -3585,7 +3585,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCRST_TIM12; @@ -3594,7 +3594,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCRST_TIM13; @@ -3603,7 +3603,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCRST_TIM14; @@ -3612,7 +3612,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCRST_TIM15; @@ -3621,7 +3621,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCRST_TIM16; @@ -3630,7 +3630,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCRST_TIM17; @@ -3747,7 +3747,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3758,7 +3758,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3766,7 +3766,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3774,7 +3774,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3782,7 +3782,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3790,7 +3790,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3801,7 +3801,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3809,7 +3809,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3817,7 +3817,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3825,7 +3825,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { lower = &g_pwm15dev; @@ -3833,7 +3833,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { lower = &g_pwm16dev; @@ -3841,7 +3841,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { lower = &g_pwm17dev; @@ -3861,4 +3861,4 @@ errout: return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32H7_PWM */ +#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/stm32h7/stm32_pwm.h b/arch/arm/src/stm32h7/stm32_pwm.h index bc6002af3bf..8cb724fca02 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.h +++ b/arch/arm/src/stm32h7/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -57,41 +57,41 @@ * pulsed output signal generation. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32H7_TIM5 -# undef CONFIG_STM32H7_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32H7_TIM12 -# undef CONFIG_STM32H7_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32H7_TIM13 -# undef CONFIG_STM32H7_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32H7_TIM14 -# undef CONFIG_STM32H7_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif -#ifndef CONFIG_STM32H7_TIM15 -# undef CONFIG_STM32H7_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32H7_TIM16 -# undef CONFIG_STM32H7_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32H7_TIM17 -# undef CONFIG_STM32H7_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output @@ -103,38 +103,38 @@ /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32H7_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,59 +269,59 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 # define PWM_TIM15_CHANNEL1 1 #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 # define PWM_TIM15_CHANNEL2 1 #else # define PWM_TIM15_CHANNEL2 0 #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 # define PWM_TIM16_CHANNEL1 1 #else # define PWM_TIM16_CHANNEL1 0 #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 # define PWM_TIM17_CHANNEL1 1 #else # define PWM_TIM17_CHANNEL1 0 #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_STM32H7_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: @@ -338,425 +338,425 @@ * is not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32H7_TIM1_PWM -# if !defined(CONFIG_STM32H7_TIM1_CHANNEL) -# error "CONFIG_STM32H7_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM1_CHANNEL == 1 -# define CONFIG_STM32H7_TIM1_CHANNEL1 1 -# define CONFIG_STM32H7_TIM1_CH1MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 2 -# define CONFIG_STM32H7_TIM1_CHANNEL2 1 -# define CONFIG_STM32H7_TIM1_CH2MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 3 -# define CONFIG_STM32H7_TIM1_CHANNEL3 1 -# define CONFIG_STM32H7_TIM1_CH3MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 4 -# define CONFIG_STM32H7_TIM1_CHANNEL4 1 -# define CONFIG_STM32H7_TIM1_CH4MODE CONFIG_STM32H7_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM2_PWM -# if !defined(CONFIG_STM32H7_TIM2_CHANNEL) -# error "CONFIG_STM32H7_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM2_CHANNEL == 1 -# define CONFIG_STM32H7_TIM2_CHANNEL1 1 -# define CONFIG_STM32H7_TIM2_CH1MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 2 -# define CONFIG_STM32H7_TIM2_CHANNEL2 1 -# define CONFIG_STM32H7_TIM2_CH2MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 3 -# define CONFIG_STM32H7_TIM2_CHANNEL3 1 -# define CONFIG_STM32H7_TIM2_CH3MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 4 -# define CONFIG_STM32H7_TIM2_CHANNEL4 1 -# define CONFIG_STM32H7_TIM2_CH4MODE CONFIG_STM32H7_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM3_PWM -# if !defined(CONFIG_STM32H7_TIM3_CHANNEL) -# error "CONFIG_STM32H7_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM3_CHANNEL == 1 -# define CONFIG_STM32H7_TIM3_CHANNEL1 1 -# define CONFIG_STM32H7_TIM3_CH1MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 2 -# define CONFIG_STM32H7_TIM3_CHANNEL2 1 -# define CONFIG_STM32H7_TIM3_CH2MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 3 -# define CONFIG_STM32H7_TIM3_CHANNEL3 1 -# define CONFIG_STM32H7_TIM3_CH3MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 4 -# define CONFIG_STM32H7_TIM3_CHANNEL4 1 -# define CONFIG_STM32H7_TIM3_CH4MODE CONFIG_STM32H7_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM4_PWM -# if !defined(CONFIG_STM32H7_TIM4_CHANNEL) -# error "CONFIG_STM32H7_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM4_CHANNEL == 1 -# define CONFIG_STM32H7_TIM4_CHANNEL1 1 -# define CONFIG_STM32H7_TIM4_CH1MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 2 -# define CONFIG_STM32H7_TIM4_CHANNEL2 1 -# define CONFIG_STM32H7_TIM4_CH2MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 3 -# define CONFIG_STM32H7_TIM4_CHANNEL3 1 -# define CONFIG_STM32H7_TIM4_CH3MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 4 -# define CONFIG_STM32H7_TIM4_CHANNEL4 1 -# define CONFIG_STM32H7_TIM4_CH4MODE CONFIG_STM32H7_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM5_PWM -# if !defined(CONFIG_STM32H7_TIM5_CHANNEL) -# error "CONFIG_STM32H7_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM5_CHANNEL == 1 -# define CONFIG_STM32H7_TIM5_CHANNEL1 1 -# define CONFIG_STM32H7_TIM5_CH1MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 2 -# define CONFIG_STM32H7_TIM5_CHANNEL2 1 -# define CONFIG_STM32H7_TIM5_CH2MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 3 -# define CONFIG_STM32H7_TIM5_CHANNEL3 1 -# define CONFIG_STM32H7_TIM5_CH3MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 4 -# define CONFIG_STM32H7_TIM5_CHANNEL4 1 -# define CONFIG_STM32H7_TIM5_CH4MODE CONFIG_STM32H7_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM8_PWM -# if !defined(CONFIG_STM32H7_TIM8_CHANNEL) -# error "CONFIG_STM32H7_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM8_CHANNEL == 1 -# define CONFIG_STM32H7_TIM8_CHANNEL1 1 -# define CONFIG_STM32H7_TIM8_CH1MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 2 -# define CONFIG_STM32H7_TIM8_CHANNEL2 1 -# define CONFIG_STM32H7_TIM8_CH2MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 3 -# define CONFIG_STM32H7_TIM8_CHANNEL3 1 -# define CONFIG_STM32H7_TIM8_CH3MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 4 -# define CONFIG_STM32H7_TIM8_CHANNEL4 1 -# define CONFIG_STM32H7_TIM8_CH4MODE CONFIG_STM32H7_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM12_PWM -# if !defined(CONFIG_STM32H7_TIM12_CHANNEL) -# error "CONFIG_STM32H7_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM12_CHANNEL == 1 -# define CONFIG_STM32H7_TIM12_CHANNEL1 1 -# define CONFIG_STM32H7_TIM12_CH1MODE CONFIG_STM32H7_TIM12_CHMODE -# elif CONFIG_STM32H7_TIM12_CHANNEL == 2 -# define CONFIG_STM32H7_TIM12_CHANNEL2 1 -# define CONFIG_STM32H7_TIM12_CH2MODE CONFIG_STM32H7_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM13_PWM -# if !defined(CONFIG_STM32H7_TIM13_CHANNEL) -# error "CONFIG_STM32H7_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM13_CHANNEL == 1 -# define CONFIG_STM32H7_TIM13_CHANNEL1 1 -# define CONFIG_STM32H7_TIM13_CH1MODE CONFIG_STM32H7_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM14_PWM -# if !defined(CONFIG_STM32H7_TIM14_CHANNEL) -# error "CONFIG_STM32H7_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM14_CHANNEL == 1 -# define CONFIG_STM32H7_TIM14_CHANNEL1 1 -# define CONFIG_STM32H7_TIM14_CH1MODE CONFIG_STM32H7_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM15_PWM -# if !defined(CONFIG_STM32H7_TIM15_CHANNEL) -# error "CONFIG_STM32H7_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM15_CHANNEL == 1 -# define CONFIG_STM32H7_TIM15_CHANNEL1 1 -# define CONFIG_STM32H7_TIM15_CH1MODE CONFIG_STM32H7_TIM15_CHMODE -# elif CONFIG_STM32H7_TIM15_CHANNEL == 2 -# define CONFIG_STM32H7_TIM15_CHANNEL2 1 -# define CONFIG_STM32H7_TIM15_CH2MODE CONFIG_STM32H7_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM16_PWM -# if !defined(CONFIG_STM32H7_TIM16_CHANNEL) -# error "CONFIG_STM32H7_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM16_CHANNEL == 1 -# define CONFIG_STM32H7_TIM16_CHANNEL1 1 -# define CONFIG_STM32H7_TIM16_CH1MODE CONFIG_STM32H7_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM17_PWM -# if !defined(CONFIG_STM32H7_TIM17_CHANNEL) -# error "CONFIG_STM32H7_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM17_CHANNEL == 1 -# define CONFIG_STM32H7_TIM17_CHANNEL1 1 -# define CONFIG_STM32H7_TIM17_CH1MODE CONFIG_STM32H7_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#endif /* CONFIG_STM32H7_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32H7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT #else # define PWM_TIM15_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT #else # define PWM_TIM15_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT #else # define PWM_TIM15_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT #else # define PWM_TIM16_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT #else # define PWM_TIM16_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT #else # define PWM_TIM17_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT #else # define PWM_TIM17_CH1NCFG 0 @@ -764,21 +764,21 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32H7_TIM1_CH1NOUT) || defined(CONFIG_STM32H7_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32H7_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM8_CH1NOUT) || defined(CONFIG_STM32H7_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32H7_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -789,7 +789,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -925,7 +925,7 @@ enum stm32_pwm_output_e #endif }; -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -1011,7 +1011,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32H7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1057,5 +1057,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_PWM_H */ diff --git a/arch/arm/src/stm32h7/stm32_pwr.c b/arch/arm/src/stm32h7/stm32_pwr.c index c1d97009676..287ca4b42ea 100644 --- a/arch/arm/src/stm32h7/stm32_pwr.c +++ b/arch/arm/src/stm32h7/stm32_pwr.c @@ -37,7 +37,7 @@ #include "stm32_pwr.h" #include "stm32_gpio.h" -#if defined(CONFIG_STM32H7_PWR) +#if defined(CONFIG_STM32_PWR) #define BREG_WAIT_USTIMEOUT 1000 /* uS to wait for regulator to come ready */ diff --git a/arch/arm/src/stm32h7/stm32_qencoder.c b/arch/arm/src/stm32h7/stm32_qencoder.c index 406ec36796b..d3d29deb35c 100644 --- a/arch/arm/src/stm32h7/stm32_qencoder.c +++ b/arch/arm/src/stm32h7/stm32_qencoder.c @@ -60,14 +60,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32H7_TIM2_QE) || defined(CONFIG_STM32H7_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM3_QE) || \ - defined(CONFIG_STM32H7_TIM4_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -89,51 +89,51 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32H7_QENCODER_FILTER -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_1) +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_2) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_4) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif @@ -276,7 +276,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -287,7 +287,7 @@ static const struct stm32_qeconfig_s g_tim1config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM1EN, .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32H7_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -302,7 +302,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -313,7 +313,7 @@ static const struct stm32_qeconfig_s g_tim2config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM2EN, .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32H7_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -328,7 +328,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -339,7 +339,7 @@ static const struct stm32_qeconfig_s g_tim3config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM3EN, .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32H7_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -354,7 +354,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -365,7 +365,7 @@ static const struct stm32_qeconfig_s g_tim4config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM4EN, .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32H7_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -380,7 +380,7 @@ static struct stm32_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, @@ -391,7 +391,7 @@ static const struct stm32_qeconfig_s g_tim5config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM5EN, .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32H7_TIM5_QEPSC, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -406,7 +406,7 @@ static struct stm32_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, @@ -417,7 +417,7 @@ static const struct stm32_qeconfig_s g_tim8config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM8EN, .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32H7_TIM8_QEPSC, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -562,7 +562,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -593,27 +593,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -733,7 +733,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -944,37 +944,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; diff --git a/arch/arm/src/stm32h7/stm32_qencoder.h b/arch/arm/src/stm32h7/stm32_qencoder.h index a8b93505d59..0af33dc2c71 100644 --- a/arch/arm/src/stm32h7/stm32_qencoder.h +++ b/arch/arm/src/stm32h7/stm32_qencoder.h @@ -43,23 +43,23 @@ * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32H7_TIM5 -# undef CONFIG_STM32H7_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index c6f72058489..f09d07c0d57 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -57,7 +57,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32H7_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32H7_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -81,7 +81,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) && defined(CONFIG_STM32H7_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -93,7 +93,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -105,26 +105,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32H7_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32H7_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32H7_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32H7_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -189,14 +189,14 @@ struct stm32h7_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -206,11 +206,11 @@ struct stm32h7_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32H7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32h7_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -247,7 +247,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -260,7 +260,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32h7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -287,16 +287,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32H7_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32h7_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32h7_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32h7_qspidev_s *priv); @@ -306,8 +306,8 @@ static void qspi_dma_sampledone(struct stm32h7_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32H7_QSPI_DMATHRESHOLD -# define CONFIG_STM32H7_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -361,13 +361,13 @@ static struct stm32h7_qspidev_s g_qspi0dev = }, .base = STM32_QUADSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -393,7 +393,7 @@ static struct stm32h7_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32h7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -445,7 +445,7 @@ static inline uint32_t qspi_getreg(struct stm32h7_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -468,7 +468,7 @@ static inline void qspi_putreg(struct stm32h7_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -649,7 +649,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32H7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -867,7 +867,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1010,7 +1010,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1135,7 +1135,7 @@ static void qspi_ccrconfig(struct stm32h7_qspidev_s *priv, } } -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1358,7 +1358,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32H7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1631,7 +1631,7 @@ static int qspi_memory_dma(struct stm32h7_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2065,7 +2065,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2246,7 +2246,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2307,11 +2307,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32H7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32H7_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2473,18 +2473,18 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_FSEL | QSPI_CR_DFM); -#if defined(CONFIG_STM32H7_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_FSEL; #endif -#if defined(CONFIG_STM32H7_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DFM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32H7_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2505,10 +2505,10 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32H7_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32H7_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32H7_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2618,7 +2618,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2632,7 +2632,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2658,7 +2658,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2666,12 +2666,12 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2737,7 +2737,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2756,7 +2756,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2802,4 +2802,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32H7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32h7/stm32_qspi.h b/arch/arm/src/stm32h7/stm32_qspi.h index dd2c257584c..096b3cdf257 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.h +++ b/arch/arm/src/stm32h7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H7_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -127,5 +127,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.c b/arch/arm/src/stm32h7/stm32_rcc.c index 668be18c4dd..dcb7abdbe98 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.c +++ b/arch/arm/src/stm32h7/stm32_rcc.c @@ -59,15 +59,15 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h7x7xx_rcc.c" #else # error "Unsupported STM32 H7 chip" @@ -86,9 +86,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -100,19 +100,19 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, void stm32_clockconfig(void) { -#ifndef CONFIG_STM32H7_BYPASS_CLOCKCONFIG +#ifndef CONFIG_STM32_BYPASS_CLOCKCONFIG /* Make sure that we are starting in the reset state */ rcc_reset(); -# if defined(CONFIG_STM32H7_PWR) +# if defined(CONFIG_STM32_PWR) /* Insure the bkp is initialized */ stm32_pwr_initbkp(false); # endif -# if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG) +# if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -127,13 +127,13 @@ void stm32_clockconfig(void) stm32_stdclockconfig(); # endif -#endif /* !CONFIG_STM32H7_BYPASS_CLOCKCONFIG */ +#endif /* !CONFIG_STM32_BYPASS_CLOCKCONFIG */ /* Enable peripheral clocking */ rcc_enableperipherals(); -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION /* Enable I/O Compensation */ stm32_iocompensation(); @@ -153,9 +153,9 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -168,7 +168,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.h b/arch/arm/src/stm32h7/stm32_rcc.h index 786bb7064db..8dfaf0eb654 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.h +++ b/arch/arm/src/stm32h7/stm32_rcc.h @@ -124,9 +124,9 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -157,7 +157,7 @@ void stm32_stdclockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -174,9 +174,9 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None diff --git a/arch/arm/src/stm32h7/stm32_rng.c b/arch/arm/src/stm32h7/stm32_rng.c index 0e6e67df1c5..df53d7f7343 100644 --- a/arch/arm/src/stm32h7/stm32_rng.c +++ b/arch/arm/src/stm32h7/stm32_rng.c @@ -41,7 +41,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32H7_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -311,4 +311,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32H7_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32h7/stm32_rptun.c b/arch/arm/src/stm32h7/stm32_rptun.c index 648af00143d..c46354c4569 100644 --- a/arch/arm/src/stm32h7/stm32_rptun.c +++ b/arch/arm/src/stm32h7/stm32_rptun.c @@ -60,7 +60,7 @@ #define VRING_NR (8) /* Number of descriptors */ #define VRING_SIZE (512) /* Size of one descriptor */ -#ifdef CONFIG_STM32H7_SHMEM_SRAM3 +#ifdef CONFIG_STM32_SHMEM_SRAM3 /* Use 32kB of the SRAM3 as a shared memory */ # define VRING_SHMEM STM32_SRAM3_BASE diff --git a/arch/arm/src/stm32h7/stm32_rtc.c b/arch/arm/src/stm32h7/stm32_rtc.c index ed25043062d..4bfbe237a91 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.c +++ b/arch/arm/src/stm32h7/stm32_rtc.c @@ -44,7 +44,7 @@ #include -#ifdef CONFIG_STM32H7_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32H7_PWR -# error "CONFIG_STM32H7_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ -#if defined(CONFIG_STM32H7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE #else # warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count" @@ -491,7 +491,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* STMicro app note AN4759 suggests using 7999 and 124 to * get exactly 1MHz when using the RTC at 8MHz. */ @@ -940,17 +940,17 @@ int up_rtc_initialize(void) * external high rate clock */ -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ rtc_dumpregs("On reset HSE"); -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ rtc_dumpregs("On reset LSI"); -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ rtc_dumpregs("On reset LSE"); @@ -1102,7 +1102,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) #else int up_rtc_getdatetime(struct tm *tp) @@ -1111,7 +1111,7 @@ int up_rtc_getdatetime(struct tm *tp) uint32_t dr; uint32_t tr; uint32_t tmp; -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; uint32_t prediv_s; uint32_t usecs; @@ -1129,7 +1129,7 @@ int up_rtc_getdatetime(struct tm *tp) { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1186,7 +1186,7 @@ int up_rtc_getdatetime(struct tm *tp) clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900)); tp->tm_isdst = 0; -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS /* Return RTC sub-seconds if a non-NULL value * of nsec has been provided to receive the sub-second value. */ @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime(struct tm *tp) } rtc_dumptime((const struct tm *)tp, &usecs, "Returning"); -#else /* CONFIG_STM32H7_HAVE_RTC_SUBSECONDS */ +#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ rtc_dumptime((const struct tm *)tp, NULL, "Returning"); #endif @@ -1237,7 +1237,7 @@ int up_rtc_getdatetime(struct tm *tp) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int up_rtc_getdatetime(struct tm *tp) { return stm32_rtc_getdatetime_with_subseconds(tp, NULL); @@ -1270,8 +1270,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32H7_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1775,11 +1775,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32H7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1950,4 +1950,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32H7_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32h7/stm32_rtc.h b/arch/arm/src/stm32h7/stm32_rtc.h index e3b3f69096c..82290558797 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.h +++ b/arch/arm/src/stm32h7/stm32_rtc.h @@ -46,21 +46,21 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32H7_RTC_MAGIC) -# define CONFIG_STM32H7_RTC_MAGIC (0xfacefeed) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) #endif -#if !defined(CONFIG_STM32H7_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32H7_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32H7_RTC_MAGIC_REG) -# define CONFIG_STM32H7_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32H7_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32H7_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32H7_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -106,7 +106,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index cfddcb3be49..2aca3035cd2 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "stm32_sdmmc.h" -#if defined(CONFIG_STM32H7_SDMMC1) || defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -101,14 +101,14 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32H7_SDMMC_IDMA - Enable SDMMC IDMA. + * CONFIG_STM32_SDMMC_IDMA - Enable SDMMC IDMA. * DMA support for SDMMC. If disabled, the SDMMC will work in * interrupt mode and still use the IDMA to a local buffer for data * lengths less the 32 bytes due to the FIFO limitations. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). - * CONFIG_STM32H7_SDMMC_XFRDEBUG - Enables some very low-level debug + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level debug * output This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO * CONFIG_SDMMC1/2_SDIO_MODE * Build ins additional support needed only for SDIO cards (vs. SD memory @@ -125,15 +125,15 @@ * hence, if only SDMMC2 is defined it will be slot 0. */ -#if !defined(CONFIG_STM32H7_SDMMC1) +#if !defined(CONFIG_STM32_SDMMC1) # define SDMMC2_SLOT 0 #else # define SDMMC2_SLOT 1 #endif -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) # warning "Large Non-DMA transfer may result in RX overrun failures" -#elif defined(CONFIG_STM32H7_SDMMC1) +#elif defined(CONFIG_STM32_SDMMC1) # define SRAM123_START STM32_SRAM123_BASE # define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) # define SRAM4_START STM32_SRAM4_BASE @@ -150,7 +150,7 @@ #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32H7_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif #ifdef CONFIG_SDMMC1_SDIO_PULLUP @@ -316,7 +316,7 @@ /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_AFTER_SETUP 1 # define SAMPLENDX_END_TRANSFER 2 @@ -381,7 +381,7 @@ struct stm32_dev_s uint32_t blocksize; /* Current block size */ uint32_t receivecnt; /* Real count to receive */ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) struct work_s cbfifo; /* Monitor for Lame FIFO */ #endif uint8_t rxfifo[FIFO_SIZE_IN_BYTES] /* To offload with IDMA and support un-alinged buffers */ @@ -389,7 +389,7 @@ struct stm32_dev_s bool unaligned_rx; /* read buffer is not cache-line or 32 bit aligned */ /* Input dma buffer for unaligned transfers */ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) uint8_t sdmmc_rxbuffer[SDMMC_MAX_BLOCK_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); #endif @@ -397,7 +397,7 @@ struct stm32_dev_s /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) struct stm32_sdioregs_s { uint8_t power; @@ -434,7 +434,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* Debug Helpers ************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -456,7 +456,7 @@ static uint8_t stm32_log2(uint16_t value); static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, uint32_t dlen, bool receive); static void stm32_datadisable(struct stm32_dev_s *priv); -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static void stm32_sendfifo(struct stm32_dev_s *priv); static void stm32_recvfifo(struct stm32_dev_s *priv); #else @@ -499,7 +499,7 @@ static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg); static void stm32_blocksetup(struct sdio_dev_s *dev, unsigned int blocksize, unsigned int nblocks); -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t nbytes); static int stm32_sendsetup(struct sdio_dev_s *dev, @@ -527,7 +527,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -546,7 +546,7 @@ static void stm32_default(struct stm32_dev_s *priv); /**************************************************************************** * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -562,7 +562,7 @@ struct stm32_dev_s g_sdmmcdev1 = .attach = stm32_attach, .sendcmd = stm32_sendcmd, .blocksetup = stm32_blocksetup, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) .recvsetup = stm32_dmarecvsetup, .sendsetup = stm32_dmasendsetup, #else @@ -582,7 +582,7 @@ struct stm32_dev_s g_sdmmcdev1 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) .dmapreflight = stm32_dmapreflight, # endif @@ -601,7 +601,7 @@ struct stm32_dev_s g_sdmmcdev1 = #endif }; #endif -#if defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC2) struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -617,7 +617,7 @@ struct stm32_dev_s g_sdmmcdev2 = .attach = stm32_attach, .sendcmd = stm32_sendcmd, .blocksetup = stm32_blocksetup, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) .recvsetup = stm32_dmarecvsetup, .sendsetup = stm32_dmasendsetup, #else @@ -637,7 +637,7 @@ struct stm32_dev_s g_sdmmcdev2 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) .dmapreflight = stm32_dmapreflight, # endif @@ -658,7 +658,7 @@ struct stm32_dev_s g_sdmmcdev2 = #endif /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -899,7 +899,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * @@ -915,7 +915,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -938,7 +938,7 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; @@ -954,7 +954,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -985,7 +985,7 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) @@ -1002,7 +1002,7 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], @@ -1104,7 +1104,7 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, { DEBUGASSERT((dlen % priv->blocksize) == 0); -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) /* If this is an unaligned receive, then receive one block at a * time to the internal buffer */ @@ -1202,7 +1202,7 @@ static void stm32_datadisable(struct stm32_dev_s *priv) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_sendfifo(struct stm32_dev_s *priv) { union @@ -1267,7 +1267,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_recvfifo(struct stm32_dev_s *priv) { union @@ -1328,7 +1328,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined (CONFIG_STM32H7_SDMMC_IDMA) +#if defined (CONFIG_STM32_SDMMC_IDMA) static void stm32_recvdma(struct stm32_dev_s *priv) { uint32_t dctrl; @@ -1547,7 +1547,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_sdmmc_fifo_monitor(void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1643,7 +1643,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA /* Is the RX FIFO half full or more? Is so then we must be * processing a receive transaction. */ @@ -1689,7 +1689,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) * half-full interrupt will be received. */ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA /* If the transfer would not trigger fifo half full * we used IDMA to manage the lame fifo @@ -1909,7 +1909,7 @@ static void stm32_reset(struct sdio_dev_s *dev) flags = enter_critical_section(); -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (priv->base == STM32_SDMMC1_BASE) { regaddress = STM32_RCC_AHB3RSTR; @@ -1917,7 +1917,7 @@ static void stm32_reset(struct sdio_dev_s *dev) } #endif -#if defined CONFIG_STM32H7_SDMMC2 +#if defined CONFIG_STM32_SDMMC2 if (priv->base == STM32_SDMMC2_BASE) { regaddress = STM32_RCC_AHB2RSTR; @@ -1998,7 +1998,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_DMABEFOREWRITE; -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2305,7 +2305,7 @@ static void stm32_blocksetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t nbytes) { @@ -2381,7 +2381,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, * ****************************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_sendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t nbytes) { @@ -3065,7 +3065,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_IDMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3074,7 +3074,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, /* IDMA must be possible to the buffer */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (priv->base == STM32_SDMMC1_BASE) { /* For SDMMC1, IDMA cannot access SRAM123 or SRAM4. */ @@ -3134,7 +3134,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -3239,7 +3239,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3423,7 +3423,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (slotno == 0) { /* Select SDMMC 1 */ @@ -3456,7 +3456,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#if defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC2) if (slotno == SDMMC2_SLOT) { /* Select SDMMC 2 */ @@ -3629,4 +3629,4 @@ void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, } #endif -#endif /* CONFIG_STM32H7_SDMMC1 || CONFIG_STM32H7_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index e7442fe452c..cf668117e80 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -81,11 +81,11 @@ # if !defined(DMAMAP_USART1_RX) # error "USART1 DMA map not defined (DMAMAP_USART1_RX)" # endif -# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -93,11 +93,11 @@ # if !defined(DMAMAP_USART2_RX) # error "USART2 DMA map not defined (DMAMAP_USART2_RX)" # endif -# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -105,11 +105,11 @@ # if !defined(DMAMAP_USART3_RX) # error "USART3 DMA map not defined (DMAMAP_USART3_RX)" # endif -# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -117,11 +117,11 @@ # if !defined(DMAMAP_UART4_RX) # error "UART4 DMA map not defined (DMAMAP_UART4_RX)" # endif -# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -129,11 +129,11 @@ # if !defined(DMAMAP_UART5_RX) # error "UART5 DMA map not defined (DMAMAP_UART5_RX)" # endif -# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -141,11 +141,11 @@ # if !defined(DMAMAP_USART6_RX) # error "USART6 DMA map not defined (DMAMAP_USART6_RX)" # endif -# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -153,11 +153,11 @@ # if !defined(DMAMAP_UART7_RX) # error "UART7 DMA map not defined (DMAMAP_UART7_RX)" # endif -# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -165,11 +165,11 @@ # if !defined(DMAMAP_UART8_RX) # error "UART8 DMA map not defined (DMAMAP_UART8_RX)" # endif -# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -205,14 +205,14 @@ # define ARMV7M_DCACHE_LINESIZE 32 # endif -# if !defined(CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE) || \ - (CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) -# undef CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE -# define CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE # endif # define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \ +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* DMA priority */ @@ -247,11 +247,11 @@ # if !defined(DMAMAP_USART1_TX) # error "USART1 DMA map not defined (DMAMAP_USART1_TX)" # endif -# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -259,11 +259,11 @@ # if !defined(DMAMAP_USART2_TX) # error "USART2 DMA map not defined (DMAMAP_USART2_TX)" # endif -# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -271,11 +271,11 @@ # if !defined(DMAMAP_USART3_TX) # error "USART3 DMA map not defined (DMAMAP_USART3_TX)" # endif -# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -283,11 +283,11 @@ # if !defined(DMAMAP_UART4_TX) # error "UART4 DMA map not defined (DMAMAP_UART4_TX)" # endif -# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -295,11 +295,11 @@ # if !defined(DMAMAP_UART5_TX) # error "UART5 DMA map not defined (DMAMAP_UART5_TX)" # endif -# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -307,11 +307,11 @@ # if !defined(DMAMAP_USART6_TX) # error "USART6 DMA map not defined (DMAMAP_USART6_TX)" # endif -# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -319,11 +319,11 @@ # if !defined(DMAMAP_UART7_TX) # error "UART7 DMA map not defined (DMAMAP_UART7_TX)" # endif -# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -331,11 +331,11 @@ # if !defined(DMAMAP_UART8_TX) # error "UART8 DMA map not defined (DMAMAP_UART8_TX)" # endif -# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif #endif @@ -371,7 +371,7 @@ #endif #define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -#define TXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \ +#define TXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and @@ -475,8 +475,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32H7_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32H7_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # warning stm32h7 serial power managemnt was taken from stm32f7 and is untested! @@ -501,7 +501,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32H7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -511,13 +511,13 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32H7_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif -#ifndef CONFIG_STM32H7_FLOWCONTROL_BROKEN +#ifndef CONFIG_STM32_FLOWCONTROL_BROKEN /* Combination of RXDMA + IFLOWCONTROL does not work as one might expect. * Since RXDMA uses circular DMA-buffer, DMA will always keep reading new * data from USART peripheral even if DMA buffer underruns. Thus this @@ -560,7 +560,7 @@ # warning "RXDMA and IFLOWCONTROL both enabled for UART8. \ This combination can lead to data loss." # endif -#endif /* CONFIG_STM32H7_FLOWCONTROL_BROKEN */ +#endif /* CONFIG_STM32_FLOWCONTROL_BROKEN */ /**************************************************************************** * Private Types @@ -868,49 +868,49 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE] /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[USART1_TXBUFSIZE_ADJUSTED] \ USART1_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[USART2_TXBUFSIZE_ADJUSTED] \ USART2_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[USART3_TXBUFSIZE_ADJUSTED] \ USART3_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[UART4_TXBUFSIZE_ADJUSTED] \ UART4_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[UART5_TXBUFSIZE_ADJUSTED] \ UART5_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[USART6_TXBUFSIZE_ADJUSTED] \ USART6_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[UART7_TXBUFSIZE_ADJUSTED] \ UART7_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ UART8_TXBUFSIZE_ALGN; @@ -918,7 +918,7 @@ static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -988,7 +988,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -1058,7 +1058,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -1128,7 +1128,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 static struct up_dev_s g_uart4priv = { .dev = @@ -1198,7 +1198,7 @@ static struct up_dev_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 static struct up_dev_s g_uart5priv = { .dev = @@ -1268,7 +1268,7 @@ static struct up_dev_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 static struct up_dev_s g_usart6priv = { .dev = @@ -1338,7 +1338,7 @@ static struct up_dev_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 static struct up_dev_s g_uart7priv = { .dev = @@ -1408,7 +1408,7 @@ static struct up_dev_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 static struct up_dev_s g_uart8priv = { .dev = @@ -1480,28 +1480,28 @@ static struct up_dev_s g_uart8priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 [3] = &g_uart4priv, #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 [4] = &g_uart5priv, #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 [5] = &g_usart6priv, #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 [6] = &g_uart7priv, #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 [7] = &g_uart8priv, #endif }; @@ -1797,7 +1797,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1990,49 +1990,49 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1LENR_USART2EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1LENR_USART3EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 case STM32_UART4_BASE: rcc_en = RCC_APB1LENR_UART4EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 case STM32_UART5_BASE: rcc_en = RCC_APB1LENR_UART5EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 case STM32_USART6_BASE: rcc_en = RCC_APB2ENR_USART6EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 case STM32_UART7_BASE: rcc_en = RCC_APB1LENR_UART7EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 case STM32_UART8_BASE: rcc_en = RCC_APB1LENR_UART8EN; regaddr = STM32_RCC_APB1LENR; @@ -2104,7 +2104,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32H7_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2477,8 +2477,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32H7_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32H7_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Get the masked USART status word. */ @@ -2592,14 +2592,14 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32H7_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) \ - || defined(CONFIG_STM32H7_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -2622,7 +2622,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2689,7 +2689,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2740,7 +2740,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2877,8 +2877,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32H7_USART_BREAKS -# ifdef CONFIG_STM32H7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -3088,7 +3088,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3911,7 +3911,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32H7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3940,7 +3940,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32H7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c index 329abb73f25..7ca1e810308 100644 --- a/arch/arm/src/stm32h7/stm32_spi.c +++ b/arch/arm/src/stm32h7/stm32_spi.c @@ -75,9 +75,9 @@ #include "stm32_spi.h" #include "stm32_dma.h" -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI5) || defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -87,19 +87,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H7_SPI_INTERRUPTS) && defined(CONFIG_STM32H7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -137,39 +137,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI1_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI2_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI3_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI4_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI5_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32H7_SPI6_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -180,8 +180,8 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) # if STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL1 # define SPI123_KERNEL_CLOCK_FREQ STM32_PLL1Q_FREQUENCY # elif STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL2 @@ -194,7 +194,7 @@ # endif #endif /* SPI123 */ -#if defined(CONFIG_STM32H7_SPI4) || defined(CONFIG_STM32H7_SPI5) +#if defined(CONFIG_STM32_SPI4) || defined(CONFIG_STM32_SPI5) # if STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_APB # define SPI45_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY # elif STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_PLL2 @@ -207,7 +207,7 @@ # endif #endif /* SPI45 */ -#if defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI6) # if STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PCLK4 # define SPI6_KERNEL_CLOCK_FREQ STM32_PCLK4_FREQUENCY # elif STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PLL2 @@ -238,7 +238,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -288,7 +288,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -354,7 +354,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -403,7 +403,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32H7_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -418,15 +418,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI1_COMMTYPE - .config = CONFIG_STM32H7_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -475,7 +475,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32H7_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -490,15 +490,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI2_COMMTYPE - .config = CONFIG_STM32H7_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -547,7 +547,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32H7_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -562,15 +562,15 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI3_COMMTYPE - .config = CONFIG_STM32H7_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -619,7 +619,7 @@ static struct stm32_spidev_s g_spi4dev = .spibase = STM32_SPI4_BASE, .spiclock = SPI45_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI4, -#ifdef CONFIG_STM32H7_SPI4_DMA +#ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # if defined(SPI4_DMABUFSIZE_ADJUSTED) @@ -634,15 +634,15 @@ static struct stm32_spidev_s g_spi4dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI4_COMMTYPE - .config = CONFIG_STM32H7_SPI4_COMMTYPE, +#ifdef CONFIG_STM32_SPI4_COMMTYPE + .config = CONFIG_STM32_SPI4_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -691,7 +691,7 @@ static struct stm32_spidev_s g_spi5dev = .spibase = STM32_SPI5_BASE, .spiclock = SPI45_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI5, -#ifdef CONFIG_STM32H7_SPI5_DMA +#ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # if defined(SPI5_DMABUFSIZE_ADJUSTED) @@ -706,15 +706,15 @@ static struct stm32_spidev_s g_spi5dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI5_COMMTYPE - .config = CONFIG_STM32H7_SPI5_COMMTYPE, +#ifdef CONFIG_STM32_SPI5_COMMTYPE + .config = CONFIG_STM32_SPI5_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI5 */ +#endif /* CONFIG_STM32_SPI5 */ -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -764,7 +764,7 @@ static struct stm32_spidev_s g_spi6dev = .spibase = STM32_SPI6_BASE, .spiclock = SPI6_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI6, -#ifdef CONFIG_STM32H7_SPI6_DMA +#ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # if defined(SPI6_DMABUFSIZE_ADJUSTED) @@ -779,13 +779,13 @@ static struct stm32_spidev_s g_spi6dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI6_COMMTYPE - .config = CONFIG_STM32H7_SPI6_COMMTYPE, +#ifdef CONFIG_STM32_SPI6_COMMTYPE + .config = CONFIG_STM32_SPI6_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI6 */ +#endif /* CONFIG_STM32_SPI6 */ /**************************************************************************** * Private Functions @@ -1107,7 +1107,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -1124,7 +1124,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -1164,7 +1164,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -1213,7 +1213,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -1228,7 +1228,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1248,7 +1248,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1310,7 +1310,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1370,7 +1370,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1394,7 +1394,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1929,9 +1929,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SPI_DMA) || defined(CONFIG_STM32H7_DMACAPABLE) || \ - defined(CONFIG_STM32H7_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32H7_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -2020,8 +2020,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32H7_SPI_DMA || CONFIG_STM32H7_DMACAPABLE || - * CONFIG_STM32H7_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -2045,7 +2045,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -2063,12 +2063,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32H7_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32H7_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -2132,7 +2132,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -2264,7 +2264,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32H7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2285,7 +2285,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2519,7 +2519,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2601,7 +2601,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2626,7 +2626,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2651,7 +2651,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2676,7 +2676,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2701,7 +2701,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2726,7 +2726,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2759,6 +2759,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32H7_SPI1 || CONFIG_STM32H7_SPI2 || CONFIG_STM32H7_SPI3 || - * CONFIG_STM32H7_SPI4 || CONFIG_STM32H7_SPI5 || CONFIG_STM32H7_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32h7/stm32_spi.h b/arch/arm/src/stm32h7/stm32_spi.h index a9b0532e075..663a2eac486 100644 --- a/arch/arm/src/stm32h7/stm32_spi.h +++ b/arch/arm/src/stm32h7/stm32_spi.h @@ -114,42 +114,42 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -177,32 +177,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32h7/stm32_spi_slave.c b/arch/arm/src/stm32h7/stm32_spi_slave.c index efa9fc56411..83499c4d8ef 100644 --- a/arch/arm/src/stm32h7/stm32_spi_slave.c +++ b/arch/arm/src/stm32h7/stm32_spi_slave.c @@ -67,19 +67,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H7_SPI_INTERRUPTS) && defined(CONFIG_STM32H7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -187,7 +187,7 @@ struct stm32_spidev_s uint32_t spiclock; /* Clocking for the SPI module */ uint8_t irq; /* SPI IRQ number */ uint32_t nss_pin; /* Chip select pin configuration */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the TX DMA */ uint32_t rxch; /* The RX DMA channel number */ @@ -221,7 +221,7 @@ struct stm32_spidev_s /* Input queue */ uint16_t ihead; /* Location of next unread value */ -#ifndef CONFIG_STM32H7_SPI_DMA +#ifndef CONFIG_STM32_SPI_DMA uint16_t itail; /* Index of next free memory pointer */ #endif uint8_t *inq; @@ -250,7 +250,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, @@ -311,7 +311,7 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = #define SPI_SLAVE_OUTQ(x) spi##x##_outq #define SPI_SLAVE_INQ(x) spi##x##_inq -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #define SPI_SLAVE_INIT_DMA(x) \ .rxch = DMAMAP_SPI##x##_RX, \ .txch = DMAMAP_SPI##x##_TX, \ @@ -340,7 +340,7 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = .initialized = false, \ .lock = NXMUTEX_INITIALIZER, \ SPI_SLAVE_INIT_PM_PREPARE \ - .config = CONFIG_STM32H7_SPI##x##_COMMTYPE, \ + .config = CONFIG_STM32_SPI##x##_COMMTYPE, \ } #ifdef CONFIG_STM32H7_SPI1_SLAVE @@ -706,7 +706,7 @@ static inline bool spi_9to16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -726,7 +726,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -746,7 +746,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) { stm32_dmacfg_t dmacfg; @@ -795,7 +795,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, size_t nwords) { /* TODO: set up dma to transfer out the new data from priv->outq, @@ -850,7 +850,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, size_t nwords) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -875,7 +875,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1223,7 +1223,7 @@ static int spi_nssinterrupt(int irq, void *context, void *arg) spi_enable(priv, false); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Setup DMAs */ @@ -1363,7 +1363,7 @@ static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) DEBUGASSERT(priv != NULL && priv->dev != NULL); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (!priv->dmarunning) { return; @@ -1377,7 +1377,7 @@ static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) /* Flush the input buffers */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->ihead = CONFIG_STM32H7_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); #else @@ -1454,7 +1454,7 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) DEBUGASSERT(priv != NULL && priv->dev != NULL); DEBUGASSERT(priv->ihead < CONFIG_STM32H7_SPI_SLAVE_QSIZE); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (!priv->dmarunning) { return 0; @@ -1465,7 +1465,7 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) spi_lock(ctrlr, true); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA itail = CONFIG_STM32H7_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); #else #error Support only simplex mode rx with dma @@ -1657,7 +1657,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* DMA will be started in the interrupt handler, synchronized to the master * nss */ @@ -1796,4 +1796,4 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) return (struct spi_slave_ctrlr_s *)priv; } -#endif /* CONFIG_STM32H7_SPI1..6_SLAVE */ +#endif /* CONFIG_STM32_SPI1..6_SLAVE */ diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index 70c7d4ade3f..fa55412dc06 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -305,7 +305,7 @@ void __start(void) #if defined(CONFIG_ARCH_STM32H7_DUALCORE) && \ defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Start CM4 core after clock configuration is done */ diff --git a/arch/arm/src/stm32h7/stm32_tickless.c b/arch/arm/src/stm32h7/stm32_tickless.c index 1de1d5abf73..7fb140248cb 100644 --- a/arch/arm/src/stm32h7/stm32_tickless.c +++ b/arch/arm/src/stm32h7/stm32_tickless.c @@ -89,23 +89,23 @@ #undef HAVE_32BIT_TICKLESS -#if (CONFIG_STM32H7_TICKLESS_TIMER == 2) || \ - (CONFIG_STM32H7_TICKLESS_TIMER == 5) +#if (CONFIG_STM32_TICKLESS_TIMER == 2) || \ + (CONFIG_STM32_TICKLESS_TIMER == 5) #define HAVE_32BIT_TICKLESS 1 #endif -#if (CONFIG_STM32H7_TICKLESS_TIMER == 6) || \ - (CONFIG_STM32H7_TICKLESS_TIMER == 7) +#if (CONFIG_STM32_TICKLESS_TIMER == 6) || \ + (CONFIG_STM32_TICKLESS_TIMER == 7) # error Basic timers not supported by the tickless driver #endif -#if CONFIG_STM32H7_TICKLESS_CHANNEL == 1 +#if CONFIG_STM32_TICKLESS_CHANNEL == 1 #define DIER_CAPT_IE GTIM_DIER_CC1IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 2 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 2 #define DIER_CAPT_IE GTIM_DIER_CC2IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 3 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 3 #define DIER_CAPT_IE GTIM_DIER_CC3IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 4 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 4 #define DIER_CAPT_IE GTIM_DIER_CC4IE #endif @@ -413,50 +413,50 @@ static uint64_t stm32_get_counter(void) void up_timer_initialize(void) { - switch (CONFIG_STM32H7_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM1STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM2STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: g_tickless.base = STM32_TIM3_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM3STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: g_tickless.base = STM32_TIM4_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM4STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: g_tickless.base = STM32_TIM5_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM5STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: g_tickless.base = STM32_TIM8_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM8STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: g_tickless.base = STM32_TIM9_BASE; @@ -464,7 +464,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: g_tickless.base = STM32_TIM10_BASE; @@ -473,7 +473,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: g_tickless.base = STM32_TIM11_BASE; @@ -481,40 +481,40 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: g_tickless.base = STM32_TIM12_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM12STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: g_tickless.base = STM32_TIM13_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM13STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: g_tickless.base = STM32_TIM14_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM14STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: g_tickless.base = STM32_TIM15_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM15STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM16STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM17STOP); @@ -528,8 +528,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32H7_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32H7_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -1001,10 +1001,10 @@ int up_alarm_start(const struct timespec *ts) flags = enter_critical_section(); - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32H7_TICKLESS_CHANNEL, tm); + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); stm32_tickless_ackint(g_tickless.channel); - stm32_tickless_enableint(CONFIG_STM32H7_TICKLESS_CHANNEL); + stm32_tickless_enableint(CONFIG_STM32_TICKLESS_CHANNEL); g_tickless.pending = true; @@ -1021,7 +1021,7 @@ int up_alarm_start(const struct timespec *ts) while (tm <= stm32_get_counter()) { tm = stm32_get_counter() + offset++; - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32H7_TICKLESS_CHANNEL, + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); } @@ -1042,7 +1042,7 @@ int up_alarm_cancel(struct timespec *ts) ts->tv_sec = nsecs / NSEC_PER_SEC; ts->tv_nsec = nsecs - ts->tv_sec * NSEC_PER_SEC; - stm32_tickless_disableint(CONFIG_STM32H7_TICKLESS_CHANNEL); + stm32_tickless_disableint(CONFIG_STM32_TICKLESS_CHANNEL); return 0; } diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c index 4b04b9a9f24..63f84f00a15 100644 --- a/arch/arm/src/stm32h7/stm32_tim.c +++ b/arch/arm/src/stm32h7/stm32_tim.c @@ -72,77 +72,77 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32H7_TIM1_PWM) || defined (CONFIG_STM32H7_TIM1_ADC) || \ - defined(CONFIG_STM32H7_TIM1_DAC) || defined(CONFIG_STM32H7_TIM1_QE) -# undef CONFIG_STM32H7_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32H7_TIM2_PWM) || defined (CONFIG_STM32H7_TIM2_ADC) || \ - defined(CONFIG_STM32H7_TIM2_DAC) || defined(CONFIG_STM32H7_TIM2_QE) -# undef CONFIG_STM32H7_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) || defined (CONFIG_STM32H7_TIM3_ADC) || \ - defined(CONFIG_STM32H7_TIM3_DAC) || defined(CONFIG_STM32H7_TIM3_QE) -# undef CONFIG_STM32H7_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32H7_TIM4_PWM) || defined (CONFIG_STM32H7_TIM4_ADC) || \ - defined(CONFIG_STM32H7_TIM4_DAC) || defined(CONFIG_STM32H7_TIM4_QE) -# undef CONFIG_STM32H7_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32H7_TIM5_PWM) || defined (CONFIG_STM32H7_TIM5_ADC) || \ - defined(CONFIG_STM32H7_TIM5_DAC) || defined(CONFIG_STM32H7_TIM5_QE) -# undef CONFIG_STM32H7_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32H7_TIM6_PWM) || defined (CONFIG_STM32H7_TIM6_ADC) || \ - defined(CONFIG_STM32H7_TIM6_DAC) || defined(CONFIG_STM32H7_TIM6_QE) -# undef CONFIG_STM32H7_TIM6 +#if defined(CONFIG_STM32H7_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32H7_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32H7_TIM7_PWM) || defined (CONFIG_STM32H7_TIM7_ADC) || \ - defined(CONFIG_STM32H7_TIM7_DAC) || defined(CONFIG_STM32H7_TIM7_QE) -# undef CONFIG_STM32H7_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32H7_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32H7_TIM8_PWM) || defined (CONFIG_STM32H7_TIM8_ADC) || \ - defined(CONFIG_STM32H7_TIM8_DAC) || defined(CONFIG_STM32H7_TIM8_QE) -# undef CONFIG_STM32H7_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32H7_TIM12_PWM) || defined (CONFIG_STM32H7_TIM12_ADC) || \ - defined(CONFIG_STM32H7_TIM12_DAC) || defined(CONFIG_STM32H7_TIM12_QE) -# undef CONFIG_STM32H7_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32H7_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32H7_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32H7_TIM13_PWM) || defined (CONFIG_STM32H7_TIM13_ADC) || \ - defined(CONFIG_STM32H7_TIM13_DAC) || defined(CONFIG_STM32H7_TIM13_QE) -# undef CONFIG_STM32H7_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32H7_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32H7_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32H7_TIM14_PWM) || defined (CONFIG_STM32H7_TIM14_ADC) || \ - defined(CONFIG_STM32H7_TIM14_DAC) || defined(CONFIG_STM32H7_TIM14_QE) -# undef CONFIG_STM32H7_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32H7_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32H7_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32H7_TIM15_PWM) || defined (CONFIG_STM32H7_TIM15_ADC) || \ +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ defined(CONFIG_STM32H7_TIM15_DAC) || defined(CONFIG_STM32H7_TIM15_QE) -# undef CONFIG_STM32H7_TIM15 +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32H7_TIM16_PWM) || defined (CONFIG_STM32H7_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32H7_TIM16_ADC) || \ defined(CONFIG_STM32H7_TIM16_DAC) || defined(CONFIG_STM32H7_TIM16_QE) -# undef CONFIG_STM32H7_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32H7_TIM17_PWM) || defined (CONFIG_STM32H7_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32H7_TIM17_ADC) || \ defined(CONFIG_STM32H7_TIM17_DAC) || defined(CONFIG_STM32H7_TIM17_QE) -# undef CONFIG_STM32H7_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32H7_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) @@ -150,35 +150,35 @@ # endif #endif -#if defined(CONFIG_STM32H7_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) @@ -186,37 +186,37 @@ # endif #endif -#if defined(CONFIG_STM32H7_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) # define HAVE_TIM12_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) # define HAVE_TIM13_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) # define HAVE_TIM14_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) # define HAVE_TIM15_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) # define HAVE_TIM16_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) # define HAVE_TIM17_GPIOCONFIG 1 # endif @@ -226,13 +226,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H7_TIM1) || defined(CONFIG_STM32H7_TIM2) || \ - defined(CONFIG_STM32H7_TIM3) || defined(CONFIG_STM32H7_TIM4) || \ - defined(CONFIG_STM32H7_TIM5) || defined(CONFIG_STM32H7_TIM6) || \ - defined(CONFIG_STM32H7_TIM7) || defined(CONFIG_STM32H7_TIM8) || \ - defined(CONFIG_STM32H7_TIM12) || defined(CONFIG_STM32H7_TIM13) || \ - defined(CONFIG_STM32H7_TIM14) || defined(CONFIG_STM32H7_TIM15) || \ - defined(CONFIG_STM32H7_TIM16) || defined(CONFIG_STM32H7_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -312,7 +312,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = &stm32_tim_checkint, }; -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -320,7 +320,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -329,7 +329,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -338,7 +338,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -347,7 +347,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -356,7 +356,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -365,7 +365,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -374,7 +374,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -383,7 +383,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -392,7 +392,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -401,7 +401,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -410,7 +410,7 @@ struct stm32_tim_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -419,7 +419,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -428,7 +428,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -519,12 +519,12 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32H7_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif -#if defined(CONFIG_STM32H7_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -626,72 +626,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -745,72 +745,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1016,7 +1016,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1049,7 +1049,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1078,7 +1078,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1107,7 +1107,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1136,7 +1136,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1165,7 +1165,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1199,7 +1199,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1218,7 +1218,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1232,7 +1232,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1247,7 +1247,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1266,7 +1266,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1280,7 +1280,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1364,85 +1364,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1474,72 +1474,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1555,4 +1555,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c index 895e54e7a2f..cc5e18737e5 100644 --- a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c @@ -58,13 +58,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32H7_TIM1) || defined(CONFIG_STM32H7_TIM2) || \ - defined(CONFIG_STM32H7_TIM3) || defined(CONFIG_STM32H7_TIM4) || \ - defined(CONFIG_STM32H7_TIM5) || defined(CONFIG_STM32H7_TIM6) || \ - defined(CONFIG_STM32H7_TIM7) || defined(CONFIG_STM32H7_TIM8) || \ - defined(CONFIG_STM32H7_TIM9) || defined(CONFIG_STM32H7_TIM10) || \ - defined(CONFIG_STM32H7_TIM11) || defined(CONFIG_STM32H7_TIM12) || \ - defined(CONFIG_STM32H7_TIM13) || defined(CONFIG_STM32H7_TIM14)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) /**************************************************************************** * Pre-processor Definitions @@ -135,7 +135,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -143,7 +143,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 static struct stm32_lowerhalf_s g_tim9_lowerhalf = { .ops = &g_timer_ops, @@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim9_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 static struct stm32_lowerhalf_s g_tim10_lowerhalf = { .ops = &g_timer_ops, @@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim10_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 static struct stm32_lowerhalf_s g_tim11_lowerhalf = { .ops = &g_timer_ops, @@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim11_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -473,72 +473,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: lower = &g_tim9_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: lower = &g_tim10_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: lower = &g_tim11_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; diff --git a/arch/arm/src/stm32h7/stm32_uart.h b/arch/arm/src/stm32h7/stm32_uart.h index ea171109805..8748d83c343 100644 --- a/arch/arm/src/stm32h7/stm32_uart.h +++ b/arch/arm/src/stm32h7/stm32_uart.h @@ -41,43 +41,43 @@ */ #if STM32_NUART < 4 -# undef CONFIG_STM32H7_UART8 +# undef CONFIG_STM32_UART8 #endif #if STM32_NUART < 3 -# undef CONFIG_STM32H7_UART7 +# undef CONFIG_STM32_UART7 #endif #if STM32_NUART < 2 -# undef CONFIG_STM32H7_UART5 +# undef CONFIG_STM32_UART5 #endif #if STM32_NUART < 1 -# undef CONFIG_STM32H7_UART4 +# undef CONFIG_STM32_UART4 #endif #if STM32_NUSART < 4 -# undef CONFIG_STM32H7_USART6 +# undef CONFIG_STM32_USART6 #endif #if STM32_NUSART < 3 -# undef CONFIG_STM32H7_USART3 +# undef CONFIG_STM32_USART3 #endif #if STM32_NUSART < 2 -# undef CONFIG_STM32H7_USART2 +# undef CONFIG_STM32_USART2 #endif #if STM32_NUSART < 1 -# undef CONFIG_STM32H7_USART1 +# undef CONFIG_STM32_USART1 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32H7_USART1) || defined(CONFIG_STM32H7_USART2) || \ - defined(CONFIG_STM32H7_USART3) || defined(CONFIG_STM32H7_UART4) || \ - defined(CONFIG_STM32H7_UART5) || defined(CONFIG_STM32H7_USART6) || \ - defined(CONFIG_STM32H7_UART7) || defined(CONFIG_STM32H7_UART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \ + defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_UART7) || defined(CONFIG_STM32_UART8) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART1) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -87,7 +87,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -97,7 +97,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART3) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -107,7 +107,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -117,7 +117,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART5) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART6) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -137,7 +137,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART7) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -147,7 +147,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART8) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -296,42 +296,42 @@ /* Is RX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_RXDMA 1 -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA #endif /* Is TX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_TXDMA 1 -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_TXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_TXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_TXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_TXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_TXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_TXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_TXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_TXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA #endif @@ -343,28 +343,28 @@ /* No DMA ops */ #undef SERIAL_HAVE_NODMA_OPS -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_RXDMA) && \ +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) && \ !defined(CONFIG_USART1_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_RXDMA) && \ +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) && \ !defined(CONFIG_USART2_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_RXDMA) && \ +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) && \ !defined(CONFIG_USART3_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_RXDMA) && \ +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) && \ !defined(CONFIG_UART4_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_RXDMA) && \ +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) && \ !defined(CONFIG_UART5_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_RXDMA) && \ +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) && \ !defined(CONFIG_USART6_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_RXDMA) && \ +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) && \ !defined(CONFIG_UART7_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_RXDMA) && \ +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) && \ !defined(CONFIG_UART8_TXDMA) # define SERIAL_HAVE_NODMA_OPS #endif diff --git a/arch/arm/src/stm32h7/stm32_usbhost.h b/arch/arm/src/stm32h7/stm32_usbhost.h index 031b66ad229..798b0aaf965 100644 --- a/arch/arm/src/stm32h7/stm32_usbhost.h +++ b/arch/arm/src/stm32h7/stm32_usbhost.h @@ -28,10 +28,10 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block * or - * CONFIG_STM32H7_OTGHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32H7_SYSCFG - Needed + * CONFIG_STM32_OTGHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * @@ -44,7 +44,7 @@ * CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. */ @@ -58,7 +58,7 @@ #include #include -#if (defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS)) && \ +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) && \ defined(CONFIG_USBHOST) #ifdef HAVE_USBHOST_TRACE @@ -190,5 +190,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* (CONFIG_STM32H7_OTGFS || CONFIG_STM32H7_OTGHS) && CONFIG_USBHOST */ +#endif /* (CONFIG_STM32_OTGFS || CONFIG_STM32_OTGHS) && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32h7/stm32_wdg.h b/arch/arm/src/stm32h7/stm32_wdg.h index f869669264a..f5f51837661 100644 --- a/arch/arm/src/stm32h7/stm32_wdg.h +++ b/arch/arm/src/stm32h7/stm32_wdg.h @@ -71,7 +71,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif @@ -92,7 +92,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_WWDG +#ifdef CONFIG_STM32_WWDG void stm32_wwdginitialize(const char *devpath); #endif diff --git a/arch/arm/src/stm32h7/stm32_wwdg.c b/arch/arm/src/stm32h7/stm32_wwdg.c index 4e96d10a3d3..7a4c29aeb9a 100644 --- a/arch/arm/src/stm32h7/stm32_wwdg.c +++ b/arch/arm/src/stm32h7/stm32_wwdg.c @@ -39,7 +39,7 @@ #include "arm_internal.h" #include "stm32_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32H7_WWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) /**************************************************************************** * Pre-processor Definitions @@ -783,9 +783,9 @@ void stm32_wwdginitialize(const char *devpath) * on the WWDG1 STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32H7_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr = getreg32(STM32_DBGMCU_APB3_FZ1); cr |= DBGMCU_APB3_WWDG1STOP; @@ -794,4 +794,4 @@ void stm32_wwdginitialize(const char *devpath) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32H7_WWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/stm32h7/stm32h743xx_flash.c b/arch/arm/src/stm32h7/stm32h743xx_flash.c index ddf3c13a5b8..9e996ee83f3 100644 --- a/arch/arm/src/stm32h7/stm32h743xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h743xx_flash.c @@ -69,7 +69,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with * CONFIG_STM32H7_FLASH_OVERRIDE_x @@ -85,49 +85,49 @@ #define FLASH_SECTOR_SIZE _K(128) #define FLASH_PAGE_SIZE 32 -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_I) -# define CONFIG_STM32H7_FLASH_OVERRIDE_B +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_B # warning "Flash size not defined defaulting to 128KiB (B)" #endif -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H7_FLASH_CONFIG_B -# undef CONFIG_STM32H7_FLASH_CONFIG_G -# undef CONFIG_STM32H7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32H7_FLASH_OVERRIDE_B) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_B) -# define CONFIG_STM32H7_FLASH_CONFIG_B +# define CONFIG_STM32_FLASH_CONFIG_B -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32H7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32H7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32H7_FLASH_CONFIG_B) +#if defined(CONFIG_STM32_FLASH_CONFIG_B) # define STM32_FLASH_NBLOCKS 1 # define STM32_FLASH_SIZE _K(1 * 128) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NBLOCKS 8 # define STM32_FLASH_SIZE _K(8 * 128) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NBLOCKS 16 # define STM32_FLASH_SIZE _K(16 * 128) @@ -135,10 +135,10 @@ #endif -#ifndef CONFIG_STM32H7_FLASH_CR_PSIZE +#ifndef CONFIG_STM32_FLASH_CR_PSIZE #define FLASH_CR_PSIZE FLASH_CR_PSIZE_X64 #else -#define FLASH_CR_PSIZE (CONFIG_STM32H7_FLASH_CR_PSIZE << FLASH_CR_PSIZE_SHIFT) +#define FLASH_CR_PSIZE (CONFIG_STM32_FLASH_CR_PSIZE << FLASH_CR_PSIZE_SHIFT) #endif #define FLASH_KEY1 0x45670123 diff --git a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c index 278d0d2171d..7e1f8eb7d64 100644 --- a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c @@ -69,7 +69,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with * CONFIG_STM32H7_FLASH_OVERRIDE_x @@ -86,38 +86,38 @@ #define FLASH_PAGE_SIZE 16 -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_I) -# define CONFIG_STM32H7_FLASH_OVERRIDE_G +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_G # warning "Flash size not defined defaulting to 1024KiB (G)" #endif -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H7_FLASH_CONFIG_B -# undef CONFIG_STM32H7_FLASH_CONFIG_G -# undef CONFIG_STM32H7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32H7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32H7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32H7_FLASH_CONFIG_G) +#if defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NBLOCKS 128 # define STM32_FLASH_SIZE _K(128 * 8) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NBLOCKS 256 # define STM32_FLASH_SIZE _K(256 * 8) diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index 5fb2cae9f94..c65bc2feeda 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -146,23 +146,23 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * When the Soc does not supports SMPS we support only the LDO supply. */ -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_MASK ~(STM32_PWR_CR3_BYPASS | \ STM32_PWR_CR3_LDOEN | \ STM32_PWR_CR3_SDEN | \ STM32_PWR_CR3_SMPSEXTHP | \ STM32_PWR_CR3_SMPSLEVEL_MASK) -# if defined(CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY) +# if defined(CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY) # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_SDEN -# elif defined(CONFIG_STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY) +# elif defined(CONFIG_STM32_PWR_EXTERNAL_SOURCE_SUPPLY) # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_BYPASS # else # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_LDOEN # endif #else # define STM32_PWR_CR3_MASK 0xffffffff -# if defined(CONFIG_STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY) +# if defined(CONFIG_STM32_PWR_EXTERNAL_SOURCE_SUPPLY) # define STM32_PWR_CR3_SELECTION (STM32_PWR_CR3_BYPASS | STM32_PWR_CR3_SCUEN) # else # define STM32_PWR_CR3_SELECTION (STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_SCUEN) @@ -192,7 +192,7 @@ static inline void rcc_reset(void) regval |= RCC_CR_HSION; putreg32(regval, STM32_RCC_CR); -#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) +#if defined(CONFIG_STM32_AXI_SRAM_CORRUPTION_WAR) /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to * data read corruption. See ES0392 Rev 6. */ @@ -250,32 +250,32 @@ static inline void rcc_enableahb1(void) */ regval = getreg32(STM32_RCC_AHB1ENR); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* ADC1 & 2 clock enable */ regval |= RCC_AHB1ENR_ADC12EN; #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB1ENR_OTGFSEN; #endif -#ifdef CONFIG_STM32H7_OTGHS -# ifndef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS +# ifndef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /* Enable only clocking for USB OTG HS */ regval |= RCC_AHB1ENR_OTGHSEN; @@ -286,7 +286,7 @@ static inline void rcc_enableahb1(void) # endif #endif -#ifdef CONFIG_STM32H7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Enable ethernet clocks */ regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN | @@ -314,19 +314,19 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32H7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC2 clock enable */ regval |= RCC_AHB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32H7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic clock enable */ regval |= RCC_AHB2ENR_CRYPTEN; @@ -353,25 +353,25 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA clock enable */ regval |= RCC_AHB3ENR_MDMAEN; #endif -#ifdef CONFIG_STM32H7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC clock enable */ regval |= RCC_AHB3ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#if defined(CONFIG_STM32H7_LTDC) && defined(CONFIG_STM32H7_DMA2D) +#if defined(CONFIG_STM32_LTDC) && defined(CONFIG_STM32_DMA2D) /* Enable DMA2D */ regval |= RCC_AHB3ENR_DMA2DEN; @@ -400,7 +400,7 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_AHB4ENR_ADC3EN; @@ -422,10 +422,10 @@ static inline void rcc_enableahb4(void) #if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif #if STM32_NGPIO > 7 @@ -443,25 +443,25 @@ static inline void rcc_enableahb4(void) ); #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA clock enable */ regval |= RCC_AHB4ENR_BDMAEN; #endif -#ifdef CONFIG_STM32H7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB4ENR_CRCEN; #endif -#ifdef CONFIG_STM32H7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB4ENR_BKPSRAMEN; #endif -#ifdef CONFIG_STM32H7_HSEM +#ifdef CONFIG_STM32_HSEM /* HSEM clock enable */ regval |= RCC_AHB4ENR_HSEMEN; @@ -488,31 +488,31 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1LENR_I2C3EN; @@ -522,7 +522,7 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1HENR); -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN /* FDCAN clock enable */ regval |= RCC_APB1HENR_FDCANEN; @@ -549,31 +549,31 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; @@ -600,13 +600,13 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB3ENR_LTDCEN; #endif -#ifdef CONFIG_STM32H7_WWDG +#ifdef CONFIG_STM32_WWDG /* RM0433 Rev 8 * Reference manual - STM32H742, STM32H743/753 and STM32H750 Value line @@ -651,19 +651,19 @@ static inline void rcc_enableapb4(void) regval = getreg32(STM32_RCC_APB4ENR); -#ifdef CONFIG_STM32H7_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* System configuration controller clock enable */ regval |= RCC_APB4ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB4ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB4ENR_SPI6EN; @@ -762,7 +762,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_HSI48 +#ifdef CONFIG_STM32_HSI48 /* Enable HSI48 */ regval = getreg32(STM32_RCC_CR); @@ -776,7 +776,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_CSI +#ifdef CONFIG_STM32_CSI /* Enable CSI */ regval = getreg32(STM32_RCC_CR); @@ -832,7 +832,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_D3CFGR_D3PPRE; putreg32(regval, STM32_RCC_D3CFGR); -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -963,7 +963,7 @@ void stm32_stdclockconfig(void) { } -#ifndef CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY +#ifndef CONFIG_STM32_PWR_IGNORE_ACTVOSRDY /* See Reference manual Section 5.4.1, System supply startup */ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) @@ -1105,13 +1105,13 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D2CCIP1R); #endif -#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 481183e8ea5..526dc538e4a 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -139,7 +139,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * When the Soc does not supports SMPS we support only the LDO supply. */ -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_MASK ~(STM32_PWR_CR3_BYPASS | \ STM32_PWR_CR3_LDOEN | \ STM32_PWR_CR3_SDEN | \ @@ -179,7 +179,7 @@ static inline void rcc_reset(void) regval |= RCC_CR_HSION; putreg32(regval, STM32_RCC_CR); -#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) +#if defined(CONFIG_STM32_AXI_SRAM_CORRUPTION_WAR) /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to * data read corruption. See ES0392 Rev 6. */ @@ -237,32 +237,32 @@ static inline void rcc_enableahb1(void) */ regval = getreg32(STM32_RCC_AHB1ENR); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* ADC1 & 2 clock enable */ regval |= RCC_AHB1ENR_ADC12EN; #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB1ENR_OTGFSEN; #endif -#ifdef CONFIG_STM32H7_OTGHS -# if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGHS +# if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); @@ -273,7 +273,7 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32H7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Enable ethernet clocks */ regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN | @@ -301,13 +301,13 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32H7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC2 clock enable */ regval |= RCC_AHB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -334,19 +334,19 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA clock enable */ regval |= RCC_AHB3ENR_MDMAEN; #endif -#ifdef CONFIG_STM32H7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC clock enable */ regval |= RCC_AHB3ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; @@ -375,7 +375,7 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_AHB4ENR_ADC3EN; @@ -397,10 +397,10 @@ static inline void rcc_enableahb4(void) #if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif #if STM32_NGPIO > 7 @@ -418,19 +418,19 @@ static inline void rcc_enableahb4(void) ); #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA clock enable */ regval |= RCC_AHB4ENR_BDMAEN; #endif -#ifdef CONFIG_STM32H7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB4ENR_CRCEN; #endif -#ifdef CONFIG_STM32H7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB4ENR_BKPSRAMEN; @@ -457,31 +457,31 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1LENR_I2C3EN; @@ -516,31 +516,31 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; @@ -590,19 +590,19 @@ static inline void rcc_enableapb4(void) regval = getreg32(STM32_RCC_APB4ENR); -#ifdef CONFIG_STM32H7_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* System configuration controller clock enable */ regval |= RCC_APB4ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB4ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB4ENR_SPI6EN; @@ -696,7 +696,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_HSI48 +#ifdef CONFIG_STM32_HSI48 /* Enable HSI48 */ regval = getreg32(STM32_RCC_CR); @@ -710,7 +710,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_CSI +#ifdef CONFIG_STM32_CSI /* Enable CSI */ regval = getreg32(STM32_RCC_CR); @@ -766,7 +766,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_D3CFGR_D3PPRE; putreg32(regval, STM32_RCC_D3CFGR); -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -897,7 +897,7 @@ void stm32_stdclockconfig(void) { } -#ifndef CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY +#ifndef CONFIG_STM32_PWR_IGNORE_ACTVOSRDY /* See Reference manual Section 5.4.1, System supply startup */ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) @@ -1038,13 +1038,13 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D2CCIP1R); #endif -#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig index 81256b344b3..6c5b66cd269 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,13 +48,13 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CH2OUT=y -CONFIG_STM32H7_TIM4_CHANNEL=2 -CONFIG_STM32H7_TIM4_PWM=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH2OUT=y +CONFIG_STM32_TIM4_CHANNEL=2 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig index 5ead89d6a20..007834df663 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,10 +49,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig index 2f5b1ee1c58..dad31466087 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -50,9 +51,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig index d0502ff974d..ed872fc7b3b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -57,11 +58,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_QSPI=y -CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_INTERRUPTS=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=2048 CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig index 0478f186776..676f5681af1 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig @@ -6,13 +6,14 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -66,14 +67,14 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0xC0600000 -CONFIG_STM32H7_LTDC_FB_SIZE=2097152 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xC0600000 +CONFIG_STM32_LTDC_FB_SIZE=2097152 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig index 5f25013c7d1..a1d0ec0844f 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,10 +49,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig index 6486a55fbbb..8f04d2c7ab6 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -60,11 +61,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_UART4=y -CONFIG_STM32H7_USART1=y -CONFIG_STM32H7_USART6=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=38400 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig index 2579b2ca842..8498dcc669e 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,11 +52,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_UART4=y -CONFIG_STM32H7_USART1=y -CONFIG_STM32H7_USART6=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=38400 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig index 8d434e7ed5e..0f07506b59b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -69,18 +70,18 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_PHYSR=30 -CONFIG_STM32H7_PHYSR_100FD=0x6 -CONFIG_STM32H7_PHYSR_100HD=0x2 -CONFIG_STM32H7_PHYSR_10FD=0x5 -CONFIG_STM32H7_PHYSR_10HD=0x1 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x7 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RMII_MCO1=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYSR=30 +CONFIG_STM32_PHYSR_100FD=0x6 +CONFIG_STM32_PHYSR_100HD=0x2 +CONFIG_STM32_PHYSR_10FD=0x5 +CONFIG_STM32_PHYSR_10HD=0x1 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x7 +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_MCO1=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig index 293a768c652..4f5046b5bf4 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,9 +46,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig index 25020b5ef45..b15a5f909aa 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,11 +52,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_QSPI=y -CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_INTERRUPTS=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_NXFFS=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig index 790cb3c5968..483c66da524 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,11 +49,11 @@ CONFIG_SENSORS_QENCODER=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM5=y -CONFIG_STM32H7_TIM5_QE=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM5=y +CONFIG_STM32_TIM5_QE=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig index c50bb277960..ccccc22e495 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -68,11 +69,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig index 3dbb6830e69..f341419ebfc 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -58,11 +59,11 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig index b7502e7c4a2..3578ec87beb 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,10 +46,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig index f79049ddbd2..7ef37a7cbf7 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -66,9 +67,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig index 7f6c62f7326..2dec3ec8389 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,15 +56,15 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ONESHOT=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM17=y -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CH2OUT=y -CONFIG_STM32H7_TIM4_CHANNEL=2 -CONFIG_STM32H7_TIM4_PWM=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_ONESHOT=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM17=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH2OUT=y +CONFIG_STM32_TIM4_CHANNEL=2 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig index 0c36755c1c7..3a56b8e9afa 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig @@ -8,11 +8,12 @@ # CONFIG_MMCSD_HAVE_WRITEPROTECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_SDMMC_IDMA is not set +# CONFIG_STM32_SDMMC_IDMA is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -60,12 +61,12 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig index 77d040d77ad..3772f3440ed 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -49,11 +50,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig index 12364f56d13..e2faa065b1b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,12 +66,12 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_ZMODEM=y CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h index 3072adbe60f..6cccfd1a0ba 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h @@ -488,7 +488,7 @@ * linum board routes only DQ[15:0] bits. */ -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 120000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" @@ -502,7 +502,7 @@ * this value will need to be doubled. */ -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC # define BOARD_SDRAM1_SIZE (6*1024*1024) #else # define BOARD_SDRAM1_SIZE (8*1024*1024) diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt index d0d7904d73a..e4b1d4e9275 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt @@ -30,11 +30,11 @@ if(CONFIG_USERLED) list(APPEND SRCS stm32_userled.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -70,7 +70,7 @@ if(CONFIG_CL_MFRC522) list(APPEND SRCS stm32_mfrc522.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile index c2ae5df6f58..56336dc4c5a 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile @@ -32,11 +32,11 @@ else endif endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif @@ -68,7 +68,7 @@ ifeq ($(CONFIG_CL_MFRC522),y) CSRCS += stm32_mfrc522.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h index 8ce1c6eee65..64027b170b9 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h @@ -86,7 +86,7 @@ * PD7 Enable power supply SD Card pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -162,7 +162,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -225,7 +225,7 @@ int stm32_pwm_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c index bab56899d14..02f6a1cc0ae 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c @@ -47,7 +47,7 @@ # include "stm32_rtc.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -132,10 +132,10 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } @@ -166,7 +166,7 @@ int stm32_bringup(void) struct rtc_lowerhalf_s *lower; #endif -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII /* Reset Ethernet PHY */ stm32_configgpio(GPIO_ETH_RESET); @@ -289,7 +289,7 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 /* Enable and configure CAN1 */ @@ -298,7 +298,7 @@ int stm32_bringup(void) stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 /* Enable and configure CAN2 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c index 15113bb0f06..bc5b9ffcacb 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c @@ -39,7 +39,7 @@ #include "linum-stm32h753bi.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c index de8539d1a6f..097d5fc17ae 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c @@ -36,7 +36,7 @@ #include "linum-stm32h753bi.h" #include "stm32_spi.h" -#if defined(CONFIG_SPI) && defined(CONFIG_STM32H7_SPI4) && defined(CONFIG_CL_MFRC522) +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI4) && defined(CONFIG_CL_MFRC522) /**************************************************************************** * Pre-processor Definitions @@ -83,4 +83,4 @@ int stm32_mfrc522initialize(const char *devpath) return ret; } -#endif /* CONFIG_SPI && CONFIG_STM32H7_SPI4 && CONFIG_MFRC522 */ +#endif /* CONFIG_SPI && CONFIG_STM32_SPI4 && CONFIG_MFRC522 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c index b64a561aa2a..18b39f615b1 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM4 +#ifndef CONFIG_STM32_TIM4 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c index cf5467941e0..77db8bb8c3f 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "linum-stm32h753bi.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -89,7 +89,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -132,7 +132,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -140,4 +140,4 @@ int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c index 0ffbbc6e81a..76ff702a627 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c @@ -48,8 +48,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C3 -# error "FT5x06 support requires CONFIG_STM32H7_I2C3" +#ifndef CONFIG_STM32_I2C3 +# error "FT5x06 support requires CONFIG_STM32_I2C3" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c index 88b139eb458..884e370b0c9 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "linum-stm32h753bi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig index 9008dcbeb95..e73fc9f8fa8 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -67,19 +68,19 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig index bd2ea04db96..11f85e483ed 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,10 +46,10 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig index 314c36575b7..715f1f0df18 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -73,11 +74,11 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_SPI3=y -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING6=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt index f27901f9491..45813c92cc5 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGHS) +if(CONFIG_STM32_OTGHS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile b/boards/arm/stm32h7/nucleo-h723zg/src/Makefile index dedc375fb9c..f57fd57f306 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h723zg/src/Makefile @@ -38,11 +38,11 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H7_OTGHS),y) +ifeq ($(CONFIG_STM32_OTGHS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h index b9036604f88..4302c7eec2e 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h +++ b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h @@ -46,7 +46,7 @@ /* Can't support USB host or device features if USB OTG HS is not enabled */ -#ifndef CONFIG_STM32H7_OTGHS +#ifndef CONFIG_STM32_OTGHS # undef HAVE_USBDEV #endif @@ -74,7 +74,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -213,7 +213,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -250,7 +250,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS void weak_function stm32_usbinitialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c index 60de3707aae..1a4bc8d2eaf 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c @@ -48,8 +48,8 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -61,7 +61,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 15, 18, 19, 7, 12}; @@ -83,12 +83,12 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC123_INP12 }; -#endif /* CONFIG_STM32H7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ /**************************************************************************** * ADC2 ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_adc2_chanlist[ADC2_NCHANNELS] = { @@ -103,9 +103,9 @@ static const uint32_t g_adc2_pinlist[ADC2_NCHANNELS] = GPIO_ADC12_INP4, GPIO_ADC12_INP8 }; -#endif /* CONFIG_STM32H7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -146,7 +146,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -158,7 +158,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -190,7 +190,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC2_NCHANNELS; i++) @@ -222,7 +222,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -252,8 +252,8 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -265,5 +265,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c index 4b07cc70335..8caa51be221 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c index 445db3e6757..43d7a676c91 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c @@ -97,16 +97,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c index 8df03e00109..f8b200de768 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c index 23d61b098aa..0570f528631 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-h723zg.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -63,7 +63,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 spiinfo("Configure GPIO for SPI3/CS\n"); # ifdef CONFIG_NET_OA_TC6 @@ -101,7 +101,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -159,7 +159,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -173,7 +173,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -187,7 +187,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -225,42 +225,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -268,4 +268,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c index 2216484a508..953b452e86f 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c @@ -78,7 +78,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS stm32_configgpio(GPIO_OTGHS_VBUS); stm32_configgpio(GPIO_OTGHS_PWRON); stm32_configgpio(GPIO_OTGHS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig index 35961190575..2ffafc58713 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,9 +44,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CAP=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CAP=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig index 81c3cdcdab6..b36d0f21e25 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -75,10 +76,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_SPI3=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_USBMSC=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig index 2fa4212858e..27247352da0 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_DTCMEXCLUDE is not set +# CONFIG_STM32_DTCMEXCLUDE is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -54,9 +55,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y CONFIG_STM32_ROMFS=y CONFIG_STM32_ROMFS_IMAGEFILE="../../apps/examples/elf/main/elf_romfs.img" +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TLS_NELEM=4 diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig index 6966a2baf20..9be0478f7ea 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -73,18 +74,18 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_OVERRIDE_I=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig index 73d680b2e78..ac1dce20115 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,10 +56,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig index 67f590adaf0..ec57eb558ba 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig index 7fe65a420a1..788de2f32ef 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig index 7afab9a8915..8d9cdb06d9a 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -54,10 +55,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_NXBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig index 108860120e5..ceb8ba55d35 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,10 +57,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_NXBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig index 8f193c58d45..86c0aa28e5d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -59,8 +60,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig index 25861432828..5977b0463ba 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig index 36c6b375d46..e43edd2ca1d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,21 +46,21 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_CH1NOUT=y -CONFIG_STM32H7_TIM1_CH1OUT=y -CONFIG_STM32H7_TIM1_CH2NOUT=y -CONFIG_STM32H7_TIM1_CH2OUT=y -CONFIG_STM32H7_TIM1_CH3NOUT=y -CONFIG_STM32H7_TIM1_CH3OUT=y -CONFIG_STM32H7_TIM1_CH4OUT=y -CONFIG_STM32H7_TIM1_CHANNEL1=y -CONFIG_STM32H7_TIM1_CHANNEL2=y -CONFIG_STM32H7_TIM1_CHANNEL3=y -CONFIG_STM32H7_TIM1_CHANNEL4=y -CONFIG_STM32H7_TIM1_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3NOUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig index 9060c7e249b..914de95443f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -69,9 +70,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt index d4e92b8f5ed..4967d7e733d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt @@ -40,11 +40,11 @@ if(CONFIG_STM32_ROMFS) list(APPEND SRCS stm32_romfs_initialize.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -72,7 +72,7 @@ if(CONFIG_LCD_SSD1306) list(APPEND SRCS stm32_ssd1306.c) endif() -if(CONFIG_STM32H7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_progmem.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi/src/Makefile index 985900a61a9..bf54e0db6ef 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi/src/Makefile @@ -42,11 +42,11 @@ ifeq ($(CONFIG_STM32_ROMFS),y) CSRCS += stm32_romfs_initialize.c endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif @@ -74,7 +74,7 @@ ifeq ($(CONFIG_LCD_SSD1306),y) CSRCS += stm32_ssd1306.c endif -ifeq ($(CONFIG_STM32H7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CSRCS += stm32_progmem.c endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h index 4bcfe00d50b..2523adbe4a9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h +++ b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h @@ -47,7 +47,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -82,7 +82,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -251,7 +251,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -288,7 +288,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -302,7 +302,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c index a4ac81103a6..1b0a972921a 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c @@ -48,8 +48,8 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -61,7 +61,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 15, 18, 19, 7, 12}; @@ -83,12 +83,12 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC123_INP12 }; -#endif /* CONFIG_STM32H7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ /**************************************************************************** * ADC2 ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_adc2_chanlist[ADC2_NCHANNELS] = { @@ -103,9 +103,9 @@ static const uint32_t g_adc2_pinlist[ADC2_NCHANNELS] = GPIO_ADC12_INP4, GPIO_ADC12_INP8 }; -#endif /* CONFIG_STM32H7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -146,7 +146,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -158,7 +158,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -190,7 +190,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC2_NCHANNELS; i++) @@ -222,7 +222,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -252,8 +252,8 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -265,5 +265,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c index 17cfeed669d..70d9ebd007e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c index a8999a87a40..ac08dece22d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" #endif @@ -62,7 +62,7 @@ # include "stm32_capture.h" #endif -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG # include "stm32_wdg.h" #endif @@ -96,40 +96,40 @@ static int stm32_capture_setup(void) int ret; struct cap_lowerhalf_s *lower[] = { -#if defined(CONFIG_STM32H7_TIM1_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) stm32_cap_initialize(1), #endif -#if defined(CONFIG_STM32H7_TIM2_CAP) +#if defined(CONFIG_STM32_TIM2_CAP) stm32_cap_initialize(2), #endif -#if defined(CONFIG_STM32H7_TIM3_CAP) +#if defined(CONFIG_STM32_TIM3_CAP) stm32_cap_initialize(3), #endif -#if defined(CONFIG_STM32H7_TIM4_CAP) +#if defined(CONFIG_STM32_TIM4_CAP) stm32_cap_initialize(4), #endif -#if defined(CONFIG_STM32H7_TIM5_CAP) +#if defined(CONFIG_STM32_TIM5_CAP) stm32_cap_initialize(5), #endif -#if defined(CONFIG_STM32H7_TIM8_CAP) +#if defined(CONFIG_STM32_TIM8_CAP) stm32_cap_initialize(8), #endif -#if defined(CONFIG_STM32H7_TIM12_CAP) +#if defined(CONFIG_STM32_TIM12_CAP) stm32_cap_initialize(12), #endif -#if defined(CONFIG_STM32H7_TIM13_CAP) +#if defined(CONFIG_STM32_TIM13_CAP) stm32_cap_initialize(13), #endif -#if defined(CONFIG_STM32H7_TIM14_CAP) +#if defined(CONFIG_STM32_TIM14_CAP) stm32_cap_initialize(14), #endif -#if defined(CONFIG_STM32H7_TIM15_CAP) +#if defined(CONFIG_STM32_TIM15_CAP) stm32_cap_initialize(15), #endif -#if defined(CONFIG_STM32H7_TIM16_CAP) +#if defined(CONFIG_STM32_TIM16_CAP) stm32_cap_initialize(16), #endif -#if defined(CONFIG_STM32H7_TIM17_CAP) +#if defined(CONFIG_STM32_TIM17_CAP) stm32_cap_initialize(17), #endif /* TODO: LPTIMy_CAP */ @@ -216,16 +216,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } @@ -487,7 +487,7 @@ int stm32_bringup(void) #endif /* HAVE_PROGMEM_CHARDEV */ #endif /* CONFIG_MTD */ -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG /* Initialize the watchdog timer */ stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c index 6412aca6a93..6017b9b69ad 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM303AGR driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM303AGR driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -62,7 +62,7 @@ int stm32_lsm303agr_initialize(char *devpath) sninfo("INFO: Initializing LMS303AGR sensor over I2C\n"); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c index a7037b3c4cc..0d1e8807238 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM6DSL driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM6DSL driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -66,7 +66,7 @@ int stm32_lsm6dsl_initialize(char *devpath) stm32_configgpio(GPIO_LPS22HB_INT1); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c index 6f5276f12d6..bb50400bd61 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM9DS1 driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM9DS1 driver requires CONFIG_STM32_I2C1 to be enabled" #endif #define LSM9DS1MAG_DEVPATH "/dev/lsm9ds1mag0" @@ -66,7 +66,7 @@ int stm32_lsm9ds1_initialize(void) sninfo("Initializing LMS9DS1!\n"); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(LMS9DS1_I2CBUS); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c index 40dbe2fcbf4..7979ef412b8 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c @@ -44,7 +44,7 @@ # error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" #endif -#ifndef CONFIG_STM32H7_SPI3 +#ifndef CONFIG_STM32_SPI3 # error "MMC/SD requires SPI3 enabled" #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c index 0631fcba688..fba60268a2f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c index 04b75b9f41d..42f9a514fe6 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-h743zi.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -63,7 +63,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 spiinfo("Configure GPIO for SPI3/CS\n"); # ifdef CONFIG_WL_NRF24L01 @@ -108,7 +108,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -122,7 +122,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -136,7 +136,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -192,7 +192,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -206,7 +206,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -220,7 +220,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -258,42 +258,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -301,4 +301,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c index 3efae55c0f7..ed51bc58578 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h743zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig index 23c77196423..436b8c8c378 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -104,19 +105,19 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_TIM8=y -CONFIG_STM32H7_TIM8_PULSECOUNT=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_PULSECOUNT=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_INTBUFFER=y CONFIG_SYSLOG_PRIORITY=y CONFIG_SYSLOG_PROCESS_NAME=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig index 42df2d25cf2..c5bbd8b5b27 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig index 238e410712d..66ec35fe74b 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig index 1148378b855..2f4276ac9c9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig index 5eb5fce08d0..68c89eacc79 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -62,9 +63,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt index ce26e66e8cc..1d7544f8cdb 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt @@ -32,7 +32,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile index 9991b451550..f05dd5b891c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile @@ -38,7 +38,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h index ad98bd39fd3..6d63033cbb3 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -143,7 +143,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) # define NUCLEOH743ZI2_PWMTIMER 1 #else # define NUCLEOH743ZI2_PWMTIMER 3 @@ -175,7 +175,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -213,7 +213,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c index c11ea35b3f3..3d2ddaf2c32 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -91,7 +91,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -132,7 +132,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -144,7 +144,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -175,7 +175,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -217,5 +217,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c index be6710f36d0..36ad112abab 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c @@ -58,7 +58,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c index f0d0a7df159..f526cd6876b 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c @@ -35,11 +35,11 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -242,18 +242,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -264,7 +264,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -275,7 +275,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c index 51afc1e4447..943a4c4a884 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c index 547fda201e6..3b7a541084e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h743zi2.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h745zi/Kconfig b/boards/arm/stm32h7/nucleo-h745zi/Kconfig index bff59a18183..bdc477c0e39 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/Kconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/Kconfig @@ -11,7 +11,7 @@ choice config NUCLEOH745ZI_SMPS bool "Internal SMPS only (default)" - select STM32H7_PWR_DIRECT_SMPS_SUPPLY + select STM32_PWR_DIRECT_SMPS_SUPPLY config NUCLEOH745ZI_LDO bool "Internal LDO only" diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig index 4d056b4494f..66d8897395c 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -38,6 +39,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig index f404c9aca7c..f339a51f052 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig index a4a5abb06fc..5aed1797432 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,6 +43,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig index 32deeca5826..b64fcb0e0aa 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,7 +49,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_NSH=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig index 5876e49c1e4..2d7fa0de5d0 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld index c4bf2bd60d6..56c5da03c47 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld +++ b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld @@ -22,7 +22,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -40,7 +40,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K diff --git a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld index b24bcef0596..7c33bec3bd8 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile b/boards/arm/stm32h7/nucleo-h745zi/src/Makefile index df3be92d509..37c9b6b815d 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h745zi/src/Makefile @@ -34,7 +34,7 @@ else CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h index b3b16bee6f6..fa2747b2f48 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h +++ b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h @@ -47,7 +47,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -82,7 +82,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -226,7 +226,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) #define NUCLEOH745ZI_PWMTIMER 1 #else #define NUCLEOH745ZI_PWMTIMER 3 @@ -249,7 +249,7 @@ int stm32_bringup(void); -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -287,7 +287,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c index 7ab6b8a0331..cba9c51771b 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c @@ -49,9 +49,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -64,7 +64,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -92,7 +92,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -133,7 +133,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(int adcno) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -147,7 +147,7 @@ int stm32_adc_setup(int adcno) snprintf(devname, sizeof(devname), "/dev/adc%d", adcno); #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -178,7 +178,7 @@ int stm32_adc_setup(int adcno) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -208,7 +208,7 @@ int stm32_adc_setup(int adcno) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -220,5 +220,5 @@ int stm32_adc_setup(int adcno) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c index dfbbfecba2b..4e56b563eee 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c index a8e26a5b591..aa9ab6abbc6 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c @@ -144,11 +144,11 @@ int stm32_bringup(void) int adcno = 0; -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 adcno = 0; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 adcno = 2; #endif @@ -172,18 +172,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -194,7 +194,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -205,7 +205,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c index 1e34ac8a093..adeaaf3673c 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c index 77b5638be1f..c06f89ef35a 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h745zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig index e36ef998844..9f75e257f09 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,8 +48,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_CRYP=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_CRYP=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_CRYPTO=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig index 4482d9ba53b..64f82396477 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -103,17 +104,17 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSLOG_INTBUFFER=y CONFIG_SYSLOG_PRIORITY=y CONFIG_SYSLOG_PROCESS_NAME=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig index 6d3d69392c9..690987ab92f 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig index 4e017f8e0db..d4005fc697a 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig index 6851a571ec6..d6e87352352 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig index 602d566130d..f9643ef1a1a 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -62,9 +63,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt index 73ac7a500a7..8e61aeb5382 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt @@ -32,7 +32,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile b/boards/arm/stm32h7/nucleo-h753zi/src/Makefile index 0f164c5b1a4..e310e6c8a8e 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h753zi/src/Makefile @@ -38,7 +38,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h b/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h index 8549c8b633a..ff4a7a9380b 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h +++ b/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -143,7 +143,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) # define NUCLEOH753ZI_PWMTIMER 1 #else # define NUCLEOH753ZI_PWMTIMER 3 @@ -175,7 +175,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -213,7 +213,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c index 8bc9ba8841a..fca934607ef 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -91,7 +91,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -132,7 +132,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -144,7 +144,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -175,7 +175,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -217,5 +217,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c index 027cde005d7..d24de71d2ea 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c @@ -58,7 +58,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c index be030dcb4d2..805c1c46368 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c @@ -36,11 +36,11 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -218,18 +218,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -240,7 +240,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -251,7 +251,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c index 24eae1bc1cf..8898b9655fa 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c index 668f6ac2e23..73ddf89178f 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h753zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig index ad92a680c99..8bca8857583 100644 --- a/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -75,9 +76,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_SDMMC1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SDMMC1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig index 42eadf579ad..5cf6dd2376c 100644 --- a/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -72,11 +73,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGHS=y -CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_SYSCFG_IOCOMPENSATION=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/openh743i/configs/nsh/defconfig b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig index 51e03a5d33f..e3de0edfcde 100644 --- a/boards/arm/stm32h7/openh743i/configs/nsh/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,7 +43,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig index 5122941e7e5..6c37d27f4ad 100644 --- a/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,12 +56,12 @@ CONFIG_STACK_USAGE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_OTGFS_HOST=y -CONFIG_STM32H7_OTGHS=y -CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y -CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_OTGFS_HOST=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32_SYSCFG_IOCOMPENSATION=y CONFIG_SYSTEM_CDCACM=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=32 diff --git a/boards/arm/stm32h7/openh743i/src/CMakeLists.txt b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt index d6e3a6040cb..7e8e6aa2334 100644 --- a/boards/arm/stm32h7/openh743i/src/CMakeLists.txt +++ b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c) -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/openh743i/src/Makefile b/boards/arm/stm32h7/openh743i/src/Makefile index eda04e7c3af..c9f0115dbab 100644 --- a/boards/arm/stm32h7/openh743i/src/Makefile +++ b/boards/arm/stm32h7/openh743i/src/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/openh743i/src/openh743i.h b/boards/arm/stm32h7/openh743i/src/openh743i.h index 1645ce01182..ffab25f074b 100644 --- a/boards/arm/stm32h7/openh743i/src/openh743i.h +++ b/boards/arm/stm32h7/openh743i/src/openh743i.h @@ -105,7 +105,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SDMMC +#ifdef CONFIG_STM32_SDMMC int stm32_sdio_initialize(void); #endif @@ -118,7 +118,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif diff --git a/boards/arm/stm32h7/openh743i/src/stm32_boot.c b/boards/arm/stm32h7/openh743i/src/stm32_boot.c index df105a23b30..77c613755ab 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_boot.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_boot.c @@ -52,7 +52,7 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_OTGFS_HOST) || defined(CONFIG_STM32H7_OTGHS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) || defined(CONFIG_STM32H7_OTGHS_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/openh743i/src/stm32_bringup.c b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c index 1bf485416d9..a9dbd9ae9e7 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_bringup.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" #endif @@ -91,7 +91,7 @@ int stm32_bringup(void) usbdev_rndis_initialize(mac); #endif -#if defined(CONFIG_STM32H7_SDMMC) && !defined(CONFIG_CDCACM_CONSOLE) +#if defined(CONFIG_STM32_SDMMC) && !defined(CONFIG_CDCACM_CONSOLE) /* Initialize the SDIO block driver */ ret = stm32_sdio_initialize(); diff --git a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c index 600ace9250a..eb8a354de6a 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c @@ -45,13 +45,13 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC1 +#ifndef CONFIG_STM32_SDMMC1 # error SDMMC1 supported only #endif /* If IDMA is enabled, internal SRAM must be excluded from heap */ -#if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32H7_SDMMC_IDMA) +#if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32_SDMMC_IDMA) # error SDMMC1 with IDMA does not work CONFIG_MM_REGIONS > 1 #endif diff --git a/boards/arm/stm32h7/openh743i/src/stm32_usb.c b/boards/arm/stm32h7/openh743i/src/stm32_usb.c index 5e53687605c..59dbdf27b08 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_usb.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_usb.c @@ -44,7 +44,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_HOST) && defined(CONFIG_STM32_OTGHS_USBDEV) # ifndef CONFIG_OPENH743I_DISABLE_OTGFS_PWRON # error PWRON must be disabled for this configuration # endif @@ -121,7 +121,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); @@ -307,7 +307,7 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) uinfo("resume: %d\n", resume); } -#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /**************************************************************************** * Name: stm32_usbulpireset * diff --git a/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig b/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig index c8778936d3e..f324baba7d7 100644 --- a/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig +++ b/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="portenta-h7" CONFIG_ARCH_BOARD_PORTENTA_H7=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,9 +57,9 @@ CONFIG_SIGNAL_FD=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C1=y -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_I2CTOOL=y diff --git a/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig index e3c035673f4..8b65fcd4526 100644 --- a/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="portenta-h7" CONFIG_ARCH_BOARD_PORTENTA_H7=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,6 +43,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/portenta-h7/scripts/flash.ld b/boards/arm/stm32h7/portenta-h7/scripts/flash.ld index ad17d4464f0..b6cbb61a0c1 100644 --- a/boards/arm/stm32h7/portenta-h7/scripts/flash.ld +++ b/boards/arm/stm32h7/portenta-h7/scripts/flash.ld @@ -28,7 +28,7 @@ # define FLASH_START 0x08000000 #endif -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -46,7 +46,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = FLASH_START, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = FLASH_START, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K diff --git a/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld b/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld index c8122812f94..8627f095004 100644 --- a/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c b/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c index a61fab1bb64..cfbcb8fec4c 100644 --- a/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c +++ b/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c @@ -85,16 +85,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig index 5690c750d37..e1284a69ff0 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig @@ -6,15 +6,16 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_BOARD_STM32H745I_DISCO_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,15 +66,15 @@ CONFIG_SIG_DEFAULT=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_DMA2=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0x24020000 -CONFIG_STM32H7_LTDC_FB_SIZE=261120 -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0x24020000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TTY_SIGINT=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig index a8fe4e516ef..ea4a80f74f3 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig @@ -6,11 +6,12 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -63,19 +64,19 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_MII=y -CONFIG_STM32H7_PHYADDR=1 -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FMC=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYADDR=1 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig index c138b61ca01..28dcea36030 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -41,9 +42,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig index b1c3acf72f0..d4f0bbb49a9 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -38,9 +39,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_UART7=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_UART7=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART7_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig index d3dd2789880..35697fcdf37 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -43,7 +44,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig index e02a55c70a6..dcee32242f0 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,9 +43,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig index 52f90e5c3f8..9ee4b9596d6 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig index d187e442ce2..665a08ff3b2 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig @@ -6,12 +6,13 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_BOARD_STM32H745I_DISCO_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,10 +52,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/include/board.h b/boards/arm/stm32h7/stm32h745i-disco/include/board.h index 1593c65b032..4a60a547713 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/include/board.h +++ b/boards/arm/stm32h7/stm32h745i-disco/include/board.h @@ -343,7 +343,7 @@ #define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 100000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" diff --git a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld index e0f982d7c64..3ed5b169c6c 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld +++ b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld @@ -97,7 +97,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -115,7 +115,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K @@ -192,7 +192,7 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram -#ifdef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifdef CONFIG_STM32_CORTEXM4_ENABLED .shmem (NOLOAD): { . = ALIGN(4); diff --git a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld index 74787002507..98296d3ffd1 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt index 424170bc1a1..bb605d54ac7 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt @@ -28,7 +28,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -44,7 +44,7 @@ if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile b/boards/arm/stm32h7/stm32h745i-disco/src/Makefile index 59db9b7cd6a..13359572cb5 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile +++ b/boards/arm/stm32h7/stm32h745i-disco/src/Makefile @@ -30,7 +30,7 @@ else CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif @@ -46,7 +46,7 @@ ifeq ($(CONFIG_INPUT_FT5X06),y) CSRCS += stm32_ft5x06.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c index 24b15202874..24c252bc0cc 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c @@ -56,7 +56,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c index 5af6ac7f31f..def80baa810 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c @@ -35,7 +35,7 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c index df62ee84f7d..639db95d733 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c @@ -49,8 +49,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C4 -# error "FT5x06 support requires CONFIG_STM32H7_I2C4" +#ifndef CONFIG_STM32_I2C4 +# error "FT5x06 support requires CONFIG_STM32_I2C4" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c index 7a5b17ad617..eb02f937d6e 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c @@ -39,7 +39,7 @@ #include "stm32h745i_disco.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c index d08defcdbc5..07f43943a3e 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32h745i_disco.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h index 57ef2b05e63..5a2ec9fad06 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -184,7 +184,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -198,7 +198,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig index 43a7a87143c..3ddf480334a 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h747i-disco" CONFIG_ARCH_BOARD_STM32H747I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -44,7 +45,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt index 2aff1364c44..4583b43c5e7 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGHS) +if(CONFIG_STM32_OTGHS) list(APPEND SRCS stm32_usb.c) endif() @@ -48,7 +48,7 @@ if(CONFIG_BOARDCTL_UNIQUEID) list(APPEND SRCS stm32_uid.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile b/boards/arm/stm32h7/stm32h747i-disco/src/Makefile index 788e0f0d91f..2f0eaeee20f 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile +++ b/boards/arm/stm32h7/stm32h747i-disco/src/Makefile @@ -38,11 +38,11 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H7_OTGHS),y) +ifeq ($(CONFIG_STM32_OTGHS),y) CSRCS += stm32_usb.c endif @@ -50,7 +50,7 @@ ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) CSRCS += stm32_uid.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c index 89c9a723d69..de53c2b8742 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -87,7 +87,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -124,7 +124,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -136,7 +136,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -167,7 +167,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -197,7 +197,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -209,5 +209,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c index 595a6acb393..b994aaeeab1 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGHS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGHS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c index 84e93d0e997..12a8a37d4fd 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c @@ -90,16 +90,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c index a5885be43e0..b038469e60b 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "stm32h747i-disco.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -91,7 +91,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -105,7 +105,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -119,7 +119,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -157,7 +157,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -171,7 +171,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -209,42 +209,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -252,4 +252,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c index 7295b74cebe..84c95e9204b 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "stm32h747i-disco.h" -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS /**************************************************************************** * Pre-processor Definitions @@ -54,7 +54,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32H7_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -132,7 +132,7 @@ void stm32_usbinitialize(void) { /* Configure the Overcurrent GPIO */ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS stm32_configgpio(GPIO_OTGHS_OVER); #endif } diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h b/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h index c53bb6f8a76..e1e5d28eedf 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h @@ -95,7 +95,7 @@ /* SD/TF Card'detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -129,7 +129,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig b/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig index f4913aa50bb..66fe8ef9f05 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig @@ -6,14 +6,15 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h750b-dk" CONFIG_ARCH_BOARD_STM32H750B_DK=y CONFIG_ARCH_BOARD_STM32H750B_DK_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750XB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -67,14 +68,14 @@ CONFIG_SIG_DEFAULT=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_DMA2=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0xd0000000 -CONFIG_STM32H7_LTDC_FB_SIZE=522240 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xd0000000 +CONFIG_STM32_LTDC_FB_SIZE=522240 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TTY_SIGINT=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h750b-dk/include/board.h b/boards/arm/stm32h7/stm32h750b-dk/include/board.h index c63ca3b3fdc..62830d321eb 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/include/board.h +++ b/boards/arm/stm32h7/stm32h750b-dk/include/board.h @@ -340,7 +340,7 @@ #define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 100000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" diff --git a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld index eae68e2f5a1..d08b0b9d475 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld +++ b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld @@ -95,7 +95,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -114,7 +114,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K @@ -191,7 +191,7 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram -#ifdef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifdef CONFIG_STM32_CORTEXM4_ENABLED .shmem (NOLOAD): { . = ALIGN(4); diff --git a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld index ed39a30ec56..d6f3372fd37 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld @@ -20,9 +20,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -32,7 +32,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt index d89067b817f..4424e927661 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt @@ -26,7 +26,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -42,7 +42,7 @@ if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile b/boards/arm/stm32h7/stm32h750b-dk/src/Makefile index 7dec83d2100..942bfb9fd3e 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile +++ b/boards/arm/stm32h7/stm32h750b-dk/src/Makefile @@ -28,7 +28,7 @@ else CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif @@ -44,7 +44,7 @@ ifeq ($(CONFIG_INPUT_FT5X06),y) CSRCS += stm32_ft5x06.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c index 0095a26c9b8..414344c964a 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c index a7200dffe19..8282101411b 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c @@ -33,7 +33,7 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c index e719e3ac6fd..72e3d357b34 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c @@ -47,8 +47,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C4 -# error "FT5x06 support requires CONFIG_STM32H7_I2C4" +#ifndef CONFIG_STM32_I2C4 +# error "FT5x06 support requires CONFIG_STM32_I2C4" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c index de3e72c627f..9ffca9632b1 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c @@ -37,7 +37,7 @@ #include "stm32h750b-dk.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c index 882307c6985..50d12205e65 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c @@ -43,7 +43,7 @@ #include "stm32h750b-dk.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -136,7 +136,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h index 5e0e6b7f2de..ff114ac8193 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h @@ -42,7 +42,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -182,7 +182,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -196,7 +196,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig index 3a3b4caf7f8..3ed170d4cce 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig index bb9f06926d9..52d6fd71d4d 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -58,10 +59,10 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig index 5aedb0aecee..fc9b8d1a017 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,8 +56,8 @@ CONFIG_SPI_CMDDATA=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig index 53715932255..e2a79412f1c 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,9 +48,9 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt index af3c82ac515..6f41b679d00 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt +++ b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt @@ -34,7 +34,7 @@ if(CONFIG_VIDEO_FB) endif() endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/weact-stm32h743/src/Makefile b/boards/arm/stm32h7/weact-stm32h743/src/Makefile index 3d686ef415e..0bbd3d18694 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/Makefile +++ b/boards/arm/stm32h7/weact-stm32h743/src/Makefile @@ -36,7 +36,7 @@ ifeq ($(CONFIG_VIDEO_FB),y) endif endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c index 4c09ec8ce10..6173d41518e 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c index a11654bc8fa..91513bcf091 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c @@ -87,7 +87,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -130,7 +130,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_ST7735 diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c index eb46659de26..4aff43a107a 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "weact-stm32h743.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h index 34f91044d7e..c97eb79129b 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h +++ b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h @@ -53,7 +53,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -88,7 +88,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -131,7 +131,7 @@ * PD4 Card detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig index 70ab99d673a..edb8697b24e 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,7 +43,7 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig index d1fa7662bd6..ffe5056a984 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -59,10 +60,10 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig index 5098495e7f2..df870df8aef 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,8 +57,8 @@ CONFIG_SPI_CMDDATA=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig index f8e8e730321..bb2110e2862 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt index 6c5220cccc2..2d990344622 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt +++ b/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt @@ -34,15 +34,15 @@ if(CONFIG_VIDEO_FB) endif() endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/weact-stm32h750/src/Makefile b/boards/arm/stm32h7/weact-stm32h750/src/Makefile index 80033455ab3..083f46024de 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/Makefile +++ b/boards/arm/stm32h7/weact-stm32h750/src/Makefile @@ -36,7 +36,7 @@ ifeq ($(CONFIG_VIDEO_FB),y) endif endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c index 34102ce9f2d..4c9423b7a3b 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c index 226882d0e6c..46b87280b62 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c @@ -87,7 +87,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -130,7 +130,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_ST7735 diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c index ca8e4cbab7b..506bb238ed0 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "weact-stm32h750.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h b/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h index ecf03db7907..26c286a16b3 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h +++ b/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h @@ -53,7 +53,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -88,7 +88,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -131,7 +131,7 @@ * PD4 Card detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif