From 60dffa100433f5c2a5b415d1b019810a238f8e34 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:44 +0200 Subject: [PATCH] !arm/stm32l5: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32L5 interfaces were renamed from stm32l5_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names in STM32L5 timer/GPIO/EXTI and related API-facing declarations were normalized to stm32_* equivalents. The STM32L5 root family header was renamed from stm32l5.h to stm32.h; all STM32L5 arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32l5/{stm32l5.h => stm32.h} | 2 +- arch/arm/src/stm32l5/stm32l562xx_rcc.c | 18 +- arch/arm/src/stm32l5/stm32l5_allocateheap.c | 8 +- arch/arm/src/stm32l5/stm32l5_dumpgpio.c | 4 +- arch/arm/src/stm32l5/stm32l5_exti.h | 16 +- arch/arm/src/stm32l5/stm32l5_exti_gpio.c | 10 +- arch/arm/src/stm32l5/stm32l5_flash.c | 16 +- arch/arm/src/stm32l5/stm32l5_flash.h | 8 +- arch/arm/src/stm32l5/stm32l5_gpio.c | 28 +- arch/arm/src/stm32l5/stm32l5_gpio.h | 36 +- arch/arm/src/stm32l5/stm32l5_irq.c | 40 +- arch/arm/src/stm32l5/stm32l5_lowputc.c | 20 +- arch/arm/src/stm32l5/stm32l5_lowputc.h | 4 +- arch/arm/src/stm32l5/stm32l5_lse.c | 10 +- arch/arm/src/stm32l5/stm32l5_lsi.c | 8 +- arch/arm/src/stm32l5/stm32l5_mpuinit.c | 8 +- arch/arm/src/stm32l5/stm32l5_mpuinit.h | 12 +- arch/arm/src/stm32l5/stm32l5_pwr.c | 44 +- arch/arm/src/stm32l5/stm32l5_pwr.h | 14 +- arch/arm/src/stm32l5/stm32l5_rcc.c | 28 +- arch/arm/src/stm32l5/stm32l5_rcc.h | 42 +- arch/arm/src/stm32l5/stm32l5_serial.c | 204 ++++---- arch/arm/src/stm32l5/stm32l5_spi.c | 184 +++---- arch/arm/src/stm32l5/stm32l5_spi.h | 48 +- arch/arm/src/stm32l5/stm32l5_start.c | 12 +- arch/arm/src/stm32l5/stm32l5_start.h | 4 +- arch/arm/src/stm32l5/stm32l5_tim.c | 460 +++++++++--------- arch/arm/src/stm32l5/stm32l5_tim.h | 54 +- arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c | 110 ++--- arch/arm/src/stm32l5/stm32l5_timerisr.c | 8 +- arch/arm/src/stm32l5/stm32l5_uart.h | 4 +- arch/arm/src/stm32l5/stm32l5_uid.c | 2 +- arch/arm/src/stm32l5/stm32l5_uid.h | 2 +- arch/arm/src/stm32l5/stm32l5_userspace.c | 6 +- arch/arm/src/stm32l5/stm32l5_userspace.h | 4 +- arch/arm/src/stm32l5/stm32l5_waste.c | 2 +- arch/arm/src/stm32l5/stm32l5_waste.h | 4 +- .../arm/stm32l5/nucleo-l552ze/include/board.h | 4 +- .../nucleo-l552ze/src/stm32_autoleds.c | 4 +- .../stm32l5/nucleo-l552ze/src/stm32_boot.c | 12 +- .../stm32l5/nucleo-l552ze/src/stm32_buttons.c | 6 +- .../nucleo-l552ze/src/stm32_userleds.c | 6 +- .../arm/stm32l5/stm32l562e-dk/include/board.h | 4 +- .../stm32l562e-dk/src/stm32_autoleds.c | 4 +- .../stm32l5/stm32l562e-dk/src/stm32_boot.c | 6 +- .../stm32l5/stm32l562e-dk/src/stm32_buttons.c | 6 +- .../stm32l562e-dk/src/stm32_clockconfig.c | 2 +- .../stm32l562e-dk/src/stm32_userleds.c | 6 +- 48 files changed, 772 insertions(+), 772 deletions(-) rename arch/arm/src/stm32l5/{stm32l5.h => stm32.h} (98%) diff --git a/arch/arm/src/stm32l5/stm32l5.h b/arch/arm/src/stm32l5/stm32.h similarity index 98% rename from arch/arm/src/stm32l5/stm32l5.h rename to arch/arm/src/stm32l5/stm32.h index 7cedda9b78c..da1a85b295c 100644 --- a/arch/arm/src/stm32l5/stm32l5.h +++ b/arch/arm/src/stm32l5/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l5/stm32l5.h + * arch/arm/src/stm32l5/stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l5/stm32l562xx_rcc.c b/arch/arm/src/stm32l5/stm32l562xx_rcc.c index 39636e57719..50591f093a3 100644 --- a/arch/arm/src/stm32l5/stm32l562xx_rcc.c +++ b/arch/arm/src/stm32l5/stm32l562xx_rcc.c @@ -575,10 +575,10 @@ static inline void rcc_enableccip(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals ****************************************************************************/ -void stm32l5_rcc_enableperipherals(void) +void stm32_rcc_enableperipherals(void) { rcc_enableccip(); rcc_enableahb1(); @@ -589,7 +589,7 @@ void stm32l5_rcc_enableperipherals(void) } /**************************************************************************** - * Name: stm32l5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -599,7 +599,7 @@ void stm32l5_rcc_enableperipherals(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG -void stm32l5_stdclockconfig(void) +void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -687,7 +687,7 @@ void stm32l5_stdclockconfig(void) } #else -# error stm32l5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -704,7 +704,7 @@ void stm32l5_stdclockconfig(void) /* Ensure Power control is enabled before modifying it. */ - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* Select correct main regulator range */ @@ -901,7 +901,7 @@ void stm32l5_stdclockconfig(void) #if defined(CONFIG_STM32L5_IWDG) || defined(CONFIG_STM32L5_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l5_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -916,7 +916,7 @@ void stm32l5_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -927,7 +927,7 @@ void stm32l5_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l5_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ diff --git a/arch/arm/src/stm32l5/stm32l5_allocateheap.c b/arch/arm/src/stm32l5/stm32l5_allocateheap.c index 5547109564e..d2c56c99527 100644 --- a/arch/arm/src/stm32l5/stm32l5_allocateheap.c +++ b/arch/arm/src/stm32l5/stm32l5_allocateheap.c @@ -240,7 +240,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32l5_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -318,7 +318,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2 heap */ - stm32l5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif @@ -338,7 +338,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM3 heap */ - stm32l5_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); + stm32_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); #endif @@ -357,7 +357,7 @@ void arm_addregion(void) /* Allow user-mode access to the FSMC SRAM user heap memory */ - stm32l5_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c index f5dc0ed6ce7..cf5760c43f6 100644 --- a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c +++ b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c @@ -86,14 +86,14 @@ static const char g_portchar[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32l5_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; diff --git a/arch/arm/src/stm32l5/stm32l5_exti.h b/arch/arm/src/stm32l5/stm32l5_exti.h index 7093f76a75e..b64a8055015 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/stm32l5_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32l5_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l5_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l5_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -142,7 +142,7 @@ int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_STM32L5_COMP -int stm32l5_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c index 67a6a051e23..10e1099e0ec 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c @@ -67,7 +67,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routine - Dispatcher ****************************************************************************/ -static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) +static int stm32_exti0_15_isr(int irq, void *context, void *arg) { int ret = OK; int exti; @@ -98,7 +98,7 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -120,7 +120,7 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { uint32_t pin = pinset & GPIO_PIN_MASK; @@ -134,7 +134,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (func) { - irq_attach(irq, stm32l5_exti0_15_isr, NULL); + irq_attach(irq, stm32_exti0_15_isr, NULL); up_enable_irq(irq); } else @@ -151,7 +151,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32l5_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index d7d9915e709..8f9625bb34c 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -107,7 +107,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_LOCK) @@ -156,7 +156,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); @@ -166,14 +166,14 @@ static inline void flash_erase(size_t page) * Public Functions ****************************************************************************/ -void stm32l5_flash_unlock(void) +void stm32_flash_unlock(void) { nxmutex_lock(&g_lock); flash_unlock(); nxmutex_unlock(&g_lock); } -void stm32l5_flash_lock(void) +void stm32_flash_lock(void) { nxmutex_lock(&g_lock); flash_lock(); @@ -181,7 +181,7 @@ void stm32l5_flash_lock(void) } /**************************************************************************** - * Name: stm32l5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -197,7 +197,7 @@ void stm32l5_flash_lock(void) * ****************************************************************************/ -uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; @@ -229,7 +229,7 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -431,7 +431,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32l5/stm32l5_flash.h b/arch/arm/src/stm32l5/stm32l5_flash.h index 0a3f7076c90..81d15ed8a13 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/stm32l5_flash.h @@ -34,11 +34,11 @@ * Public Function Prototypes ****************************************************************************/ -void stm32l5_flash_lock(void); -void stm32l5_flash_unlock(void); +void stm32_flash_lock(void); +void stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32l5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -54,6 +54,6 @@ void stm32l5_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c index 2d9afa34849..297a5deb182 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_gpio.c @@ -91,13 +91,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l5_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -105,17 +105,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32l5_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32l5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -126,7 +126,7 @@ void stm32l5_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32l5_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -169,7 +169,7 @@ int stm32l5_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32l5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -304,7 +304,7 @@ int stm32l5_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32l5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -324,7 +324,7 @@ int stm32l5_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32l5_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -333,18 +333,18 @@ int stm32l5_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32l5_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32l5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l5_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -378,14 +378,14 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32l5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l5_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h index 2bb1f035651..16caeb1a50e 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/stm32l5_gpio.h @@ -49,7 +49,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32l5_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -248,12 +248,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -262,10 +262,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32l5_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -284,30 +284,30 @@ int stm32l5_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32l5_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l5_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32l5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l5_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -326,11 +326,11 @@ bool stm32l5_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32l5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -338,23 +338,23 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32l5_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32l5_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32l5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l5_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32l5_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index f42f2dda2ab..46195910a0c 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32l5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32l5_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -112,11 +112,11 @@ static void stm32l5_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32l5_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32l5_nmi, stm32l5_pendsv, stm32l5_pendsv, stm32l5_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -126,7 +126,7 @@ static void stm32l5_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32l5_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -134,7 +134,7 @@ static int stm32l5_nmi(int irq, void *context, void *arg) return 0; } -static int stm32l5_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -142,7 +142,7 @@ static int stm32l5_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32l5_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -152,7 +152,7 @@ static int stm32l5_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l5_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -160,7 +160,7 @@ static int stm32l5_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32l5_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -173,7 +173,7 @@ static inline void stm32l5_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32l5_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -181,7 +181,7 @@ static inline void stm32l5_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -309,7 +309,7 @@ void up_irqinitialize(void) #endif - stm32l5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -323,19 +323,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32l5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32l5_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32l5_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32l5_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -360,7 +360,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l5_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -395,7 +395,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l5_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -472,7 +472,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32l5_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.c b/arch/arm/src/stm32l5/stm32l5_lowputc.c index 6229979f9a2..d10ce831abf 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.c +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.c @@ -33,7 +33,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_rcc.h" #include "stm32l5_gpio.h" #include "stm32l5_uart.h" @@ -308,7 +308,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -319,7 +319,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -327,7 +327,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32l5_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -336,7 +336,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32l5_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -352,19 +352,19 @@ void stm32l5_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32l5_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32l5_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32l5_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32l5_configgpio(STM32_CONSOLE_RS485_DIR); - stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.h b/arch/arm/src/stm32l5/stm32l5_lowputc.h index 29e808377c3..c3e60eb22ae 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.h +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l5_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. Performs low level @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index f3e6827279b..e89c3a1887b 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -68,14 +68,14 @@ static const uint32_t drives[4] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator and the LSE system clock. * ****************************************************************************/ -void stm32l5_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { bool writable; uint32_t regval; @@ -100,7 +100,7 @@ void stm32l5_rcc_enablelse(void) * the PWR CR register before to configuring the LSE. */ - writable = stm32l5_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON * bit the RCC BDCR register. @@ -173,7 +173,7 @@ void stm32l5_rcc_enablelse(void) while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { - stm32l5_waste(); + stm32_waste(); } } @@ -188,6 +188,6 @@ void stm32l5_rcc_enablelse(void) /* Disable backup domain access if it was disabled on entry */ - stm32l5_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c index a47bd5ea1dd..6d57b07aac4 100644 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ b/arch/arm/src/stm32l5/stm32l5_lsi.c @@ -33,14 +33,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -54,14 +54,14 @@ void stm32l5_rcc_enablelsi(void) } /**************************************************************************** - * Name: stm32l5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32l5/stm32l5_mpuinit.c b/arch/arm/src/stm32l5/stm32l5_mpuinit.c index 94d42c795ae..2c70971fdde 100644 --- a/arch/arm/src/stm32l5/stm32l5_mpuinit.c +++ b/arch/arm/src/stm32l5/stm32l5_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32l5_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32l5_mpuinitialize(void) } /**************************************************************************** - * Name: stm32l5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32l5_mpuinitialize(void) * ****************************************************************************/ -void stm32l5_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32l5/stm32l5_mpuinit.h b/arch/arm/src/stm32l5/stm32l5_mpuinit.h index 94ee60dc285..d31d148496d 100644 --- a/arch/arm/src/stm32l5/stm32l5_mpuinit.h +++ b/arch/arm/src/stm32l5/stm32l5_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32l5_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32l5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32l5_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32l5_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.c b/arch/arm/src/stm32l5/stm32l5_pwr.c index 3b306923e8e..90ac2900f6b 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.c +++ b/arch/arm/src/stm32l5/stm32l5_pwr.c @@ -39,12 +39,12 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32l5_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } @@ -70,7 +70,7 @@ static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) * ****************************************************************************/ -bool stm32l5_pwr_enableclk(bool enable) +bool stm32_pwr_enableclk(bool enable) { uint32_t regval; bool wasenabled; @@ -99,7 +99,7 @@ bool stm32l5_pwr_enableclk(bool enable) } /**************************************************************************** - * Name: stm32l5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -113,14 +113,14 @@ bool stm32l5_pwr_enableclk(bool enable) * ****************************************************************************/ -bool stm32l5_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32L5 PWR control register 1 */ - regval = stm32l5_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -148,7 +148,7 @@ bool stm32l5_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32l5_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -163,7 +163,7 @@ bool stm32l5_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32l5_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; @@ -174,12 +174,12 @@ bool stm32l5_pwr_enableusv(bool set) if (!was_clk_enabled) { - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,26 +189,26 @@ bool stm32l5_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l5_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l5_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -223,7 +223,7 @@ bool stm32l5_pwr_enableusv(bool set) * ****************************************************************************/ -bool stm32l5_pwr_vddio2_valid(bool set) +bool stm32_pwr_vddio2_valid(bool set) { uint32_t regval; bool was_set; @@ -234,12 +234,12 @@ bool stm32l5_pwr_vddio2_valid(bool set) if (!was_clk_enabled) { - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -249,19 +249,19 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l5_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.h b/arch/arm/src/stm32l5/stm32l5_pwr.h index 611eaf8e001..637150d65c1 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/stm32l5_pwr.h @@ -70,10 +70,10 @@ extern "C" * ****************************************************************************/ -bool stm32l5_pwr_enableclk(bool enable); +bool stm32_pwr_enableclk(bool enable); /**************************************************************************** - * Name: stm32l5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -87,10 +87,10 @@ bool stm32l5_pwr_enableclk(bool enable); * ****************************************************************************/ -bool stm32l5_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32l5_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -105,10 +105,10 @@ bool stm32l5_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32l5_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** - * Name: stm32l5_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -123,7 +123,7 @@ bool stm32l5_pwr_enableusv(bool set); * ****************************************************************************/ -bool stm32l5_pwr_vddio2_valid(bool set); +bool stm32_pwr_vddio2_valid(bool set); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index 8164097f5a0..d0a29a8c2c6 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -37,7 +37,7 @@ #include "chip.h" #include "stm32l5_rcc.h" #include "stm32l5_flash.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_waste.h" /**************************************************************************** @@ -90,7 +90,7 @@ static inline void rcc_resetbkp(void) /* Check if the RTC is already configured */ - init_stat = stm32l5_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -107,7 +107,7 @@ static inline void rcc_resetbkp(void) * backup data registers and backup SRAM). */ - stm32l5_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -128,7 +128,7 @@ static inline void rcc_resetbkp(void) putreg32(bkregs[i], STM32_RTC_BKR(i)); } - stm32l5_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -150,7 +150,7 @@ static inline void rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -160,7 +160,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32l5_clockconfig(void) +void stm32_clockconfig(void) { #if 0 /* Make sure that we are starting in the reset state */ @@ -175,7 +175,7 @@ void stm32l5_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32l5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -183,13 +183,13 @@ void stm32l5_clockconfig(void) * board.h */ - stm32l5_stdclockconfig(); + stm32_stdclockconfig(); #endif /* Enable peripheral clocking */ - stm32l5_rcc_enableperipherals(); + stm32_rcc_enableperipherals(); } /**************************************************************************** @@ -202,12 +202,12 @@ void stm32l5_clockconfig(void) * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32l5_clockconfig() + * stm32_clockconfig() * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -218,13 +218,13 @@ void stm32l5_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32l5_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32l5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -232,7 +232,7 @@ void stm32l5_clockenable(void) * board.h */ - stm32l5_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index 5157e85ce53..0b3f4a7740a 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -58,7 +58,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32l562xx @@ -75,7 +75,7 @@ extern "C" * ****************************************************************************/ -static inline void stm32l5_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; @@ -92,7 +92,7 @@ static inline void stm32l5_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -102,7 +102,7 @@ static inline void stm32l5_mcoconfig(uint32_t source) * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -112,10 +112,10 @@ static inline void stm32l5_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32l5_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32l5_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32L5 board may replace the "standard" board clock configuration @@ -124,11 +124,11 @@ void stm32l5_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG -void stm32l5_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32l5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * The standard logic to configure the clocks based on settings in board.h. @@ -139,11 +139,11 @@ void stm32l5_board_clockconfig(void); ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG -void stm32l5_stdclockconfig(void); +void stm32_stdclockconfig(void); #endif /**************************************************************************** - * Name: stm32l5_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -152,12 +152,12 @@ void stm32l5_stdclockconfig(void); * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32l5_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -168,11 +168,11 @@ void stm32l5_stdclockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32l5_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32l5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -185,30 +185,30 @@ void stm32l5_clockenable(void); * ****************************************************************************/ -void stm32l5_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32l5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32l5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); /**************************************************************************** - * Name: stm32l5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals * * Description: * Enable all the chip peripherals according to configuration. This is @@ -217,7 +217,7 @@ void stm32l5_rcc_disablelsi(void); * ****************************************************************************/ -void stm32l5_rcc_enableperipherals(void); +void stm32_rcc_enableperipherals(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index e39dad2f74e..ea07188a10c 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -212,7 +212,7 @@ * Private Types ****************************************************************************/ -struct stm32l5_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -327,9 +327,9 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev); static void stm32l5serial_dmashutdown(struct uart_dev_s *dev); static int stm32l5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv); +static void stm32l5serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv); +static bool stm32l5serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev); @@ -446,7 +446,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER -static struct stm32l5_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -506,7 +506,7 @@ static struct stm32l5_serial_s g_lpuart1priv = #endif #ifdef CONFIG_STM32L5_USART1_SERIALDRIVER -static struct stm32l5_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -568,7 +568,7 @@ static struct stm32l5_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ #ifdef CONFIG_STM32L5_USART2_SERIALDRIVER -static struct stm32l5_serial_s g_usart2priv = +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -630,7 +630,7 @@ static struct stm32l5_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ #ifdef CONFIG_STM32L5_USART3_SERIALDRIVER -static struct stm32l5_serial_s g_usart3priv = +static struct stm32_serial_s g_usart3priv = { .dev = { @@ -692,7 +692,7 @@ static struct stm32l5_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ #ifdef CONFIG_STM32L5_UART4_SERIALDRIVER -static struct stm32l5_serial_s g_uart4priv = +static struct stm32_serial_s g_uart4priv = { .dev = { @@ -754,7 +754,7 @@ static struct stm32l5_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ #ifdef CONFIG_STM32L5_UART5_SERIALDRIVER -static struct stm32l5_serial_s g_uart5priv = +static struct stm32_serial_s g_uart5priv = { .dev = { @@ -815,7 +815,7 @@ static struct stm32l5_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32l5_serial_s * const +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER @@ -862,7 +862,7 @@ static struct serialpm_s g_serialpm = ****************************************************************************/ static inline -uint32_t stm32l5serial_getreg(struct stm32l5_serial_s *priv, int offset) +uint32_t stm32l5serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -872,7 +872,7 @@ uint32_t stm32l5serial_getreg(struct stm32l5_serial_s *priv, int offset) ****************************************************************************/ static inline -void stm32l5serial_putreg(struct stm32l5_serial_s *priv, +void stm32l5serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -883,7 +883,7 @@ void stm32l5serial_putreg(struct stm32l5_serial_s *priv, ****************************************************************************/ static inline -void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, +void stm32l5serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -911,7 +911,7 @@ void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, * Name: up_restoreusartint ****************************************************************************/ -static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, +static void stm32l5serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -927,7 +927,7 @@ static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, * Name: stm32l5serial_disableusartint ****************************************************************************/ -static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, +static void stm32l5serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -988,11 +988,11 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32l5serial_dmanextrx(struct stm32l5_serial_s *priv) +static int stm32l5serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32l5_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -1009,8 +1009,8 @@ static int stm32l5serial_dmanextrx(struct stm32l5_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32l5serial_setformat(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* This first implementation is for U[S]ARTs that support oversampling @@ -1140,7 +1140,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_DMA bool dmarestored = false; #endif @@ -1159,7 +1159,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32l5_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -1188,7 +1188,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32l5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1229,7 +1229,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32l5_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1278,7 +1278,7 @@ static void stm32l5serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1304,8 +1304,8 @@ static void stm32l5serial_pm_setsuspend(bool suspend) static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1376,14 +1376,14 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32l5serial_setup(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32l5_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1394,18 +1394,18 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l5_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l5_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1419,15 +1419,15 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32l5_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_configgpio(priv->rs485_dir_gpio); - stm32l5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1502,8 +1502,8 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static int stm32l5serial_dmasetup(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1520,14 +1520,14 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32l5_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1538,7 +1538,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1565,7 +1565,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, false); } else @@ -1576,7 +1576,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, true); } @@ -1595,8 +1595,8 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) static void stm32l5serial_shutdown(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1627,32 +1627,32 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l5_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l5_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l5_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32l5_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1669,8 +1669,8 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1678,11 +1678,11 @@ static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32l5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32l5_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1705,8 +1705,8 @@ static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) static int stm32l5serial_attach(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1737,8 +1737,8 @@ static int stm32l5serial_attach(struct uart_dev_s *dev) static void stm32l5serial_detach(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1757,7 +1757,7 @@ static void stm32l5serial_detach(struct uart_dev_s *dev) static int stm32l5serial_interrupt(int irq, void *context, void *arg) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1817,7 +1817,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32l5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32l5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1883,8 +1883,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1893,9 +1893,9 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32l5_serial_s *user; + struct stm32_serial_s *user; - user = (struct stm32l5_serial_s *)arg; + user = (struct stm32_serial_s *)arg; if (!user) { @@ -1903,7 +1903,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, } else { - memcpy(user, dev, sizeof(struct stm32l5_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -1958,7 +1958,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1969,7 +1969,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32l5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -2195,7 +2195,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32l5_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -2212,7 +2212,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -2275,8 +2275,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, static int stm32l5serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ @@ -2305,8 +2305,8 @@ static int stm32l5serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32l5serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2365,8 +2365,8 @@ static void stm32l5serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); @@ -2400,8 +2400,8 @@ static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) @@ -2409,7 +2409,7 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32l5_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2484,8 +2484,8 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32l5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32l5serial_dmanextrx(priv) != priv->rxdmanext) @@ -2523,14 +2523,14 @@ static int stm32l5serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) -static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) +static void stm32l5serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2541,7 +2541,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2562,7 +2562,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) * in and DMA transfer is stopped. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, false); } else @@ -2573,7 +2573,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, true); } @@ -2594,7 +2594,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv) +static bool stm32l5serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2645,8 +2645,8 @@ static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv) #ifdef SERIAL_HAVE_DMA static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2680,8 +2680,8 @@ static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_DMA static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2701,13 +2701,13 @@ static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev) static void stm32l5serial_send(struct uart_dev_s *dev, int ch) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif @@ -2724,8 +2724,8 @@ static void stm32l5serial_send(struct uart_dev_s *dev, int ch) static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; /* USART transmit interrupts: @@ -2793,8 +2793,8 @@ static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32l5serial_txready(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); @@ -2813,7 +2813,7 @@ static bool stm32l5serial_txready(struct uart_dev_s *dev) static void stm32l5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32l5serial_dmarxavailable(&priv->dev)) { @@ -2971,7 +2971,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32l5_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -2980,7 +2980,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -3144,7 +3144,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32l5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -3155,7 +3155,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32l5_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -3218,7 +3218,7 @@ void stm32l5_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32l5_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32l5serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index 6fc62e9eaab..c1a374c8b91 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32l5_spi1/2/3select and stm32l5_spi1/2/3status + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32l5_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l5_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l5_spi1/2/3select() and stm32l5_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your board * is configured. - * 3. Add a calls to stm32l5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l5_spibus_initialize() may then be used to + * 4. The handle returned by stm32_spibus_initialize() may then be used to * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -74,7 +74,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #ifdef CONFIG_STM32L5_SPI_DMA # include "stm32l5_dma.h" @@ -135,7 +135,7 @@ * Private Types ****************************************************************************/ -struct stm32l5_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -176,34 +176,34 @@ struct stm32l5_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32l5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv); -static inline void spi_writeword(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmarxwait(struct stm32l5_spidev_s *priv); -static void spi_dmatxwait(struct stm32l5_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv); +static void spi_dmarxwait(struct stm32_spidev_s *priv); +static void spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -234,7 +234,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32l5_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -251,16 +251,16 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32l5_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -273,13 +273,13 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -309,16 +309,16 @@ static struct stm32l5_spidev_s g_spi1dev = static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32l5_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -331,13 +331,13 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { @@ -365,16 +365,16 @@ static struct stm32l5_spidev_s g_spi2dev = static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, - .select = stm32l5_spi3select, + .select = stm32_spi3select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi3status, + .status = stm32_spi3status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi3cmddata, + .cmddata = stm32_spi3cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -387,13 +387,13 @@ static const struct spi_ops_s g_spi3ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi3register, /* provided externally */ + .registercallback = stm32_spi3register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi3dev = +static struct stm32_spidev_s g_spi3dev = { .spidev = { @@ -436,7 +436,7 @@ static struct stm32l5_spidev_s g_spi3dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -458,7 +458,7 @@ static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32l5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -479,7 +479,7 @@ static inline void spi_putreg(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32l5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -498,7 +498,7 @@ static inline uint8_t spi_getreg8(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32l5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -518,7 +518,7 @@ static inline void spi_putreg8(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -543,7 +543,7 @@ static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -569,7 +569,7 @@ static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32l5_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -596,7 +596,7 @@ static inline void spi_writeword(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32l5_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ @@ -622,7 +622,7 @@ static inline void spi_writebyte(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -636,7 +636,7 @@ static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmarxwait(struct stm32l5_spidev_s *priv) +static void spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -667,7 +667,7 @@ static void spi_dmarxwait(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmatxwait(struct stm32l5_spidev_s *priv) +static void spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -698,7 +698,7 @@ static void spi_dmatxwait(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -713,7 +713,7 @@ static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -730,7 +730,7 @@ static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) #ifdef CONFIG_STM32L5_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -750,7 +750,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32L5_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -768,7 +768,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -805,7 +805,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, /* Configure the RX DMA */ - stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -819,7 +819,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -856,7 +856,7 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, /* Setup the TX DMA */ - stm32l5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -870,10 +870,10 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32l5_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -886,10 +886,10 @@ static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32l5_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -909,7 +909,7 @@ static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32l5_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -943,7 +943,7 @@ static void spi_modifycr(uint32_t addr, struct stm32l5_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -979,7 +979,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1087,7 +1087,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1155,7 +1155,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; int savbits = nbits; @@ -1225,7 +1225,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1289,7 +1289,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1363,7 +1363,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, void *rxbuffer, size_t nwords) #endif { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1464,13 +1464,13 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #ifdef CONFIG_STM32L5_DMACAPABLE if ((txbuffer && - !stm32l5_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && - !stm32l5_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1654,9 +1654,9 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l5_spidev_s *priv = - (struct stm32l5_spidev_s *)((char *)cb - - offsetof(struct stm32l5_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = + (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1707,7 +1707,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32l5_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1750,17 +1750,17 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) #ifdef CONFIG_STM32L5_SPI_DMA /* Get DMA channels. - * NOTE: stm32l5_dmachannel() will always assign the DMA channel. - * If the channel is not available, then stm32l5_dmachannel() will + * NOTE: stm32_dmachannel() will always assign the DMA channel. + * If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. * WARNING: If you have another device sharing a DMA channel with SPI and * the code never releases that channel, then the call to - * stm32l5_dmachannel() will hang forever in this function! + * stm32_dmachannel() will hang forever in this function! * Don't let your design do that! */ - priv->rxdma = stm32l5_dmachannel(priv->rxch); - priv->txdma = stm32l5_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr(STM32_SPI_CR2_OFFSET, priv, @@ -1785,7 +1785,7 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1798,9 +1798,9 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32l5_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32l5_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1817,9 +1817,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI1_SCK); - stm32l5_configgpio(GPIO_SPI1_MISO); - stm32l5_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1842,9 +1842,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI2_SCK); - stm32l5_configgpio(GPIO_SPI2_MISO); - stm32l5_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1867,9 +1867,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI3 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI3_SCK); - stm32l5_configgpio(GPIO_SPI3_MISO); - stm32l5_configgpio(GPIO_SPI3_MOSI); + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.h b/arch/arm/src/stm32l5/stm32l5_spi.h index c13661243a8..005843df694 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/stm32l5_spi.h @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,33 +71,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32l5_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32l5_spi1/2/...select and stm32l5_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32l5_spi1/2/...select, - * stm32l5_spi1/2/...status, and stm32l5_spi1/2/...cmddata must be provided + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be provided * by board-specific logic. These are implementations of the select, * status, and cmddata methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32l5_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l5_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l5_spi1/2/...select() and stm32l5_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32l5_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data * selection operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32l5_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32l5_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -105,28 +105,28 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI1 -void stm32l5_spi1select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32L5_SPI2 -void stm32l5_spi2select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32L5_SPI3 -void stm32l5_spi3select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32l5_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -147,19 +147,19 @@ int stm32l5_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32L5_SPI1 -int stm32l5_spi1register(struct spi_dev_s *dev, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32L5_SPI2 -int stm32l5_spi2register(struct spi_dev_s *dev, +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32L5_SPI3 -int stm32l5_spi3register(struct spi_dev_s *dev, +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 6978b6013b4..919e9edafea 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #include "stm32l5_userspace.h" #include "stm32l5_start.h" @@ -151,10 +151,10 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32l5_clockconfig(); + stm32_clockconfig(); arm_fpuconfig(); - stm32l5_lowsetup(); - stm32l5_gpioinit(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -205,13 +205,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32l5_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32l5_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32l5/stm32l5_start.h b/arch/arm/src/stm32l5/stm32l5_start.h index 11f34ab293a..45e47f28bf2 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.h +++ b/arch/arm/src/stm32l5/stm32l5_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_START_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index 7e2d91bc1fd..509c9f3e9bb 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -40,7 +40,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #include "stm32l5_tim.h" @@ -208,10 +208,10 @@ /* TIM Device Structure */ -struct stm32l5_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32l5_tim_ops_s *ops; - enum stm32l5_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -221,179 +221,179 @@ struct stm32l5_tim_priv_s /* Register helpers */ -static inline uint16_t stm32l5_getreg16(struct stm32l5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l5_putreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l5_tim_gpioconfig(uint32_t cfg, - enum stm32l5_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif /* Timer methods */ -static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode); -static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32l5_tim_getperiod(struct stm32l5_tim_dev_s *dev); -static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev); -static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode); -static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l5_tim_ops_s stm32l5_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32l5_tim_enable, - .disable = stm32l5_tim_disable, - .setmode = stm32l5_tim_setmode, - .setclock = stm32l5_tim_setclock, - .getclock = stm32l5_tim_getclock, - .setperiod = stm32l5_tim_setperiod, - .getperiod = stm32l5_tim_getperiod, - .getcounter = stm32l5_tim_getcounter, - .setchannel = stm32l5_tim_setchannel, - .setcompare = stm32l5_tim_setcompare, - .getcapture = stm32l5_tim_getcapture, - .setisr = stm32l5_tim_setisr, - .enableint = stm32l5_tim_enableint, - .disableint = stm32l5_tim_disableint, - .ackint = stm32l5_tim_ackint, - .checkint = stm32l5_tim_checkint, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, }; #ifdef CONFIG_STM32L5_TIM1 -struct stm32l5_tim_priv_s stm32l5_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM2 -struct stm32l5_tim_priv_s stm32l5_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM3 -struct stm32l5_tim_priv_s stm32l5_tim3_priv = +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM3_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM4 -struct stm32l5_tim_priv_s stm32l5_tim4_priv = +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM4_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM5 -struct stm32l5_tim_priv_s stm32l5_tim5_priv = +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM5_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM6 -struct stm32l5_tim_priv_s stm32l5_tim6_priv = +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM6_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM7 -struct stm32l5_tim_priv_s stm32l5_tim7_priv = +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM7_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM8 -struct stm32l5_tim_priv_s stm32l5_tim8_priv = +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM8_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM15 -struct stm32l5_tim_priv_s stm32l5_tim15_priv = +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM15_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM16 -struct stm32l5_tim_priv_s stm32l5_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM17 -struct stm32l5_tim_priv_s stm32l5_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -404,51 +404,51 @@ struct stm32l5_tim_priv_s stm32l5_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32l5_getreg16(struct stm32l5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32l5_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l5_putreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32l5_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32l5_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l5_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the @@ -456,14 +456,14 @@ static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32l5_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the @@ -471,48 +471,48 @@ static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32l5_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -520,14 +520,14 @@ static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) * ****************************************************************************/ -static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32l5_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32l5_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -535,28 +535,28 @@ static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l5_tim_gpioconfig(uint32_t cfg, - enum stm32l5_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ if (mode & STM32_TIM_CH_MODE_MASK) { - stm32l5_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l5_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32l5_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -567,10 +567,10 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -610,16 +610,16 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, return -EINVAL; } - stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); #if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -627,10 +627,10 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -642,7 +642,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, if (freq == 0) { - stm32l5_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -652,7 +652,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -745,17 +745,17 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, prescaler = 0xffff; } - stm32l5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32l5_tim_enable(dev); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_tim_enable(dev); return prescaler; } /**************************************************************************** - * Name: stm32l5_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -767,7 +767,7 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -837,46 +837,46 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32l5_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32l5_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32l5_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l5_getreg32(dev, STM32_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ #if defined(CONFIG_STM32L5_TIM2) || defined(CONFIG_STM32L5_TIM5) - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM2 case STM32_TIM2_BASE: @@ -895,12 +895,12 @@ static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32l5_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -919,7 +919,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l5_getreg16(dev, STM32_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -928,10 +928,10 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -977,15 +977,15 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32l5_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32l5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -993,25 +993,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1026,25 +1026,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1059,25 +1059,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1092,24 +1092,24 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1124,25 +1124,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1157,25 +1157,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1190,25 +1190,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1223,25 +1223,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1256,25 +1256,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1292,10 +1292,10 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1303,19 +1303,19 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - stm32l5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1326,10 +1326,10 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1337,26 +1337,26 @@ static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - return stm32l5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32l5_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1364,7 +1364,7 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -1452,44 +1452,44 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32l5_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32l5_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32l5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32l5_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32l5_getreg16(dev, STM32_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1498,12 +1498,12 @@ static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32l5_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1511,76 +1511,76 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) { #ifdef CONFIG_STM32L5_TIM1 case 1: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32L5_TIM2 case 2: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32L5_TIM3 case 3: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim3_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32L5_TIM4 case 4: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim4_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32L5_TIM5 case 5: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim5_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32L5_TIM6 case 6: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim6_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32L5_TIM7 case 7: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim7_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32L5_TIM8 case 8: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim8_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32L5_TIM15 case 15: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim15_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32L5_TIM16 case 16: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32L5_TIM17 case 17: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,30 +1591,30 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32l5_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32l5_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -1687,7 +1687,7 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h index 9e420265f79..5a787e122f0 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/stm32l5_tim.h @@ -72,14 +72,14 @@ extern "C" /* TIM Device Structure */ -struct stm32l5_tim_dev_s +struct stm32_tim_dev_s { - struct stm32l5_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32l5_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -116,7 +116,7 @@ enum stm32l5_tim_mode_e /* TIM Channel Modes */ -enum stm32l5_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -147,36 +147,36 @@ enum stm32l5_tim_channel_e /* TIM Operations */ -struct stm32l5_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32l5_tim_dev_s *dev); - void (*disable)(struct stm32l5_tim_dev_s *dev); - int (*setmode)(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode); - int (*setclock)(struct stm32l5_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32l5_tim_dev_s *dev); - void (*setperiod)(struct stm32l5_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l5_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32l5_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32l5_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode); - int (*setcompare)(struct stm32l5_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32l5_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32l5_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32l5_tim_dev_s *dev, int source); - void (*disableint)(struct stm32l5_tim_dev_s *dev, int source); - void (*ackint)(struct stm32l5_tim_dev_s *dev, int source); - int (*checkint)(struct stm32l5_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); }; /**************************************************************************** @@ -185,14 +185,14 @@ struct stm32l5_tim_ops_s /* Power-up timer and get its structure */ -struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32l5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -210,7 +210,7 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l5_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c index b5e7ebcf759..bc5367fa376 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c @@ -73,10 +73,10 @@ * timer_lowerhalf_s structure. */ -struct stm32l5_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32l5_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -89,17 +89,17 @@ struct stm32l5_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32l5_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32l5_start(struct timer_lowerhalf_s *lower); -static int stm32l5_stop(struct timer_lowerhalf_s *lower); -static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -110,16 +110,16 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32l5_start, - .stop = stm32l5_stop, - .getstatus = stm32l5_getstatus, - .settimeout = stm32l5_settimeout, - .setcallback = stm32l5_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32L5_TIM1 -static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -127,7 +127,7 @@ static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM2 -static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -135,7 +135,7 @@ static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM3 -static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM3_RES, @@ -143,7 +143,7 @@ static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM4 -static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM4_RES, @@ -151,7 +151,7 @@ static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM5 -static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM5_RES, @@ -159,7 +159,7 @@ static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM6 -static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM6_RES, @@ -167,7 +167,7 @@ static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM7 -static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM7_RES, @@ -175,7 +175,7 @@ static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM8 -static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM8_RES, @@ -183,7 +183,7 @@ static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM15 -static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM15_RES, @@ -191,7 +191,7 @@ static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM16 -static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -199,7 +199,7 @@ static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM17 -static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -211,7 +211,7 @@ static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -222,10 +222,10 @@ static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32l5_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32l5_lowerhalf_s *lower = - (struct stm32l5_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, 0); @@ -239,14 +239,14 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) } else { - stm32l5_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32l5_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -260,10 +260,10 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l5_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -271,7 +271,7 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } @@ -285,7 +285,7 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l5_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -299,10 +299,10 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l5_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -319,7 +319,7 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l5_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -334,11 +334,11 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -386,7 +386,7 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l5_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -401,11 +401,11 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -430,7 +430,7 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l5_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -449,11 +449,11 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -463,7 +463,7 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } else @@ -480,7 +480,7 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -497,9 +497,9 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l5_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32l5_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -576,7 +576,7 @@ int stm32l5_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32l5_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32l5/stm32l5_timerisr.c b/arch/arm/src/stm32l5/stm32l5_timerisr.c index 85089050ec0..169200141ce 100644 --- a/arch/arm/src/stm32l5/stm32l5_timerisr.c +++ b/arch/arm/src/stm32l5/stm32l5_timerisr.c @@ -37,7 +37,7 @@ #include "clock/clock.h" #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -87,7 +87,7 @@ * ****************************************************************************/ -static int stm32l5_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -137,7 +137,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32l5/stm32l5_uart.h b/arch/arm/src/stm32l5/stm32l5_uart.h index 07fb79ab2bc..30bbad7b7bc 100644 --- a/arch/arm/src/stm32l5/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/stm32l5_uart.h @@ -275,7 +275,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -288,7 +288,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32l5_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l5/stm32l5_uid.c b/arch/arm/src/stm32l5/stm32l5_uid.c index 1b354bc4b7b..762f4e0c631 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.c +++ b/arch/arm/src/stm32l5/stm32l5_uid.c @@ -35,7 +35,7 @@ * Public Functions ****************************************************************************/ -void stm32l5_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32l5/stm32l5_uid.h b/arch/arm/src/stm32l5/stm32l5_uid.h index 6113ef1edd0..c71e4c43fd9 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.h +++ b/arch/arm/src/stm32l5/stm32l5_uid.h @@ -33,6 +33,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32l5_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_userspace.c b/arch/arm/src/stm32l5/stm32l5_userspace.c index 7b97d5b6b64..bd7d6944ab8 100644 --- a/arch/arm/src/stm32l5/stm32l5_userspace.c +++ b/arch/arm/src/stm32l5/stm32l5_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l5_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32l5_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32l5_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32l5/stm32l5_userspace.h b/arch/arm/src/stm32l5/stm32l5_userspace.h index 0e6d63d68a6..523b8c1b62b 100644 --- a/arch/arm/src/stm32l5/stm32l5_userspace.h +++ b/arch/arm/src/stm32l5/stm32l5_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_waste.c b/arch/arm/src/stm32l5/stm32l5_waste.c index 7a6a60bc8e6..5d0055c04bb 100644 --- a/arch/arm/src/stm32l5/stm32l5_waste.c +++ b/arch/arm/src/stm32l5/stm32l5_waste.c @@ -38,7 +38,7 @@ uint32_t idle_wastecounter = 0; * Public Functions ****************************************************************************/ -void stm32l5_waste(void) +void stm32_waste(void) { idle_wastecounter++; } diff --git a/arch/arm/src/stm32l5/stm32l5_waste.h b/arch/arm/src/stm32l5/stm32l5_waste.h index e9fe2209dfc..2f7b068ed28 100644 --- a/arch/arm/src/stm32l5/stm32l5_waste.h +++ b/arch/arm/src/stm32l5/stm32l5_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32l5_waste() is the logic that will be executed when portions of kernel + * stm32_waste() is the logic that will be executed when portions of kernel * or user-app is polling some register or similar, waiting for desired * status. This time is wasted away. This function offers a measure of badly * written piece of software or some undesired behavior. @@ -55,7 +55,7 @@ extern "C" * cannot be used for other purposes (yet). */ -void stm32l5_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 86a474e5a64..26c4c29257a 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -262,7 +262,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. @@ -272,7 +272,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c index 012f7938fbd..f27e0286dd9 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c @@ -64,7 +64,7 @@ static void phy_set_led(int led, bool state) { /* Active High */ - stm32l5_gpiowrite(g_ledmap[led], state); + stm32_gpiowrite(g_ledmap[led], state); } /**************************************************************************** @@ -83,7 +83,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l5_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c index 05cd210fce0..218995b6634 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -52,18 +52,18 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void) +void stm32_board_initialize(void) { - stm32l5_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); #if defined(CONFIG_STM32L5_LPUART1) /* LPUART1 uses PG7/PG8 which are powered by VDDIO2. The GPIO config in - * stm32l5_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes + * stm32_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes * silently fail. Reconfigure here after VDDIO2 is valid. */ - stm32l5_configgpio(GPIO_LPUART1_TX); - stm32l5_configgpio(GPIO_LPUART1_RX); + stm32_configgpio(GPIO_LPUART1_TX); + stm32_configgpio(GPIO_LPUART1_RX); #endif #ifdef CONFIG_ARCH_LEDS diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c index 0ade669c511..429c818dd11 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l5_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -73,7 +73,7 @@ uint32_t board_buttons(void) { /* Check the state of the USER button. */ - return stm32l5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; } /**************************************************************************** @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c index f13c4b5f627..8318cb30f2c 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c @@ -77,7 +77,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -97,7 +97,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l5_gpiowrite(g_ledcfg[led], ledon); + stm32_gpiowrite(g_ledcfg[led], ledon); } } @@ -119,7 +119,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } diff --git a/boards/arm/stm32l5/stm32l562e-dk/include/board.h b/boards/arm/stm32l5/stm32l562e-dk/include/board.h index 256110d0743..a5039f79e34 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/include/board.h +++ b/boards/arm/stm32l5/stm32l562e-dk/include/board.h @@ -185,7 +185,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. @@ -195,7 +195,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c index 0206ca6ca48..4d3dd824946 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c @@ -63,7 +63,7 @@ static void phy_set_led(int led, bool state) { /* Active Low */ - stm32l5_gpiowrite(g_ledmap[led], !state); + stm32_gpiowrite(g_ledmap[led], !state); } /**************************************************************************** @@ -82,7 +82,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l5_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c index 9f40e9807a7..458aab58733 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void) +void stm32_board_initialize(void) { /* On the STM32L562E-DK Vddio2 is supplied by Vdd_mcu. Thus, when the MCU * is running Vddio2 is guaranteed to be valid. LED LD10 is driven by @@ -59,7 +59,7 @@ void stm32l5_board_initialize(void) * Vddio2 to be valid here. */ - stm32l5_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c index 133fb020e88..3091f179081 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l5_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -73,7 +73,7 @@ uint32_t board_buttons(void) { /* Check the state of the USER button. */ - return stm32l5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; } /**************************************************************************** @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c index 170aab2fe92..4dd66b53512 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c @@ -44,7 +44,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) -void stm32l5_board_clockconfig(void) +void stm32_board_clockconfig(void) { } #endif diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c index 97342f1dfe8..fa01c257261 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c @@ -76,7 +76,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -96,7 +96,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l5_gpiowrite(g_ledcfg[led], !ledon); + stm32_gpiowrite(g_ledcfg[led], !ledon); } } @@ -118,7 +118,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); + stm32_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); } }