From 5d689fedcf95332b9977ffef481803a1eb0673f0 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Tue, 17 Nov 2015 18:02:08 +0100 Subject: [PATCH] spifi regs --- .../lpc43xx/chip/lpc4310203050_memorymap.h | 2 +- .../src/lpc43xx/chip/lpc435357_memorymap.h | 2 +- arch/arm/src/lpc43xx/chip/lpc43_spifi.h | 23 +++++++++++++++++++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h b/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h index 882444c0536..2b77b67c7a0 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h +++ b/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h @@ -110,7 +110,7 @@ #define LPC43_SCT_BASE (LPC43_AHBPERIPH_BASE + 0x00000000) #define LPC43_DMA_BASE (LPC43_AHBPERIPH_BASE + 0x00002000) -#define LPC43_SPIFI_PERIPH_BASE (LPC43_AHBPERIPH_BASE + 0x00003000) +#define LPC43_SPIFI_BASE (LPC43_AHBPERIPH_BASE + 0x00003000) #define LPC43_SDMMC_BASE (LPC43_AHBPERIPH_BASE + 0x00004000) #define LPC43_EMC_BASE (LPC43_AHBPERIPH_BASE + 0x00005000) #define LPC43_USB0_BASE (LPC43_AHBPERIPH_BASE + 0x00006000) diff --git a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h b/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h index 2cc96fb8ecb..1b8312c965f 100644 --- a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h +++ b/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h @@ -111,7 +111,7 @@ #define LPC43_SCT_BASE (LPC43_AHBPERIPH_BASE + 0x00000000) #define LPC43_DMA_BASE (LPC43_AHBPERIPH_BASE + 0x00002000) -#define LPC43_SPIFI_PERIPH_BASE (LPC43_AHBPERIPH_BASE + 0x00003000) +#define LPC43_SPIFI_BASE (LPC43_AHBPERIPH_BASE + 0x00003000) #define LPC43_SDMMC_BASE (LPC43_AHBPERIPH_BASE + 0x00004000) #define LPC43_EMC_BASE (LPC43_AHBPERIPH_BASE + 0x00005000) #define LPC43_USB0_BASE (LPC43_AHBPERIPH_BASE + 0x00006000) diff --git a/arch/arm/src/lpc43xx/chip/lpc43_spifi.h b/arch/arm/src/lpc43xx/chip/lpc43_spifi.h index ec785035816..29914a36add 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_spifi.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_spifi.h @@ -71,6 +71,29 @@ * Pre-processor Definitions ****************************************************************************/ + +/* Register addresses ***************************************************************/ + +#define LPC43_SPIFI_CTRL 0x000 +#define LPC43_SPIFI_CMD 0x004 +#define LPC43_SPIFI_ADDR 0x008 +#define LPC43_SPIFI_IDATA 0x00C +#define LPC43_SPIFI_CLIMIT 0x010 +#define LPC43_SPIFI_DATA 0x014 +#define LPC43_SPIFI_MCMD 0x018 +#define LPC43_SPIFI_STAT 0x01C + + +#define LPC43_SPIFI_CTRL (LPC43_SPIFI_BASE+LPC43_SPIFI_CTRL_OFFSET) +#define LPC43_SPIFI_CMD (LPC43_SPIFI_BASE+LPC43_SPIFI_CMD_OFFSET) +#define LPC43_SPIFI_ADDR (LPC43_SPIFI_BASE+LPC43_SPIFI_ADDR_OFFSET) +#define LPC43_SPIFI_IDATA (LPC43_SPIFI_BASE+LPC43_SPIFI_IDATA_OFFSET) +#define LPC43_SPIFI_CLIMIT (LPC43_SPIFI_BASE+LPC43_SPIFI_CLIMIT_OFFSET) +#define LPC43_SPIFI_DATA (LPC43_SPIFI_BASE+LPC43_SPIFI_DATA_OFFSET) +#define LPC43_SPIFI_MCMD (LPC43_SPIFI_BASE+LPC43_SPIFI_MCMD_OFFSET) +#define LPC43_SPIFI_STAT (LPC43_SPIFI_BASE+LPC43_SPIFI_STAT_OFFSET) + + /* The largest protection block of any serial flash that the ROM driver * can handle */