From 5b2311ef2dca2ae4e026acac87915c7ab35d535a Mon Sep 17 00:00:00 2001 From: Royyan Zahir Date: Tue, 22 Sep 2026 17:05:55 +0400 Subject: [PATCH] boards/arm/imxrt: add the Holybro Pixhawk 6X-RT A MIMXRT1176 flight controller built to the Pixhawk FMUv6X-RT standard, so the port also covers the NXP MR-VMU-RT1176. Board data comes from PX4, which already carries it as a NuttX board config: the clock tree, the LPUART1 pinmux, and the Macronix octal flash configuration block the boot ROM reads at offset 0x400. The board ships with the PX4 bootloader in the first 128 KB of QSPI, so the image links at 0x30020000 and is loaded by it rather than written to the flash base. The console is CDC/ACM as on teensy-4.x, so a USB cable is the only thing needed to run NuttX here. Signed-off-by: Royyan Zahir --- .../arm/imxrt/boards/fmu-v6xrt/index.rst | 115 ++++ .../imxrt/boards/fmu-v6xrt/pixhawk6x-rt.png | Bin 0 -> 139898 bytes boards/Kconfig | 13 + boards/arm/imxrt/fmu-v6xrt/CMakeLists.txt | 30 + boards/arm/imxrt/fmu-v6xrt/Kconfig | 38 ++ .../arm/imxrt/fmu-v6xrt/configs/nsh/defconfig | 56 ++ boards/arm/imxrt/fmu-v6xrt/include/board.h | 588 ++++++++++++++++++ boards/arm/imxrt/fmu-v6xrt/scripts/Make.defs | 49 ++ .../imxrt/fmu-v6xrt/scripts/flash-ocram.ld | 188 ++++++ boards/arm/imxrt/fmu-v6xrt/scripts/flash.ld | 152 +++++ .../imxrt/fmu-v6xrt/scripts/kernel-space.ld | 106 ++++ boards/arm/imxrt/fmu-v6xrt/scripts/memory.ld | 72 +++ .../arm/imxrt/fmu-v6xrt/scripts/user-space.ld | 122 ++++ boards/arm/imxrt/fmu-v6xrt/src/CMakeLists.txt | 33 + boards/arm/imxrt/fmu-v6xrt/src/Makefile | 34 + boards/arm/imxrt/fmu-v6xrt/src/fmu-v6xrt.h | 341 ++++++++++ boards/arm/imxrt/fmu-v6xrt/src/imxrt_boot.c | 135 ++++ .../arm/imxrt/fmu-v6xrt/src/imxrt_bringup.c | 299 +++++++++ .../imxrt/fmu-v6xrt/src/imxrt_clockconfig.c | 506 +++++++++++++++ .../fmu-v6xrt/src/imxrt_flexspi_nor_boot.c | 55 ++ .../fmu-v6xrt/src/imxrt_flexspi_nor_boot.h | 165 +++++ .../fmu-v6xrt/src/imxrt_flexspi_nor_flash.c | 178 ++++++ .../fmu-v6xrt/src/imxrt_flexspi_nor_flash.h | 359 +++++++++++ 23 files changed, 3634 insertions(+) create mode 100644 Documentation/platforms/arm/imxrt/boards/fmu-v6xrt/index.rst create mode 100644 Documentation/platforms/arm/imxrt/boards/fmu-v6xrt/pixhawk6x-rt.png create mode 100644 boards/arm/imxrt/fmu-v6xrt/CMakeLists.txt create mode 100644 boards/arm/imxrt/fmu-v6xrt/Kconfig create mode 100644 boards/arm/imxrt/fmu-v6xrt/configs/nsh/defconfig create mode 100644 boards/arm/imxrt/fmu-v6xrt/include/board.h create mode 100644 boards/arm/imxrt/fmu-v6xrt/scripts/Make.defs create mode 100644 boards/arm/imxrt/fmu-v6xrt/scripts/flash-ocram.ld create mode 100644 boards/arm/imxrt/fmu-v6xrt/scripts/flash.ld create mode 100644 boards/arm/imxrt/fmu-v6xrt/scripts/kernel-space.ld create mode 100644 boards/arm/imxrt/fmu-v6xrt/scripts/memory.ld create mode 100644 boards/arm/imxrt/fmu-v6xrt/scripts/user-space.ld create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/CMakeLists.txt create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/Makefile create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/fmu-v6xrt.h create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/imxrt_boot.c create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/imxrt_bringup.c create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/imxrt_clockconfig.c create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.c create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.h create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c create mode 100644 boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.h diff --git a/Documentation/platforms/arm/imxrt/boards/fmu-v6xrt/index.rst b/Documentation/platforms/arm/imxrt/boards/fmu-v6xrt/index.rst new file mode 100644 index 00000000000..f4af42f85a4 --- /dev/null +++ b/Documentation/platforms/arm/imxrt/boards/fmu-v6xrt/index.rst @@ -0,0 +1,115 @@ +===================== +Holybro Pixhawk 6X-RT +===================== + +.. tags:: chip:imxrt, chip:imxrt1176, vendor:holybro + +.. figure:: pixhawk6x-rt.png + :scale: 50 % + :align: center + :alt: The Holybro Pixhawk 6X-RT flight controller + + Holybro Pixhawk 6X-RT + +The `Pixhawk 6X-RT `_ +is a flight controller from Holybro built to the Pixhawk FMUv6X-RT open +standard, using the i.MX RT1176 crossover MCU. This board port targets that +standard, so it also covers the +`NXP MR-VMU-RT1176 `_. + +Features +======== + +* MIMXRT1176DVMAA, Cortex-M7 and Cortex-M4. This port clocks the M7 at 996 MHz +* 64 MB external QSPI flash, 2 MB RAM +* CAAM cryptographic accelerator with a hardware entropy source +* STM32F100 IO co-processor +* USB-C device connector +* 2 CAN buses, 100BASE-TX Ethernet, 16 PWM outputs +* Three IMUs on a vibration isolation system, two BMP388 barometers, BMM150 magnetometer +* microSD socket + +Supported in NuttX: the CAAM entropy source through ``/dev/random`` and +``/dev/urandom``, LPUART, USB device and the FlexSPI boot path. + +.. warning:: + + The sensors, CAN, Ethernet and PWM outputs listed above are board features + with no NuttX drivers in this port. Only the peripherals named as supported + are wired up. + +Buttons and LEDs +================ + +The board has no user buttons reachable from NuttX in this port. Its status +LEDs are driven by the flight stack rather than by board logic, and are not +used to signal NuttX state. + +Serial Console +============== + +LPUART1 is on the DEBUG connector at 57600 baud. + +========== ================ ================ +Pin Signal Notes +========== ================ ================ +DEBUG TX GPIO_DISP_B1_02 LPUART1_TX, ALT9 +DEBUG RX GPIO_DISP_B1_03 LPUART1_RX, ALT9 +========== ================ ================ + +The ``nsh`` configuration uses the USB CDC/ACM console instead, so the DEBUG +connector is optional and a USB-C cable is enough. + +Flash Layout +============ + +The board ships with the PX4 bootloader programmed at the base of QSPI flash. +It occupies the first 128 KB and starts the application at ``0x30020000``. +NuttX links to that address and is loaded by the bootloader rather than written +to the flash base. + +=========== ============= ========================== +Address Size Contents +=========== ============= ========================== +0x30000000 128 KB PX4 bootloader, as shipped +0x30020000 4 MB - 128 KB NuttX +=========== ============= ========================== + +.. warning:: + + Writing to the flash base removes the bootloader, and with it the ability to + load firmware over USB. Recovering from that needs SWD. + +Power Supply +============ + +The board is powered over USB-C for bench use, or from the vehicle power +module in flight. Nothing in this port manages power. + +Installation +============ + +The toolchain is the same as for every i.MX RT board; see +:doc:`the platform page <../../index>`. + +Flashing needs ``px_uploader.py`` from the PX4 source tree. The bootloader +enumerates as a USB CDC/ACM device for roughly five seconds after reset, so +start the uploader first and then reset the board: + +.. code-block:: console + + $ python Tools/px_mkfw.py --prototype firmware.prototype --image nuttx.bin > nuttx.px4 + $ python Tools/px_uploader.py --port "/dev/serial/by-id/*PX4*" nuttx.px4 + +The uploader expects a ``.px4`` container rather than a raw binary. + +Configurations +============== + +nsh +--- + +The basic NuttShell configuration. The console is USB CDC/ACM, so the shell +appears on the same connector used for flashing, at ``/dev/ttyACM0`` on the +host. ``/dev/random`` and ``/dev/urandom`` are backed by the CAAM hardware +entropy source. diff --git a/Documentation/platforms/arm/imxrt/boards/fmu-v6xrt/pixhawk6x-rt.png b/Documentation/platforms/arm/imxrt/boards/fmu-v6xrt/pixhawk6x-rt.png new file mode 100644 index 0000000000000000000000000000000000000000..a7b569663a0becaca19b82a48570b9e0ec81b5c8 GIT binary patch literal 139898 zcmeEt^;272*lqAYDOOr2&;o(tTCBJgl z<-K#izu^9QXOhXBv**k{*|MJJS!?YmbyfMN1XKh70N|;j0$39Oz|{Zm3&cd<;l(D7 z0RZR#iePDN@0^2WpVT+A#?05ND6fo2Z^NUsOdW$5ZMHO}grYa210ku zsa^Q^TMOrRB_ek7%CaTO#|ZiRgGRnc;${hc{yZSH=om^dKk&l47s3H$HPET#tZH~$ z^=Yg{?i=#zDqC{HN>_>NWn=2H%1VO!>D13(S0ehM*r4|;9gTNrJTh0 zJ+gZ{M{s)*cHAE(Y%AyI@4xO}4W%~fI`S>(} zc|>r>8i5r#0N^Y2L}5+&H-wIdkbxvKA|Z`}v6c=5FuOPh0q8&=lV%J6DXRq_61nQb zvVka1-j3Td_U#5|1!MUV<$P&^eIkklL;_{{w|mz0h%hwNNdXPqq!qVkmuftG?=R-o zd5vt|)x&&90ptL6Zjm2t``4QbV`3;_(}P0pEoa{LwmYp;tEJb->yeQoi}+&rcudbS z?JZ0DNi(-42Ph;`iseAOjvglnGx_Qk%3d|3SL5FC3gkNaMsdPn#`oUDpxvoF#ma+7 z+xU)>US%?uxwf=55c%Mres(i$@|XwTZV%9_IL*N2u6 z5D#o4Af02AAE@64-~X5^5ts>IqUtA9GAKq&EM&RgwJRznABfGcImRj`f1|Xh9#>*k zEK1G#@`cB;8u5iPO@D$-k*w4Msay3r5_6=fjIwg8pk6LX6Jn>L$fi_0Lq%SQhB74# zl1N-Sx&@-qy(--C{wIQ%Uk@9xfoom}94|FytNE_EAq2ZP(u_l;L}ZL(RxNb<-o>nY za^RI<62_x7^5@v&_el?v10PAw#Y4LqlZ;wEiQCeA%R3w|C)bbHvZkLY!^ZV`E<)5> z8{2$NHvawkML=L`(3!J+KNOQ8a~!3TV}T=Q;ITK%m+ybgm%+s)kUb)Y6c86TtP&8| zo3dYe_&b51`&&d)lBt^|hNlO!fP0k+if}KDexHm`_mHjJV@uE%SFBwXDv9L=n?oFY$+<3Iw5BWMZ9p7h4Rc$T1-IXO2|o*R8vSn zaD+^00|&JP$@56rx*)YGrkD zm+S$a&nSs*PjFm}GE|ay^Xx$3h?y1NZA`plKe&L!GsL9e9x*OKV(Q0rv9a1XrMIYm z&vdhzJM``R9Av0d7zq;LrHpSFRVVrDJ)m0fR1!g|xWj&CY&UqltYvKdfV~A(94wjf z0wS)MJjGO^z^($mfQ>+u!NWO@5xk%z5F;j73KK4cO@e_@0Klii94_Dl97gM7Sg!}Q zH0u?l_+qR>Qaa0#rka$eg%@ajvx)Z7hU z2pOpq)A!Ldj&R;eNlKtavZa-QlcS@K&>H|^7!qC zjkc{}u_`5(a123h^4r=|cm@hUrS4f}iuO!Q)Uv#EnsIW*tW}YzGvHLls0JoQvSK)| zoHwOE7{XqRke0Pe*M~RqPY*OfIEz)18E3L84YNrB1@?o_SfvQL5;YaDrH1nqgiY^S+=m$GRiy#Z11#XZ|oS-CZ z(xHi`hNU2uAbvlOc@Jrd6@kT+M1?|-Y^uI7xoo=C0LykrBpp6z7b-+j@>v)IK+?JD zK}M;;4hrANd4@loX_K@j&YH%EA5q7rQ+`YJ1%pnJ%*s7)J3BiYu3Nka#iLDTJju(P z$0N>*YC7v;AwU^<9989Q=PnWhfWgl!o@MJpv3yCl4ikDudG%VzOSCW6>c_|Z?=BGo z1M#mVJ@1r{mbwEa-RM3509CkNgnhOdt$v{PUhFU|HqPE|ls~G&<-t!}c@fD4AT6r* zbUjfjpJZ1a#cQ)jh?Fhw=xiSdDw%}9S8S(Jz!{@S+HPFICksz$80eG*3bDdguFIU= zMmf1ScNpJnc0J++xY+GZj6MDv3%q)~-4p6MG3>tb?Y{aJ^$Y>KEhP3|<8;0mloh`2 zxqGyv34?AM3dyY0jB4k`$v&hFe>7PK8Sm*x?Lf!O6?Y$T4)3Ro!lKE zg?LQ6{BDLb`IZAr(o1#sevb&L#Hu+sI&vBtfci|zi_?@E!Buj#LX;A(-u^g7fWJ{b z1%Q>ps?zBCcNsZ4+U2HI^~`}BH00)HNA7Np!wYid(G&cQk=p5@-;AC}COtfP5qwZ^ zC|8L+IJ|;qEw5x?p->^+ozO88NWjOcgJ2eqFzMh16&DwSCLCf(N%6H^bvARcrND50 z)=yk4nqSj2*S_m6#vH9F5wNf16hlXSo!wnzyV1}bNjj^0R@w;<|omfXr| z{~hC@I?vD{pawPk7Qv^u=X@3w|L}m`AIs{5=yiIU68I1$PaE*A@uzi%X}Sb9F~FzG z(`PsON_xJCMI4|HjVW@7kL55isGObDMaE7hT)FT{f#-{;2!f$BU8G z%dLqt+S|1VF0NrA>ZjHTiz5`)c#9b)>y{cfMVrq)01|Ea!~`(OzVOm?+}IkVON0f~ zMnwM6`a?~9$f4qYJbL5z+fgt(QlC70CQB9qpSfMYt+Or7VedfJfT&)+r2hnRXnK*P z4lk)5*lRv}=S|zmjH0K_Yv?-bBjj-y)fN952P>A`(Gwye`6Bx+j6^2g%0!I8d%GI3 zKnb?ACX%L}Zl)eK7p?OWdR?oc`$;-gcc9D;E@4=Ob-J+0-u+P3ee1t^h2C>x!6deK z8!15_<&I?0`8G9i6kce8|6hjDn@+v3HGdZxO43>r(Ay+Zl-A_~YuXRbkR>V5gd&CMR5+?Gh8`J3ErR#)2MXuUtz?-u!(g%li&?zLUnz&a9Tl zKfqE1Rc16j2osZhRW;A6LjZxI*VnjHOPXc|m+{A~-3nIJ{po3gpqyQ<*I9j3l(fO| z<+tTM6H6;A_`CzrYU<2P+1Oa)`U&|cLy=r~m?3pGeJUT{(tavFOB3Wj?{-{q^HLe(G>@iJjakS_>{~zG&H1` z%%~W`|Dm@sTIqQJw?v(a(tN{tRaN#3Bi>e7!YfgJ5s{O;tFH1{6i2O5#cbo=W_y>YwWeyNYk=peYSXipUf>0b4}s513m>j{>p^-0BI2;t?YbVqfd zx{B)Nr*L_;`Koop*KC8Mr$UzIq+E`mXM=Cm0K_`x4qM zIMU!$?zVAhaYiwgBihp0V#Qkrdq!=y3(nAT08NC8FA#k2-`}kAI}g! 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zVqfhf!9wP3MiPnXtyNhQMlZVzLYX^g_~nVC(z?O85JBV!Fbn5>s@!%jy7K8!_Zf61 z{?L#m=%4UaYT*m^knm-(K9%}Me#cbL$3OG`Y=T+!bM+A#vR?e{V&}JYPMkLE(S(f3 zD|z166*=Kje|Bm&v<&xzPi)(f(UJX7AM`CT0$;+*WXJFRx3g@;U;=F1RiHWA`pFoc zCkq(M7Q1d2M?wT#%3PiuE2Fes-9)U^Qw;SfO(vr)X$GG1vES(AD&Lw+{I8#F<9=q? zn$O2<>?X7(D2n_z^0-BG$r5Sa-g5*_>kPB5*tg#~pWK#*q(w(_KzeA?sX$8h zF|OClus0nRySue+{}TcBAP!_Tkj@lqb|95ECjYYYiLcprshBHHA~(~Pxm#l_wR>f9 zgQQTZYYHl$q7Ie;$4T~_c9PVS=JkGs64VVoc1&QFS1rd)UX-4Cw)&;q8#aP9a;@Se z+|-fx*B-bx{;{e(dBfbtGiv#F8K!kaH}MbB=xlIwT$aXN2D(CHJJZZ80f)U3vCzGnLHz=C4z+Hz4#u7|t z_LzhMY?C|?Zi4ueXR;cy-QM+F_ddP>>A!eD0`9WIz9vH=)p&hiNIYJ-rp5;kTY-d~ znwZHvR+wnfw1}vhRV-2LPX>!*;+HNb5$_=mCRr4MOD|4qYR( z+PXX|4*xAkgan%P#X8tnc_yMY>l<$^nE7rb+A)HNjEPw497aYA@$a`|+QKqrV>v1% z#N=)n^WNg%WMYMkm}n+8|23I6iaZH~>i=T^>Tjxl1hvDb*Q@%u5AwK>Z&EP9jQH=# zUYiGlUW?}ehWusiKPUg=7tXb4HqJpiXu$ca7<)^3M%Pd}|M + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_IMXRT_FMU_V6XRT_INCLUDE_BOARD_H +#define __BOARDS_ARM_IMXRT_FMU_V6XRT_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The ARM PLL is 996MHz; see imxrt_clockconfig.c for the dividers. */ + +#define BOARD_CPU_FREQUENCY 996000000 +#define IMXRT_IPG_PODF_DIVIDER 5 +#define BOARD_GPT_FREQUENCY 24000000 +#define BOARD_XTAL_FREQUENCY 24000000 +#define BOARD_FLEXIO_PREQ 108000000 + +/* SDIO *********************************************************************/ + +/* Pin drive characteristics - drive strength in particular may need tuning + * for specific boards. + */ + +/* GPIO_SD_B1_02 */ + +#define PIN_USDHC1_D0 (GPIO_USDHC1_DATA0_1 | IOMUX_USDHC1_DATAX_DEFAULT) + +/* GPIO_SD_B1_03 */ + +#define PIN_USDHC1_D1 (GPIO_USDHC1_DATA1_1 | IOMUX_USDHC1_DATAX_DEFAULT) + +/* GPIO_SD_B1_04 */ + +#define PIN_USDHC1_D2 (GPIO_USDHC1_DATA2_1 | IOMUX_USDHC1_DATAX_DEFAULT) + +/* GPIO_SD_B1_05 */ + +#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3_1 | IOMUX_USDHC1_DATAX_DEFAULT) + +/* GPIO_SD_B1_01 */ + +#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | IOMUX_USDHC1_CLK_DEFAULT) + +/* GPIO_SD_B1_00 */ + +#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | IOMUX_USDHC1_CMD_DEFAULT) + +/* GPIO_AD_32 */ + +#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | IOMUX_USDHC1_CLK_DEFAULT) + +/* 386 KHz for initial inquiry stuff */ + +#define BOARD_USDHC_IDMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV256 +#define BOARD_USDHC_IDMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(2) + +/* 24.8MHz for other modes */ + +#define BOARD_USDHC_MMCMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_USDHC_MMCMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) + +#define BOARD_USDHC_SD1MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_USDHC_SD1MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) + +#define BOARD_USDHC_SD4MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_USDHC_SD4MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) + +/* LED definitions **********************************************************/ + +/* The px4 fmu-v6x board has numerous LEDs but only three, LED_GREEN a Green + * LED_BLUE a Blue LED and LED_RED a Red LED, that can be controlled by + * software. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_RED BOARD_LED1 +#define BOARD_LED_GREEN BOARD_LED2 +#define BOARD_LED_BLUE BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/imxrt_autoleds.c. The LEDs encode OS events as + * follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ ---- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */ + +/* Thus if the Green LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If the Red LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/* PIO Disambiguation *******************************************************/ + +/* LPUARTs + * + * We pull down CTS so that if nothing is connected, conde will not block. + */ +#define IOMUX_UART_CTS_DEFAULT (IOMUX_PULL_DOWN | IOMUX_DRIVE_HIGHSTRENGTH | IOMUX_SLEW_SLOW) +#define IOMUX_UART_BOARD_DEFAULT (IOMUX_PULL_NONE | IOMUX_DRIVE_HIGHSTRENGTH | IOMUX_SLEW_FAST) + +/* Debug */ + +/* UART1_RX_DEBUG GPIO_DISP_B1_03 */ + +#define GPIO_LPUART1_RX (GPIO_LPUART1_RX_2|IOMUX_UART_DEFAULT|PADMUX_SION) + +/* UART1_TX_DEBUG GPIO_DISP_B1_02 */ + +#define GPIO_LPUART1_TX (GPIO_LPUART1_TX_2|IOMUX_UART_BOARD_DEFAULT) + +/* GPS 1 */ + +/* UART3_RX_GPS1 GPIO_AD_31 */ + +#define GPIO_LPUART3_RX (GPIO_LPUART3_RX_1|IOMUX_UART_DEFAULT|PADMUX_SION) + +/* UART3_TX_GPS1 GPIO_AD_30 */ + +#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_1|IOMUX_UART_DEFAULT) + +/* Telem 1 */ + +/* UART4_CTS_TELEM1 GPIO_DISP_B1_05 */ + +#define GPIO_LPUART4_CTS (GPIO_LPUART4_CTS_1|IOMUX_UART_CTS_DEFAULT|PADMUX_SION) + +/* UART4_RTS_TELEM1 GPIO_DISP_B1_07 GPIO4 Pin 28 */ + +#define GPIO_LPUART4_RTS (GPIO_PORT4 | GPIO_PIN28 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_UART_DEFAULT) + +/* UART4_RX_TELEM1 GPIO_DISP_B1_04 */ + +#define GPIO_LPUART4_RX (GPIO_LPUART4_RX_1|IOMUX_UART_DEFAULT|PADMUX_SION) + +/* UART4_TX_TELEM1 GPIO_DISP_B1_06 */ + +#define GPIO_LPUART4_TX (GPIO_LPUART4_TX_1|IOMUX_UART_BOARD_DEFAULT) + +/* GPS 2 */ + +/* UART5_RX_GPS2 GPIO_AD_29 */ + +#define GPIO_LPUART5_RX (GPIO_LPUART5_RX_1|IOMUX_UART_DEFAULT|PADMUX_SION) + +/* UART5_TX_GPS2 GPIO_AD_28 */ + +#define GPIO_LPUART5_TX (GPIO_LPUART5_TX_1|IOMUX_UART_DEFAULT) + +/* PX4IO */ + +/* UART6_RX_FROM_IO__NC GPIO_EMC_B1_41 */ + +#define GPIO_LPUART6_RX (GPIO_LPUART6_RX_1|IOMUX_UART_DEFAULT|PADMUX_SION) + +/* UART6_TX_TO_IO__RC_INPUT GPIO_EMC_B1_40 */ + +#define GPIO_LPUART6_TX (GPIO_LPUART6_TX_1|IOMUX_UART_DEFAULT) + +/* Telem 2 */ + +/* UART8_CTS_TELEM2 GPIO_AD_04 */ + +#define GPIO_LPUART8_CTS (GPIO_LPUART8_CTS_1|IOMUX_UART_CTS_DEFAULT|PADMUX_SION) + +/* UART8_RTS_TELEM2 GPIO_AD_05 GPIO3 Pin 4 */ + +#define GPIO_LPUART8_RTS (GPIO_PORT3 | GPIO_PIN4 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_UART_DEFAULT) + +/* UART8_RX_TELEM2 GPIO_AD_03 */ + +#define GPIO_LPUART8_RX (GPIO_LPUART8_RX_2|IOMUX_UART_DEFAULT|PADMUX_SION) + +/* UART8_TX_TELEM2 GPIO_AD_02 */ + +#define GPIO_LPUART8_TX (GPIO_LPUART8_TX_2|IOMUX_UART_BOARD_DEFAULT) + +/* Telem 3 */ + +/* UART10_CTS_TELEM3 GPIO_AD_34 */ + +#define GPIO_LPUART10_CTS (GPIO_LPUART10_CTS_1|IOMUX_UART_CTS_DEFAULT|PADMUX_SION) + +/* UART10_RTS_TELEM3 GPIO_AD_35 GPIO4 Pin 2 */ + +#define GPIO_LPUART10_RTS (GPIO_PORT4 | GPIO_PIN2 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_UART_DEFAULT) + +/* UART10_RX_TELEM3 GPIO_AD_33 */ + +#define GPIO_LPUART10_RX (GPIO_LPUART10_RX_2|IOMUX_UART_DEFAULT|PADMUX_SION) + +/* UART10_TX_TELEM3 GPIO_AD_15 */ + +#define GPIO_LPUART10_TX (GPIO_LPUART10_TX_1|IOMUX_UART_BOARD_DEFAULT) + +/* Ext 2 */ + +/* No DMA Support at this time for lack of DMA1, DMAMUX1 support */ + +/* UART11_RX_EXTERNAL2 GPIO_LPSR_05 */ + +#define GPIO_LPUART11_RX (GPIO_LPUART11_RX_2|IOMUX_UART_DEFAULT|PADMUX_SION) + +/* UART11_TX_EXTERNAL2 GPIO_LPSR_04 */ + +#define GPIO_LPUART11_TX (GPIO_LPUART11_TX_2|IOMUX_UART_DEFAULT) + +/* CAN + * + * CAN1 is routed to transceiver. + * CAN2 is routed to transceiver. + * CAN3 is routed to transceiver. + */ + +#define FLEXCAN_IOMUX (IOMUX_PULL_UP | IOMUX_SLEW_FAST) + +/* GPIO_AD_06 */ + +#define GPIO_FLEXCAN1_TX (GPIO_FLEXCAN1_TX_1 | FLEXCAN_IOMUX) + +/* GPIO_AD_07 */ + +#define GPIO_FLEXCAN1_RX (GPIO_FLEXCAN1_RX_1 | FLEXCAN_IOMUX) + +/* GPIO_AD_00 */ + +#define GPIO_FLEXCAN2_TX (GPIO_FLEXCAN2_TX_1 | FLEXCAN_IOMUX) + +/* GPIO_AD_01 */ + +#define GPIO_FLEXCAN2_RX (GPIO_FLEXCAN2_RX_1 | FLEXCAN_IOMUX) + +/* GPIO_LPSR_00 */ + +#define GPIO_FLEXCAN3_TX (GPIO_FLEXCAN3_TX_1 | FLEXCAN_IOMUX) + +/* GPIO_LPSR_01 */ + +#define GPIO_FLEXCAN3_RX (GPIO_FLEXCAN3_RX_1 | FLEXCAN_IOMUX) + +/* LPSPI */ + +/* SPI1_MISO_SENSOR1 GPIO_EMC_B2_03 */ + +#define GPIO_LPSPI1_MISO (GPIO_LPSPI1_SDI_2|IOMUX_LPSPI_DEFAULT) + +/* SPI1_MOSI_SENSOR1 GPIO_EMC_B2_02 */ + +#define GPIO_LPSPI1_MOSI (GPIO_LPSPI1_SDO_2|IOMUX_LPSPI_DEFAULT) + +/* SPI1_SCK_SENSOR1 GPIO_EMC_B2_00 */ + +#define GPIO_LPSPI1_SCK (GPIO_LPSPI1_SCK_2|IOMUX_LPSPI_DEFAULT) + +/* SPI2_MISO_SENSOR2 GPIO_AD_27 */ + +#define GPIO_LPSPI2_MISO (GPIO_LPSPI2_SDI_1|IOMUX_LPSPI_DEFAULT) + +/* SPI2_MOSI_SENSOR2 GPIO_AD_26 */ + +#define GPIO_LPSPI2_MOSI (GPIO_LPSPI2_SDO_1|IOMUX_LPSPI_DEFAULT) + +/* SPI2_SCK_SENSOR2 GPIO_AD_24 */ + +#define GPIO_LPSPI2_SCK (GPIO_LPSPI2_SCK_1|IOMUX_LPSPI_DEFAULT) + +/* SPI3_MISO_SENSOR3 GPIO_EMC_B2_07 */ + +#define GPIO_LPSPI3_MISO (GPIO_LPSPI3_SDI_1|IOMUX_LPSPI_DEFAULT) + +/* SPI3_MOSI_SENSOR3 GPIO_EMC_B2_06 */ + +#define GPIO_LPSPI3_MOSI (GPIO_LPSPI3_SDO_1|IOMUX_LPSPI_DEFAULT) + +/* SPI3_SCK_SENSOR3 GPIO_EMC_B2_04 */ + +#define GPIO_LPSPI3_SCK (GPIO_LPSPI3_SCK_1|IOMUX_LPSPI_DEFAULT) + +/* SPI4 Not connected to anything */ + +/* LPSPI6 No DMA Support at this time for lack of DMA1, DMAMUX1 support */ + +/* SPI6_MISO_EXTERNAL1 GPIO_LPSR_12 */ + +#define GPIO_LPSPI6_MISO (GPIO_LPSPI6_SDI_1|IOMUX_LPSPI_DEFAULT) + +/* SPI6_MOSI_EXTERNAL1 GPIO_LPSR_11 */ + +#define GPIO_LPSPI6_MOSI (GPIO_LPSPI6_SDO_1|IOMUX_LPSPI_DEFAULT) + +/* SPI6_SCK_EXTERNAL1 GPIO_LPSR_10 */ + +#define GPIO_LPSPI6_SCK (GPIO_LPSPI6_SCK_1|IOMUX_LPSPI_DEFAULT) + +/* LPI2Cs */ + +/* I2C1_SCL_GPS1 GPIO_AD_08 GPIO_GPIO3_IO07 */ + +#define GPIO_LPI2C1_SCL_RESET (GPIO_PORT3 | GPIO_PIN7 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* I2C1_SDA_GPS1 GPIO_AD_09 GPIO_GPIO3_IO08 */ + +#define GPIO_LPI2C1_SDA_RESET (GPIO_PORT3 | GPIO_PIN8 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* I2C1_SCL_GPS1 GPIO_AD_08 */ + +#define GPIO_LPI2C1_SCL (GPIO_LPI2C1_SCL_2|IOMUX_LPI2C_DEFAULT) + +/* I2C1_SDA_GPS1 GPIO_AD_09 */ + +#define GPIO_LPI2C1_SDA (GPIO_LPI2C1_SDA_2|IOMUX_LPI2C_DEFAULT) + +/* I2C2_SCL_GPS2 GPIO_AD_18 GPIO_GPIO3_IO17 */ + +#define GPIO_LPI2C2_SCL_RESET (GPIO_PORT3 | GPIO_PIN17 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* I2C2_SDA_GPS2 GPIO_AD_19 GPIO_GPIO3_IO18 */ + +#define GPIO_LPI2C2_SDA_RESET (GPIO_PORT3 | GPIO_PIN18 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* I2C2_SCL_GPS2 GPIO_AD_18 */ + +#define GPIO_LPI2C2_SCL (GPIO_LPI2C2_SCL_2|IOMUX_LPI2C_DEFAULT) + +/* I2C2_SDA_GPS2 GPIO_AD_19 */ + +#define GPIO_LPI2C2_SDA (GPIO_LPI2C2_SDA_2|IOMUX_LPI2C_DEFAULT) + +/* I2C3_SCL_FMU GPIO_DISP_B2_10 GPIO_GPIO5_IO11_1 */ + +#define GPIO_LPI2C3_SCL_RESET (GPIO_PORT5 | GPIO_PIN11 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* I2C3_SDA_FMU GPIO_DISP_B2_11 GPIO_GPIO5_IO12_1 */ + +#define GPIO_LPI2C3_SDA_RESET (GPIO_PORT5 | GPIO_PIN12 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* I2C3_SCL_FMU GPIO_DISP_B2_10 */ + +#define GPIO_LPI2C3_SCL (GPIO_LPI2C3_SCL_2|IOMUX_LPI2C_DEFAULT) + +/* I2C3_SDA_FMU GPIO_DISP_B2_11 */ + +#define GPIO_LPI2C3_SDA (GPIO_LPI2C3_SDA_2|IOMUX_LPI2C_DEFAULT) + +/* I2C6_SCL_EXTERNAL2 GPIO_LPSR_07 GPIO_GPIO6_IO07_1 */ + +#define GPIO_LPI2C6_SCL_RESET (GPIO_PORT6 | GPIO_PIN7 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* I2C6_SDA_EXTERNAL2 GPIO_LPSR_06 GPIO_GPIO6_IO06_1 */ + +#define GPIO_LPI2C6_SDA_RESET (GPIO_PORT6 | GPIO_PIN6 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* LPI2C6 No DMA Support at this time for lack of DMA1, DMAMUX1 support */ + +/* I2C6_SCL_EXTERNAL2 GPIO_LPSR_07 */ + +#define GPIO_LPI2C6_SCL (GPIO_LPI2C6_SCL_1|IOMUX_LPI2C_DEFAULT) + +/* I2C6_SDA_EXTERNAL2 GPIO_LPSR_06 */ + +#define GPIO_LPI2C6_SDA (GPIO_LPI2C6_SDA_1|IOMUX_LPI2C_DEFAULT) + +/* ETH Disambiguation *******************************************************/ + +/* This is the ENET_1G interface. */ + +/* Compile time selection */ +#if defined(CONFIG_ETH0_PHY_TJA1103) +# define BOARD_PHY_ADDR (18) +#endif +#if defined(CONFIG_ETH0_PHY_LAN8742A) +# define BOARD_PHY_ADDR (0) +#endif + +/* Run time selection see mii.h */ + +#define BOARD_ETH0_PHY_LIST \ + { \ + "LAN8742A", \ + MII_PHYID1_LAN8742A, \ + MII_PHYID2_LAN8742A, \ + MII_LAN8740_SCSR, \ + 0, \ + 0xffff, \ + MII_LAN8720_SPSCR_10MBPS, \ + MII_LAN8720_SPSCR_100MBPS, \ + MII_LAN8720_SPSCR_DUPLEX, \ + 22, \ + }, \ + { \ + "TJA1103", \ + MII_PHYID1_TJA1103, \ + MII_PHYID2_TJA1103, \ + 0xffff, \ + 18, \ + 0xffff, \ + 0, \ + MII_LAN8720_SPSCR_100MBPS, \ + MII_LAN8720_SPSCR_DUPLEX, \ + 45, \ + }, \ + +/* GPIO_DISP_B1_09 */ + +#define GPIO_ENET2_TX_DATA00 (GPIO_ENET_1G_TX_DATA0_1|IOMUX_ENET_DATA_DEFAULT) + +/* GPIO_DISP_B1_08 */ + +#define GPIO_ENET2_TX_DATA01 (GPIO_ENET_1G_TX_DATA1_1|IOMUX_ENET_DATA_DEFAULT) + +/* GPIO_EMC_B2_15 */ + +#define GPIO_ENET2_RX_DATA00 (GPIO_ENET_1G_RX_DATA0_2|IOMUX_ENET_DATA_DEFAULT) + +/* GPIO_EMC_B2_16 */ + +#define GPIO_ENET2_RX_DATA01 (GPIO_ENET_1G_RX_DATA1_2|IOMUX_ENET_DATA_DEFAULT) + +/* GPIO_EMC_B2_20 */ + +#define GPIO_ENET2_MDIO (GPIO_ENET_1G_MDIO_1|IOMUX_ENET_MDIO_DEFAULT) + +/* GPIO_EMC_B2_19 */ + +#define GPIO_ENET2_MDC (GPIO_ENET_1G_MDC_1|IOMUX_ENET_MDC_DEFAULT) + +/* GPIO_DISP_B1_00 */ + +#define GPIO_ENET2_RX_EN (GPIO_ENET_1G_RX_EN_1|IOMUX_ENET_EN_DEFAULT) + +/* GPIO_DISP_B1_01 */ + +#define GPIO_ENET2_RX_ER (GPIO_ENET_RX_ER_1|IOMUX_ENET_RXERR_DEFAULT) + +/* GPIO_DISP_B1_11 */ + +#define GPIO_ENET2_TX_CLK (GPIO_ENET_1G_REF_CLK_1|IOMUX_ENET_TX_CLK_DEFAULT) + +/* GPIO_DISP_B1_10 */ + +#define GPIO_ENET2_TX_EN (GPIO_ENET_1G_TX_EN_1|IOMUX_ENET_EN_DEFAULT) + +/* Board provides GPIO or other Hardware for signaling to timing analyzer */ + +#if defined(CONFIG_BOARD_USE_PROBES) +#define PROBE_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_SLEW_FAST) +# define PROBE_N(n) (1<<((n)-1)) +# define PROBE_1 /* GPIO_EMC_B1_23 */ (GPIO_PORT1 | GPIO_PIN23 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_2 /* GPIO_EMC_B1_25 */ (GPIO_PORT1 | GPIO_PIN25 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_3 /* GPIO_EMC_B1_27 */ (GPIO_PORT1 | GPIO_PIN27 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_4 /* GPIO_EMC_B1_06 */ (GPIO_PORT1 | GPIO_PIN6 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_5 /* GPIO_EMC_B1_08 */ (GPIO_PORT1 | GPIO_PIN8 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_6 /* GPIO_EMC_B1_10 */ (GPIO_PORT1 | GPIO_PIN10 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_7 /* GPIO_EMC_B1_19 */ (GPIO_PORT1 | GPIO_PIN19 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_8 /* GPIO_EMC_B1_29 */ (GPIO_PORT1 | GPIO_PIN29 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_9 /* GPIO_EMC_B1_31 */ (GPIO_PORT1 | GPIO_PIN31 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_10 /* GPIO_EMC_B1_21 */ (GPIO_PORT1 | GPIO_PIN21 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_11 /* GPIO_EMC_B1_00 */ (GPIO_PORT1 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) +# define PROBE_12 /* GPIO_EMC_B1_02 */ (GPIO_PORT1 | GPIO_PIN2 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | PROBE_IOMUX) + +# define PROBE_INIT(mask) \ + do { \ + if ((mask)& PROBE_N(1)) { imxrt_config_gpio(PROBE_1); } \ + if ((mask)& PROBE_N(2)) { imxrt_config_gpio(PROBE_2); } \ + if ((mask)& PROBE_N(3)) { imxrt_config_gpio(PROBE_3); } \ + if ((mask)& PROBE_N(4)) { imxrt_config_gpio(PROBE_4); } \ + if ((mask)& PROBE_N(5)) { imxrt_config_gpio(PROBE_5); } \ + if ((mask)& PROBE_N(6)) { imxrt_config_gpio(PROBE_6); } \ + if ((mask)& PROBE_N(7)) { imxrt_config_gpio(PROBE_7); } \ + if ((mask)& PROBE_N(8)) { imxrt_config_gpio(PROBE_8); } \ + if ((mask)& PROBE_N(9)) { imxrt_config_gpio(PROBE_9); } \ + if ((mask)& PROBE_N(10)) { imxrt_config_gpio(PROBE_10); } \ + if ((mask)& PROBE_N(11)) { imxrt_config_gpio(PROBE_11); } \ + if ((mask)& PROBE_N(12)) { imxrt_config_gpio(PROBE_12); } \ + } while(0) + +# define PROBE(n,s) do {imxrt_gpio_write(PROBE_##n,(s));}while(0) +# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true) +#else +# define PROBE_INIT(mask) +# define PROBE(n,s) +# define PROBE_MARK(n) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_IMXRT_FMU_V6XRT_INCLUDE_BOARD_H */ diff --git a/boards/arm/imxrt/fmu-v6xrt/scripts/Make.defs b/boards/arm/imxrt/fmu-v6xrt/scripts/Make.defs new file mode 100644 index 00000000000..fa147466fff --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/scripts/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# boards/arm/imxrt/fmu-v6xrt/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y) + LDSCRIPT = flash.ld +else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y) + LDSCRIPT = flash-ocram.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/elf/gnu-elf.ld) diff --git a/boards/arm/imxrt/fmu-v6xrt/scripts/flash-ocram.ld b/boards/arm/imxrt/fmu-v6xrt/scripts/flash-ocram.ld new file mode 100644 index 00000000000..a3b10c27dd5 --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/scripts/flash-ocram.ld @@ -0,0 +1,188 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/scripts/flash-ocram.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Specify the memory areas */ + +/* The fmu-v6xrt has 8MiB of QSPI FLASH beginning at address, + * 0x0060:0000, Upto 512Kb of DTCM RAM beginning at 0x2000:0000, and 1MiB OCRAM + * beginning at 0x2020:0000. Neither DTCM or SDRAM are used in this + * configuration. + * + * The default flexram setting on the iMXRT 1064 is + * 256Kib to OCRRAM, 128Kib ITCM and 128Kib DTCM. + * This can be changed by using a dcd by minipulating + * IOMUX GPR16 and GPR17. + * The configuration we will use is 384Kib to OCRRAM, 0Kib ITCM and + * 128Kib DTCM. + * + * This is the OCRAM inker script. + * The NXP ROM bootloader will move the FLASH image to OCRAM. + * We must reserve 32K for the bootloader' OCRAM usage from the OCRAM Size + * and an additional 8K for the ivt_s which is IVT_SIZE(8K) This 40K can be + * reused once the application is running. + * + * 0x2020:A000 to 0x202d:ffff - The application Image's vector table + * 0x2020:8000 to 0x2020:A000 - IVT + * 0x2020:0000 to 0x2020:7fff - NXP ROM bootloader. + * + * We artificially split the FLASH to allow locating sections that we do not + * want loaded inoto OCRAM. This is to save on OCRAM where the speen of the + * code does not matter. + * + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x30000000, LENGTH = 3M + flashxip (rx) : ORIGIN = 0x30300000, LENGTH = 1M + /* Vectors @ boot+ivt OCRAM2 Flex RAM Boot IVT */ + sram (rwx) : ORIGIN = 0x20240000, LENGTH = 512K /* TODO OCRAM2*/ + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 0K + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 0 +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +EXTERN(g_flash_config) +EXTERN(g_image_vector_table) +EXTERN(g_boot_data) +EXTERN(g_dcd_data) + +ENTRY(_stext) + +SECTIONS +{ + /* Image Vector Table and Boot Data for booting from external flash */ + + .boot_hdr : ALIGN(4) + { + FILL(0xff) + __boot_hdr_start__ = ABSOLUTE(.) ; + KEEP(*(.boot_hdr.conf)) + . = 0x1000 ; + KEEP(*(.boot_hdr.ivt)) + . = 0x1020 ; + KEEP(*(.boot_hdr.boot_data)) + . = 0x1030 ; + KEEP(*(.boot_hdr.dcd_data)) + __boot_hdr_end__ = ABSOLUTE(.) ; + . = 0x2000 ; + } > flash + + /* Catch all the section we want not in OCRAM so that the *(.text .text.*) in flash does not */ + + .flashxip : ALIGN(4) + { + FILL(0xff) + + /* Order matters */ + + imxrt_start.o(.text) + imxrt_boot.o(.text) + + *(.slow_memory) + *(.rodata .rodata.*) + KEEP(*(__param*)) + *(.fixup) + *(.gnu.warning) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + + } > flashxip + + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + _etext = ABSOLUTE(.); + } > sram AT > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > sram AT > flash + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > sram AT > flash + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/imxrt/fmu-v6xrt/scripts/flash.ld b/boards/arm/imxrt/fmu-v6xrt/scripts/flash.ld new file mode 100644 index 00000000000..6e40c634ea4 --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/scripts/flash.ld @@ -0,0 +1,152 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Specify the memory areas */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x30020000, LENGTH = 4M-128K /* loaded by the PX4 bootloader */ + sram (rwx) : ORIGIN = 0x20240000, LENGTH = 1024K /* OCRAM1 + OCRAM2*/ + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 256K /* TODO FlexRAM partition */ + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 256K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +EXTERN(g_flash_config) +EXTERN(g_image_vector_table) +EXTERN(g_boot_data) + +ENTRY(_stext) + +SECTIONS +{ + /* Image Vector Table and Boot Data for booting from external flash */ + + .boot_hdr : ALIGN(4) + { + FILL(0xff) + . = 0x400 ; + __boot_hdr_start__ = ABSOLUTE(.) ; + KEEP(*(.boot_hdr.conf)) + . = 0x1000 ; + KEEP(*(.boot_hdr.ivt)) + . = 0x1020 ; + KEEP(*(.boot_hdr.boot_data)) + . = 0x1030 ; + KEEP(*(.boot_hdr.dcd_data)) + __boot_hdr_end__ = ABSOLUTE(.) ; + . = 0x2000 ; + } >flash + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .text : ALIGN(4) + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _boot_loadaddr = ORIGIN(flash); + _boot_size = LENGTH(flash); + _ram_size = LENGTH(sram); +} diff --git a/boards/arm/imxrt/fmu-v6xrt/scripts/kernel-space.ld b/boards/arm/imxrt/fmu-v6xrt/scripts/kernel-space.ld new file mode 100644 index 00000000000..c65ce0efdcc --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/scripts/kernel-space.ld @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : + { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > kocram AT > kflash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > kocram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/imxrt/fmu-v6xrt/scripts/memory.ld b/boards/arm/imxrt/fmu-v6xrt/scripts/memory.ld new file mode 100644 index 00000000000..968e0e421b8 --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/scripts/memory.ld @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The i.MXRT1064-EVK has 8MiB of Hyper FLASH beginning at address, + * 0x0060:0000, Up to 512Kb of DTCM RAM beginning at 0x2000:0000, and 1MiB OCRAM + * beginning at 0x2020:0000. Neither DTCM or SDRAM are used in this + * configuration. + * + * The user and kernel space partitions will be spanned with a single + * region of size 2**n bytes. As a consequence, as the partitions increase + * in size, the alignment requirement also increases. The sizes below give + * the largest possible user address spaces (but leave far too much for the + * OS). + * + * The solution to this wasted memory is to (1) use more than one region to + * span the user spaces, or (2) poke holes in a larger region (via sub- + * regions) to trim it to fit better. + * + * A detailed memory map for the 512KB SRAM region is as follows: + * + * 0x2020 0000: Kernel .data region. Typical size: 0.1KB + * ------ ---- Kernel .bss region. Typical size: 1.8KB + * 0x2020 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------ ---- Padded to 4KB + * 0x2040 0000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x2042 0000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------ ---- Beginning of user heap. Can vary with other settings. + * 0x2080 0000: End+1 of mappable OCRAM + */ + +/* Specify the memory areas */ + +MEMORY +{ + /* 16MiB of QSPI */ + + kflash (rx) : ORIGIN = 0x30000000, LENGTH = 1M + uflash (rx) : ORIGIN = 0x30200000, LENGTH = 1M + flash (rx) : ORIGIN = 0x30400000, LENGTH = 14M + + /* 1MiB of OCRAM */ + + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 256K + kocram (rwx) : ORIGIN = 0x20240000, LENGTH = 512K + uocram (rwx) : ORIGIN = 0x20280000, LENGTH = 512K +} + + + _ram_size = LENGTH(kocram) + LENGTH(uocram); \ No newline at end of file diff --git a/boards/arm/imxrt/fmu-v6xrt/scripts/user-space.ld b/boards/arm/imxrt/fmu-v6xrt/scripts/user-space.ld new file mode 100644 index 00000000000..bf11418dcdb --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/scripts/user-space.ld @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) +EXTERN(umm_trysemaphore) +EXTERN(umm_givesemaphore) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : + { + *(.userspace) + } > uflash + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : + { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > uocram AT > uflash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > uocram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/imxrt/fmu-v6xrt/src/CMakeLists.txt b/boards/arm/imxrt/fmu-v6xrt/src/CMakeLists.txt new file mode 100644 index 00000000000..22596a36b9c --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/CMakeLists.txt @@ -0,0 +1,33 @@ +# ############################################################################## +# boards/arm/imxrt/fmu-v6xrt/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS imxrt_boot.c imxrt_flexspi_nor_boot.c imxrt_flexspi_nor_flash.c + imxrt_clockconfig.c imxrt_bringup.c) + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_BOOT_RUNFROMFLASH) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") +elseif(CONFIG_BOOT_RUNFROMISRAM) + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/flash-ocram.ld") +endif() diff --git a/boards/arm/imxrt/fmu-v6xrt/src/Makefile b/boards/arm/imxrt/fmu-v6xrt/src/Makefile new file mode 100644 index 00000000000..f11b15bd63a --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/Makefile @@ -0,0 +1,34 @@ +############################################################################ +# boards/arm/imxrt/fmu-v6xrt/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = imxrt_boot.c imxrt_flexspi_nor_boot.c imxrt_flexspi_nor_flash.c +CSRCS += imxrt_clockconfig.c + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += imxrt_bringup.c +else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) +CSRCS += imxrt_bringup.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/imxrt/fmu-v6xrt/src/fmu-v6xrt.h b/boards/arm/imxrt/fmu-v6xrt/src/fmu-v6xrt.h new file mode 100644 index 00000000000..09e2401339b --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/fmu-v6xrt.h @@ -0,0 +1,341 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/src/fmu-v6xrt.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +#ifndef __BOARDS_ARM_IMXRT_FMU_V6XRT_SRC_FMU_V6XRT_H +#define __BOARDS_ARM_IMXRT_FMU_V6XRT_SRC_FMU_V6XRT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "imxrt_gpio.h" +#include "imxrt_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Touchscreen definitions **************************************************/ + +/* The i.MX RT1170 EVK has a connector (J48) for RK055AHD091-CTG or + * RK055IQH091-CTG LCDs. The RK055AHD091-CTG comes with the GT911 + * touchscreen driver chip integrated. GT911 is connected to the LPI2C5 bus. + */ + +/* LPI2C address of the GT911 touchscreen driver chip */ + +#define GT911_I2C_ADDRESS 0x5d + +/* i.MX RT 1176 GPIO Pin Definitions ****************************************/ + +/* LEDs */ + +/* There are five LED status indicators located on the EVK Board. + * The functions of these LEDs include: + * + * - Main Power Supply (D16) + * Green: DC 5V main supply is normal. + * Red: J43 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset LED - Red (D7) + * - OpenSDA LED - Red (D5) + * - USER LED 1 - Green (D6) + * - USER LED 2 - Red (D34) + * + * Only two LEDs, D6 & D34, are under software control. + */ + +#define GPIO_LED1 (GPIO_OUTPUT | IOMUX_LED_DEFAULT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT3 | GPIO_PIN3) /* GPIO_AD_04 */ +#define GPIO_LED2 (GPIO_OUTPUT | IOMUX_LED_DEFAULT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT3 | GPIO_PIN25) /* GPIO_AD_26 */ + +#define LED_DRIVER_PATH "/dev/userleds" + +/* Buttons ******************************************************************/ + +/* The IMXRT1170-EVK board has seven (sets of) switches or buttons: + * + * - External boot configuration switches (SW1) + * - External boot configuration switches (SW2) + * - MCU reset button (SW3) + * - System Reset Button / POR_BUTTON (SW4) + * - 5V power switch (SW5) + * - CPU ONOFF Button (SW6) + * - CPU Wakeup Button / USER_BUTTON (SW7) + * + * Only one button, SW7, can be used for user input. + */ + +#define GPIO_SW7 (GPIO_INTERRUPT | GPIO_INTBOTH_EDGES | \ + IOMUX_SW_DEFAULT | GPIO_PORT13 | \ + GPIO_PIN0) /* WAKEUP */ + +#define GPIO_SW7_INT (_IMXRT_GPIO13_BASE+0) + +/* LCD Backlight */ + +#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT3 | \ + GPIO_PIN30 | IOMUX_LCD_BL_DEFAULT) /* GPIO_AD_30 */ + +/* 10/100 Mbps Ethernet & Gigabit Ethernet */ + +/* 10/100 Mbps Ethernet Interrupt: GPIO_AD_12 + * Gigabit Ethernet Interrupt: GPIO_DISP_B2_12 + * + * This pin has a week pull-up within the PHY, is open-drain, and requires + * an external 1k ohm pull-up resistor (present on the EVK). A falling + * edge then indicates a change in state of the PHY. + */ + +#define GPIO_ENET_INT (IOMUX_ENET_INT_DEFAULT | GPIO_OUTPUT | \ + GPIO_PORT3 | GPIO_PIN11) /* GPIO_AD_12 */ +#define GPIO_ENET_IRQ IMXRT_IRQ_GPIO3_0_15 + +#define GPIO_ENET1G_INT (IOMUX_ENET_INT_DEFAULT | \ + GPIO_PORT5 | GPIO_PIN13) /* GPIO_DISP_B2_12 */ +#define GPIO_ENET1G_IRQ IMXRT_IRQ_GPIO5_13 + +/* 10/100 Mbps Ethernet Reset: GPIO_LPSR_12 + * Gigabit Ethernet Reset: GPIO_DISP_B2_13 + * + * The #RST uses inverted logic. The initial value of zero will put the + * PHY into the reset state. + */ + +#define GPIO_ENET_RST (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT6 | GPIO_PIN12 | \ + IOMUX_ENET_RST_DEFAULT) /* GPIO_LPSR_12 */ + +#define GPIO_ENET1G_RST (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT5 | GPIO_PIN14 | \ + IOMUX_ENET_RST_DEFAULT) /* GPIO_DISP_B2_13 */ + +/* LPSPI1 CS: GPIO_AD_29 */ + +#define IOMUX_LPSPI1_CS (IOMUX_SLEW_FAST | IOMUX_DRIVE_HIGHSTRENGTH | \ + IOMUX_PULL_UP) +#define GPIO_LPSPI1_CS (GPIO_OUTPUT | GPIO_OUTPUT_ONE | \ + GPIO_PORT3 | GPIO_PIN28 | \ + IOMUX_LPSPI1_CS) /* GPIO_AD_29 */ + +/* LPSPI6 CS: GPIO_LPSR_09 */ + +#define IOMUX_LPSPI6_CS (IOMUX_SLEW_FAST | IOMUX_DRIVE_HIGHSTRENGTH | \ + IOMUX_PULL_UP) +#define GPIO_LPSPI6_CS (GPIO_OUTPUT | GPIO_OUTPUT_ONE | \ + GPIO_PORT6 | GPIO_PIN9 | \ + IOMUX_LPSPI6_CS) /* GPIO_LPSR_09 */ + +/* Touchscreen + * + * Interrupt line: GPIO_AD_00 + * + * The interrupt line coming from the GT911 touchscreen driver IC. + * The touchscreen driver is integrated into the optional RK055AHD091-CTG LCD + * panel and it's connected to the LPI2C5 bus. + * + * Reset line: GPIO_AD_01 + * + * The reset line is active low. + */ + +#define GPIO_GT911_INTR IMXRT_IRQ_GPIO2_31 /* GPIO_AD_00 */ + +#define IOMUX_GT911_RST (IOMUX_PULL_NONE | IOMUX_CMOS_OUTPUT | \ + IOMUX_DRIVE_40OHM | IOMUX_SPEED_MEDIUM | \ + IOMUX_SLEW_SLOW) +#define GPIO_GT911_CTRST_N (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT3 | GPIO_PIN0 | \ + IOMUX_GT911_RST) /* GPIO_AD_01 */ + +/* Test Pins ****************************************************************/ + +#define BOARD_NGPIOIN 0 /* Amount of GPIO Input pins */ +#define BOARD_NGPIOOUT 4 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 0 /* Amount of GPIO Input w/ Interruption pins */ + +#define GPIO_GOUT1 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ + GPIO_PORT5 | GPIO_PIN12) /* GPIO_DISP_B2_11 */ + +#define GPIO_GOUT2 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ + GPIO_PORT5 | GPIO_PIN11) /* GPIO_DISP_B2_10 */ + +#define GPIO_GOUT3 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ + GPIO_PORT5 | GPIO_PIN13) /* GPIO_DISP_B2_12 */ + +#define GPIO_GOUT4 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \ + GPIO_PORT3 | GPIO_PIN3) /* GPIO_AD_04 */ + +/* USB OTG1 ID Pin： GPIO_AD_09 + * USB OTG2 ID Pin： GPIO_AD_08 + */ + +#define GPIO_USBOTG1_ID (GPIO_USB_OTG1_ID_1 | IOMUX_USBOTG_ID_DEFAULT) /* GPIO_AD_09 */ +#define GPIO_USBOTG2_ID (GPIO_USB_OTG2_ID_1 | IOMUX_USBOTG_ID_DEFAULT) /* GPIO_AD_08 */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: imxrt_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) +int imxrt_bringup(void); +#endif + +/**************************************************************************** + * Name: imxrt_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the i.MXRT1050 EVK. + * + ****************************************************************************/ + +void imxrt_spidev_initialize(void); + +/**************************************************************************** + * Name: imxrt_mmcsd_spi_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + * + ****************************************************************************/ + +#ifdef CONFIG_MMCSD_SPI +int imxrt_mmcsd_spi_initialize(int minor) +#endif + +/**************************************************************************** + * Name: imxrt_autoled_initialize + * + * Description: + * Initialize NuttX-controlled LED logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void imxrt_autoled_initialize(void); +#endif + +/**************************************************************************** + * Name: imxrt_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int imxrt_gpio_initialize(void); +#endif + +/**************************************************************************** + * Name: imxrt_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_FLEXCAN +int imxrt_can_setup(void); +#endif + +/**************************************************************************** + * Name: imxrt_adc_initialize + * + * Description: + * Initialize ADC drivers + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_ADC +int imxrt_adc_initialize(void); +#endif + +/**************************************************************************** + * Name: imxrt_ft5x06_register + * + * Description: + * Initialize ft5x06 IC touchscreen driver + * + ****************************************************************************/ + +#ifdef CONFIG_INPUT_FT5X06 +int imxrt_ft5x06_register(void); +#endif + +/**************************************************************************** + * Name: imxrt_backlight + * + * Description: + * Initialize the backlight pins of the LCD and turn it ON + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_LCD +void imxrt_lcd_initialize(void); +#endif + +#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST) +int imxrt_usbhost_initialize(void); +#endif + +#ifdef CONFIG_IMXRT1170_FLEXSPI_NOR +int imxrt_flexspi_nor_initialize(void); +#endif + +#ifdef CONFIG_IMXRT1170_FLEXSPI_FRAM +int imxrt_flexspi_fram_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_IMXRT_FMU_V6XRT_SRC_FMU_V6XRT_H */ diff --git a/boards/arm/imxrt/fmu-v6xrt/src/imxrt_boot.c b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_boot.c new file mode 100644 index 00000000000..ad3135f0de7 --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_boot.c @@ -0,0 +1,135 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/src/imxrt_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "imxrt_start.h" +#include "fmu-v6xrt.h" +#include "arm_internal.h" +#include "imxrt_flexspi_nor_boot.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_ocram_initialize + * + * Description: + * Called off reset vector to reconfigure the flexRAM + * and finish the FLASH to RAM Copy. + * + ****************************************************************************/ + +void imxrt_ocram_initialize(void) +{ + const uint32_t *src; + uint32_t *dest; + uint32_t regval; + + /* Reallocate 128K of Flex RAM from ITCM to OCRAM + * Final Configuration is + * 128 DTCM + * + * 128 FlexRAM OCRAM (202C:0000-202D:ffff) + * 256 FlexRAM OCRAM (2028:0000-202B:ffff) + * 512 System OCRAM2 (2020:0000-2027:ffff) + * */ + + putreg32(0xaa555555, IMXRT_IOMUXC_GPR_GPR17); + regval = getreg32(IMXRT_IOMUXC_GPR_GPR16); + putreg32(regval | GPR_GPR16_FLEXRAM_BANK_CFG_SEL, IMXRT_IOMUXC_GPR_GPR16); + + src = (uint32_t *) (LOCATE_IN_SRC(g_boot_data.start) + g_boot_data.size); + dest = (uint32_t *) (g_boot_data.start + g_boot_data.size); + + while (dest < (uint32_t *) &_etext) + { + *dest++ = *src++; + } +} + +/**************************************************************************** + * Name: imxrt_flexram_partition + * + * Description: + * Sets FlexRAM partitioning + * + ****************************************************************************/ + +void imxrt_flexram_partition(void) +{ +} + +/**************************************************************************** + * Name: imxrt_boardinitialize + * + * Description: + * All i.MX RT architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. + * + ****************************************************************************/ + +void imxrt_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + imxrt_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_intitialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + imxrt_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/imxrt/fmu-v6xrt/src/imxrt_bringup.c b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_bringup.c new file mode 100644 index 00000000000..c8aaed2b7ea --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_bringup.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/src/imxrt_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_IMXRT_USDHC +# include "imxrt_usdhc.h" +#endif + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_PL2303 +# include +#endif + +#include "imxrt_enet.h" +#include "fmu-v6xrt.h" + +#include /* Must always be included last */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Checking needed by MMC/SDCard */ + +#ifdef CONFIG_NSH_MMCSDMINOR +# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR +#else +# define MMCSD_MINOR 0 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if defined(CONFIG_I2C_DRIVER) && defined(CONFIG_IMXRT_LPI2C) +static void imxrt_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = imxrt_i2cbus_initialize(bus); + if (i2c == NULL) + { + i2cerr("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + imxrt_i2cbus_uninitialize(i2c); + } + } +} +#endif + +#ifdef CONFIG_IMXRT_USDHC +static int nsh_sdmmc_initialize(void) +{ + struct sdio_dev_s *sdmmc; + int ret = 0; + + /* Get an instance of the SDIO interface */ + + sdmmc = imxrt_usdhc_initialize(0); + if (!sdmmc) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SD/MMC\n"); + } + else + { + /* Bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(0, sdmmc); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + } + + imxrt_usdhc_set_sdio_card_isr(sdmmc, NULL, NULL); + } + + return OK; +} +#else +# define nsh_sdmmc_initialize() (OK) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int imxrt_bringup(void) +{ + int ret; + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_I2C_DRIVER) && defined(CONFIG_IMXRT_LPI2C5) + imxrt_i2c_register(5); +#endif + +#ifdef CONFIG_IMXRT_USDHC + /* Initialize SDHC-base MMC/SD card support */ + + nsh_sdmmc_initialize(); +#endif + +#ifdef CONFIG_IMXRT_LPSPI + imxrt_spidev_initialize(); +#endif + +#ifdef CONFIG_MMCSD_SPI + /* Initialize SPI-based MMC/SD card support */ + + ret = imxrt_mmcsd_spi_initialize(MMCSD_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SD slot %d: %d\n", ret); + } +#endif + +#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST) + ret = imxrt_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB host services: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#if defined(CONFIG_IMXRT_ENET) && defined(CONFIG_NETDEV_LATEINIT) + ret = imxrt_netinitialize(0); +#endif + +#ifdef CONFIG_IMXRT_FLEXCAN + ret = imxrt_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: imxrt_can_setup() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Initialize the GPIO driver */ + + ret = imxrt_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_IMXRT_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = imxrt_adc_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: imxrt_adc_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_FT5X06 + /* Initialize the FT5X06 touchscreen driver */ + + ret = imxrt_ft5x06_register(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: imxrt_ft5x06_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_IMXRT_LCD + /* Initialize the backlight pin and turn it to ON. */ + + imxrt_lcd_initialize(); +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif /* CONFIG_INPUT_BUTTONS */ + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PL2303 + usbdev_serialinitialize(0); +#endif + +#ifdef CONFIG_IMXRT1170_FLEXSPI_NOR + ret = imxrt_flexspi_nor_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: imxrt_flexspi_nor_initialize failed: %d\n", ret); + } +#endif /* CONFIG_IMXRT1170_FLEXSPI_NOR */ + +#ifdef CONFIG_IMXRT1170_FLEXSPI_FRAM + ret = imxrt_flexspi_fram_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: imxrt_flexspi_nor_initialize failed: %d\n", ret); + } +#endif /* CONFIG_IMXRT1170_FLEXSPI_FRAM */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/imxrt/fmu-v6xrt/src/imxrt_clockconfig.c b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_clockconfig.c new file mode 100644 index 00000000000..730ee18dc16 --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_clockconfig.c @@ -0,0 +1,506 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/src/imxrt_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imxrt_clockconfig.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each FMU-V6XRT board must provide the following initialized structure. + * This is needed to establish the initial board clocking. + */ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .ccm = + { + .m7_clk_root = + { + .enable = 1, + .div = 1, + .mux = M7_CLK_ROOT_PLL_ARM_CLK, + }, + .m4_clk_root = + { + .enable = 1, + .div = 1, + .mux = M4_CLK_ROOT_SYS_PLL3_PFD3, + }, + .bus_clk_root = + { + .enable = 1, + .div = 2, + .mux = BUS_CLK_ROOT_SYS_PLL3_CLK, + }, + .bus_lpsr_clk_root = + { + .enable = 1, + .div = 3, + .mux = BUS_LPSR_CLK_ROOT_SYS_PLL3_CLK, + }, + .semc_clk_root = + { + .enable = 0, + .div = 3, + .mux = SEMC_CLK_ROOT_SYS_PLL2_PFD1, + }, + .cssys_clk_root = + { + .enable = 1, + .div = 1, + .mux = CSSYS_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .cstrace_clk_root = + { + .enable = 1, + .div = 4, + .mux = CSTRACE_CLK_ROOT_SYS_PLL2_CLK, + }, + .m4_systick_clk_root = + { + .enable = 1, + .div = 1, + .mux = M4_SYSTICK_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .m7_systick_clk_root = + { + .enable = 1, + .div = 240, + .mux = M7_SYSTICK_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .adc1_clk_root = + { + .enable = 1, + .div = 6, + .mux = ADC1_CLK_ROOT_SYS_PLL2_CLK, + }, + .adc2_clk_root = + { + .enable = 1, + .div = 6, + .mux = ADC2_CLK_ROOT_SYS_PLL2_CLK, + }, + .acmp_clk_root = + { + .enable = 1, + .div = 1, + .mux = ACMP_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .flexio1_clk_root = /* 432 / 4 = 108Mhz */ + { + .enable = 1, + .div = 4, + .mux = FLEXIO1_CLK_ROOT_SYS_PLL2_PFD3, + }, + .flexio2_clk_root = + { + .enable = 1, + .div = 1, + .mux = FLEXIO2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .gpt1_clk_root = + { + .enable = 1, + .div = 1, + .mux = GPT1_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .gpt2_clk_root = + { + .enable = 1, + .div = 1, + .mux = GPT2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .gpt3_clk_root = + { + .enable = 1, + .div = 1, + .mux = GPT3_CLK_ROOT_OSC_24M, + }, + .gpt4_clk_root = + { + .enable = 1, + .div = 1, + .mux = GPT4_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .gpt5_clk_root = + { + .enable = 1, + .div = 1, + .mux = GPT5_CLK_ROOT_OSC_24M, + }, + .gpt6_clk_root = + { + .enable = 1, + .div = 1, + .mux = GPT6_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .flexspi1_clk_root = + { + .enable = 1, + .div = 4, + .mux = FLEXSPI1_CLK_ROOT_SYS_PLL2_CLK, + }, + .flexspi2_clk_root = + { + .enable = 1, + .div = 1, + .mux = FLEXSPI2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .can1_clk_root = /* 240 / 3 = 80Mhz */ + { + .enable = 1, + .div = 3, + .mux = CAN1_CLK_ROOT_SYS_PLL3_DIV2, + }, + .can2_clk_root = /* 240 / 3 = 80Mhz */ + { + .enable = 1, + .div = 3, + .mux = CAN2_CLK_ROOT_SYS_PLL3_DIV2, + }, + .can3_clk_root = /* 480 / 6 = 80Mhz */ + { + .enable = 1, + .div = 6, + .mux = CAN3_CLK_ROOT_SYS_PLL3_CLK, + }, + .lpuart1_clk_root = /* 528 / 22 = 24Mhz */ + { + .enable = 1, + .div = 22, + .mux = LPUART1_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpuart3_clk_root = /* 528 / 11 = 48Mhz */ + { + .enable = 1, + .div = 11, + .mux = LPUART3_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpuart4_clk_root = /* 528 / 11 = 48Mhz */ + { + .enable = 1, + .div = 11, + .mux = LPUART4_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpuart5_clk_root = /* 528 / 11 = 48Mhz */ + { + .enable = 1, + .div = 11, + .mux = LPUART5_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpuart6_clk_root = /* 528 / 11 = 48Mhz */ + { + .enable = 1, + .div = 11, + .mux = LPUART6_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpuart8_clk_root = /* 528 / 11 = 48Mhz */ + { + .enable = 1, + .div = 11, + .mux = LPUART8_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpuart10_clk_root = /* 528 / 11 = 48Mhz */ + { + .enable = 1, + .div = 11, + .mux = LPUART10_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpuart11_clk_root = /* 480 / 10 = 48Mhz */ + { + .enable = 1, + .div = 10, + .mux = LPUART11_CLK_ROOT_SYS_PLL3_CLK, + }, + .lpi2c1_clk_root = /* 528 / 22 = 24Mhz */ + { + .enable = 1, + .div = 22, + .mux = LPI2C1_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpi2c2_clk_root = /* 528 / 22 = 24Mhz */ + { + .enable = 1, + .div = 22, + .mux = LPI2C2_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpi2c3_clk_root = /* 528 / 22 = 24Mhz */ + { + .enable = 1, + .div = 22, + .mux = LPI2C3_CLK_ROOT_SYS_PLL2_CLK, + }, + .lpi2c6_clk_root = /* 480 / 20 = 24Mhz */ + { + .enable = 1, + .div = 20, + .mux = LPI2C6_CLK_ROOT_SYS_PLL3_CLK, + }, + .lpspi1_clk_root = /* 200 / 2 = 100Mhz */ + { + .enable = 1, + .div = 2, + .mux = LPSPI1_CLK_ROOT_SYS_PLL1_DIV5, + }, + .lpspi2_clk_root = /* 200 / 2 = 100Mhz */ + { + .enable = 1, + .div = 2, + .mux = LPSPI2_CLK_ROOT_SYS_PLL1_DIV5, + }, + .lpspi3_clk_root = /* 200 / 2 = 100Mhz */ + { + .enable = 1, + .div = 2, + .mux = LPSPI3_CLK_ROOT_SYS_PLL1_DIV5, + }, + .lpspi6_clk_root = /* 200 / 2 = 100Mhz */ + { + .enable = 1, + .div = 2, + .mux = LPSPI6_CLK_ROOT_SYS_PLL1_DIV5, + }, + .emv1_clk_root = + { + .enable = 0, + .div = 1, + .mux = EMV1_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .emv2_clk_root = + { + .enable = 0, + .div = 1, + .mux = EMV2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .enet1_clk_root = + { + .enable = 0, + .div = 10, + .mux = ENET1_CLK_ROOT_SYS_PLL1_DIV2, + }, + .enet2_clk_root = + { + .enable = 0, + .div = 10, + .mux = ENET2_CLK_ROOT_SYS_PLL1_DIV2, + }, + .enet_qos_clk_root = + { + .enable = 0, + .div = 1, + .mux = ENET_QOS_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .enet_25m_clk_root = + { + .enable = 1, + .div = 1, + .mux = ENET_25M_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .enet_timer1_clk_root = + { + .enable = 0, + .div = 1, + .mux = ENET_TIMER1_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .enet_timer2_clk_root = + { + .enable = 0, + .div = 1, + .mux = ENET_TIMER2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .enet_timer3_clk_root = + { + .enable = 0, + .div = 1, + .mux = ENET_TIMER3_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .usdhc1_clk_root = + { + .enable = 1, + .div = 2, + .mux = USDHC1_CLK_ROOT_SYS_PLL2_PFD2, + }, + .usdhc2_clk_root = + { + .enable = 0, + .div = 1, + .mux = USDHC2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .asrc_clk_root = + { + .enable = 0, + .div = 1, + .mux = ASRC_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .mqs_clk_root = + { + .enable = 0, + .div = 1, + .mux = MQS_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .mic_clk_root = + { + .enable = 0, + .div = 1, + .mux = MIC_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .spdif_clk_root = + { + .enable = 0, + .div = 1, + .mux = SPDIF_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .sai1_clk_root = + { + .enable = 0, + .div = 1, + .mux = SAI1_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .sai2_clk_root = + { + .enable = 0, + .div = 1, + .mux = SAI2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .sai3_clk_root = + { + .enable = 0, + .div = 1, + .mux = SAI3_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .sai4_clk_root = + { + .enable = 0, + .div = 1, + .mux = SAI4_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .gc355_clk_root = + { + .enable = 0, + .div = 2, + .mux = GC355_CLK_ROOT_VIDEO_PLL_CLK, + }, + .lcdif_clk_root = + { + .enable = 0, + .div = 1, + .mux = LCDIF_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .lcdifv2_clk_root = + { + .enable = 0, + .div = 1, + .mux = LCDIFV2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .mipi_ref_clk_root = + { + .enable = 0, + .div = 1, + .mux = MIPI_REF_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .mipi_esc_clk_root = + { + .enable = 0, + .div = 1, + .mux = MIPI_ESC_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .csi2_clk_root = + { + .enable = 0, + .div = 1, + .mux = CSI2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .csi2_esc_clk_root = + { + .enable = 0, + .div = 1, + .mux = CSI2_ESC_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .csi2_ui_clk_root = + { + .enable = 0, + .div = 1, + .mux = CSI2_UI_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .csi_clk_root = + { + .enable = 0, + .div = 1, + .mux = CSI_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .cko1_clk_root = + { + .enable = 0, + .div = 1, + .mux = CKO1_CLK_ROOT_OSC_RC_48M_DIV2, + }, + .cko2_clk_root = + { + .enable = 0, + .div = 1, + .mux = CKO2_CLK_ROOT_OSC_RC_48M_DIV2, + }, + }, + .arm_pll = + { + /* ARM_PLL = Fin * (loop_div / (2 * post_div)), so 166 / 4 here. */ + + .post_div = 0, /* 0 = /2, 1 = /4, 2 = /8, 3 = /1 */ + .loop_div = 166, /* ARM_PLL = 996 MHz */ + }, + .sys_pll1 = + { + .enable = 1, + .div = 41, + .num = 178956970, + .denom = 268435455, + }, + .sys_pll2 = + { + .mfd = 268435455, + .ss_enable = 0, + .pfd0 = 27, /* (528 * 18) / 27 = 352 MHz */ + .pfd1 = 16, /* (528 * 18) / 16 = 594 MHz */ + .pfd2 = 24, /* (528 * 18) / 24 = 396 MHz */ + .pfd3 = 22, /* (528 * 18) / 22 = 216 MHz */ + }, + .sys_pll3 = + { + .pfd0 = 13, /* (480 * 18) / 13 = 8640/13 = 664.62 MHz */ + .pfd1 = 17, /* (480 * 18) / 17 = 8640/17 = 508.24 MHz */ + .pfd2 = 32, /* (480 * 18) / 32 = 270 MHz */ + .pfd3 = 22, /* (480 * 18) / 22 = 8640/20 = 392.73 MHz */ + } +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.c b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.c new file mode 100644 index 00000000000..56a16cae551 --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.c @@ -0,0 +1,55 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "imxrt_flexspi_nor_boot.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +locate_data(".boot_hdr.ivt") +const struct ivt_s g_image_vector_table = +{ + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)IMAG_VECTOR_TABLE, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +locate_data(".boot_hdr.boot_data") +const struct boot_data_s g_boot_data = +{ + IMAGE_DEST, /* boot start location */ + (IMAGE_DEST_END - IMAGE_DEST), /* size */ + PLUGIN_FLAG, /* Plugin flag */ + 0xffffffff /* empty - extra data word */ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.h b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.h new file mode 100644 index 00000000000..d433c1f32f2 --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.h @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_boot.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_BOOT_H +#define __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_BOOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IVT Data */ + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xf +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xf + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +#define IVT_TAG_HEADER (0xd1) /* Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) + +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) +#define IVT_RSVD (uint32_t)(0x00000000) + +/* DCD Data */ + +#define DCD_TAG_HEADER (0xd2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#define FLASH_BASE 0x30000000 +/* The part holds 64M, but programming all of it costs more time than the + * image needs. + */ + +#define FLASH_END FLASH_BASE + (3 * (1024 * 1024)) + +/* This has to account for the memory configuration the bootloader + * leaves behind. + */ + +#define ROM_BOOTLOADER_OCRAM_RES 0x8000 +#define OCRAM_BASE (0x20200000 + ROM_BOOTLOADER_OCRAM_RES) +#define OCRAM_END (OCRAM_BASE + (512 * 1024) + (256 * 1024) - ROM_BOOTLOADER_OCRAM_RES) + +#define SCLK 1 +#if defined(CONFIG_BOOT_RUNFROMFLASH) +# define IMAGE_DEST FLASH_BASE +# define IMAGE_DEST_END FLASH_END +# define IMAGE_DEST_OFFSET 0 +#else +# define IMAGE_DEST OCRAM_BASE +# define IMAGE_DEST_END OCRAM_END +# define IMAGE_DEST_OFFSET IVT_SIZE +#endif + +#define LOCATE_IN_DEST(x) (((uint32_t)(x)) - FLASH_BASE + IMAGE_DEST) +#define LOCATE_IN_SRC(x) (((uint32_t)(x)) - IMAGE_DEST + FLASH_BASE) + +#define DCD_ADDRESS 0 +#define BOOT_DATA_ADDRESS LOCATE_IN_DEST(&g_boot_data) +#define CSF_ADDRESS 0 +#define PLUGIN_FLAG (uint32_t)0 + +/* Located in Destination Memory */ + +#define IMAGE_ENTRY_ADDRESS ((uint32_t)&_vectors) +#define IMAG_VECTOR_TABLE LOCATE_IN_DEST(&g_image_vector_table) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* IVT Data */ + +struct ivt_s +{ + /* Header with tag #HAB_TAG_IVT, length and HAB version fields + * (see data) + */ + + uint32_t hdr; + + /* Absolute address of the first instruction to execute from the + * image + */ + + uint32_t entry; + + /* Reserved in this version of HAB: should be NULL. */ + + uint32_t reserved1; + + /* Absolute address of the image DCD: may be NULL. */ + + uint32_t dcd; + + /* Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + + uint32_t boot_data; + + /* Absolute address of the IVT. */ + + uint32_t self; + + /* Absolute address of the image CSF. */ + + uint32_t csf; + + /* Reserved in this version of HAB: should be zero. */ + + uint32_t reserved2; +}; + +/* Boot Data */ + +struct boot_data_s +{ + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placeholder to make even 0x10 size */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern const struct boot_data_s g_boot_data; +extern const uint8_t g_dcd_data[]; +extern const void * const _vectors[]; + +#endif /* __BOARDS_PX4_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_BOOT_H */ diff --git a/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c new file mode 100644 index 00000000000..01802cc0930 --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c @@ -0,0 +1,178 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http: + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "imxrt_flexspi_nor_flash.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +locate_data(".boot_hdr.conf") +const struct flexspi_nor_config_s g_flash_config = +{ + .mem_config = + { +#if !defined(CONFIG_BOARD_BOOTLOADER_INVALID_FCB) + .tag = FLEXSPI_CFG_BLK_TAG, +#else + .tag = 0xffffffffl, +#endif + .version = FLEXSPI_CFG_BLK_VERSION, + .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY, + .cs_hold_time = 1, + .cs_setup_time = 1, + .device_mode_cfg_enable = 1, + .device_mode_type = DEVICE_CONFIG_CMD_TYPE_GENERIC, + .wait_time_cfg_commands = 1, + .controller_misc_option = + (1u << FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN), + .device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR, + .sflash_pad_type = SERIAL_FLASH_1PAD, + .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_30MHz, + .sflash_a1size = 64ul * 1024u * 1024u, + .data_valid_time = + { + [0] = 0, + }, + .busy_offset = 0u, + .busybit_polarity = 0u, + .lookup_table = + { + /* Read Dedicated 3Byte Address Read(0x03), 24bit address */ + + [0 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x03, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + [0 + 1] = FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x04, + STOP, FLEXSPI_1PAD, 0), + }, + }, + .page_size = 256u, + .sector_size = 4u * 1024u, + .blocksize = 64u * 1024u, + .is_uniform_blocksize = false, + .ipcmd_serial_clkfreq = 1, + .serial_nor_type = 2, + .reserve2[0] = 0x7008200, +}; + +const struct flexspi_nor_config_s g_flash_fast_config = +{ + .mem_config = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_EXT_INPUT_FROM_DQSPAD, + .cs_hold_time = 1, + .cs_setup_time = 1, + .device_mode_cfg_enable = 1, + .device_mode_type = DEVICE_CONFIG_CMD_TYPE_SPI2XPI, + .wait_time_cfg_commands = 1, + .device_mode_seq = + { + .seq_num = 1, + .seq_id = 6, /* See Lookup table for more details */ + .reserved = 0, + }, + .device_mode_arg = 2, /* Enable OPI DDR mode */ + .controller_misc_option = + (1u << FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN) | + (1u << FLEXSPIMISC_OFFSET_DDR_MODE_EN), + .device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR, + .sflash_pad_type = SERIAL_FLASH_8PADS, + .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_200MHz, + .sflash_a1size = 64ul * 1024u * 1024u, + .data_valid_time = + { + [0] = 0, + }, + .busy_offset = 0u, + .busybit_polarity = 0u, + .lookup_table = + { + /* Read. Macronix wants 20 dummy cycles at 200MHz, and the + * operand is 2N in DDR mode, hence 0x28. + */ + + [0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xee, + CMD_DDR, FLEXSPI_8PAD, 0x11), + [0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, + DUMMY_DDR, FLEXSPI_8PAD, 0x28), + [0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, + STOP, FLEXSPI_1PAD, 0x00), + + /* Read status */ + + [4 * 2 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x05, + CMD_DDR, FLEXSPI_8PAD, 0xfa), + [4 * 2 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, + DUMMY_DDR, FLEXSPI_8PAD, 0x04), + [4 * 2 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, + STOP, FLEXSPI_1PAD, 0x00), + + /* Write enable SPI */ + + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, + STOP, FLEXSPI_1PAD, 0x00), + + /* Write enable OPI SPI */ + + [4 * 4 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x06, + CMD_DDR, FLEXSPI_8PAD, 0xf9), + + /* Erase sector */ + + [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x21, + CMD_DDR, FLEXSPI_8PAD, 0xde), + [4 * 5 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, + STOP, FLEXSPI_1PAD, 0x00), + + /* Write Configuration Register 2 =01, Enable OPI DDR mode */ + + [4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x72, + CMD_SDR, FLEXSPI_1PAD, 0x00), + [4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, + CMD_SDR, FLEXSPI_1PAD, 0x00), + [4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + + /* Page program */ + + [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x12, + CMD_DDR, FLEXSPI_8PAD, 0xed), + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, + WRITE_DDR, FLEXSPI_8PAD, 0x04), + }, + }, + .page_size = 256u, + .sector_size = 4u * 1024u, + .blocksize = 64u * 1024u, + .is_uniform_blocksize = false, + .ipcmd_serial_clkfreq = 1, + .serial_nor_type = 2, + .reserve2[0] = 0x7008200, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.h b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.h new file mode 100644 index 00000000000..4abd98e0bd8 --- /dev/null +++ b/boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.h @@ -0,0 +1,359 @@ +/**************************************************************************** + * boards/arm/imxrt/fmu-v6xrt/src/imxrt_flexspi_nor_flash.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_IMXRT_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_FLASH_H +#define __BOARDS_ARM_IMXRT_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* FLEXSPI memory config block related definitions */ + +#define FLEXSPI_CFG_BLK_TAG (0x42464346ul) +#define FLEXSPI_CFG_BLK_VERSION (0x56010400ul) +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ + +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related definitions */ + +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0a +#define LEARN_DDR 0x2a +#define DATSZ_SDR 0x0b +#define DATSZ_DDR 0x2b +#define DUMMY_SDR 0x0c +#define DUMMY_DDR 0x2c +#define DUMMY_RWDS_SDR 0x0d +#define DUMMY_RWDS_DDR 0x2d +#define JMP_ON_CS 0x1f +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_OPERAND0_MASK (0xffu) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & \ + FLEXSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300u) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8u) +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & \ + FLEXSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_OPCODE0_MASK (0xfc00u) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10u) +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & \ + FLEXSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPERAND1_MASK (0xff0000u) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & \ + FLEXSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000u) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24u) +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t) \ + (((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & \ + FLEXSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_OPCODE1_MASK (0xfc000000u) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26u) +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & \ + FLEXSPI_LUT_OPCODE1_MASK) + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ + FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +/* */ + +#define NOR_CMD_INDEX_READ CMD_INDEX_READ +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE +#define NOR_CMD_INDEX_ERASESECTOR 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE +#define NOR_CMD_INDEX_CHIPERASE 5 +#define NOR_CMD_INDEX_DUMMY 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 + +/* READ LUT sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ + +/* Read Status LUT sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS + +/* 2 Read status DPI/QPI/OPI sequence id in LUT stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2 + +/* 3 Write Enable sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE + +/* 4 Write Enable DPI/QPI/OPI sequence id in LUT stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 + +/* 5 Erase Sector sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 + +/* 8 Erase Block sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 + +/* 9 Program sequence id in lookupTable stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE + +/* 11 Chip Erase sequence in lookupTable id stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 + +/* 13 Read SFDP sequence in lookupTable id stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 + +/* 14 Restore 0-4-4/0-8-8 mode sequence id in LUT stored in config block */ + +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14 + +/* 15 Exit 0-4-4/0-8-8 mode sequence id in LUT stored in config blobk */ + +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Definitions for FlexSPI Serial Clock Frequency */ + +enum flexspi_serial_clkfreq_e +{ + FLEXSPI_SERIAL_CLKFREQ_30MHz = 1, + FLEXSPI_SERIAL_CLKFREQ_50MHz = 2, + FLEXSPI_SERIAL_CLKFREQ_60MHz = 3, + FLEXSPI_SERIAL_CLKFREQ_75MHz = 4, + FLEXSPI_SERIAL_CLKFREQ_80MHz = 5, + FLEXSPI_SERIAL_CLKFREQ_100MHz = 6, + FLEXSPI_SERIAL_CLKFREQ_133MHz = 7, + FLEXSPI_SERIAL_CLKFREQ_166MHz = 8, + FLEXSPI_SERIAL_CLKFREQ_200MHz = 9, +}; + +/* FlexSPI clock configuration type */ + +enum flexspi_serial_clockmode_e +{ + FLEXSPI_CLKMODE_SDR, + FLEXSPI_CLKMODE_DDR, +}; + +/* FlexSPI Read Sample Clock Source definition */ + +enum flash_read_sample_clk_e +{ + FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY = 0, + FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD = 1, + FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD = 2, + FLASH_READ_SAMPLE_CLK_EXT_INPUT_FROM_DQSPAD = 3, +}; + +/* Misc feature bit definitions */ + +enum flash_misc_feature_e +{ + FLEXSPIMISC_OFFSET_DIFFCLKEN = 0, /* Bit for Differential clock enable */ + FLEXSPIMISC_OFFSET_CK2EN = 1, /* Bit for CK2 enable */ + FLEXSPIMISC_OFFSET_PARALLELEN = 2, /* Bit for Parallel mode enable */ + FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */ + FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */ + FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */ + FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock configuration indication. */ +}; + +/* Flash Type Definition */ + +enum flash_flash_type_e +{ + FLEXSPI_DEVICE_TYPE_SERIAL_NOR = 1, /* Flash devices are Serial NOR */ + FLEXSPI_DEVICE_TYPE_SERIAL_NAND = 2, /* Flash devices are Serial NAND */ + FLEXSPI_DEVICE_TYPE_SERIAL_RAM = 3, /* Flash devices are Serial RAM/HyperFLASH */ + FLEXSPI_DEVICE_TYPE_MCP_NOR_NAND = 0x12, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */ + FLEXSPI_DEVICE_TYPE_MCP_NOR_RAM = 0x13, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */ +}; + +/* Flash Pad Definitions */ + +enum flash_flash_pad_e +{ + SERIAL_FLASH_1PAD = 1, + SERIAL_FLASH_2PADS = 2, + SERIAL_FLASH_4PADS = 4, + SERIAL_FLASH_8PADS = 8, +}; + +/* Flash Configuration Command Type */ + +enum flash_config_cmd_e +{ + DEVICE_CONFIG_CMD_TYPE_GENERIC, /* Generic command, for example: configure dummy cycles, drive strength, etc */ + DEVICE_CONFIG_CMD_TYPE_QUADENABLE, /* Quad Enable command */ + DEVICE_CONFIG_CMD_TYPE_SPI2XPI, /* Switch from SPI to DPI/QPI/OPI mode */ + DEVICE_CONFIG_CMD_TYPE_XPI2SPI, /* Switch from DPI/QPI/OPI to SPI mode */ + DEVICE_CONFIG_CMD_TYPE_SPI2NO_CMD, /* Switch to 0-4-4/0-8-8 mode */ + DEVICE_CONFIG_CMD_TYPE_RESET, /* Reset device command */ +}; + +/* FlexSPI LUT Sequence structure */ + +struct flexspi_lut_seq_s +{ + uint8_t seq_num; /* Sequence Number, valid number: 1-16 */ + uint8_t seq_id; /* Sequence Index, valid number: 0-15 */ + uint16_t reserved; +}; + +/* FlexSPI Memory Configuration Block */ + +struct flexspi_mem_config_s +{ + uint32_t tag; + uint32_t version; + uint32_t reserved0; + uint8_t read_sample_clksrc; + uint8_t cs_hold_time; + uint8_t cs_setup_time; + uint8_t column_address_width; /* [0x00f-0x00f] Column Address with, for + * HyperBus protocol, it is fixed to 3, + * For Serial NAND, need to refer to + * datasheet + */ + uint8_t device_mode_cfg_enable; + uint8_t device_mode_type; + uint16_t wait_time_cfg_commands; + struct flexspi_lut_seq_s device_mode_seq; + uint32_t device_mode_arg; + uint8_t config_cmd_enable; + uint8_t config_mode_type[3]; + struct flexspi_lut_seq_s config_cmd_seqs[3]; + uint32_t reserved1; + uint32_t config_cmd_args[3]; + uint32_t reserved2; + uint32_t controller_misc_option; + uint8_t device_type; + uint8_t sflash_pad_type; + uint8_t serial_clk_freq; + uint8_t lut_custom_seq_enable; + uint32_t reserved3[2]; + uint32_t sflash_a1size; + uint32_t sflash_a2size; + uint32_t sflash_b1size; + uint32_t sflash_b2size; + uint32_t cspad_setting_override; + uint32_t sclkpad_setting_override; + uint32_t datapad_setting_override; + uint32_t dqspad_setting_override; + uint32_t timeout_in_ms; + uint32_t command_interval; + uint16_t data_valid_time[2]; + uint16_t busy_offset; + uint16_t busybit_polarity; + uint32_t lookup_table[64]; + struct flexspi_lut_seq_s lut_customseq[12]; + uint32_t reserved4[4]; +}; + +/* Serial NOR configuration block */ + +struct flexspi_nor_config_s +{ + struct flexspi_mem_config_s mem_config; /* Common memory configuration info + * via FlexSPI + */ + + uint32_t page_size; /* Page size of Serial NOR */ + uint32_t sector_size; /* Sector size of Serial NOR */ + uint8_t ipcmd_serial_clkfreq; /* Clock frequency for IP command */ + uint8_t is_uniform_blocksize; /* Sector/Block size is the same */ + uint8_t reserved0[2]; /* Reserved for future use */ + uint8_t serial_nor_type; /* Serial NOR Flash type: 0/1/2/3 */ + uint8_t need_exit_nocmdmode; /* Need to exit NoCmd mode before + * other IP command + */ + + uint8_t halfclk_for_nonreadcmd; /* Half the Serial Clock for non-read + * command: true/false + */ + + uint8_t need_restore_nocmdmode; /* Need to Restore NoCmd mode after IP + * command execution + */ + + uint32_t blocksize; /* Block size */ + uint32_t reserve2[11]; /* Reserved for future use */ +}; + +#endif /* __BOARDS_ARM_IMXRT_FMU_V6XRT_SRC_IMXRT_FLEXSPI_NOR_FLASH_H */