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arch/arm/imxrt: Clean up imxrt118x System Reset Controller definitions
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Move the imxrt118x SRC register defintions to an own file. They differ from the other imxrt chips, and were also scattered between blockctrl and a common imxrt_src headers. Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit is contained in:
Jukka Laitinen
Xiang Xiao
parent
45de63940b
commit
59faf7ed2b
4 changed files with 110 additions and 50 deletions
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@ -30,6 +30,10 @@
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#include <nuttx/config.h>
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#include "hardware/imxrt_memorymap.h"
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#if defined(CONFIG_ARCH_FAMILY_IMXRT118x)
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# include "hardware/rt118x/imxrt118x_src.h"
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#else
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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@ -141,4 +145,6 @@
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* by application software.
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*/
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#endif /* CONFIG_ARCH_FAMILY_IMXRT118x */
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#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SRC_H */
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@ -84,54 +84,4 @@
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#define AON_NMI_CTRL_M7_NMI_MASK (1u << 0)
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#define AON_NMI_CTRL_M33_NMI_MASK (1u << 1)
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/* SRC general registers (IMXRT1180RM Ch. 27) *******************************/
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#define IMXRT_SRC_AUTHEN_CTRL (IMXRT_SRC_BASE + 0x004)
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#define IMXRT_SRC_SCR (IMXRT_SRC_BASE + 0x010) /* Control */
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#define IMXRT_SRC_SRTMR (IMXRT_SRC_BASE + 0x014) /* Reset Trigger */
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#define IMXRT_SRC_SRMASK (IMXRT_SRC_BASE + 0x018) /* Reset Mask */
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#define IMXRT_SRC_SBMR1 (IMXRT_SRC_BASE + 0x040) /* Boot Mode 1 */
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#define IMXRT_SRC_SBMR2 (IMXRT_SRC_BASE + 0x044) /* Boot Mode 2 */
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#define IMXRT_SRC_SRSR_BBSM (IMXRT_SRC_BASE + 0x04c)
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#define IMXRT_SRC_SRSR (IMXRT_SRC_BASE + 0x050) /* Reset Status */
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/* SRC.SCR bit fields */
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#define SRC_SCR_BT_RELEASE_M7 (1u << 0) /* Release M7 from boot hold */
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/* SRC MIX_SLICE registers (IMXRT1180RM Ch. 27, per power domain slice).
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* Bases for each slice (AON/WAKEUP/MEGA/NETC/CM33/CM7 platforms) are in
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* hardware/rt118x/imxrt118x_memorymap.h.
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*/
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#define IMXRT_SRC_SLICE_AUTHEN_CTRL(base) ((base) + 0x004)
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#define IMXRT_SRC_SLICE_SW_CTRL(base) ((base) + 0x010)
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#define IMXRT_SRC_SLICE_FUNC_STAT(base) ((base) + 0x014)
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#define IMXRT_SRC_SLICE_UPI_STAT_0(base) ((base) + 0x020)
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#define IMXRT_SRC_SLICE_UPI_STAT_1(base) ((base) + 0x024)
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#define IMXRT_SRC_SLICE_LPM_SETTING_0(base) ((base) + 0x030)
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#define IMXRT_SRC_SLICE_LPM_SETTING_1(base) ((base) + 0x034)
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#define IMXRT_SRC_SLICE_LPM_SETTING_2(base) ((base) + 0x038)
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#define IMXRT_SRC_SLICE_EDGELOCK_HDSK_CTRL(base) ((base) + 0x040)
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#define IMXRT_SRC_SLICE_EDGELOCK_HDSK_STAT(base) ((base) + 0x044)
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#define IMXRT_SRC_SLICE_PSW_CTRL(base) ((base) + 0x05c)
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#define IMXRT_SRC_SLICE_PSW_STAT(base) ((base) + 0x060)
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#define IMXRT_SRC_SLICE_MLPL_CFG(base) ((base) + 0x084)
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#define IMXRT_SRC_SLICE_MLPL_STAT(base) ((base) + 0x088)
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/* SLICE_SW_CTRL bit fields */
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#define SRC_SLICE_SW_CTRL_PSW_OFF_SOFT (1u << 0) /* 1 = software power off */
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#define SRC_SLICE_SW_CTRL_RST_CTRL_SOFT (1u << 2) /* 1 = software reset assert */
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#define SRC_SLICE_SW_CTRL_ISO_ON_SOFT (1u << 4) /* 1 = software isolation on */
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#define SRC_SLICE_SW_CTRL_EDGELOCK_HDSK_SOFT (1u << 6) /* Edgelock handshake */
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#define SRC_SLICE_SW_CTRL_PDN_SOFT (1u << 31) /* 1 = SW power-down sequence */
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/* FUNC_STAT bit fields (all read-only) */
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#define SRC_SLICE_FUNC_STAT_PSW_STAT (1u << 0) /* 0 = power on, 1 = power off */
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#define SRC_SLICE_FUNC_STAT_RST_STAT (1u << 2) /* 0 = reset held, 1 = released */
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#define SRC_SLICE_FUNC_STAT_ISO_STAT (1u << 4) /* 0 = isolation off */
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#define SRC_SLICE_FUNC_STAT_EDGELOCK_HDSK (1u << 6) /* Edgelock handshake done */
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#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_BLKCTRL_H */
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103
arch/arm/src/imxrt/hardware/rt118x/imxrt118x_src.h
Normal file
103
arch/arm/src/imxrt/hardware/rt118x/imxrt118x_src.h
Normal file
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@ -0,0 +1,103 @@
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/****************************************************************************
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* arch/arm/src/imxrt/hardware/rt118x/imxrt118x_src.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_SRC_H
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#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_SRC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "hardware/imxrt_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* SRC general registers (IMXRT1180RM Ch. 27) *******************************/
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/* Register offsets *********************************************************/
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#define IMXRT_SRC_AUTHEN_CTRL_OFFSET 0x0004
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#define IMXRT_SRC_SCR_OFFSET 0x0010 /* Control */
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#define IMXRT_SRC_SRTMR_OFFSET 0x0014 /* Reset Trigger */
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#define IMXRT_SRC_SRMASK_OFFSET 0x0018 /* Reset Mask */
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#define IMXRT_SRC_SBMR1_OFFSET 0x0040 /* Boot Mode 1 */
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#define IMXRT_SRC_SBMR2_OFFSET 0x0044 /* Boot Mode 2 */
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#define IMXRT_SRC_SRSR_BBSM_OFFSET 0x004c
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#define IMXRT_SRC_SRSR_OFFSET 0x0050 /* Reset Status */
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#define IMXRT_SRC_GPR0_OFFSET 0x0054 /* General Purpose Register 0 */
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/* Register addresses *******************************************************/
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#define IMXRT_SRC_AUTHEN_CTRL (IMXRT_SRC_BASE + IMXRT_SRC_AUTHEN_CTRL_OFFSET)
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#define IMXRT_SRC_SCR (IMXRT_SRC_BASE + IMXRT_SRC_SCR_OFFSET)
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#define IMXRT_SRC_SRTMR (IMXRT_SRC_BASE + IMXRT_SRC_SRTMR_OFFSET)
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#define IMXRT_SRC_SRMASK (IMXRT_SRC_BASE + IMXRT_SRC_SRMASK_OFFSET)
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#define IMXRT_SRC_SBMR1 (IMXRT_SRC_BASE + IMXRT_SRC_SBMR1_OFFSET)
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#define IMXRT_SRC_SBMR2 (IMXRT_SRC_BASE + IMXRT_SRC_SBMR2_OFFSET)
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#define IMXRT_SRC_SRSR_BBSM (IMXRT_SRC_BASE + IMXRT_SRC_SRSR_BBSM_OFFSET)
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#define IMXRT_SRC_SRSR (IMXRT_SRC_BASE + IMXRT_SRC_SRSR_OFFSET)
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#define IMXRT_SRC_GPR(n) (IMXRT_SRC_BASE + IMXRT_SRC_GPR0_OFFSET + \
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((n) * 4))
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/* SRC.SCR bit fields */
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#define SRC_SCR_BT_RELEASE_M7 (1u << 0) /* Release M7 from boot hold */
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/* SRC MIX_SLICE registers (IMXRT1180RM Ch. 27, per power domain slice).
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* Bases for each slice (AON/WAKEUP/MEGA/NETC/CM33/CM7 platforms) are in
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* hardware/rt118x/imxrt118x_memorymap.h.
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*/
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#define IMXRT_SRC_SLICE_AUTHEN_CTRL(base) ((base) + 0x004)
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#define IMXRT_SRC_SLICE_SW_CTRL(base) ((base) + 0x010)
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#define IMXRT_SRC_SLICE_FUNC_STAT(base) ((base) + 0x014)
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#define IMXRT_SRC_SLICE_UPI_STAT_0(base) ((base) + 0x020)
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#define IMXRT_SRC_SLICE_UPI_STAT_1(base) ((base) + 0x024)
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#define IMXRT_SRC_SLICE_LPM_SETTING_0(base) ((base) + 0x030)
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#define IMXRT_SRC_SLICE_LPM_SETTING_1(base) ((base) + 0x034)
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#define IMXRT_SRC_SLICE_LPM_SETTING_2(base) ((base) + 0x038)
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#define IMXRT_SRC_SLICE_EDGELOCK_HDSK_CTRL(base) ((base) + 0x040)
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#define IMXRT_SRC_SLICE_EDGELOCK_HDSK_STAT(base) ((base) + 0x044)
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#define IMXRT_SRC_SLICE_PSW_CTRL(base) ((base) + 0x05c)
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#define IMXRT_SRC_SLICE_PSW_STAT(base) ((base) + 0x060)
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#define IMXRT_SRC_SLICE_MLPL_CFG(base) ((base) + 0x084)
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#define IMXRT_SRC_SLICE_MLPL_STAT(base) ((base) + 0x088)
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/* SLICE_SW_CTRL bit fields */
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#define SRC_SLICE_SW_CTRL_PSW_OFF_SOFT (1u << 0) /* 1 = software power off */
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#define SRC_SLICE_SW_CTRL_RST_CTRL_SOFT (1u << 2) /* 1 = software reset assert */
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#define SRC_SLICE_SW_CTRL_ISO_ON_SOFT (1u << 4) /* 1 = software isolation on */
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#define SRC_SLICE_SW_CTRL_EDGELOCK_HDSK_SOFT (1u << 6) /* Edgelock handshake */
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#define SRC_SLICE_SW_CTRL_PDN_SOFT (1u << 31) /* 1 = SW power-down sequence */
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/* FUNC_STAT bit fields (all read-only) */
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#define SRC_SLICE_FUNC_STAT_PSW_STAT (1u << 0) /* 0 = power on, 1 = power off */
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#define SRC_SLICE_FUNC_STAT_RST_STAT (1u << 2) /* 0 = reset held, 1 = released */
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#define SRC_SLICE_FUNC_STAT_ISO_STAT (1u << 4) /* 0 = isolation off */
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#define SRC_SLICE_FUNC_STAT_EDGELOCK_HDSK (1u << 6) /* Edgelock handshake done */
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#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_SRC_H */
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@ -41,6 +41,7 @@
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#include "hardware/rt118x/imxrt118x_anadig.h"
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#include "hardware/rt118x/imxrt118x_blkctrl.h"
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#include "hardware/rt118x/imxrt118x_gpc.h"
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#include "hardware/imxrt_src.h"
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/****************************************************************************
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* Pre-processor Definitions
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