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arch/arm/src/lpc54xx: Finishes basic MAC configruation. Began adding DMA descriptor definitions.

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This commit is contained in:
Gregory Nutt 2017-12-29 10:27:20 -06:00
parent ebdc3b9b58
commit 5394681dea
3 changed files with 503 additions and 153 deletions
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35
arch/arm/src/lpc54xx/Kconfig
View file

@ -671,33 +671,33 @@ endmenu # EMC Configuration
menu "Ethernet configuration"
depends on LPC54_ETHERNET
config LPC54_PHYADDR
config LPC54_ETH_PHYADDR
int "PHY address"
default 1
---help---
The 5-bit address of the PHY on the board. Default: 1
config LPC54_MII
config LPC54_ETH_MII
bool "Use MII interface"
default n
---help---
Support Ethernet MII interface. Default: Use RMII interface.
config LPC54_MULTIQUEUE
config LPC54_ETH_MULTIQUEUE
bool "Use multiple queues"
default n
depends on EXPERIMENTAL
---help---
Support not yet implemented.
config LPC54_TX_STRFWD
config LPC54_ETH_TX_STRFWD
bool "Tx store and forward"
default n
---help---
Transmission starts when a full packet resides in the MTL Tx Queue.
This disables the default Tx threshold controls.
config LPC54_RX_STRFWD
config LPC54_ETH_RX_STRFWD
bool "Rx store and forward"
default n
---help---
@ -705,21 +705,21 @@ config LPC54_RX_STRFWD
been written to it. By default, the Rx Queue operates in the
threshold (cut-through) mode.
config LPC54_RX_PROMISCUOUS
config LPC54_ETH_RX_PROMISCUOUS
bool "Enable Rx promiscuous mode"
default n
---help---
If selected, the address filter module accepts all incoming frames
regardless of its destination or source address.
config LPC54_RX_BROADCAST
config LPC54_ETH_RX_BROADCAST
bool "Enable Rx broadcast"
default y
---help---
If selected, all received frames with a broadcast destination
address are accepted.
config LPC54_RX_ALLMULTICAST
config LPC54_ETH_RX_ALLMULTICAST
bool "Accept all multicast packets"
default y if NET_BROADCAST
default n if !NET_BROADCAST
@ -728,6 +728,25 @@ config LPC54_RX_ALLMULTICAST
address (first bit in the destination address field is '1') are
accepted.
config LPC54_ETH_FLOWCONTROL
bool "Enable flow control"
default n
---help---
Enable TX and RX flow control.
config LPC54_ETH_TX_PAUSETIME
int "Tx pause time"
default 0
range 0 65535
depends on LPC54_ETH_FLOWCONTROL
---help---
Value to be used in the pause time field in the transmit control
frame.
config LPC54_ETH_8023AS2K
bool "Enable 8023as support for 2K packets"
default n
endmenu # Ethernet configuration
menu "SD/MMC Configuration"

503
arch/arm/src/lpc54xx/chip/lpc54_ethernet.h
View file

@ -240,7 +240,49 @@
/* Register bit definitions *********************************************************************************/
/* MAC configuration */
#define ETH_MAC_CONFIG_
#define ETH_MAC_CONFIG_RE (1 << 0) /* Bit 0: Receiver enable */
#define ETH_MAC_CONFIG_TE (1 << 1) /* Bit 1: Transmitter enable */
#define ETH_MAC_CONFIG_PRELEN_SHIFT (2) /* Bits 2-3: Preamble length for transmit packets */
#define ETH_MAC_CONFIG_PRELEN_MASK (3 << ETH_MAC_CONFIG_PRELEN_SHIFT)
# define ETH_MAC_CONFIG_PRELEN_7 (0 << ETH_MAC_CONFIG_PRELEN_SHIFT) /* 7 bytes of preamble */
# define ETH_MAC_CONFIG_PRELEN_5 (1 << ETH_MAC_CONFIG_PRELEN_SHIFT) /* 5 bytes of preamble */
# define ETH_MAC_CONFIG_PRELEN_3 (2 << ETH_MAC_CONFIG_PRELEN_SHIFT) /* 3 bytes of preamble */
#define ETH_MAC_CONFIG_DC (1 << 4) /* Bit 4: Deferral check */
#define ETH_MAC_CONFIG_BL_SHIFT (5) /* Bits 5-6: Back-off limit */
#define ETH_MAC_CONFIG_BL_MASK (3 << ETH_MAC_CONFIG_BL_SHIFT)
# define ETH_MAC_CONFIG_BL_10 (0 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 10) */
# define ETH_MAC_CONFIG_BL_8 (1 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 8) */
# define ETH_MAC_CONFIG_BL_4 (2 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 4) */
# define ETH_MAC_CONFIG_BL_1 (3 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 1) */
#define ETH_MAC_CONFIG_DR (1 << 8) /* Bit 8: Disable retry */
#define ETH_MAC_CONFIG_DCRS (1 << 9) /* Bit 9: Disable carrier sense during transmission */
#define ETH_MAC_CONFIG_DO (1 << 10) /* Bit 10: Disable receive own */
#define ETH_MAC_CONFIG_ECRSFD (1 << 11) /* Bit 11: Enable carrier sense full-duplex mode before transmission */
#define ETH_MAC_CONFIG_LM (1 << 12) /* Bit 12: Loopback mode */
#define ETH_MAC_CONFIG_DM (1 << 13) /* Bit 13: Duplex mode */
#define ETH_MAC_CONFIG_FES (1 << 14) /* Bit 14: Speed */
#define ETH_MAC_CONFIG_PS (1 << 15) /* Bit 15: Port select */
#define ETH_MAC_CONFIG_JE (1 << 16) /* Bit 16: Jumbo frame enable */
#define ETH_MAC_CONFIG_JD (1 << 17) /* Bit 17: Jabber disable */
#define ETH_MAC_CONFIG_BE (1 << 18) /* Bit 18: Packet burst enable */
#define ETH_MAC_CONFIG_WD (1 << 19) /* Bit 19: Watchdog disable */
#define ETH_MAC_CONFIG_ACS (1 << 20) /* Bit 20: Automatic pad or CRC stripping */
#define ETH_MAC_CONFIG_CST (1 << 21) /* Bit 21: CRC stripping for type packets */
#define ETH_MAC_CONFIG_S2KP (1 << 22) /* Bit 22: IEEE 802.3as support for 2K packets */
#define ETH_MAC_CONFIG_GPSLCE (1 << 23) /* Bit 23: Giant packet size limit control enable */
#define ETH_MAC_CONFIG_IPG_SHIFT (24) /* Bits 24-26: Inter-packet gap */
#define ETH_MAC_CONFIG_IPG_MASK (7 << ETH_MAC_CONFIG_IPG_SHIFT)
# define ETH_MAC_CONFIG_IPG_96 (0 << ETH_MAC_CONFIG_IPG_SHIFT) /* 96 bit times */
# define ETH_MAC_CONFIG_IPG_88 (1 << ETH_MAC_CONFIG_IPG_SHIFT) /* 88 bit times */
# define ETH_MAC_CONFIG_IPG_80 (2 << ETH_MAC_CONFIG_IPG_SHIFT) /* 80 bit times */
# define ETH_MAC_CONFIG_IPG_72 (3 << ETH_MAC_CONFIG_IPG_SHIFT) /* 72 bit times */
# define ETH_MAC_CONFIG_IPG_64 (4 << ETH_MAC_CONFIG_IPG_SHIFT) /* 64 bit times */
# define ETH_MAC_CONFIG_IPG_56 (5 << ETH_MAC_CONFIG_IPG_SHIFT) /* 56 bit times */
# define ETH_MAC_CONFIG_IPG_48 (6 << ETH_MAC_CONFIG_IPG_SHIFT) /* 48 bit times */
# define ETH_MAC_CONFIG_IPG_40 (7 << ETH_MAC_CONFIG_IPG_SHIFT) /* 40 bit times */
#define ETH_MAC_CONFIG_IPC (1 << 27) /* Bit 27: Checksum offload */
/* MAC extended configuration */
#define ETH_MAC_EXT_CONFIG_
@ -264,24 +306,52 @@
#define ETH_MAC_WD_TIMEROUT_
/* VLAN tag */
#define ETH_MAC_VLAN_TAG_
/* Transmit flow control 0 */
#define ETH_MAC_TX_FLOW_CTRL_Q0_
/* Transmit flow control 1 */
#define ETH_MAC_TX_FLOW_CTRL_Q1_
/* Transmit flow control 0/1 */
#define ETH_MAC_TX_FLOW_CTRL_Q_FCB (1 << 0) /* Bit 0: Flow control busy/backpressure activate */
#define ETH_MAC_TX_FLOW_CTRL_Q_TFE (1 << 1) /* Bit 1: Transmit flow control enable */
#define ETH_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4) /* Bits 4-6: Pause low threshold */
#define ETH_MAC_TX_FLOW_CTRL_Q_PLT_MASK (7 << ETH_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)
# define ETH_MAC_TX_FLOW_CTRL_Q_PLT(n) ((uint32_t)(n) << ETH_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)
#define ETH_MAC_TX_FLOW_CTRL_Q_DZPQ (1 << 7) /* Bit 7: Disable zero-quanta pause */
#define ETH_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16) /* Bits 16-31: Pause time */
#define ETH_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xffff << ETH_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)
# define ETH_MAC_TX_FLOW_CTRL_Q_PT(n) ((uint32_t)(n) << ETH_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)
/* Receive flow control */
#define ETH_MAC_RX_FLOW_CTRL_
#define ETH_MAC_RX_FLOW_CTRL_RFE (1 << 0) /* Bit 0: Receive flow control enable */
#define ETH_MAC_RX_FLOW_CTRL_UP (1 << 1) /* Bit 1: Unicast pause packet detect */
/* Transmit Queue priority mapping */
#define ETH_MAC_TXQ_PRIO_MAP_
/* Receive Queue control 0 */
#define ETH_MAC_RXQ_CTRL0_
#define ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT (0) /* Bits 0-1: Rx Queue 0 enable */
#define ETH_MAC_RXQ_CTRL0_RXQ0EN_MASK (3 << ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT)
# define ETH_MAC_RXQ_CTRL0_RXQ0EN_DISABLE (0 << ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) /* Disable */
# define ETH_MAC_RXQ_CTRL0_RXQ0EN_ENABLE (1 << ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) /* Queue 0 enabled for AV */
#define ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT (2) /* Bits 2-3: Rx Queue 1 enable */
#define ETH_MAC_RXQ_CTRL0_RXQ1EN_MASK (3 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT)
# define ETH_MAC_RXQ_CTRL0_RXQ1EN_DISABLE (0 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) /* Disable */
# define ETH_MAC_RXQ_CTRL0_RXQ1EN_ENABLE (1 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) /* Queue 1 enabled for AV */
/* Receive Queue control 1 */
#define ETH_MAC_RXQ_CTRL1_
/* Receive Queue control 2 */
#define ETH_MAC_RXQ_CTRL2_
/* Interrupt status */
#define ETH_MAC_INTR_STAT_
/* Interrupt enable */
#define ETH_MAC_INTR_EN_
/* Interrupt enable and interrupt status */
#define ETH_MAC_INTR_PHYI (1 << 3) /* Bit 3: PHY interrupt */
#define ETH_MAC_INTR_PMTI (1 << 4) /* Bit 4: PMT interrupt */
#define ETH_MAC_INTR_LPII (1 << 5) /* Bit 5: LPI interrupt */
#define ETH_MAC_INTR_TSI (1 << 12) /* Bit 12: Timestamp interrupt */
#define ETH_MAC_INTR_TXSTSI (1 << 13) /* Bit 13: Transmit status interrupt */
#define ETH_MAC_INTR_RXSTSI (1 << 14) /* Bit 14: Receive status interrupt */
/* Receive transmit status */
#define ETH_MAC_RXTX_STAT_
/* MAC PMT control and status */
@ -294,8 +364,13 @@
#define ETH_MAC_LPI_TIMER_CTRL_
/* LPI entry timer */
#define ETH_MAC_LPI_ENTR_TIMR_
/* MAC 1 usec tick counter */
#define ETH_MAC_1US_TIC_COUNTR_
#define ETH_MAC_1US_TIC_COUNTR_SHIFT (0) /* Bits 0-11: 1uS TIC counter */
#define ETH_MAC_1US_TIC_COUNTR_MASK (0xfff << ETH_MAC_1US_TIC_COUNTR_SHIFT)
# define ETH_MAC_1US_TIC_COUNTR(n) ((uint32_t)((n)-1) << ETH_MAC_1US_TIC_COUNTR_SHIFT)
/* MAC version */
#define ETH_MAC_VERSION_
/* MAC debug */
@ -309,39 +384,39 @@
/* MIDO address */
#define ETH_MAC_MDIO_ADDR_MB (1 << 0) /* Bit 0 MII busy */
#define ETH_MAC_MDIO_ADDR_MOC_SHIFT (2) /* Bits 2-3: MII operation command */
#define ETH_MAC_MDIO_ADDR_MOC_MASK (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT)
# define ETH_MAC_MDIO_ADDR_MOC_WRITE (1 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Write */
# define ETH_MAC_MDIO_ADDR_MOC_READ (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Read */
#define ETH_MAC_MDIO_ADDR_CR_SHIFT (8) /* Bits 8-11: CSR clock range */
#define ETH_MAC_MDIO_ADDR_CR_MASK (15 << ETH_MAC_MDIO_ADDR_CR_SHIFT)
# define ETH_MAC_MDIO_ADDR_CR_DIV42 (0 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=60-100 MHz; MDC=CSR/42 */
# define ETH_MAC_MDIO_ADDR_CR_DIV62 (1 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=100-150 MHz; MDC=CSR/62 */
# define ETH_MAC_MDIO_ADDR_CR_DIV16 (2 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=20-35 MHz; MDC=CSR/16 */
# define ETH_MAC_MDIO_ADDR_CR_DIV26 (3 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=35-60 MHz; MDC=CSR/26 */
#define ETH_MAC_MDIO_ADDR_NTC_SHIFT (12) /* Bits 12-14: Number of training clocks */
#define ETH_MAC_MDIO_ADDR_NTC_MASK (7 << ETH_MAC_MDIO_ADDR_NTC_SHIFT)
# define ETH_MAC_MDIO_ADDR_NTC(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_NTC_SHIFT)
#define ETH_MAC_MDIO_ADDR_RDA_SHIFT (16) /* Bits 16-20: Register/device address */
#define ETH_MAC_MDIO_ADDR_RDA_MASK (31 << ETH_MAC_MDIO_ADDR_RDA_SHIFT)
# define ETH_MAC_MDIO_ADDR_RDA(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_RDA_SHIFT)
#define ETH_MAC_MDIO_ADDR_PA_SHIFT (21) /* Bits 21-25: Physical layer address */
#define ETH_MAC_MDIO_ADDR_PA_MASK (31 << ETH_MAC_MDIO_ADDR_PA_SHIFT)
# define ETH_MAC_MDIO_ADDR_PA(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_PA_SHIFT)
#define ETH_MAC_MDIO_ADDR_BTB (1 << 26) /* Bit 26 Back to back transactions */
#define ETH_MAC_MDIO_ADDR_PSE (1 << 27) /* Bit 27 Preamble suppression enable */
#define ETH_MAC_MDIO_ADDR_MB (1 << 0) /* Bit 0 MII busy */
#define ETH_MAC_MDIO_ADDR_MOC_SHIFT (2) /* Bits 2-3: MII operation command */
#define ETH_MAC_MDIO_ADDR_MOC_MASK (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT)
# define ETH_MAC_MDIO_ADDR_MOC_WRITE (1 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Write */
# define ETH_MAC_MDIO_ADDR_MOC_READ (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Read */
#define ETH_MAC_MDIO_ADDR_CR_SHIFT (8) /* Bits 8-11: CSR clock range */
#define ETH_MAC_MDIO_ADDR_CR_MASK (15 << ETH_MAC_MDIO_ADDR_CR_SHIFT)
# define ETH_MAC_MDIO_ADDR_CR_DIV42 (0 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=60-100 MHz; MDC=CSR/42 */
# define ETH_MAC_MDIO_ADDR_CR_DIV62 (1 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=100-150 MHz; MDC=CSR/62 */
# define ETH_MAC_MDIO_ADDR_CR_DIV16 (2 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=20-35 MHz; MDC=CSR/16 */
# define ETH_MAC_MDIO_ADDR_CR_DIV26 (3 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=35-60 MHz; MDC=CSR/26 */
#define ETH_MAC_MDIO_ADDR_NTC_SHIFT (12) /* Bits 12-14: Number of training clocks */
#define ETH_MAC_MDIO_ADDR_NTC_MASK (7 << ETH_MAC_MDIO_ADDR_NTC_SHIFT)
# define ETH_MAC_MDIO_ADDR_NTC(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_NTC_SHIFT)
#define ETH_MAC_MDIO_ADDR_RDA_SHIFT (16) /* Bits 16-20: Register/device address */
#define ETH_MAC_MDIO_ADDR_RDA_MASK (31 << ETH_MAC_MDIO_ADDR_RDA_SHIFT)
# define ETH_MAC_MDIO_ADDR_RDA(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_RDA_SHIFT)
#define ETH_MAC_MDIO_ADDR_PA_SHIFT (21) /* Bits 21-25: Physical layer address */
#define ETH_MAC_MDIO_ADDR_PA_MASK (31 << ETH_MAC_MDIO_ADDR_PA_SHIFT)
# define ETH_MAC_MDIO_ADDR_PA(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_PA_SHIFT)
#define ETH_MAC_MDIO_ADDR_BTB (1 << 26) /* Bit 26 Back to back transactions */
#define ETH_MAC_MDIO_ADDR_PSE (1 << 27) /* Bit 27 Preamble suppression enable */
/* MDIO data */
#define ETH_MAC_MDIO_DATA_MASK 0xffff /* Bits 0-15: 16 bit PHY data */
#define ETH_MAC_MDIO_DATA_MASK 0xffff /* Bits 0-15: 16 bit PHY data */
/* MAC address0 high */
#define ETH_MAC_ADDR_HIGH_A32_47_SHIFT (0) /* MAC address 32-47 */
#define ETH_MAC_ADDR_HIGH_A32_47_MASK (0xffff << ETH_MAC_ADDR_HIGH_A32_47_SHIFT)
# define ETH_MAC_ADDR_HIGH_A32_47(n) ((uint32_t)(n) << ETH_MAC_ADDR_HIGH_A32_47_SHIFT)
#define ETH_MAC_ADDR_HIGH_DCS (1 << 16) /* Bit 16: DMA channel select */
#define ETH_MAC_ADDR_HIGH_A32_47_SHIFT (0) /* Bits 9-15: MAC address 32-47 */
#define ETH_MAC_ADDR_HIGH_A32_47_MASK (0xffff << ETH_MAC_ADDR_HIGH_A32_47_SHIFT)
# define ETH_MAC_ADDR_HIGH_A32_47(n) ((uint32_t)(n) << ETH_MAC_ADDR_HIGH_A32_47_SHIFT)
#define ETH_MAC_ADDR_HIGH_DCS (1 << 16) /* Bit 16: DMA channel select */
/* MAC address0 low (32-bit MAC address 0-31) */
@ -381,25 +456,25 @@
/* MTL TxQn operation mode */
#define ETH_MTL_TXQ_OP_MODE_FTQ (1 << 0) /* Bit 0: Flush Tx Queue */
#define ETH_MTL_TXQ_OP_MODE_TSF (1 << 1) /* Bit 1: Transmit store and forward */
#define ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT (2) /* Bits 2-3: Tx Queue enable */
#define ETH_MTL_TXQ_OP_MODE_TXQEN_MASK (3 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TXQEN_ENABLE (0 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Not enabled */
# define ETH_MTL_TXQ_OP_MODE_TXQEN_DISABLE (2 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Enabled */
#define ETH_MTL_TXQ_OP_MODE_TTC_SHIFT (4) /* Bits 4-6: Transmit threshold control */
#define ETH_MTL_TXQ_OP_MODE_TTC_MASK (7 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_32 (0 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_64 (1 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_96 (2 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_128 (3 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_192 (4 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_256 (5 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_384 (6 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_512 (7 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
#define ETH_MTL_TXQ_OP_MODE_TQS_SHIFT (16) /* Bits 16-18: Tx Queue size (x256) */
#define ETH_MTL_TXQ_OP_MODE_TQS_MASK (7 << ETH_MTL_TXQ_OP_MODE_TQS_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TQS(n) ((uint32_t)((n)-1) << ETH_MTL_TXQ_OP_MODE_TQS_SHIFT)
#define ETH_MTL_TXQ_OP_MODE_FTQ (1 << 0) /* Bit 0: Flush Tx Queue */
#define ETH_MTL_TXQ_OP_MODE_TSF (1 << 1) /* Bit 1: Transmit store and forward */
#define ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT (2) /* Bits 2-3: Tx Queue enable */
#define ETH_MTL_TXQ_OP_MODE_TXQEN_MASK (3 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TXQEN_ENABLE (0 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Not enabled */
# define ETH_MTL_TXQ_OP_MODE_TXQEN_DISABLE (2 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Enabled */
#define ETH_MTL_TXQ_OP_MODE_TTC_SHIFT (4) /* Bits 4-6: Transmit threshold control */
#define ETH_MTL_TXQ_OP_MODE_TTC_MASK (7 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_32 (0 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_64 (1 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_96 (2 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_128 (3 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_192 (4 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_256 (5 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_384 (6 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_512 (7 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
#define ETH_MTL_TXQ_OP_MODE_TQS_SHIFT (16) /* Bits 16-18: Tx Queue size (x256) */
#define ETH_MTL_TXQ_OP_MODE_TQS_MASK (7 << ETH_MTL_TXQ_OP_MODE_TQS_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TQS(n) ((uint32_t)((n)-1) << ETH_MTL_TXQ_OP_MODE_TQS_SHIFT)
/* MTL TxQn underflow */
#define ETH_MTL_TXQ_UNDRFLW_
@ -422,19 +497,19 @@
/* MTL RxQn operation mode */
#define ETH_MTL_RXQ_OP_MODE_RTC_SHIFT (0) /* Bits 0-1: Rx Queue threshold control */
#define ETH_MTL_RXQ_OP_MODE_RTC_MASK (3 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RTC_64 (0 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RTC_32 (1 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RTC_96 (2 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RTC_128 (3 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
#define ETH_MTL_RXQ_OP_MODE_FUP (1 << 3) /* Bit 3 Forward undersized good packets */
#define ETH_MTL_RXQ_OP_MODE_FEP (1 << 4) /* Bit 4 Forward error packets */
#define ETH_MTL_RXQ_OP_MODE_RSF (1 << 5) /* Bit 5 Rx Queue store and forward */
#define ETH_MTL_RXQ_OP_MODE_DIS_TCP_EF (1 << 6) /* Bit 6 Disable dropping of TCP/IP checksum error packets */
#define ETH_MTL_RXQ_OP_MODE_RQS_SHIFT (20) /* Bits 20-22: Rx Queue size (x256) */
#define ETH_MTL_RXQ_OP_MODE_RQS_MASK (7 << ETH_MTL_RXQ_OP_MODE_RQS_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RQS(n) ((uint32_t)((n)-1) << ETH_MTL_RXQ_OP_MODE_RQS_SHIFT)
#define ETH_MTL_RXQ_OP_MODE_RTC_SHIFT (0) /* Bits 0-1: Rx Queue threshold control */
#define ETH_MTL_RXQ_OP_MODE_RTC_MASK (3 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RTC_64 (0 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RTC_32 (1 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RTC_96 (2 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RTC_128 (3 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
#define ETH_MTL_RXQ_OP_MODE_FUP (1 << 3) /* Bit 3 Forward undersized good packets */
#define ETH_MTL_RXQ_OP_MODE_FEP (1 << 4) /* Bit 4 Forward error packets */
#define ETH_MTL_RXQ_OP_MODE_RSF (1 << 5) /* Bit 5 Rx Queue store and forward */
#define ETH_MTL_RXQ_OP_MODE_DIS_TCP_EF (1 << 6) /* Bit 6 Disable dropping of TCP/IP checksum error packets */
#define ETH_MTL_RXQ_OP_MODE_RQS_SHIFT (20) /* Bits 20-22: Rx Queue size (x256) */
#define ETH_MTL_RXQ_OP_MODE_RQS_MASK (7 << ETH_MTL_RXQ_OP_MODE_RQS_SHIFT)
# define ETH_MTL_RXQ_OP_MODE_RQS(n) ((uint32_t)((n)-1) << ETH_MTL_RXQ_OP_MODE_RQS_SHIFT)
/* MTL RxQn missed packet overflow counter */
#define ETH_MTL_RXQ_MISSPKT_OVRFLW_CNT_
@ -445,69 +520,69 @@
/* DMA mode */
#define ETH_DMA_MODE_SWR (1 << 0) /* Bit 0: Software reset */
#define ETH_DMA_MODE_DA_MASK (1 << 1) /* Bit 1: DMA Tx or Rx arbitration scheme */
# define ETH_DMA_MODE_DA_WRR (0) /* Weighted round-robin with Rx:Tx or Tx:Rx */
# define ETH_DMA_MODE_DA_FIXED (1 << 1) /* Fixed priority */
#define ETH_DMA_MODE_TAA_SHIFT (2) /* Bits 2-4: Transmit arbitration algorithm */
#define ETH_DMA_MODE_TAA_MASK (7 << ETH_DMA_MODE_TAA_SHIFT)
# define ETH_DMA_MODE_TAA_FIXED (0 << ETH_DMA_MODE_TAA_SHIFT) /* Fixed priority */
# define ETH_DMA_MODE_TAA_WSP (1 << ETH_DMA_MODE_TAA_SHIFT) /* Weighted strict priority */
# define ETH_DMA_MODE_TAA_WRR (2 << ETH_DMA_MODE_TAA_SHIFT) /* Weighted round-robin */
#define ETH_DMA_MODE_TXPR (1 << 11) /* Bit 11: Transmit priority */
#define ETH_DMA_MODE_PR_SHIFT (12) /* Bits 12-14: Priority ratio */
#define ETH_DMA_MODE_PR_MASK (7 << ETH_DMA_MODE_PR_SHIFT)
# define ETH_DMA_MODE_PR_1TO1 (0 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 1:1 */
# define ETH_DMA_MODE_PR_3TO1 (2 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 3:1 */
# define ETH_DMA_MODE_PR_4TO1 (3 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 4:1 */
# define ETH_DMA_MODE_PR_5TO1 (4 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 5:1 */
# define ETH_DMA_MODE_PR_6TO1 (5 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 6:1 */
# define ETH_DMA_MODE_PR_7TO1 (6 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 7:1 */
# define ETH_DMA_MODE_PR_8TO1 (7 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 8:1 */
#define ETH_DMA_MODE_SWR (1 << 0) /* Bit 0: Software reset */
#define ETH_DMA_MODE_DA_MASK (1 << 1) /* Bit 1: DMA Tx or Rx arbitration scheme */
# define ETH_DMA_MODE_DA_WRR (0) /* Weighted round-robin with Rx:Tx or Tx:Rx */
# define ETH_DMA_MODE_DA_FIXED (1 << 1) /* Fixed priority */
#define ETH_DMA_MODE_TAA_SHIFT (2) /* Bits 2-4: Transmit arbitration algorithm */
#define ETH_DMA_MODE_TAA_MASK (7 << ETH_DMA_MODE_TAA_SHIFT)
# define ETH_DMA_MODE_TAA_FIXED (0 << ETH_DMA_MODE_TAA_SHIFT) /* Fixed priority */
# define ETH_DMA_MODE_TAA_WSP (1 << ETH_DMA_MODE_TAA_SHIFT) /* Weighted strict priority */
# define ETH_DMA_MODE_TAA_WRR (2 << ETH_DMA_MODE_TAA_SHIFT) /* Weighted round-robin */
#define ETH_DMA_MODE_TXPR (1 << 11) /* Bit 11: Transmit priority */
#define ETH_DMA_MODE_PR_SHIFT (12) /* Bits 12-14: Priority ratio */
#define ETH_DMA_MODE_PR_MASK (7 << ETH_DMA_MODE_PR_SHIFT)
# define ETH_DMA_MODE_PR_1TO1 (0 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 1:1 */
# define ETH_DMA_MODE_PR_3TO1 (2 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 3:1 */
# define ETH_DMA_MODE_PR_4TO1 (3 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 4:1 */
# define ETH_DMA_MODE_PR_5TO1 (4 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 5:1 */
# define ETH_DMA_MODE_PR_6TO1 (5 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 6:1 */
# define ETH_DMA_MODE_PR_7TO1 (6 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 7:1 */
# define ETH_DMA_MODE_PR_8TO1 (7 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 8:1 */
/* DMA system bus mode */
#define ETH_DMA_SYSBUS_MODE_FB (1 << 0) /* Bit 0: Fixed burst length */
#define ETH_DMA_SYSBUS_MODE_AAL (1 << 12) /* Bit 12: Address-aligned beats */
#define ETH_DMA_SYSBUS_MODE_MB (1 << 14) /* Bit 14: Mixed burst */
#define ETH_DMA_SYSBUS_MODE_RB (1 << 15) /* Bit 15: Rebuild INCRx burst */
#define ETH_DMA_SYSBUS_MODE_FB (1 << 0) /* Bit 0: Fixed burst length */
#define ETH_DMA_SYSBUS_MODE_AAL (1 << 12) /* Bit 12: Address-aligned beats */
#define ETH_DMA_SYSBUS_MODE_MB (1 << 14) /* Bit 14: Mixed burst */
#define ETH_DMA_SYSBUS_MODE_RB (1 << 15) /* Bit 15: Rebuild INCRx burst */
/* DMA interrupt status */
#define ETH_DMA_INTR_STAT_DC0IS (1 << 0) /* Bit 0: DMA channel 0 interrupt status */
#define ETH_DMA_INTR_STAT_DC1IS (1 << 1) /* Bit 1: DMA channel 1 interrupt status */
#define ETH_DMA_INTR_STAT_MTLIS (1 << 16) /* Bit 16: MTL interrupt status */
#define ETH_DMA_INTR_STAT_MACIS (1 << 17) /* Bit 17: MAC interrupt status */
#define ETH_DMA_INTR_STAT_DC0IS (1 << 0) /* Bit 0: DMA channel 0 interrupt status */
#define ETH_DMA_INTR_STAT_DC1IS (1 << 1) /* Bit 1: DMA channel 1 interrupt status */
#define ETH_DMA_INTR_STAT_MTLIS (1 << 16) /* Bit 16: MTL interrupt status */
#define ETH_DMA_INTR_STAT_MACIS (1 << 17) /* Bit 17: MAC interrupt status */
/* DMA debug status */
#define ETH_DMA_DBG_STAT_
/* DMA channel n control */
#define ETH_DMACH_CTRL_PBLx8 (1 << 16) /* Bit 16: 8xPBL mode */
#define ETH_DMACH_CTRL_DSL_SHIFT (18) /* Bits 18-20: Skip length */
#define ETH_DMACH_CTRL_PBLx8 (1 << 16) /* Bit 16: 8xPBL mode */
#define ETH_DMACH_CTRL_DSL_SHIFT (18) /* Bits 18-20: Skip length */
/* DMA channel n transmit control */
#define ETH_DMACH_TX_CTRL_ST (1 << 0) /* Bit 0: Start or stop transmission command */
#define ETH_DMACH_TX_CTRL_TCW_SHIFT (1) /* Bits 1-3: Transmit channel weight */
#define ETH_DMACH_TX_CTRL_TCW_MASK (7 << ETH_DMACH_TX_CTRL_TCW_SHIFT)
# define ETH_DMACH_TX_CTRL_TCW(n) ((uint32_t)(n) << ETH_DMACH_TX_CTRL_TCW_SHIFT)
#define ETH_DMACH_TX_CTRL_OSF (1 << 4) /* Bit 4: Operate on second frame */
#define ETH_DMACH_TX_CTRL_TxPBL_SHIFT (16) /* Bits 16-21: Transmit programmable burst length */
#define ETH_DMACH_TX_CTRL_TxPBL_MASK (0x3f << ETH_DMACH_TX_CTRL_TxPBL_SHIFT)
# define ETH_DMACH_TX_CTRL_TxPBL(n) ((uint32_t)(n) << ETH_DMACH_TX_CTRL_TxPBL_SHIFT)
#define ETH_DMACH_TX_CTRL_ST (1 << 0) /* Bit 0: Start or stop transmission command */
#define ETH_DMACH_TX_CTRL_TCW_SHIFT (1) /* Bits 1-3: Transmit channel weight */
#define ETH_DMACH_TX_CTRL_TCW_MASK (7 << ETH_DMACH_TX_CTRL_TCW_SHIFT)
# define ETH_DMACH_TX_CTRL_TCW(n) ((uint32_t)(n) << ETH_DMACH_TX_CTRL_TCW_SHIFT)
#define ETH_DMACH_TX_CTRL_OSF (1 << 4) /* Bit 4: Operate on second frame */
#define ETH_DMACH_TX_CTRL_TxPBL_SHIFT (16) /* Bits 16-21: Transmit programmable burst length */
#define ETH_DMACH_TX_CTRL_TxPBL_MASK (0x3f << ETH_DMACH_TX_CTRL_TxPBL_SHIFT)
# define ETH_DMACH_TX_CTRL_TxPBL(n) ((uint32_t)(n) << ETH_DMACH_TX_CTRL_TxPBL_SHIFT)
/* DMA channel n receive control */
#define ETH_DMACH_RX_CTRL_SR (1 << 0) /* Bit 0: Start or stop receive command */
#define ETH_DMACH_RX_CTRL_RBSZ_SHIFT (3) /* Bits 3-14: Receive buffer size */
#define ETH_DMACH_RX_CTRL_RBSZ_MASK (0xfff << ETH_DMACH_RX_CTRL_RBSZ_SHIFT)
# define ETH_DMACH_RX_CTRL(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RBSZ_SHIFT)
#define ETH_DMACH_RX_CTRL_RxPBL_SHIFT (16) /* Bits 16-21: Receive programmable burst length */
#define ETH_DMACH_RX_CTRL_RxPBL_MASK (0x3f << ETH_DMACH_RX_CTRL_RxPBL_SHIFT)
# define ETH_DMACH_RX_CTRL_RxPBL(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RxPBL_SHIFT)
#define ETH_DMACH_RX_CTRL_RPF (1 << 31) /* Bit 31: DMA Rx channel n packet flush */
#define ETH_DMACH_RX_CTRL_SR (1 << 0) /* Bit 0: Start or stop receive command */
#define ETH_DMACH_RX_CTRL_RBSZ_SHIFT (3) /* Bits 3-14: Receive buffer size */
#define ETH_DMACH_RX_CTRL_RBSZ_MASK (0xfff << ETH_DMACH_RX_CTRL_RBSZ_SHIFT)
# define ETH_DMACH_RX_CTRL(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RBSZ_SHIFT)
#define ETH_DMACH_RX_CTRL_RxPBL_SHIFT (16) /* Bits 16-21: Receive programmable burst length */
#define ETH_DMACH_RX_CTRL_RxPBL_MASK (0x3f << ETH_DMACH_RX_CTRL_RxPBL_SHIFT)
# define ETH_DMACH_RX_CTRL_RxPBL(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RxPBL_SHIFT)
#define ETH_DMACH_RX_CTRL_RPF (1 << 31) /* Bit 31: DMA Rx channel n packet flush */
/* DMA channel n Tx descriptor list address */
#define ETH_DMACH_TXDESC_LIST_ADDR_
@ -521,8 +596,22 @@
#define ETH_DMACH_TXDESC_RING_LENGTH_
/* DMA channel n Rx descriptor ring length */
#define ETH_DMACH_RXDESC_RING_LENGTH_
/* DMA channel n interrupt enable */
#define ETH_DMACH_INT_EN_
/* DMA channel n interrupt enable and DMA channel n DMA status */
#define ETH_DMACH_INT_TI (1 << 0) /* Bit 0: Transmit interrupt */
#define ETH_DMACH_INT_TS (1 << 1) /* Bit 1: Transmitter stopped */
#define ETH_DMACH_INT_TBU (1 << 2) /* Bit 2: Transmit buffer unavailable */
#define ETH_DMACH_INT_RI (1 << 6) /* Bit 6: Receive interrupt */
#define ETH_DMACH_INT_RBU (1 << 7) /* Bit 7: Receive buffer unavailable */
#define ETH_DMACH_INT_RS (1 << 8) /* Bit 8: Receiver stopped */
#define ETH_DMACH_INT_RWT (1 << 9) /* Bit 9: Receive watchdog timeout */
#define ETH_DMACH_INT_ETI (1 << 10) /* Bit 10: Early transmit interrupt */
#define ETH_DMACH_INT_ERI (1 << 11) /* Bit 11: Early receive interrupt */
#define ETH_DMACH_INT_FBE (1 << 12) /* Bit 12: Fatal bus error */
#define ETH_DMACH_INT_AI (1 << 14) /* Bit 14: Abnormal interrupt summary */
#define ETH_DMACH_INT_NI (1 << 15) /* Bit 15: Normal interrupt summary */
/* DMA channel n receive interrupt watchdog timer */
#define ETH_DMACH_RX_INT_WDTIMER_
/* DMA channel n slot function control and status */
@ -535,9 +624,183 @@
#define ETH_DMACH_CUR_HST_TXBUF_
/* DMA channel n current application receive buffer address */
#define ETH_DMACH_CUR_HST_RXBUF_
/* DMA channel n DMA status */
#define ETH_DMACH_STAT_
/* DMA channel n missed frame count */
#define ETH_DMACH_MISS_FRAME_CNT_
/* DMA descriptors ******************************************************************************************/
/* Receive descriptor (read-format) */
/* RDES0: 32-bit address */
/* RDES1: Reserved */
/* RDES2: 32-bit address */
/* RDES3: */
#define ETH_RXDES3_BUF1V (1 << 24) /* Bit 24: Buffer 1 address valid */
#define ETH_RXDES3_BUF2V (1 << 25) /* Bit 25: Buffer 1 address valid */
#define ETH_RXDES3_IOC (1 << 30) /* Bit 30: Interrupt enabled on completion */
#define ETH_RXDES3_OWN (1 << 31) /* Bit 31: Own bit */
/* Receive descriptor (writeback-format) */
/* RDES0: Reserved */
/* RDES1: */
#define ETH_RXDES1_PT_SHIFT (0) /* Bits 0-2: Payload type */
#define ETH_RXDES1_PT_MASK (7 << ETH_RXDES1_PT_SHIFT)
# define ETH_RXDES1_PT_UNKNOWN (0 << ETH_RXDES1_PT_SHIFT) /* Unknown */
# define ETH_RXDES1_PT_UDP (1 << ETH_RXDES1_PT_SHIFT) /* UDP */
# define ETH_RXDES1_PT_TCP (2 << ETH_RXDES1_PT_SHIFT) /* TCP */
# define ETH_RXDES1_PT_ICMP (3 << ETH_RXDES1_PT_SHIFT) /* ICMP */
# define ETH_RXDES1_PT_IGMP (4 << ETH_RXDES1_PT_SHIFT) /* IGMP */
# define ETH_RXDES1_PT_AVUCP (5 << ETH_RXDES1_PT_SHIFT) /* AV untagged control packet */
# define ETH_RXDES1_PT_AVTDP (6 << ETH_RXDES1_PT_SHIFT) /* AV tagged data packet */
# define ETH_RXDES1_PT_AVTCP (7 << ETH_RXDES1_PT_SHIFT) /* AV tagged control packet */
#define ETH_RXDES1_IPHE (1 << 3) /* Bit 3: IP header error */
#define ETH_RXDES1_IPV4 (1 << 4) /* Bit 4: IPV4 header present */
#define ETH_RXDES1_IPV6 (1 << 5) /* Bit 5: IPv6 header present */
#define ETH_RXDES1_IPCB (1 << 6) /* Bit 6: IP checksum bypassed */
#define ETH_RXDES1_IPCE (1 << 7) /* Bit 7: IP payload error */
#define ETH_RXDES1_PMT_SHIFT (8) /* Bits 8-11: PTP message type */
#define ETH_RXDES1_PMT_MASK (15 << ETH_RXDES1_PMT_SHIFT)
# define ETH_RXDES1_PMT_NONE (0 << ETH_RXDES1_PMT_SHIFT) /* No PTP message received */
# define ETH_RXDES1_PMT_SYNC (1 << ETH_RXDES1_PMT_SHIFT) /* SYNC */
# define ETH_RXDES1_PMT_FOLLOWUP (2 << ETH_RXDES1_PMT_SHIFT) /* Follow_Up */
# define ETH_RXDES1_PMT_DELAYREQ (3 << ETH_RXDES1_PMT_SHIFT) /* Delay Req */
# define ETH_RXDES1_PMT_DELAYRESP (4 << ETH_RXDES1_PMT_SHIFT) /* Delay Resp */
# define ETH_RXDES1_PMT_PDELAYREQ (5 << ETH_RXDES1_PMT_SHIFT) /* Pdelay Req */
# define ETH_RXDES1_PMT_PDELAYRESP (6 << ETH_RXDES1_PMT_SHIFT) /* Pdelay Resp */
# define ETH_RXDES1_PMT_PDELAYFOLLOWUP (7 << ETH_RXDES1_PMT_SHIFT) /* Pdelay Resp follow-up */
# define ETH_RXDES1_PMT_ANNOUNCE (8 << ETH_RXDES1_PMT_SHIFT) /* Announce */
# define ETH_RXDES1_PMT_MGMNT (9 << ETH_RXDES1_PMT_SHIFT) /* Management */
# define ETH_RXDES1_PMT_SIGNALING (10 << ETH_RXDES1_PMT_SHIFT) /* Signaling */
# define ETH_RXDES1_PMT_RESERVERD (15 << ETH_RXDES1_PMT_SHIFT) /* Reserved message type */
#define ETH_RXDES1_PFT (1 << 12) /* Bit 12: PTP packet type */
#define ETH_RXDES1_PV (1 << 13) /* Bit 13: PTP version */
#define ETH_RXDES1_TSA (1 << 14) /* Bit 14: Timestamp available */
#define ETH_RXDES1_TD (1 << 15) /* Bit 15: Timestamp dropped */
#define ETH_RXDES1_OPC_SHIFT (16) /* Bits 16-31: OAM sub-type code */
/* RXDES2: */
#define ETH_RXDES2_SAF (1 << 16) /* Bit 16: SA address filter fail */
#define ETH_RXDES2_DAF (1 << 17) /* Bit 17: Destination address filter fail */
#define ETH_RXDES2_MADRM_SHIFT (19) /* Bits 19-26: MAC address match */
#define ETH_RXDES2_MADRM_MASK (0xff << ETH_RXDES2_MADRM_SHIFT)
/* RXDES3: */
#define ETH_RXDES3_PL_SHIFT (0) /* Bits 0-14: Packet length */
#define ETH_RXDES3_PL_MASK (0x7fff << ETH_RXDES3_PL_SHIFT)
#define ETH_RXDES3_ES (1 << 15) /* Bit 15: Error summary */
#define ETH_RXDES3_LT_SHIFT (16) /* Bits 16-18: Length/type */
#define ETH_RXDES3_LT_MASK (7 << ETH_RXDES3_LT_SHIFT)
# define ETH_RXDES3_LT_PKTLEN (0 << ETH_RXDES3_LT_SHIFT) /* Packet is a length packet */
# define ETH_RXDES3_LT_PKTTYPE (1 << ETH_RXDES3_LT_SHIFT) /* Packet is a type packet */
# define ETH_RXDES3_LT_ARPREQ (3 << ETH_RXDES3_LT_SHIFT) /* Packet is a ARP request packet type */
# define ETH_RXDES3_LT_VLAN (4 << ETH_RXDES3_LT_SHIFT) /* Packet is a type packet with VLAN tag */
# define ETH_RXDES3_LT_DVLAN (5 << ETH_RXDES3_LT_SHIFT) /* Packet is a type packet with double VLAN tag */
# define ETH_RXDES3_LT_CTRLPKT (6 << ETH_RXDES3_LT_SHIFT) /* Packet is a MAC control packet type */
# define ETH_RXDES3_LT_OAM (7 << ETH_RXDES3_LT_SHIFT) /* Packet is a OAM packet type */
#define ETH_RXDES3_DE (1 << 19) /* Bit 19: Dribble bit error */
#define ETH_RXDES3_RE (1 << 20) /* Bit 20: Receive error */
#define ETH_RXDES3_OE (1 << 21) /* Bit 21: Overflow error */
#define ETH_RXDES3_RWT (1 << 22) /* Bit 22: Receive watchdog timeout */
#define ETH_RXDES3_GP (1 << 23) /* Bit 23: Giant packet */
#define ETH_RXDES3_CE (1 << 24) /* Bit 24: CRC error */
#define ETH_RXDES3_RS0V (1 << 25) /* Bit 25: Receive status RDES0 valid */
#define ETH_RXDES3_RS1V (1 << 26) /* Bit 26: Receive status RDES1 valid */
#define ETH_RXDES3_RS2V (1 << 27) /* Bit 27: Receive status RDES2 valid */
#define ETH_RXDES3_LD (1 << 28) /* Bit 28: Last descriptor */
#define ETH_RXDES3_FD (1 << 29) /* Bit 29: First descriptor */
#define ETH_RXDES3_CTXT (1 << 30) /* Bit 30: Receive context descriptor */
/* Bit 31: Own bit (see read-format) */
/* Transmit normal descriptor (read-format) */
/* TDES0/1: 32-bit address */
/* TDES2: */
#define ETH_TXDES2_B1L_SHIFT (0) /* Bits 0-13: Buffer 1 length */
#define ETH_TXDES2_B1L_MASK (0x3fff << ETH_TXDES2_B1L_SHIFT)
# define ETH_TXDES2_B1L(n) ((uint32_t)(n) << ETH_TXDES2_B1L_SHIFT)
#define ETH_TXDES2_B2L_SHIFT (16) /* Bits 16-29: Buffer 2 length */
#define ETH_TXDES2_B2L_MASK (0x3fff << ETH_TXDES2_B2L_SHIFT)
# define ETH_TXDES2_B2L(n) ((uint32_t)(n) << ETH_TXDES2_B2L_SHIFT)
#define ETH_TXDES2_TTSE (1 << 30) /* Bit 30: Transmit timestamp enable */
#define ETH_TXDES2_IOC (1 << 31) /* Bit 31: Interrupt on completion */
/* TDES3: */
#define ETH_TXDES3_FL_SHIFT (0) /* Bits 0-14: Frame length */
#define ETH_TXDES3_FL_MASK (0x7fff << ETH_TXDES3_FL_SHIFT)
#define ETH_TXDES3_CIC_SHIFT (16) /* Bits 16-17: Checksum insertion control */
#define ETH_TXDES3_CIC_MASK (3 << ETH_TXDES3_CIC_SHIFT)
# define ETH_TXDES3_CIC_DISABLED (0 << ETH_TXDES3_CIC_SHIFT) /* Checksum insertion disabled */
# define ETH_TXDES3_CIC_IPHDR (1 << ETH_TXDES3_CIC_SHIFT) /* Only IP header checksum */
# define ETH_TXDES3_CIC_PAYLOAD (2 << ETH_TXDES3_CIC_SHIFT) /* IP header checksum and payload checksum */
# define ETH_TXDES3_CIC_ALL (3 << ETH_TXDES3_CIC_SHIFT) /* IP Header checksum, payload, and pseudo-header checksum */
#define ETH_TXDES3_SLOTNUM_SHIFT (19) /* Bits 19-22: Slot number control bits in AV mode */
#define ETH_TXDES3_SLOTNUM_MASK (15 << ETH_TXDES3_SLOTNUM_SHIFT)
#define ETH_TXDES3_CPC_SHIFT (26) /* Bits 26-27: CRC pad control */
#define ETH_TXDES3_CPC_MASK (3 << ETH_TXDES2_B1L_SHIFT)
# define ETH_TXDES3_CPC_CRCPAD (0 << ETH_TXDES2_B1L_SHIFT) /* CRC and pad insertion */
# define ETH_TXDES3_CPC_CRC (1 << ETH_TXDES2_B1L_SHIFT) /* CRC insertion (disable pad insertion) */
# define ETH_TXDES3_CPC_DISABLED (2 << ETH_TXDES2_B1L_SHIFT) /* Disable CRC insertion */
# define ETH_TXDES3_CPC_REPLACMENT (3 << ETH_TXDES2_B1L_SHIFT) /* CRC replacement */
#define ETH_TXDES3_LD (1 << 28) /* Bit 28: Last descriptor */
#define ETH_TXDES3_FD (1 << 29) /* Bit 29: First descriptor */
#define ETH_TXDES3_CTXT (1 << 30) /* Bit 30: Context type */
#define ETH_TXDES3_OWN (1 << 31) /* Bit 31: Own bit */
/* Transmit normal descriptor (writeback-format) */
/* TDES0/1: 64-bit transmit packet timestamp */
/* TDES2: Reserved */
/* TDES3: */
#define ETH_TXDES3_IHE (1 << 0) /* Bit 0: IP header error */
#define ETH_TXDES3_DB (1 << 1) /* Bit 1: Deferred bit */
#define ETH_TXDES3_UF (1 << 2) /* Bit 2: Underflow error */
#define ETH_TXDES3_ED (1 << 3) /* Bit 3: Excessive deferral */
#define ETH_TXDES3_CC_SHIFT (4) /* Bits 4-7: Collision count */
#define ETH_TXDES3_EC (1 << 8) /* Bit 8: Excessive collision */
#define ETH_TXDES3_LC (1 << 9) /* Bit 9: Late collision */
#define ETH_TXDES3_NC (1 << 10) /* Bit 10: No carrier */
#define ETH_TXDES3_LOC (1 << 11) /* Bit 11: Loss of carrier */
#define ETH_TXDES3_PCE (1 << 12) /* Bit 12: Payload checksum error */
#define ETH_TXDES3_FF (1 << 13) /* Bit 13: Packet flushed */
#define ETH_TXDES3_JT (1 << 14) /* Bit 14: Jabber timeout */
#define ETH_TXDES3_ES (1 << 15) /* Bit 15: Error summary */
#define ETH_TXDES3_TTSS (1 << 17) /* Bit 17: Tx timestamp status */
/* Bit 28: (see read format) */
/* Bit 29: (see read format) */
/* Bit 30: (see read format) */
/* Bit 31: (see read format) */
/************************************************************************************************************
* Public Types
************************************************************************************************************/
/* Receive descriptor structure (read format) */
struct enet_rxdesc_s
{
uint32_t buffer1; /* Buffer 1 address */
uint32_t reserved; /* Reserved */
uint32_t buffer2; /* Buffer 2 or next descriptor address */
uint32_t control; /* Buffer 1/2 byte counts and control */
};
/* Transmit descriptor structure (read format) */
struct enet_txdesc_s
{
uint32_t buffer1; /* TDES0 Buffer 1 address */
uint32_t buffer2; /* TDES1 Buffer 2 address */
uint32_t buflen; /* TDES2 Buffer 1/2 byte counts */
uint32_t ctrlstat; /* TDES3 Control and status word */
};
#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ETHERNET_H */

118
arch/arm/src/lpc54xx/lpc54_ethernet.c
View file

@ -60,6 +60,7 @@
#include <nuttx/irq.h>
#include <nuttx/wdog.h>
#include <nuttx/wqueue.h>
#include <nuttx/clock.h>
#include <nuttx/net/mii.h>
#include <nuttx/net/arp.h>
#include <nuttx/net/netdev.h>
@ -102,7 +103,7 @@
/* PHY-related definitions */
#define LPC54_PHY_TIMEOUT 0x00ffffff /* Timeout for PHY register accesses */
#define LPC54_PHY_TIMEOUT 0x00ffffff /* Timeout for PHY register accesses */
#ifdef CONFIG_ETH0_PHY_LAN8720
# define LPC54_PHYID1_VAL MII_PHYID1_LAN8720
@ -113,10 +114,31 @@
/* MTL-related definitions */
#define LPC54_MTL_QUEUE_UNIT 256
#define LPC54_MTL_RXQUEUE_UNITS 8 /* Rx queue size = 2048 bytes */
#define LPC54_MTL_TXQUEUE_UNITS 8 /* Tx queue size = 2048 bytes */
#define LPC54_MTL_RXQUEUE_UNITS 8 /* Rx queue size = 2048 bytes */
#define LPC54_MTL_TXQUEUE_UNITS 8 /* Tx queue size = 2048 bytes */
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* MAC-related definitinons */
#define LPC54_MAC_HALFDUPLEX_IPG ETH_MAC_CONFIG_IPG_64 /* Default half-duplex IPG */
/* DMA descriptor definitions */
#define LPC54_MIN_RINGLEN 4 /* Min length of a ring */
#define LPC54_MAX_RINGS 2 /* Max number of tx/rx descriptor rings */
/* Interrupt masks */
#define LPC54_ABNORM_INTMASK (ETH_DMACH_INT_TS | ETH_DMACH_INT_RBU | \
ETH_DMACH_INT_RS | ETH_DMACH_INT_RWT | \
ETH_DMACH_INT_FBE | ETH_DMACH_INT_ETI | \
ETH_DMACH_INT_AI)
#define LPC54_NORM_INTMASK (ETH_DMACH_INT_TI | ETH_DMACH_INT_TBU | \
ETH_DMACH_INT_RI | ETH_DMACH_INT_ERI | \
ETH_DMACH_INT_NI)
/* This is a helper pointer for accessing the contents of the Ethernet
* header.
*/
#define BUF ((struct eth_hdr_s *)priv->eth_dev.d_buf)
@ -878,7 +900,7 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
{
base = LPC54_ETH_DMA_CH_CTRL_BASE(i);
#ifdef CONFIG_LPC54_MULTIQUEUE
#ifdef CONFIG_LPC54_ETH_MULTIQUEUE
/* REVISIT: burstlen setting for the case of multi-queuing. */
# warning Missing logic
#else
@ -915,7 +937,7 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
* TQS - Set to 2048 bytes
*/
#ifdef CONFIG_LPC54_TX_STRFWD
#ifdef CONFIG_LPC54_ETH_TX_STRFWD
regval = ETH_MTL_TXQ_OP_MODE_TSF;
#else
regval = 0;
@ -938,7 +960,7 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
* RQS - Set to 2048 bytes
*/
#ifdef CONFIG_LPC54_RX_STRFWD
#ifdef CONFIG_LPC54_ETH_RX_STRFWD
regval = ETH_MTL_RXQ_OP_MODE_RSF;
#else
regval = 0;
@ -948,7 +970,7 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
ETH_MTL_RXQ_OP_MODE_RQS(LPC54_MTL_RXQUEUE_UNITS);
putreg (regval, LPC54_ETH_MTL_RXQ_OP_MODE(0));
#ifdef CONFIG_LPC54_MULTIQUEUE
#ifdef CONFIG_LPC54_ETH_MULTIQUEUE
/* Set the schedule/arbitration(set for multiple queues) */
/* Set the rx queue mapping to dma channel */
/* Set the tx/rx queue weight. */
@ -972,33 +994,79 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
/* Set the receive address filter */
regval = ETH_MAC_FRAME_FILTER_PCF_NONE;
#ifdef CONFIG_LPC54_RX_PROMISCUOUS
#ifdef CONFIG_LPC54_ETH_RX_PROMISCUOUS
regval |= ETH_MAC_FRAME_FILTER_PR;
#endif
#ifndef CONFIG_LPC54_RX_BROADCAST
#ifndef CONFIG_LPC54_ETH_RX_BROADCAST
regval |= ETH_MAC_FRAME_FILTER_DBF;
#endif
#ifdef CONFIG_LPC54_RX_ALLMULTICAST
#ifdef CONFIG_LPC54_ETH_RX_ALLMULTICAST
regval |= ETH_MAC_FRAME_FILTER_PM;
#endif
putreg32(regval, LPC54_ETH_MAC_FRAME_FILTER).
#ifdef CONFIG_LPC54_ETH_FLOWCONTROL
/* Configure flow control */
#warning Missing logic
/* Set the 1us ticket */
#warning Missing logic
regval = ETH_MAC_RX_FLOW_CTRL_RFE | ETH_MAC_RX_FLOW_CTRL_UP;
putreg32(regval, LPC54_ETH_MAC_RX_FLOW_CTRL);
/* Set the speed and duplex. */
#warning Missing logic
regval = ETH_MAC_TX_FLOW_CTRL_Q_PT(CONFIG_LPC54_ETH_TX_PAUSETIME);
putreg32(regval, LPC54_ETH_MAC_TX_FLOW_CTRL_Q0);
putreg32(regval, LPC54_ETH_MAC_TX_FLOW_CTRL_Q1);
#endif
/* Enable the Rx channel */
#warning Missing logic
/* Set the 1us tick counter*/
regval = ETH_MAC_1US_TIC_COUNTR(BOARD_MAIN_CLK / USEC_PER_SEC);
putreg32(regval, LPC54_ETH_MAC_1US_TIC_COUNTR);
/* Set the speed and duplex using the values previously determined through
* autonegotiaion.
*/
regval = ETH_MAC_CONFIG_ECRSFD | ETH_MAC_CONFIG_PS;
#ifdef CONFIG_LPC54_ETH_8023AS2K
regval |= ENET_MAC_CONFIG_S2KP;
#endif
if (priv->eth_fullduplex)
{
regval |= ETH_MAC_CONFIG_DM;
}
else
{
regval |= LPC54_MAC_HALFDUPLEX_IPG;
}
if (priv->eth_100mbps)
{
regval |= ETH_MAC_CONFIG_FES;
}
putreg32(regval, LPC54_ETH_MAC_CONFIG);
/* Enable Rx queues */
regval = ETH_MAC_RXQ_CTRL0_RXQ0EN_ENABLE | ETH_MAC_RXQ_CTRL0_RXQ1EN_ENABLE;
putreg32(regval, LPC54_ETH_MAC_RXQ_CTRL0);
/* Setup up Ethernet interrupts */
regval = LPC54_NORM_INTMASK | LPC54_ABNORM_INTMASK;
putreg32(regval, LPC54_ETH_DMACH_INT_EN(0));
putreg32(regval, LPC54_ETH_DMACH_INT_EN(1));
putreg32(0, LPC54_ETH_MAC_INTR_EN);
/* Initialize descriptors */
#warning Missing logic
/* Set the sideband flow control for each channel */
/* Activate Rx and Tx */
#warning Missing logic
/* Set the sideband flow control for each channel (see UserManual) */
#warning Missing logic
#ifdef CONFIG_NET_ICMPv6
@ -1064,7 +1132,7 @@ static int lpc54_eth_ifdown(FAR struct net_driver_s *dev)
regval = getreg32(LPC54_SYSCON_ETHPHYSEL);
regval &= ~SYSCON_ETHPHYSEL_MASK;
#ifdef CONFIG_LPC54_MII
#ifdef CONFIG_LPC54_ETH_MII
retval |= SYSCON_ETHPHYSEL_MII;
#else
retval |= SYSCON_ETHPHYSEL_RMII;
@ -1331,7 +1399,7 @@ static int lpc54_eth_ioctl(FAR struct net_driver_s *dev, int cmd,
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = CONFIG_LPC54_PHYADDR;
req->phy_id = CONFIG_LPC54_ETH_PHYADDR;
ret = OK;
}
break;
@ -1429,7 +1497,7 @@ static uint16_t lpc54_phy_read(FAR struct lpc54_ethdriver_s *priv,
regval = getreg32(LPC54_ETH_MAC_MDIO_ADDR);
regval &= ETH_MAC_MDIO_ADDR_CR_MASK;
regval |= ETH_MAC_MDIO_ADDR_MOC_READ | ETH_MAC_MDIO_ADDR_RDA(phyreg) |
ETH_MAC_MDIO_ADDR_PA(CONFIG_LPC54_PHYADDR);
ETH_MAC_MDIO_ADDR_PA(CONFIG_LPC54_ETH_PHYADDR);
putreg32(regval, LPC54_ETH_MAC_MDIO_ADDR);
/* Initiate the read */
@ -1472,7 +1540,7 @@ static void lpc54_phy_write(FAR struct lpc54_ethdriver_s *priv,
regval = getreg32(LPC54_ETH_MAC_MDIO_ADDR);
regval &= ETH_MAC_MDIO_ADDR_CR_MASK;
regval |= ETH_MAC_MDIO_ADDR_MOC_WRITE | ETH_MAC_MDIO_ADDR_RDA(phyreg) |
ETH_MAC_MDIO_ADDR_PA(CONFIG_LPC54_PHYADDR);
ETH_MAC_MDIO_ADDR_PA(CONFIG_LPC54_ETH_PHYADDR);
putreg32(regval, LPC54_ETH_MAC_MDIO_ADDR);
/* Set the write data */
@ -1636,7 +1704,7 @@ static int lpc54_phy_reset(FAR struct lpc54_ethdriver_s *priv)
return -ETIMEDOUT;
}
phyval = lpc54_phy_read(base, CONFIG_LPC54_PHYADDR, MII_MCR, &reg);
phyval = lpc54_phy_read(base, CONFIG_LPC54_ETH_PHYADDR, MII_MCR);
}
while ((phyval & MII_MCR_RESET) != 0);
@ -1715,7 +1783,7 @@ int up_netinitialize(int intf)
lpc54_gpio_config(GPIO_ENET_MDIO); /* Ethernet MIIM data input and output */
lpc54_gpio_config(GPIO_ENET_MDC); /* Ethernet MIIM clock */
#ifdef CONFIG_LPC54_MII
#ifdef CONFIG_LPC54_ETH_MII
/* MII interface */
lpc54_gpio_config(GPIO_ENET_RXD0); /* Ethernet receive data 0-3 */