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risc-v/litex: Add a vexriscv and vexriscv_smp section to arty_a7 doc.

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risc-v/litex: For vexriscv_smp, explicitly document requirement for C ISA ext.

Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
This commit is contained in:
Justin Erenkrantz 2025-12-12 11:35:55 -05:00 • committed by Xiang Xiao
parent 53edfb5815
commit 52d5aeb60c
2 changed files with 33 additions and 5 deletions
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30
Documentation/platforms/risc-v/litex/boards/arty_a7/index.rst
View file

@ -58,11 +58,16 @@ You will need to download the tool-chain for this board:
$ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz
Flashing
vexriscv
========
This section is for the vexriscv softcore fpga gateware.
Flashing
--------
1. Follow the instructions on https://github.com/enjoy-digital/litex to build
the vexriscv softcore fpga gateware and flash to Arty A7 board:
the vexriscv and flash to Arty A7 board:
.. code:: console
@ -86,7 +91,7 @@ Flashing
You should then see the NSH prompt.
Configurations
==============
--------------
You can configure NuttX for this board using:
@ -97,6 +102,23 @@ You can configure NuttX for this board using:
Where ``<config>`` is the name of one of the configurations listed below.
nsh
---
^^^
A simple configuration with the NSH shell.
VexRISCV_SMP
============
This section is for the VexRISCV_SMP softcore fpga gateware.
1. For VexRISCV_SMP cores on an Arty A7, you can follow the instructions on
https://github.com/enjoy-digital/litex to build the vexriscv_smp softcore fpga gateware:
.. code:: console
$ cd litex-boards/litex_boards/targets
$ ./digilent_arty.py --with-ethernet --with-sdcard --uart-baudrate 1000000 --cpu-type=vexriscv_smp --cpu-variant=linux --with-rvc --cpu-count 8 --build --load --flash
Please consult the VexRISCV_SMP core documentation for more information about setting up a two-pass build.

8
Documentation/platforms/risc-v/litex/cores/vexriscv_smp/index.rst
View file

@ -6,6 +6,12 @@ The vexrisc_smp core supports a two-pass build, producing the kernel (nuttx.bin)
compiled into the apps/bin directory. In the standard configuration, the applications are loaded to the FPGA in a RAMdisk.
Although, for custom boards this could be extended to loading from SDCards, flash, or other mediums.
Configuration
-------------
For VexRISCV_SMP cores, the gateware requires the `--with-rvc` configuration to enable compressed
instructions. Please consult the appropriate board documentation for flashing gateware.
Building
--------
@ -53,4 +59,4 @@ Load the application over serial with::
litex_term --images=boot.json --speed=1e6 /dev/ttyUSB0
Update the baud rate and serial port to suit your configuration.
Update the baud rate and serial port to suit your configuration.