diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index febe16549dc..2a74fa07038 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -733,6 +733,7 @@ config ARCH_CHIP_STM32U5 config ARCH_CHIP_STM32WB bool "STMicro STM32 WB" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_FPU select ARCH_HAVE_MPU diff --git a/arch/arm/include/stm32wb/chip.h b/arch/arm/include/stm32wb/chip.h index 61ffe8eb774..6945832aab6 100644 --- a/arch/arm/include/stm32wb/chip.h +++ b/arch/arm/include/stm32wb/chip.h @@ -40,14 +40,14 @@ #define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ #define STM32_NGTIMNDMA 0 /* No general timers without DMA */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ #else # define STM32_NGTIM16 0 /* No 16-bit general timers */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_NDMA 2 /* DMA1-2 with 7 channels each */ # define STM32_NI2S 1 /* SAI1 (dual channel high quality audio) */ # define STM32_NI2C 2 /* I2C1, I2C3 */ @@ -67,8 +67,8 @@ # define STM32_NSPI 1 /* SPI1 */ #endif -#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) \ - || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) \ + || defined(CONFIG_STM32_STM32WB55) # define STM32_NLPUART 1 /* LPUART1 */ #else # define STM32_NLPUART 0 /* No LPUART */ @@ -80,7 +80,7 @@ # define STM32_NCAPSENSE 0 /* No Capacitive sensing */ #endif -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) # define STM32_NLCD 1 /* One LCD controller with up to 8x40 * terminals, depending on subfamily. * 55Cx: 4x13 @@ -138,20 +138,20 @@ * 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000 */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define STM32_SRAM1_SIZE (12*1024) # define STM32_SRAM2A_SIZE (32*1024) # define STM32_SRAM2B_SIZE (4*1024) -#elif defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) +#elif defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB35) # define STM32_SRAM1_SIZE (32*1024) # define STM32_SRAM2A_SIZE (32*1024) # define STM32_SRAM2B_SIZE (32*1024) -#elif (defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55)) \ +#elif (defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55)) \ && defined(CONFIG_STM32WB_IO_CONFIG_C) # define STM32_SRAM1_SIZE (64*1024) # define STM32_SRAM2A_SIZE (32*1024) # define STM32_SRAM2B_SIZE (32*1024) -#elif defined(CONFIG_STM32WB_STM32WB55) && \ +#elif defined(CONFIG_STM32_STM32WB55) && \ (defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)) # define STM32_SRAM1_SIZE (192*1024) # define STM32_SRAM2A_SIZE (32*1024) diff --git a/arch/arm/include/stm32wb/stm32wb_irq.h b/arch/arm/include/stm32wb/stm32wb_irq.h index f61881f6a7c..88eba8470cb 100644 --- a/arch/arm/include/stm32wb/stm32wb_irq.h +++ b/arch/arm/include/stm32wb/stm32wb_irq.h @@ -54,12 +54,12 @@ #define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_PVM1 (STM32_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) # define STM32_IRQ_PVM3 (STM32_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ #endif @@ -83,15 +83,15 @@ #define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ #define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define STM32_IRQ_USB_HP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ #define STM32_IRQ_USB_LP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ #endif #define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) # define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ #endif @@ -100,8 +100,8 @@ #define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ #define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ # define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ #endif @@ -112,37 +112,37 @@ #define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ #define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ # define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ #endif #define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ #endif #define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) # define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) \ - || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) \ + || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_TSC (STM32_IRQ_FIRST + 39) /* 39: TSC global interrupt */ #endif #define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ #define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_CRS (STM32_IRQ_FIRST + 42) /* 42: CRS interrupt */ #endif @@ -150,8 +150,8 @@ #define STM32_IRQ_PWRBLEACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ #define STM32_IRQ_PWRRFPHASE (STM32_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_PWR802ACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ #endif @@ -161,11 +161,11 @@ #define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ #define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_LCD (STM32_IRQ_FIRST + 49) /* 49: LCD global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ # define STM32_IRQ_AES1 (STM32_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ #endif @@ -174,7 +174,7 @@ #define STM32_IRQ_RNG (STM32_IRQ_FIRST + 53) /* 53: RNG global interrupt */ #define STM32_IRQ_FPU (STM32_IRQ_FIRST + 54) /* 54: FPU global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ # define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ # define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index 79f82cf8573..c9646782740 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -55,11 +55,11 @@ else() list(APPEND SRCS stm32wb_tickless.c) endif() -if(CONFIG_STM32WB_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c) endif() -if(CONFIG_STM32WB_FREERUN) +if(CONFIG_STM32_FREERUN) list(APPEND SRCS stm32wb_freerun.c) endif() @@ -67,11 +67,11 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32wb_userspace.c stm32wb_mpuinit.c) endif() -if(CONFIG_STM32WB_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32wb_rcc_hsi48.c) endif() -if(CONFIG_STM32WB_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32wb_dma.c) endif() @@ -84,11 +84,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32WB_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32wb_exti_pwr.c) endif() -if(CONFIG_STM32WB_RTC) +if(CONFIG_STM32_RTC) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32wb_exti_alarm.c) endif() @@ -100,15 +100,15 @@ if(CONFIG_STM32WB_RTC) endif() endif() -if(CONFIG_STM32WB_IPCC) +if(CONFIG_STM32_IPCC) list(APPEND SRCS stm32wb_ipcc.c) endif() -if(CONFIG_STM32WB_MBOX) +if(CONFIG_STM32_MBOX) list(APPEND SRCS stm32wb_mbox.c) endif() -if(CONFIG_STM32WB_BLE) +if(CONFIG_STM32_BLE) list(APPEND SRCS stm32wb_blehci.c) endif() diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index aba177dfed9..70a74724de2 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -7,6 +7,27 @@ if ARCH_CHIP_STM32WB comment "STM32WB Configuration Options" +config STM32_WB_PERIPHERALS + bool + default ARCH_CHIP_STM32WB + select STM32_HAVE_BLE + select STM32_HAVE_DMA1 + select STM32_HAVE_MBOX + select STM32_HAVE_IPCC + select STM32_HAVE_SRAM2A + select STM32_HAVE_SRAM2B + select STM32_HAVE_I2C1 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 if STM32_HAVE_LPUART + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + choice prompt "STM32 WB Chip Selection" default ARCH_CHIP_STM32WB55RG @@ -14,129 +35,129 @@ choice config ARCH_CHIP_STM32WB10CC bool "STM32WB10CC" - select STM32WB_STM32WB10 + select STM32_STM32WB10 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_320 + select STM32_FLASH_CONFIG_C_320 ---help--- STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM config ARCH_CHIP_STM32WB15CC bool "STM32WB15CC" - select STM32WB_STM32WB15 + select STM32_STM32WB15 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_320 + select STM32_FLASH_CONFIG_C_320 ---help--- STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM config ARCH_CHIP_STM32WB30CE bool "STM32WB30CE" - select STM32WB_STM32WB30 + select STM32_STM32WB30 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB50CG bool "STM32WB50CG" - select STM32WB_STM32WB50 + select STM32_STM32WB50 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB35CC bool "STM32WB35CC" - select STM32WB_STM32WB35 + select STM32_STM32WB35 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB35CE bool "STM32WB35CE" - select STM32WB_STM32WB35 + select STM32_STM32WB35 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CC bool "STM32WB55CC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RC bool "STM32WB55RC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VC bool "STM32WB55VC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CE bool "STM32WB55CE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RE bool "STM32WB55RE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VE bool "STM32WB55VE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VY bool "STM32WB55VY" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_Y_640 + select STM32_FLASH_CONFIG_Y ---help--- STM32 WB Cortex M4, 640 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CG bool "STM32WB55CG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RG bool "STM32WB55RG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VG bool "STM32WB55VG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM @@ -144,137 +165,81 @@ endchoice # STM32 WB Chip Selection # Chip product lines -config STM32WB_STM32WB10 +config STM32_STM32WB10 # STM32WB10 Value Line bool default n - select STM32WB_HAVE_TSC + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TSC -config STM32WB_STM32WB15 +config STM32_STM32WB15 # STM32WB15 Standard Line bool default n - select STM32WB_HAVE_TSC - select STM32WB_HAVE_LPUART - select STM32WB_HAVE_SMPS if !ARCH_CHIP_STM32WB15CCUXE + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TSC + select STM32_HAVE_LPUART + select STM32_HAVE_SMPS if !ARCH_CHIP_STM32WB15CCUXE -config STM32WB_STM32WB30 +config STM32_STM32WB30 # STM32WB30 Value Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 + select STM32_HAVE_HSI48 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32WB_STM32WB50 +config STM32_STM32WB50 # STM32WB50 Value Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 + select STM32_HAVE_HSI48 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32WB_STM32WB35 +config STM32_STM32WB35 # STM32WB35 Standard Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_DMA2 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 - select STM32WB_HAVE_I2C3 - select STM32WB_HAVE_QSPI - select STM32WB_HAVE_USB - select STM32WB_HAVE_SAI - select STM32WB_HAVE_COMP - select STM32WB_HAVE_SMPS + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C3 + select STM32_HAVE_QSPI + select STM32_HAVE_USB + select STM32_HAVE_SAI + select STM32_HAVE_COMP + select STM32_HAVE_SMPS -config STM32WB_STM32WB55 +config STM32_STM32WB55 # STM32WB55 Standard Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_DMA2 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 - select STM32WB_HAVE_I2C3 - select STM32WB_HAVE_SPI2 if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V - select STM32WB_HAVE_QSPI - select STM32WB_HAVE_USB - select STM32WB_HAVE_SAI - select STM32WB_HAVE_COMP - select STM32WB_HAVE_LPUART - select STM32WB_HAVE_TSC if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V - select STM32WB_HAVE_LCD - select STM32WB_HAVE_SMPS - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32WB - default STM32WB_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32WB series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - C 256 or 320 - E 512 - Y 640 - G 1024 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32WB Chip Selection. - - Examples: - If the STM32WB55RG is chosen, the Flash configuration would be 'G', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - If an STM32WB Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32WB_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32WB_FLASH_OVERRIDE_C_256 - bool "C 256 KB" - -config STM32WB_FLASH_OVERRIDE_C_320 - bool "C 320 KB" - -config STM32WB_FLASH_OVERRIDE_E_512 - bool "E 512 KB" - -config STM32WB_FLASH_OVERRIDE_Y_640 - bool "Y 640 KB" - -config STM32WB_FLASH_OVERRIDE_G_1024 - bool "G 1024 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32WB_FLASH_CONFIG_C_256 - bool - default n - -config STM32WB_FLASH_CONFIG_C_320 - bool - default n - -config STM32WB_FLASH_CONFIG_E_512 - bool - default n - -config STM32WB_FLASH_CONFIG_Y_640 - bool - default n - -config STM32WB_FLASH_CONFIG_G_1024 - bool - default n + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V + select STM32_HAVE_QSPI + select STM32_HAVE_USB + select STM32_HAVE_SAI + select STM32_HAVE_COMP + select STM32_HAVE_LPUART + select STM32_HAVE_TSC if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V + select STM32_HAVE_LCD + select STM32_HAVE_SMPS # Pin/package configurations @@ -282,13 +247,13 @@ config STM32WB_IO_CONFIG_C # UFQFPN48 package bool default n - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_C_48E # UFQFPN48E package bool default n - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_C_49 # WLCSP49 package @@ -299,889 +264,14 @@ config STM32WB_IO_CONFIG_R # VFQFPN68 package bool default n - select STM32WB_GPIO_HAVE_PORTD - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTD + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_V # WLCSP100 and UFBGA129 packages bool default n - select STM32WB_GPIO_HAVE_PORTD - select STM32WB_GPIO_HAVE_PORTE - -comment "STM32WB SRAM2a and SRAM2b Options" - -config STM32WB_SRAM2A_HEAP - bool "SRAM2a is used for heap" - default n - -config STM32WB_SRAM2A_USER_BASE_OFFSET - int "SRAM2a user application base offset" - default 2048 - range 0 32768 - depends on STM32WB_SRAM2A_HEAP - ---help--- - The beginning part of the SRAM2a memory can be used by RF stack. The - available space for the user application can be obtained from the - release notes for STM32WB coprocessor wireless binaries. - -config STM32WB_SRAM2A_USER_SIZE - int "SRAM2a user application size" - default 8192 - range 0 32768 - depends on STM32WB_SRAM2A_HEAP - ---help--- - The ending part of the SRAM2a memory contains a secure section, which - cannot be read nor written by CPU1. The secure start address for the - SRAM2a memory can be read from the SBRSA option byte. When CPU2 update - support required, there must be some free sectors just below the secure - memory to support CPU2 firmware updates requiring more sectors to be - secure. - -config STM32WB_SRAM2A_INIT - bool "SRAM2a is initialized to zero" - default y - depends on STM32WB_SRAM2A_HEAP - ---help--- - The STM32WB SRAM2a region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2a is being retained in Standby mode, this may be - undesirable (because it will destroy the contents). In that case, the board - should handle the initialization itself at the appropriate time. - -config STM32WB_SRAM2B_HEAP - bool "SRAM2b is used for heap" - default n - -config STM32WB_SRAM2B_USER_SIZE - int "SRAM2b user application size" - default 32768 - range 0 32768 - depends on STM32WB_SRAM2B_HEAP - ---help--- - For any CPU2 firmware supporting the BLE protocol the ending part of - the SRAM2b memory contains a secure section, which cannot be read nor - written by CPU1. The secure start address for the SRAM2b memory can be - read from the SNBRSA option byte. When CPU2 update support required, - there must be some free sectors just below the secure memory to support - CPU2 firmware updates requiring more sectors to be secure. The SRAM2b - memory is all secure for any CPU2 firmware supporting the Thread protocol. - -config STM32WB_SRAM2B_INIT - bool "SRAM2b is initialized to zero" - default y - depends on STM32WB_SRAM2B_HEAP - ---help--- - The STM32WB SRAM2b region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - -comment "STM32WB Peripherals" - -menu "STM32WB Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32WB_GPIO_HAVE_PORTD - bool - default n - -config STM32WB_GPIO_HAVE_PORTE - bool - default n - -config STM32WB_HAVE_COMP - bool - default n - -config STM32WB_HAVE_LPUART - bool - default n - -config STM32WB_HAVE_DMA2 - bool - default n - -config STM32WB_HAVE_TIM16 - bool - default n - -config STM32WB_HAVE_TIM17 - bool - default n - -config STM32WB_HAVE_SPI2 - bool - default n - -config STM32WB_HAVE_I2C3 - bool - default n - -config STM32WB_HAVE_SAI - bool - default n - -config STM32WB_HAVE_LCD - bool - default n - -config STM32WB_HAVE_TSC - bool - default n - -config STM32WB_HAVE_USB - bool - default n - -config STM32WB_HAVE_QSPI - bool - default n - -config STM32WB_HAVE_SMPS - bool - default n - -# These are the peripheral selections proper - -config STM32WB_RTC - bool "RTC" - default n - select RTC - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32WB_ADC - bool - default n - -config STM32WB_DMAMUX - bool - default n - -config STM32WB_DMA - bool - default n - select STM32WB_DMAMUX - -config STM32WB_IPCC - bool - default n - -config STM32WB_I2C - bool - default n - -config STM32WB_SAI - bool - default n - -config STM32WB_SPI - bool - default n - -config STM32WB_USART - bool - default n - -config STM32WB_LPTIM - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32WB_DMA1 - bool "DMA1" - default n - select ARCH_DMA - select STM32WB_DMA - -config STM32WB_DMA2 - bool "DMA2" - default n - depends on STM32WB_HAVE_DMA2 - select ARCH_DMA - select STM32WB_DMA - -config STM32WB_CRC - bool "CRC" - default n - -comment "APB1 Peripherals" - -config STM32WB_PWR - bool "PWR" - default n - -config STM32WB_TIM2 - bool "TIM2" - default n - -config STM32WB_SPI2 - bool "SPI2" - default n - depends on STM32WB_HAVE_SPI2 - select SPI - select STM32WB_SPI - -config STM32WB_LPTIM1 - bool "LPTIM1" - default n - select STM32WB_LPTIM - -config STM32WB_LPTIM2 - bool "LPTIM2" - default n - select STM32WB_LPTIM - -config STM32WB_LPUART1 - bool "LPUART1" - default n - depends on STM32WB_HAVE_LPUART - select ARCH_HAVE_SERIAL_TERMIOS - select ARCH_HAVE_LPUART1 - select STM32WB_USART - -config STM32WB_I2C1 - bool "I2C1" - default n - select I2C - select STM32WB_I2C - -config STM32WB_I2C3 - bool "I2C3" - default n - depends on STM32WB_HAVE_I2C3 - select I2C - select STM32WB_I2C - -comment "APB2 Peripherals" - -config STM32WB_SYSCFG - bool "SYSCFG" - default y - -config STM32WB_TIM1 - bool "TIM1" - default n - -config STM32WB_SPI1 - bool "SPI1" - default n - select SPI - select STM32WB_SPI - -config STM32WB_USART1 - bool "USART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WB_USART - -config STM32WB_TIM16 - bool "TIM16" - default n - depends on STM32WB_HAVE_TIM16 - -config STM32WB_TIM17 - bool "TIM17" - default n - depends on STM32WB_HAVE_TIM17 - -endmenu - -config STM32WB_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32WB clock configuration. - -config STM32WB_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32WB_RTC - -config STM32WB_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32WB_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32WB_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32WB_RTC_LSECLOCK - depends on STM32WB_RTC - -config STM32WB_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32WB_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32WB_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32WB_RTC_LSECLOCK - -config STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -endif # STM32WB_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32WB_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32WB_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32WB_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32WB_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32WB_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32WB_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -endmenu # Timer Configuration - -config STM32WB_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32WB_LPUART1 || STM32WB_USART1 - -choice - prompt "LPUART1 Driver Configuration" - default STM32WB_LPUART1_SERIALDRIVER - depends on STM32WB_LPUART1 - -config STM32WB_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32WB_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32WB_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32WB_LPUART1 && STM32WB_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32WB_USART1_SERIALDRIVER - depends on STM32WB_USART1 - -config STM32WB_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32WB_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32WB_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32WB_USART1 && STM32WB_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -if STM32WB_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32WB_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32WB_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32WB_USART1 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32WB_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32WB_USART1 - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32WB have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32WB_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32WB_USART1 - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32WB manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32WB_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32WB_USART1 && STM32WB_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32WB U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32WB_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32WB_USART1 - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32WB serial driver. - -config STM32WB_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32WB_USART1 - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32WB serial driver. - -config STM32WB_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32WB_USART1 - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32WB serial driver. - -if PM - -config STM32WB_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endif # STM32WB_SERIALDRIVER - -endmenu # [LP]U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32WB_SPI1 || STM32WB_SPI2 - -config STM32WB_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32WB_SPI_DMA - bool "SPI DMA" - depends on STM32WB_DMA - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32WB_SPI_INTERRUPT. - -endmenu - -config STM32WB_MBOX - bool - default n - select STM32WB_IPCC - -menuconfig STM32WB_BLE - bool "BLE" - default n - select STM32WB_MBOX - ---help--- - Enable BLE support. - -if STM32WB_BLE - -config STM32WB_BLE_C2HOST - bool "Enable CPU2 HOST stack" - default n - ---help--- - The full stack version of CPU2 firmware allows to enable CPU2 HOST stack and - control it using vendor ACL protocol. However, it is not expected to enable - this option in the current implementation. - -config STM32WB_BLE_MAX_CONN - int "Maximum BLE simultaneous connections" - range 1 8 - default 2 - -config STM32WB_BLE_GATT_MAX_ATTR_NUM - int "GATT attributes max count" - range 9 255 - default 64 - -config STM32WB_BLE_GATT_MAX_SVC_NUM - int "GATT services max count" - range 2 64 - default 8 - -config STM32WB_BLE_GATT_ATTR_BUF_SIZE - int "GATT attributes storage buf size" - default 1344 - ---help--- - Size of the storage area for attribute values. Hardcoded in CPU2 firmware. - -config STM32WB_BLE_DLE - bool "Support Data Length Extension (DLE)" - default y - -config STM32WB_BLE_MAX_ATT_MTU - int "Maximum supported attribute MTU" - range 23 512 - default 156 - -config STM32WB_BLE_SLAVE_SCA - int "Sleep clock accuracy in slave mode [PPM]" - default 500 - ---help--- - Sleep clock accuracy (ppm value) in slave mode. - -choice - prompt "Sleep clock accuracy in master mode" - default STM32WB_BLE_MASTER_SCA_0 - ---help--- - Sleep clock accuracy in master mode. - -config STM32WB_BLE_MASTER_SCA_0 - bool "251-500 ppm" - -config STM32WB_BLE_MASTER_SCA_1 - bool "151-250 ppm" - -config STM32WB_BLE_MASTER_SCA_2 - bool "101-150 ppm" - -config STM32WB_BLE_MASTER_SCA_3 - bool "76-100 ppm" - -config STM32WB_BLE_MASTER_SCA_4 - bool "51-75 ppm" - -config STM32WB_BLE_MASTER_SCA_5 - bool "31-50 ppm" - -config STM32WB_BLE_MASTER_SCA_6 - bool "21-30 ppm" - -config STM32WB_BLE_MASTER_SCA_7 - bool "0-20 ppm" - -endchoice # Sleep clock accuracy in master mode - -config STM32WB_BLE_MASTER_SCA - int - default 7 if STM32WB_BLE_MASTER_SCA_7 - default 6 if STM32WB_BLE_MASTER_SCA_6 - default 5 if STM32WB_BLE_MASTER_SCA_5 - default 4 if STM32WB_BLE_MASTER_SCA_4 - default 3 if STM32WB_BLE_MASTER_SCA_3 - default 2 if STM32WB_BLE_MASTER_SCA_2 - default 1 if STM32WB_BLE_MASTER_SCA_1 - default 0 - -choice - prompt "Low speed clock source" - default STM32WB_BLE_LS_CLK_SRC_LSE - ---help--- - Low speed 32 kHz clock source. - -config STM32WB_BLE_LS_CLK_SRC_LSE - bool "LSE" - -config STM32WB_BLE_LS_CLK_SRC_HSE - bool "HSE" - -endchoice # Low speed clock source - -config STM32WB_BLE_LS_CLK_SRC - int - default 1 if STM32WB_BLE_LS_CLKSRC_HSE - default 0 - -config STM32WB_BLE_MAX_CONN_EVT_LENGTH - hex "Max connection event length" - default 0xffffffff - ---help--- - Maximum duration of a slave connection event in units of 625/256us (~2.44us). - -config STM32WB_BLE_HSE_STARTUP - hex "HSE startup time" - default 0x148 - ---help--- - HSE startup time in units of 625/256us (~2.44us). - -config STM32WB_BLE_VITERBI - bool "Enable Viterbi algorithm" - default y - ---help--- - Enable Viterbi algorithm implementation - -config STM32WB_BLE_MAX_INITOR_COC_NUM - int "Max number of connection-oriented channels" - range 0 64 - default 32 - ---help--- - Maximum number of connection-oriented channels in initiator mode. - -config STM32WB_BLE_SVC_CHANGED_CHAR - bool "Enable service changed characteristic" - default n - -config STM32WB_BLE_WRITABLE_DEVICE_NAME - bool "Writable device name" - default y - -config STM32WB_BLE_CHAN_SEL_ALG2 - bool "Enable channel selection algorithm 2" - default n - -choice - prompt "Power class" - default STM32WB_BLE_POWER_CLASS_2_3 - -config STM32WB_BLE_POWER_CLASS_2_3 - bool "Power Class 2-3" - -config STM32WB_BLE_POWER_CLASS_1 - bool "Power Class 1" - -endchoice # Power class - -config STM32WB_BLE_MIN_TX_POWER - int "Minimum transmit power [dBm]" - range -127 20 - default 0 - -config STM32WB_BLE_MAX_TX_POWER - int "Maximum transmit power [dBm]" - range -127 20 - default 0 - -choice - prompt "AGC RSSI model" - default STM32WB_BLE_AGC_RSSI_LEGACY - -config STM32WB_BLE_AGC_RSSI_LEGACY - bool "AGC RSSI Legacy" - -config STM32WB_BLE_AGC_RSSI_IMPROVED - bool "AGC RSSI Improved" - -endchoice # AGC RSSI model - -config STM32WB_BLE_ADVERTISING - bool "Support advertising" - default y - -config STM32WB_BLE_SCANNING - bool "Support scanning" - default y - -config STM32WB_BLE_LE_2M_PHY - bool "Support LE 2M PHY" - default y - -config STM32WB_BLE_LE_CODED_PHY - bool "Support LE Coded PHY" - default STM32WB_STM32WB15 || STM32WB_STM32WB35 || STM32WB_STM32WB55 - depends on STM32WB_STM32WB15 || STM32WB_STM32WB35 || STM32WB_STM32WB55 - -config STM32WB_BLE_FICR_STATIC_ADDR - bool "Configure factory generated static random address" - default n - -config STM32WB_BLE_PUB_ADDR - hex "Configure BT public address" - default 0x0000000000 - -endif # STM32WB_BLE - -if STM32WB_MBOX - -config STM32WB_MBOX_TX_CMD_QUEUE_LEN - int "Mailbox TX command queue length" - default 2 - -config STM32WB_MBOX_RX_EVT_QUEUE_LEN - int "Mailbox RX event queue length" - default 5 - -endif # STM32WB_MBOX + select STM32_GPIO_HAVE_PORTD + select STM32_GPIO_HAVE_PORTE endif # ARCH_CHIP_STM32WB diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index a8ff0d7afa9..2bf29ecfd14 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -50,11 +50,11 @@ else CHIP_CSRCS += stm32wb_tickless.c endif -ifeq ($(CONFIG_STM32WB_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c endif -ifeq ($(CONFIG_STM32WB_FREERUN),y) +ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32wb_freerun.c endif @@ -62,11 +62,11 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32wb_userspace.c stm32wb_mpuinit.c endif -ifeq ($(CONFIG_STM32WB_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32wb_rcc_hsi48.c endif -ifeq ($(CONFIG_STM32WB_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32wb_dma.c endif @@ -79,11 +79,11 @@ CHIP_CSRCS += stm32wb_pminitialize.c endif endif -ifeq ($(CONFIG_STM32WB_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32wb_exti_pwr.c endif -ifeq ($(CONFIG_STM32WB_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32wb_exti_alarm.c endif @@ -95,15 +95,15 @@ CHIP_CSRCS += stm32wb_rtc.c stm32wb_rtc_lowerhalf.c endif endif -ifeq ($(CONFIG_STM32WB_IPCC),y) +ifeq ($(CONFIG_STM32_IPCC),y) CHIP_CSRCS += stm32wb_ipcc.c endif -ifeq ($(CONFIG_STM32WB_MBOX),y) +ifeq ($(CONFIG_STM32_MBOX),y) CHIP_CSRCS += stm32wb_mbox.c endif -ifeq ($(CONFIG_STM32WB_BLE),y) +ifeq ($(CONFIG_STM32_BLE),y) CHIP_CSRCS += stm32wb_blehci.c endif diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h index 90991b1ee21..0aad9fd84aa 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h @@ -35,7 +35,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32WB_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with * CONFIG_STM32WB_FLASH_OVERRIDE_x @@ -50,38 +50,38 @@ * N.B. Only Single bank mode is supported */ -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_Y) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C_320) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_Y) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) # error "Flash size not defined" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32WB_FLASH_CONFIG_C_256 -# undef CONFIG_STM32WB_FLASH_CONFIG_C_320 -# undef CONFIG_STM32WB_FLASH_CONFIG_E_512 -# undef CONFIG_STM32WB_FLASH_CONFIG_Y_640 -# undef CONFIG_STM32WB_FLASH_CONFIG_G_1024 -# if defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256) -# define CONFIG_STM32WB_FLASH_CONFIG_C_256 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320) -# define CONFIG_STM32WB_FLASH_CONFIG_C_320 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512) -# define CONFIG_STM32WB_FLASH_CONFIG_E_512 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640) -# define CONFIG_STM32WB_FLASH_CONFIG_Y_640 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024) -# define CONFIG_STM32WB_FLASH_CONFIG_G_1024 +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_C_320 +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_Y +# undef CONFIG_STM32_FLASH_CONFIG_G +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) +# define CONFIG_STM32_FLASH_CONFIG_C_320 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_Y) +# define CONFIG_STM32_FLASH_CONFIG_Y +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif @@ -89,15 +89,15 @@ #define STM32_FLASH_PAGESIZE 4096 -#if defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) /* 256 kB */ +#if defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ # define STM32_FLASH_NPAGES 64 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) /* 320 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_C_320) /* 320 kB */ # define STM32_FLASH_NPAGES 80 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) /* 512 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ # define STM32_FLASH_NPAGES 128 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) /* 640 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_Y) /* 640 kB */ # define STM32_FLASH_NPAGES 160 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) /* 1 MB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ # define STM32_FLASH_NPAGES 256 #else # error "Unknown flash configuration!" diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h index 390dc47c2e0..180972f07a7 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h @@ -79,7 +79,7 @@ #define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) #define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) # define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -93,7 +93,7 @@ # define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h index d5e25cae2f5..a16c5a97dff 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h @@ -55,7 +55,7 @@ #define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) #define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) -#ifdef CONFIG_STM32WB_HAVE_I2C3 +#ifdef CONFIG_STM32_HAVE_I2C3 # define STM32_I2C3_CR1 (STM32_I2C3_BASE + STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE + STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE + STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h index 5b364b57164..547d650589c 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || \ - defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) || \ - defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || \ + defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB35) || \ + defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55) # include "hardware/stm32wbxx_pinmap.h" #else # error "Unsupported STM32WB Pin map" diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h index ddf8e305d01..fd433817a3d 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h @@ -58,7 +58,7 @@ #define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) #define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) -#if CONFIG_STM32WB_HAVE_SPI2 +#if CONFIG_STM32_HAVE_SPI2 # define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h index ab8255bba6b..7c9a15dd045 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h @@ -58,7 +58,7 @@ /* ADC */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_ADC1_IN2_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) # define GPIO_ADC1_IN3_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) # define GPIO_ADC1_IN4_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) @@ -77,8 +77,8 @@ #define GPIO_ADC1_IN10_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) #define GPIO_ADC1_IN11_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define GPIO_ADC1_IN12_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) # define GPIO_ADC1_IN15_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) # define GPIO_ADC1_IN16_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) @@ -95,7 +95,7 @@ /* Comparators */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_COMP1_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) #define GPIO_COMP1_INP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) @@ -128,7 +128,7 @@ # define GPIO_COMP2_OUT_4 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN11) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* I2C */ @@ -145,7 +145,7 @@ # define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN9) #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_I2C3_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN4) #define GPIO_I2C3_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN7) @@ -161,7 +161,7 @@ # define GPIO_I2C3_SDA_4 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTC | GPIO_PIN1) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* JTAG/SWD */ @@ -176,7 +176,7 @@ /* QUADSPI */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_QSPI_NCS_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN2) #define GPIO_QSPI_CLK_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN3) @@ -198,7 +198,7 @@ # define GPIO_QSPI_BK1_IO3_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN7) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* RTC */ @@ -215,7 +215,7 @@ /* SAI */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_SAI1_EXTCLK_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN0) #define GPIO_SAI1_EXTCLK_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN2) @@ -257,7 +257,7 @@ # define GPIO_SAI1_PDMDI1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN6) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* SPI */ @@ -277,14 +277,14 @@ # define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_SPI1_MOSI_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN5) # define GPIO_SPI1_MOSI_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN13) # define GPIO_SPI1_NSS_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN14) # define GPIO_SPI1_NSS_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN6) #endif -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) #define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9) #define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12) @@ -305,7 +305,7 @@ # define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN3) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB55) */ /* Timers */ @@ -346,7 +346,7 @@ # define GPIO_TIM1_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN15) #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_TIM1_CH3IN_2 (GPIO_ALT | GPIO_AF12 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN7) # define GPIO_TIM1_CH3OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) #endif @@ -393,8 +393,8 @@ # define GPIO_TIM2_CH3OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13) #endif -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_TIM16_BKIN_0 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN5) #define GPIO_TIM16_CH1IN_1 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN8) @@ -420,7 +420,7 @@ # define GPIO_TIM17_CH1OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN1) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ #define GPIO_LPTIM1_ETR_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6) #define GPIO_LPTIM1_OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14) @@ -453,7 +453,7 @@ /* Touch Screen Controller */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB55) #if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_SYNC_1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN10) @@ -523,7 +523,7 @@ # define GPIO_TSC_G7_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN2) #endif -#if defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB15) # define GPIO_TSC_G7_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN13) # define GPIO_TSC_G7_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN10) # define GPIO_TSC_G7_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN8) @@ -531,12 +531,12 @@ #define GPIO_TSC_G7_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN9) -#endif /* defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB55) */ /* IR interface (with timers 16 and 17) */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define GPIO_IR_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN13) # define GPIO_IR_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN9) #endif @@ -570,7 +570,7 @@ # define GPIO_USART1_RTS_DE_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_LPUART1_TX_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN2) #define GPIO_LPUART1_TX_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN5) @@ -588,11 +588,11 @@ # define GPIO_LPUART1_RTS_DE_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN12) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* USB */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_USB_CRS_SYNC_0 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN10) #define GPIO_USB_DM_0 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) @@ -603,6 +603,6 @@ # define GPIO_USB_NOE_2 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN9) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ #endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WBXX_PINMAP_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c index d22ff6b51de..6b94fcd1402 100644 --- a/arch/arm/src/stm32wb/stm32wb_allocateheap.c +++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c @@ -65,16 +65,16 @@ /* Set the range of SRAM2a as well, requires a second memory region */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) -# define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2A_HEAP +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_END (SRAM2A_START + CONFIG_STM32_SRAM2A_USER_SIZE) #endif /* Set the range of SRAM2b as well, requires a third memory region */ -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP # define SRAM2B_START STM32_SRAM2B_BASE -# define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) +# define SRAM2B_END (SRAM2B_START + CONFIG_STM32_SRAM2B_USER_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify @@ -82,25 +82,25 @@ * that we have been asked to add to the heap. */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP +#ifdef CONFIG_STM32_SRAM2A_HEAP # if SRAM2A_END > STM32_SRAM2A_BASE + STM32_SRAM2A_SIZE # error "SRAM2a heap memory region is out of it's physical address space" # endif #endif -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP # if SRAM2B_END > STM32_SRAM2B_BASE + STM32_SRAM2B_SIZE # error "SRAM2b heap memory region is out of it's physical address space" # endif #endif -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32WB_SRAM2A_HEAP) + \ - defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2A_HEAP) + \ + defined(CONFIG_STM32_SRAM2B_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32WB_SRAM2A_HEAP) + \ - defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2A_HEAP) + \ + defined(CONFIG_STM32_SRAM2B_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -283,7 +283,7 @@ void arm_addregion(void) * from the release notes for STM32WB coprocessor wireless binaries. */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP +#ifdef CONFIG_STM32_SRAM2A_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -301,9 +301,9 @@ void arm_addregion(void) kumm_addregion((void *)SRAM2A_START, SRAM2A_END - SRAM2A_START); -#endif /* CONFIG_STM32WB_SRAM2A_HEAP */ +#endif /* CONFIG_STM32_SRAM2A_HEAP */ -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -321,6 +321,6 @@ void arm_addregion(void) kumm_addregion((void *)SRAM2B_START, SRAM2B_END - SRAM2B_START); -#endif /* CONFIG_STM32WB_SRAM2B_HEAP */ +#endif /* CONFIG_STM32_SRAM2B_HEAP */ } #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 7b69d9b314f..3df0927bd0e 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -54,38 +54,38 @@ /* BLE init configuration params */ #define STM32_BLE_PREP_WRITE_NUM \ - STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU) + STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU) #define STM32_C2_MEM_BLOCK_NUM \ - STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU, \ - CONFIG_STM32WB_BLE_MAX_CONN, \ + STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU, \ + CONFIG_STM32_BLE_MAX_CONN, \ STM32_BLE_PREP_WRITE_NUM) -#ifdef CONFIG_STM32WB_BLE_C2HOST +#ifdef CONFIG_STM32_BLE_C2HOST # define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST #else # define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL #endif -#ifdef CONFIG_STM32WB_BLE_SVC_CHANGED_CHAR +#ifdef CONFIG_STM32_BLE_SVC_CHANGED_CHAR # define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED #else # define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED #endif -#ifdef CONFIG_STM32WB_BLE_WRITABLE_DEVICE_NAME +#ifdef CONFIG_STM32_BLE_WRITABLE_DEVICE_NAME # define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW #else # define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO #endif -#ifdef CONFIG_STM32WB_BLE_CHAN_SEL_ALG2 +#ifdef CONFIG_STM32_BLE_CHAN_SEL_ALG2 # define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED #else # define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED #endif -#ifdef CONFIG_STM32WB_BLE_POWER_CLASS_1 +#ifdef CONFIG_STM32_BLE_POWER_CLASS_1 # define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 #else # define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 @@ -96,7 +96,7 @@ STM32_BLE_DEVICE_NAME_MODE | STM32_BLE_CS_ALG2 | \ STM32_BLE_POWER_CLASS) -#ifdef CONFIG_STM32WB_BLE_AGC_RSSI_IMPROVED +#ifdef CONFIG_STM32_BLE_AGC_RSSI_IMPROVED # define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED #else # define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY @@ -299,25 +299,25 @@ static void stm32_blehci_bleinit(void) { .ble_buf = NULL, .ble_buf_size = 0, - .gatt_attr_num = CONFIG_STM32WB_BLE_GATT_MAX_ATTR_NUM, - .gatt_srv_num = CONFIG_STM32WB_BLE_GATT_MAX_SVC_NUM, - .gatt_attr_buf_size = CONFIG_STM32WB_BLE_GATT_ATTR_BUF_SIZE, - .max_conn = CONFIG_STM32WB_BLE_MAX_CONN, - .dle_enable = CONFIG_STM32WB_BLE_DLE, + .gatt_attr_num = CONFIG_STM32_BLE_GATT_MAX_ATTR_NUM, + .gatt_srv_num = CONFIG_STM32_BLE_GATT_MAX_SVC_NUM, + .gatt_attr_buf_size = CONFIG_STM32_BLE_GATT_ATTR_BUF_SIZE, + .max_conn = CONFIG_STM32_BLE_MAX_CONN, + .dle_enable = CONFIG_STM32_BLE_DLE, .prep_write_op_num = STM32_BLE_PREP_WRITE_NUM, .mem_block_num = STM32_C2_MEM_BLOCK_NUM, - .att_max_mtu_size = CONFIG_STM32WB_BLE_MAX_ATT_MTU, - .slave_sca = CONFIG_STM32WB_BLE_SLAVE_SCA, - .master_sca_range = CONFIG_STM32WB_BLE_MASTER_SCA, - .ls_clock_source = CONFIG_STM32WB_BLE_LS_CLK_SRC, - .conn_event_length = CONFIG_STM32WB_BLE_MAX_CONN_EVT_LENGTH, - .hse_startup = CONFIG_STM32WB_BLE_HSE_STARTUP, - .viterbi_enable = CONFIG_STM32WB_BLE_VITERBI, + .att_max_mtu_size = CONFIG_STM32_BLE_MAX_ATT_MTU, + .slave_sca = CONFIG_STM32_BLE_SLAVE_SCA, + .master_sca_range = CONFIG_STM32_BLE_MASTER_SCA, + .ls_clock_source = CONFIG_STM32_BLE_LS_CLK_SRC, + .conn_event_length = CONFIG_STM32_BLE_MAX_CONN_EVT_LENGTH, + .hse_startup = CONFIG_STM32_BLE_HSE_STARTUP, + .viterbi_enable = CONFIG_STM32_BLE_VITERBI, .options = STM32_BLE_INIT_OPTIONS, .hw_version = 0, - .max_initor_coc_num = CONFIG_STM32WB_BLE_MAX_INITOR_COC_NUM, - .tx_power_min = CONFIG_STM32WB_BLE_MIN_TX_POWER, - .tx_power_max = CONFIG_STM32WB_BLE_MAX_TX_POWER, + .max_initor_coc_num = CONFIG_STM32_BLE_MAX_INITOR_COC_NUM, + .tx_power_min = CONFIG_STM32_BLE_MIN_TX_POWER, + .tx_power_max = CONFIG_STM32_BLE_MAX_TX_POWER, .rx_model_config = STM32_BLE_RXMOD_AGC_RSSI }; diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c index d8674fd279c..2ba7cdd517d 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.c +++ b/arch/arm/src/stm32wb/stm32wb_dma.c @@ -42,19 +42,19 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32WB_DMAMUX -# error "Configuration error, CONFIG_STM32WB_DMAMUX not defined!" +#ifndef CONFIG_STM32_DMAMUX +# error "Configuration error, CONFIG_STM32_DMAMUX not defined!" #endif #define DMAMUX_NUM 1 #define DMA_CONTROLLERS 2 -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NCHAN 7 #else # define DMA1_NCHAN 0 #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NCHAN 7 #else # define DMA2_NCHAN 0 @@ -159,7 +159,7 @@ struct stm32_dma_ops_s * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32_dma12_disable(DMA_CHANNEL dmachan); static int stm32_dma12_interrupt(int irq, void *context, void *arg); static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, @@ -205,7 +205,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { @@ -225,7 +225,7 @@ static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { @@ -286,7 +286,7 @@ static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { @@ -346,7 +346,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { @@ -564,7 +564,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, * DMA controller functions ****************************************************************************/ -#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32_dma12_disable @@ -616,14 +616,14 @@ static int stm32_dma12_interrupt(int irq, void *context, void *arg) if (0) { } -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { channel = irq - STM32_IRQ_DMA2CH1; @@ -689,7 +689,7 @@ static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, " ntransfers: %zd ccr: %08" PRIx32 "\n", paddr, maddr, ntransfers, ccr); -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); #endif @@ -878,7 +878,7 @@ static void stm32_dma12_dump(DMA_HANDLE handle, } #endif -#endif /* CONFIG_STM32WB_DMA1 || CONFIG_STM32WB_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Name: stm32_dmamux_sample @@ -1270,7 +1270,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; diff --git a/arch/arm/src/stm32wb/stm32wb_dma.h b/arch/arm/src/stm32wb/stm32wb_dma.h index baf212c4dbd..b8ac1d99217 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/stm32wb_dma.h @@ -78,7 +78,7 @@ struct stm32_dmaregs_s uint32_t cndtr; /* Channel Count Register; determines number of transfers */ uint32_t cpar; /* Channel Peripheral Address Register; determines start */ uint32_t cmar; /* Channel Memory Address Register; determines start */ -#ifndef CONFIG_STM32WB_HAVE_DMAMUX +#ifndef CONFIG_STM32_HAVE_DMAMUX uint32_t cselr; /* Channel Selection Register; chooses peripheral bound */ #else struct @@ -233,7 +233,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) diff --git a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c index 2b33764174a..6d3a9fddd60 100644 --- a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c +++ b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c @@ -52,10 +52,10 @@ static const char g_portchar[STM32_NPORTS] = { 'A', 'B', 'C', -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) 'D', #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) 'E', #endif 'H' diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 4d6432f6af5..4b1baf8a7ae 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -48,7 +48,7 @@ #include "stm32wb_waste.h" #include "stm32wb_flash.h" -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c index 570f3b3f2f1..c308a611db3 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ b/arch/arm/src/stm32wb/stm32wb_freerun.c @@ -37,7 +37,7 @@ #include "stm32wb_freerun.h" -#ifdef CONFIG_STM32WB_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Private Functions @@ -297,4 +297,4 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) return OK; } -#endif /* CONFIG_STM32WB_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h index 9f1a86dc817..ae4dd49ba9c 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ b/arch/arm/src/stm32wb/stm32wb_freerun.h @@ -35,7 +35,7 @@ #include "stm32wb_tim.h" -#ifdef CONFIG_STM32WB_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Public Types @@ -158,5 +158,5 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); } #endif -#endif /* CONFIG_STM32WB_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.h b/arch/arm/src/stm32wb/stm32wb_gpio.h index 1103b50cbc2..3e2a3f73e1e 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/stm32wb_gpio.h @@ -44,9 +44,9 @@ * Pre-Processor Declarations ****************************************************************************/ -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) && defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define STM32_NPORTS 6 -#elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#elif defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define STM32_NPORTS 5 #else # define STM32_NPORTS 4 @@ -195,11 +195,11 @@ # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) && defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ # define GPIO_PORTH (5 << GPIO_PORT_SHIFT) /* GPIOH */ -#elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#elif defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define GPIO_PORTE (3 << GPIO_PORT_SHIFT) /* GPIOE */ # define GPIO_PORTH (4 << GPIO_PORT_SHIFT) /* GPIOH */ #else diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index 85d42440330..50fdb01b3fd 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -111,26 +111,26 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32WB_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32WB_I2C1 - * CONFIG_STM32WB_I2C3 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C3 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32WB_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32WB_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32WB_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32WB_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32WB_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -190,7 +190,7 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32WB_I2C1) || defined(CONFIG_STM32WB_I2C3) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C3) /**************************************************************************** * Pre-processor Definitions @@ -202,25 +202,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32WB_I2CTIMEOSEC) && !defined(CONFIG_STM32WB_I2CTIMEOMS) -# define CONFIG_STM32WB_I2CTIMEOSEC 0 -# define CONFIG_STM32WB_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32WB_I2CTIMEOSEC) -# define CONFIG_STM32WB_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32WB_I2CTIMEOMS) -# define CONFIG_STM32WB_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32WB_I2CTIMEOTICKS -# define CONFIG_STM32WB_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32WB_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32WB_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32WB_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert an I2C pin to a GPIO output */ @@ -383,9 +383,9 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32WB_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline @@ -429,7 +429,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -465,7 +465,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -598,7 +598,7 @@ void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -615,7 +615,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -673,12 +673,12 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32WB_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -717,10 +717,10 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32WB_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -863,10 +863,10 @@ void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32WB_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2561,12 +2561,12 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; @@ -2651,4 +2651,4 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) kmm_free(dev); return OK; } -#endif /* CONFIG_STM32WB_I2C1 || CONFIG_STM32WB_I2C3 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.h b/arch/arm/src/stm32wb/stm32wb_i2c.h index adb5a001e6e..299eb53b686 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/stm32wb_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO -# if CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32WB_I2C_DYNTIMEO because of CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32wb/stm32wb_idle.c b/arch/arm/src/stm32wb/stm32wb_idle.c index 0a0e6d1ad06..4001f8210e5 100644 --- a/arch/arm/src/stm32wb/stm32wb_idle.c +++ b/arch/arm/src/stm32wb/stm32wb_idle.c @@ -184,7 +184,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); __asm__ volatile ("wfi"); END_IDLE(); diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index f92be7547f5..b066a6a804d 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -64,7 +64,7 @@ #define STM32_MBOX_ACLPKT_BUF_SIZE 264 #define STM32_MBOX_RX_BUF_SIZE \ - (CONFIG_STM32WB_MBOX_RX_EVT_QUEUE_LEN * STM32_MBOX_CMDPKT_BUF_SIZE) + (CONFIG_STM32_MBOX_RX_EVT_QUEUE_LEN * STM32_MBOX_CMDPKT_BUF_SIZE) /**************************************************************************** * Private Types @@ -150,18 +150,18 @@ struct stm32_mbox_shared_buffer_s aligned_data(4) struct stm32_mbox_mem_manager_table_s mm_table; aligned_data(4) stm32_mbox_list_t evtfree_buffer; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE aligned_data(4) stm32_mbox_list_t ble_evt_queue; #endif aligned_data(4) stm32_mbox_list_t sys_evt_queue; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE aligned_data(4) uint8_t ble_cs_buffer[STM32_MBOX_CS_BUF_SIZE]; #endif aligned_data(4) uint8_t evtpool_buffer[STM32_MBOX_RX_BUF_SIZE]; aligned_data(4) uint8_t sys_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; aligned_data(4) uint8_t sys_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE aligned_data(4) uint8_t ble_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; aligned_data(4) uint8_t ble_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; aligned_data(4) uint8_t ble_acl_buffer[STM32_MBOX_ACLPKT_BUF_SIZE]; @@ -204,12 +204,12 @@ static struct work_s g_tx_cmd_work; static stm32_mbox_list_t g_rx_evt_queue; static stm32_mbox_list_t g_tx_evtfree_queue; -static uint8_t g_free_buffers[CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN] +static uint8_t g_free_buffers[CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN] [STM32_MBOX_CMDPKT_BUF_SIZE]; static stm32_mbox_list_t g_free_buffers_pool; static struct stm32_mbox_channel_s g_syscmd_channel; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE static struct stm32_mbox_channel_s g_blecmd_channel; static struct stm32_mbox_channel_s g_bleacl_channel; #endif @@ -243,7 +243,7 @@ static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_SYSEVT_CHANNEL); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Pull events from BLE channel into processing queue */ @@ -363,7 +363,7 @@ static void stm32_mbox_txworker(void *arg) handled = stm32_mbox_txnext(&g_syscmd_channel); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE if (!stm32_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) { handled |= stm32_mbox_txnext(&g_blecmd_channel); @@ -628,7 +628,7 @@ void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) stm32_mbox_list_initialize(&stm32_mbox_shared.sys_evt_queue); stm32_mbox_list_initialize(&stm32_mbox_shared.evtfree_buffer); -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE stm32_mbox_list_initialize(&stm32_mbox_shared.ble_evt_queue); #endif @@ -648,12 +648,12 @@ void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) .evtfree_buffer; stm32_mbox_mm_table.sys_spare_buffer = &stm32_mbox_shared .sys_spare_buffer; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE stm32_mbox_mm_table.ble_spare_buffer = &stm32_mbox_shared .ble_spare_buffer; #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE stm32_mbox_ble_table.cmd_buffer = &stm32_mbox_shared.ble_cmd_buffer; stm32_mbox_ble_table.acl_buffer = &stm32_mbox_shared.ble_acl_buffer; stm32_mbox_ble_table.cs_buffer = &stm32_mbox_shared.ble_cs_buffer; @@ -667,7 +667,7 @@ void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) stm32_mbox_shared.sys_cmd_buffer; stm32_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Init BLE command channel data */ g_blecmd_channel.ch_num = STM32_MBOX_BLECMD_CHANNEL; @@ -689,7 +689,7 @@ void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) stm32_mbox_list_initialize(&g_tx_evtfree_queue); stm32_mbox_list_initialize(&g_free_buffers_pool); - for (i = 0; i < CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN; i++) + for (i = 0; i < CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN; i++) { stm32_mbox_list_add_tail(&g_free_buffers_pool, (stm32_mbox_list_t *)g_free_buffers[i]); @@ -751,7 +751,7 @@ int stm32_mbox_syscmd(void *data, size_t len) data, len); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /**************************************************************************** * Name: stm32_mbox_blecmd * @@ -812,4 +812,4 @@ void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params) stm32_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); } -#endif /* CONFIG_STM32WB_BLE */ +#endif /* CONFIG_STM32_BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c index 9666c714bda..80e63c4b4e9 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.c @@ -39,7 +39,7 @@ #include "stm32wb_oneshot.h" -#ifdef CONFIG_STM32WB_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes @@ -51,7 +51,7 @@ static int stm32_oneshot_handler(int irq, void *context, void *arg); * Private Data ****************************************************************************/ -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions @@ -117,19 +117,19 @@ static int stm32_oneshot_handler(int irq, void *context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32WB_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32WB_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -456,4 +456,4 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32WB_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h index d84e8f15b1c..9b02e37ca1c 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.h @@ -36,22 +36,22 @@ #include "stm32wb_tim.h" -#ifdef CONFIG_STM32WB_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32WB_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32WB_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32WB_ONESHOT_MAXTIMERS -# define CONFIG_STM32WB_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32WB_ONESHOT_MAXTIMERS -# define CONFIG_STM32WB_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -75,7 +75,7 @@ typedef void (*oneshot_handler_t)(void *arg); struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ @@ -194,5 +194,5 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32WB_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index 5a7bb4f22ba..d7dd502e49b 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -61,7 +61,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32WB_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -150,31 +150,31 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32WB_DMAMUX +#ifdef CONFIG_STM32_DMAMUX /* DMAMUX 1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32WB_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32WB_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; @@ -204,15 +204,15 @@ static inline void rcc_enableahb2(void) /* Enable GPIO ports A-E, H */ regval |= (RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) | RCC_AHB2ENR_GPIODEN #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) | RCC_AHB2ENR_GPIOEEN #endif | RCC_AHB2ENR_GPIOHEN); -#if defined(CONFIG_STM32WB_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; @@ -245,13 +245,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32WB_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif -#ifdef CONFIG_STM32WB_PKA +#ifdef CONFIG_STM32_PKA /* Public key accelerator clock enable */ regval |= RCC_AHB3ENR_PKAEN; @@ -263,25 +263,25 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_AES2EN; #endif -#ifdef CONFIG_STM32WB_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB3ENR_RNGEN; #endif -#ifdef CONFIG_STM32WB_HSEM +#ifdef CONFIG_STM32_HSEM /* Hardware semaphore clock enable */ regval |= RCC_AHB3ENR_HSEMEN; #endif -#ifdef CONFIG_STM32WB_IPCC +#ifdef CONFIG_STM32_IPCC /* Inter-processor communication controller clock enable */ regval |= RCC_AHB3ENR_IPCCEN; #endif -#ifdef CONFIG_STM32WB_FLASH +#ifdef CONFIG_STM32_FLASH /* Flash memory interface clock enable */ regval |= RCC_AHB3ENR_FLASHEN; @@ -308,43 +308,43 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32WB_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#if defined(CONFIG_STM32WB_RTC) +#if defined(CONFIG_STM32_RTC) /* RTC APB clock enable */ regval |= RCC_APB1ENR1_RTCAPBEN; #endif -#if defined(CONFIG_STM32WB_WWDG) +#if defined(CONFIG_STM32_WWDG) /* Window watchdog clock enable */ regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; @@ -359,13 +359,13 @@ static inline void rcc_enableapb1(void) } #endif -#if defined(CONFIG_STM32WB_USB) +#if defined(CONFIG_STM32_USB) /* USB clock enable */ regval |= RCC_APB1ENR1_USBEN; #endif -#ifdef CONFIG_STM32WB_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; @@ -377,13 +377,13 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32WB_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32WB_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; @@ -410,37 +410,37 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32WB_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32WB_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; @@ -469,13 +469,13 @@ static inline void rcc_enableccip(void) regval = getreg32(STM32_RCC_CCIPR); #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI16; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; @@ -493,7 +493,7 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_CLK48SEL_HSI48; #endif -#if defined(CONFIG_STM32WB_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; @@ -513,7 +513,7 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -713,7 +713,7 @@ static void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32WB_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ regval = getreg32(STM32_RCC_PLLSAI1CFG); @@ -764,7 +764,7 @@ static void stm32_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache and data cache */ -#ifdef CONFIG_STM32WB_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval |= FLASH_ACR_PRFTEN; #else regval &= ~FLASH_ACR_PRFTEN; @@ -786,7 +786,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32WB_IWDG) || defined(CONFIG_STM32WB_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enable_lsi(); @@ -871,7 +871,7 @@ static inline void rcc_enableperipherals(void) * ****************************************************************************/ -#if defined(CONFIG_STM32WB_PWR) && defined(CONFIG_STM32WB_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -930,7 +930,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -952,7 +952,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); -#if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -987,7 +987,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -1002,7 +1002,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index a8cd788caeb..438138e0de7 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -29,6 +29,7 @@ #include +#include "arm_internal.h" #include "chip.h" #include "hardware/stm32wb_rcc.h" @@ -115,7 +116,7 @@ static inline void stm32_mcoconfig(uint32_t source, uint32_t divider) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -138,7 +139,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -156,7 +157,7 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index 1e56d0e3cd8..8a830216564 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -35,16 +35,16 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -86,11 +86,11 @@ void stm32_rcc_enable_lse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif @@ -103,18 +103,18 @@ void stm32_rcc_enable_lse(void) stm32_waste(); } -#if defined(CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 # error "STM32WB only allows lowering LSE drive capability to zero" # endif /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.c b/arch/arm/src/stm32wb/stm32wb_rtc.c index 2b849fd12c2..ed057295c69 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc.c @@ -43,7 +43,7 @@ #include "stm32wb_rtc.h" #include "stm32wb_exti.h" -#ifdef CONFIG_STM32WB_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -64,8 +64,8 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32WB_PWR -# error "CONFIG_STM32WB_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ @@ -860,13 +860,13 @@ int up_rtc_initialize(void) stm32_pwr_enablebkp(true); -#if defined(CONFIG_STM32WB_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); -#elif defined(CONFIG_STM32WB_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else @@ -909,7 +909,7 @@ int up_rtc_initialize(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32WB_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* The HSE is divided by 32 prior to the prescaler we set here. * 1953 * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC @@ -922,7 +922,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), STM32_RTC_PRER); -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) */ @@ -930,7 +930,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), STM32_RTC_PRER); -#else /* defined(CONFIG_STM32WB_RTC_LSECLOCK) */ +#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | @@ -1012,7 +1012,7 @@ int up_rtc_initialize(void) int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; #endif uint32_t dr; @@ -1031,7 +1031,7 @@ int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1089,7 +1089,7 @@ int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, * of nsec has been provided to receive the sub-second value. */ -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS if (nsec) { uint32_t prediv_s; @@ -1169,8 +1169,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32WB_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1655,11 +1655,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32WB_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32WB_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1830,4 +1830,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32WB_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index 65a8edf5387..500d5dfcd4d 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -43,21 +43,21 @@ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed * of 16384 Hz */ -#if !defined(CONFIG_STM32WB_RTC_MAGIC) -# define CONFIG_STM32WB_RTC_MAGIC (0xfacefeee) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeee) #endif -#if !defined(CONFIG_STM32WB_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32WB_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32WB_RTC_MAGIC_REG) -# define CONFIG_STM32WB_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32WB_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32WB_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32WB_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -158,7 +158,7 @@ bool stm32_rtc_is_initialized(void); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index 78bd2aaef33..a67006f7cf9 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -87,11 +87,11 @@ * The buffer size should be an even multiple of ARMV7M_DCACHE_LINESIZE. */ -# if !defined(CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -123,8 +123,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32WB_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32WB_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -141,7 +141,7 @@ * See stm32_serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -335,7 +335,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -343,7 +343,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -353,7 +353,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32WB LPUART1 port. */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -415,7 +415,7 @@ static struct stm32_serial_s g_lpuart1priv = /* This describes the state of the STM32WB USART1 port. */ -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -480,10 +480,10 @@ static struct stm32_serial_s g_usart1priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif }; @@ -727,7 +727,7 @@ static void stm32_serial_setbaud_usart(struct stm32_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static void stm32_serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -771,7 +771,7 @@ static void stm32_serial_setformat(struct uart_dev_s *dev) /* Set baud rate */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER if (priv->usartbase == STM32_LPUART1_BASE) { stm32_serial_setbaud_lpuart(priv); @@ -841,7 +841,7 @@ static void stm32_serial_setformat(struct uart_dev_s *dev) regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1044,13 +1044,13 @@ static void stm32_serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; @@ -1118,7 +1118,7 @@ static int stm32_serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32WB_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1463,8 +1463,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32WB_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32WB_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1608,7 +1608,7 @@ static int stm32_serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WB_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1677,7 +1677,7 @@ static int stm32_serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WB_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -1728,7 +1728,7 @@ static int stm32_serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WB_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -1865,8 +1865,8 @@ static int stm32_serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32WB_USART_BREAKS -# ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2093,7 +2093,7 @@ static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2444,7 +2444,7 @@ static void stm32_serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2767,7 +2767,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32WB_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -2796,7 +2796,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32WB_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 84e96d003b6..515f98920ab 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -80,7 +80,7 @@ #include -#if defined(CONFIG_STM32WB_SPI1) || defined(CONFIG_STM32WB_SPI2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) /**************************************************************************** * Pre-processor Definitions @@ -90,19 +90,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32WB_SPI_INTERRUPTS) && defined(CONFIG_STM32WB_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -136,10 +136,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -183,7 +183,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -243,7 +243,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -283,10 +283,10 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMAMAP_SPI1_RX, @@ -301,7 +301,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -341,10 +341,10 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -575,7 +575,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -608,7 +608,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -641,7 +641,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -656,7 +656,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -671,7 +671,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -691,7 +691,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -711,7 +711,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -761,7 +761,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -812,7 +812,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -828,7 +828,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1290,8 +1290,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32WB_SPI_DMA) || defined(CONFIG_STM32WB_DMACAPABLE) -#if !defined(CONFIG_STM32WB_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1374,7 +1374,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32WB_SPI_DMA || CONFIG_STM32WB_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1397,14 +1397,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer != NULL && !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && @@ -1466,7 +1466,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32WB_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1487,7 +1487,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1688,7 +1688,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If @@ -1742,7 +1742,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1767,7 +1767,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1800,4 +1800,4 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32WB_SPI1 || CONFIG_STM32WB_SPI2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/arch/arm/src/stm32wb/stm32wb_spi.h b/arch/arm/src/stm32wb/stm32wb_spi.h index 79fb78f1dee..59e20e91e18 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/stm32wb_spi.h @@ -104,14 +104,14 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); @@ -139,12 +139,12 @@ int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_start.c b/arch/arm/src/stm32wb/stm32wb_start.c index eade4167de7..6e80fa7f6d8 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.c +++ b/arch/arm/src/stm32wb/stm32wb_start.c @@ -63,14 +63,14 @@ #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) -# define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2A_HEAP +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_END (SRAM2A_START + CONFIG_STM32_SRAM2A_USER_SIZE) #endif -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP # define SRAM2B_START STM32_SRAM2B_BASE -# define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) +# define SRAM2B_END (SRAM2B_START + CONFIG_STM32_SRAM2B_USER_SIZE) #endif /* g_idle_topstack: _sbss is the start of the BSS region as defined by the @@ -148,14 +148,14 @@ void __start(void) * using this memory for, say, additional heap space, then this is handy. */ -#ifdef CONFIG_STM32WB_SRAM2A_INIT +#ifdef CONFIG_STM32_SRAM2A_INIT for (dest = (uint32_t *)SRAM2A_START; dest < (uint32_t *)SRAM2A_END; ) { *dest++ = 0; } #endif -#ifdef CONFIG_STM32WB_SRAM2B_INIT +#ifdef CONFIG_STM32_SRAM2B_INIT for (dest = (uint32_t *)SRAM2B_START; dest < (uint32_t *)SRAM2B_END; ) { *dest++ = 0; @@ -165,7 +165,7 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ stm32_clockconfig(); -#ifdef CONFIG_STM32WB_IPCC +#ifdef CONFIG_STM32_IPCC stm32_ipccreset(); #endif arm_fpuconfig(); diff --git a/arch/arm/src/stm32wb/stm32wb_tickless.c b/arch/arm/src/stm32wb/stm32wb_tickless.c index 7d99e9082c9..a8ae84dc54e 100644 --- a/arch/arm/src/stm32wb/stm32wb_tickless.c +++ b/arch/arm/src/stm32wb/stm32wb_tickless.c @@ -84,8 +84,8 @@ #undef HAVE_32BIT_TICKLESS -#ifdef CONFIG_STM32WB_TICKLESS_TIMER -# if CONFIG_STM32WB_TICKLESS_TIMER == 2 +#ifdef CONFIG_STM32_TICKLESS_TIMER +# if CONFIG_STM32_TICKLESS_TIMER == 2 # define HAVE_32BIT_TICKLESS 1 # endif #else @@ -360,27 +360,27 @@ static int stm32_tickless_handler(int irq, void *context, void *arg) void up_timer_initialize(void) { - switch (CONFIG_STM32WB_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; break; @@ -393,8 +393,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32WB_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32WB_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c index 2e7b56cf817..acccf75792a 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ b/arch/arm/src/stm32wb/stm32wb_tim.c @@ -67,48 +67,48 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32WB_TIM1_PWM) || defined (CONFIG_STM32WB_TIM1_ADC) || \ - defined(CONFIG_STM32WB_TIM1_QE) -# undef CONFIG_STM32WB_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32WB_TIM2_PWM) || defined (CONFIG_STM32WB_TIM2_ADC) || \ - defined(CONFIG_STM32WB_TIM2_QE) -# undef CONFIG_STM32WB_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32WB_TIM16_PWM) || defined (CONFIG_STM32WB_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32WB_TIM16_ADC) || \ defined(CONFIG_STM32WB_TIM16_QE) -# undef CONFIG_STM32WB_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32WB_TIM17_PWM) || defined (CONFIG_STM32WB_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32WB_TIM17_ADC) || \ defined(CONFIG_STM32WB_TIM17_QE) -# undef CONFIG_STM32WB_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32WB_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) || defined(GPIO_TIM16_CH2OUT) || \ defined(GPIO_TIM16_CH3OUT) || defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) || defined(GPIO_TIM17_CH2OUT) || \ defined(GPIO_TIM17_CH3OUT) || defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -119,8 +119,8 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) || \ - defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -221,7 +221,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .dump_regs = stm32_tim_dumpregs, }; -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -229,7 +229,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -238,7 +238,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -247,7 +247,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -465,17 +465,17 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* The modes DOWN and UPDOWN are not supported on TIM16 and TIM17. */ -#if defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) { -#if defined(CONFIG_STM32WB_TIM16) +#if defined(CONFIG_STM32_TIM16) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM16_BASE) { return -EINVAL; } #endif -#if defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM17) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM17_BASE) { return -EINVAL; @@ -496,7 +496,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, val = GTIM_CR1_CEN | GTIM_CR1_ARPE; break; -#if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) case STM32_TIM_MODE_DOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_DIR; break; @@ -522,7 +522,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, stm32_tim_reload_counter(dev); stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 /* Advanced registers require Main Output Enable */ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE) @@ -563,25 +563,25 @@ static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -680,25 +680,25 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -753,25 +753,25 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -818,7 +818,7 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) /* TIM2 is a 32-bit timer. */ -#if defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM2) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return counter; @@ -836,7 +836,7 @@ static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* Only TIM2 is a 32-bit timer. */ -#if defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM2) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return 32; @@ -913,7 +913,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -946,7 +946,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -979,7 +979,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -994,7 +994,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1092,25 +1092,25 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1192,28 +1192,28 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1251,25 +1251,25 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1286,4 +1286,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) return OK; } -#endif /* defined(CONFIG_STM32WB_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c index 37e35b0f985..38e8db5b4aa 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c @@ -37,8 +37,8 @@ #include "stm32wb_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) || \ - defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -103,7 +103,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -111,7 +111,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -119,7 +119,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -127,7 +127,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -426,25 +426,25 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index 7a9f118a595..ea28a500667 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -56,9 +56,9 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32WB_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) @@ -121,7 +121,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; diff --git a/arch/arm/src/stm32wb/stm32wb_uart.h b/arch/arm/src/stm32wb/stm32wb_uart.h index 2fd4f3019d1..8733ba88da4 100644 --- a/arch/arm/src/stm32wb/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/stm32wb_uart.h @@ -39,28 +39,28 @@ /* Sanity checks */ -#if !defined(CONFIG_STM32WB_LPUART1) -# undef CONFIG_STM32WB_LPUART1_SERIALDRIVER -# undef CONFIG_STM32WB_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WB_USART1) -# undef CONFIG_STM32WB_USART1_SERIALDRIVER -# undef CONFIG_STM32WB_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32WB_LPUART1) || defined(CONFIG_STM32WB_USART1) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WB_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WB_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 @@ -82,11 +82,11 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif @@ -109,9 +109,9 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32WB_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WB_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig b/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig index c127e72875f..d1a1619b32a 100644 --- a/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig +++ b/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="flipperzero" CONFIG_ARCH_BOARD_FLIPPERZERO=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -46,11 +47,11 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_ST7565_MIRROR_Y=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_SPI2=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c index 334cf54abbe..2f549b32aac 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c @@ -47,7 +47,7 @@ # include "stm32wb_rtc.h" #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE # include "stm32wb_blehci.h" #endif @@ -183,7 +183,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ stm32_blehci_initialize(); diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c index 9e4e5fd13be..fedf459ecee 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c @@ -85,7 +85,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { #ifdef CONFIG_LCD_ST7565 diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig index ff3325b96d8..cb0bc5bb913 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -41,11 +42,11 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32WB_BLE=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_BLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig index 7e9dcb33872..73b3510b415 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -46,11 +47,11 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SIG_EVTHREAD=y -CONFIG_STM32WB_BLE=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_BLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig index 0738f6cea58..cdd024ed73b 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -30,10 +31,10 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c index 140f2dbb255..ff849aff0db 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c @@ -47,7 +47,7 @@ # include "stm32wb_rtc.h" #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE # include "stm32wb_blehci.h" #endif @@ -164,7 +164,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ stm32_blehci_initialize();