From 4d5789dfddb1338a8c9b31e4c1f750f7c1956be5 Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Mon, 19 Aug 2013 15:03:14 -0600
Subject: [PATCH] SAMA5 OHCI+EHCI mostly cosmetic changes

---
 arch/arm/src/sama5/sam_clockconfig.c | 27 +++++++++++++++++++++++++--
 arch/arm/src/sama5/sam_ohci.c        |  9 +++------
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/arch/arm/src/sama5/sam_clockconfig.c b/arch/arm/src/sama5/sam_clockconfig.c
index f8ecdbd108f..0dc6884cdbc 100644
--- a/arch/arm/src/sama5/sam_clockconfig.c
+++ b/arch/arm/src/sama5/sam_clockconfig.c
@@ -343,14 +343,37 @@ static inline void sam_usbclockconfig(void)
    *      value and USB Full-speed accuracy.
    *   4) Enable the OHCI clocks, UHP bit in PMC_SCER register.
    *
-   * Steps 2 and 3 are done here.  1 and 2 are performed with the USB device
-   * driver is opened.
+   * Steps 2 and 3 are done here.  1 and 2 are performed with the OHCI
+   * driver is initialized.
    */
 
   putreg32(BOARD_OHCI_INPUT | BOARD_OHCI_DIVIDER << PMC_USB_USBDIV_SHIFT,
           SAM_PMC_USB);
 #endif
 
+#ifdef CONFIG_SAMA5_EHCI
+  /* For High-speed operations, the user has to perform the following:
+   *
+   *   1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
+   *      PMC_PCER register.
+   *   2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
+   *   3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
+   *   4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
+   *   5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
+   *   6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
+   *      register.
+   *   7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
+   *      PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
+   *      selected.
+   *   8) Enable OHCI clocks, UHP bit in PMC_SCER register.
+   *
+   * Steps 2 through 7 performed here.  1 and 8 are performed in the EHCI
+   * driver is initialized.
+   */
+
+#  warning Missing logic
+#endif
+
 #if 0 // #ifdef CONFIG_USBDEV
   uint32_t regval;
 
diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c
index 43e28029c9e..2c2fe658220 100644
--- a/arch/arm/src/sama5/sam_ohci.c
+++ b/arch/arm/src/sama5/sam_ohci.c
@@ -186,7 +186,7 @@ struct sam_eplist_s
   struct sam_gtd_s *tail;      /* Tail transfer descriptor (TD) */
 };
 
-/* This structure retins the state of one root hub port */
+/* This structure retains the state of one root hub port */
 
 struct sam_rhport_s
 {
@@ -2792,9 +2792,6 @@ static int sam_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
   struct sam_ed_s *ed;
   uint32_t dirpid;
   uint32_t regval;
-#if SAM_IOBUFFERS > 0
-  uint8_t *origbuf = NULL;
-#endif
   bool in;
   int ret;
 
@@ -3015,7 +3012,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
 
   /* Enable OHCI clocks */
 
-  regval = getreg32(SAM_PMC_SCER);
+  regval  = getreg32(SAM_PMC_SCER);
   regval |= PMC_UHP;
   putreg32(regval, SAM_PMC_SCER);
   irqrestore(flags);
@@ -3035,7 +3032,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
    * dedicated function
    */
 
-  udbg("Initializing Host Stack\n");
+  udbg("Initializing OHCI Stack\n");
 
   /* Initialize all the HCCA to 0 */