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SAMA5: Add file structure to support board-specific initialization of NOR flash

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This commit is contained in:
Gregory Nutt 2013-07-29 07:41:53 -06:00
parent 9a94a3707c
commit 4ba648aaae
9 changed files with 286 additions and 22 deletions
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4
ChangeLog
View file

@ -5212,3 +5212,7 @@
* configs/sama5d3x-ek/ostest/: This configuration has been modified
to run out NOR flash. More work is still needed to reconfigure the
SMC so the the NOR flash can work with the high clock (2013-7-28).
* arch/arm/src/sama5/sam_clockconfig.c/h and
configs/sama5d3x-ek/src/sam_norflash.c: Add a file structure that
will (eventually) support reconfiguration of NOR flash when NuttX
boots from NOR FLASH (2013-7-29).

64
arch/arm/src/armv7-a/arm_head.S
View file

@ -267,7 +267,7 @@ __start:
#ifndef CONFIG_IDENTITY_TEXTMAP
mksection r0, r4 /* r0=phys. base section */
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
ldr r1, .LCtextflags /* R1=.text section MMU flags */
add r3, r1, r0 /* r3=flags + base */
str r3, [r4, r0, lsr #18] /* identity mapping */
#endif
@ -319,7 +319,7 @@ __start:
#ifdef CONFIG_IDENTITY_TEXTMAP
mksection r0, r4 /* r0=phys. base section */
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
ldr r1, .LCtextflags /* R1=.text section MMU flags */
add r3, r1, r0 /* r3=flags + base */
#endif
@ -525,50 +525,66 @@ __start:
.type .LCvstart, %object
.LCvstart:
.long .Lvstart
.size .LCvstart, . -.LCvstart
#ifndef CONFIG_ARCH_ROMPGTABLE
.type .LCmmuflags, %object
.LCmmuflags:
.long MMU_MEMFLAGS /* MMU flags for memory sections */
.type .LCtextflags, %object
.LCtextflags:
#ifdef CONFIG_BOOT_RUNFROMFLASH
.long MMU_ROMFLAGS /* MMU flags text section in FLASH/ROM */
#else
.long MMU_MEMFLAGS /* MMU flags for text section in RAM */
#endif
.size .LCtextflags, . -.LCtextflags
#endif
.type .LCppgtable, %object
.LCppgtable:
.long PGTABLE_BASE_PADDR /* Physical start of page table */
.size .LCppgtable, . -.LCppgtable
#ifndef CONFIG_ARCH_ROMPGTABLE
.type .LCvpgtable, %object
.LCvpgtable:
.long PGTABLE_BASE_VADDR /* Virtual start of page table */
.size .LCvpgtable, . -.LCvpgtable
#endif
#ifdef CONFIG_PAGING
.type .Ltxtspan, %object
.Ltxtspan:
.long PG_L1_TEXT_PADDR /* Physical address in the L1 table */
.long PG_L2_TEXT_PBASE /* Physical address of the start of the L2 page table */
.long PG_TEXT_NVPAGES /* Total (virtual) text pages to be mapped */
.long PG_L2_TEXT_NPAGE1 /* The number of text pages in the first page table */
.long MMU_L1_TEXTFLAGS /* L1 MMU flags to use */
.size .Ltxtspan, . -.Ltxtspan
.type .Ltxtmap, %object
.Ltxtmap:
.long PG_L2_LOCKED_PADDR /* Physical address in the L2 table */
.long PG_LOCKED_PBASE /* Physical address of locked base memory */
.long CONFIG_PAGING_NLOCKED /* Number of pages in the locked region */
.long MMU_L2_TEXTFLAGS /* L2 MMU flags to use */
.size .Ltxtmap, . -.Ltxtmap
.type .Lptabspan, %object
.Lptabspan:
.long PG_L1_PGTABLE_PADDR /* Physical address in the L1 table */
.long PG_L2_PGTABLE_PBASE /* Physical address of the start of the L2 page table */
.long PG_PGTABLE_NPAGES /* Total mapped page table pages */
.long PG_L2_PGTABLE_NPAGE1 /* The number of text pages in the first page table */
.long MMU_L1_PGTABFLAGS /* L1 MMU flags to use */
.size .Lptabspan, . -.Lptabspan
.type .Lptabmap, %object
.Lptabmap:
.long PG_L2_PGTABLE_PADDR /* Physical address in the L2 table */
.long PGTABLE_BASE_PADDR /* Physical address of the page table memory */
.long PG_PGTABLE_NPAGES /* Total mapped page table pages */
.long MMU_L2_PGTABFLAGS /* L2 MMU flags to use */
.size .Lptabmap, . -.Lptabmap
#endif /* CONFIG_PAGING */
.size __start, .-__start
@ -583,6 +599,7 @@ __start:
.align 5
.local .Lvstart
.type .Lvstart, %function
.Lvstart:
/* Remove the temporary mapping (if one was made). The following assumes
@ -629,7 +646,7 @@ __start:
* We round NUTTX_TEXT_VADDR down to the nearest megabyte boundary.
*/
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
ldr r1, .LCtextflags /* R1=.text section MMU flags */
add r3, r3, r1 /* r3=flags + base */
add r0, r4, #(NUTTX_TEXT_VADDR & 0xfff00000) >> 18
@ -652,29 +669,21 @@ __start:
* paging of the .text region, then the RAM-based .data/.bss/heap section
* will still probably be located in a separate (virtual) address region.
*
* Here we have:
*
* R4 = The virtual address of the page table.
* R1 = MMU_MEMFLAGS
* Here we still have R4 = The virtual address of the page table.
*/
#ifdef CONFIG_BOOT_RUNFROMFLASH
/* Get the following values
*
* R3 = Physical address of the NuttX RAM space (aligned to a
* one megabyte addres boundary).
*/
/* Get R3 = Value of RAM L1 page table entry */
ldr r3, .LCnuttxpram /* r3=Aligned Nuttx RAM address (physical) */
ldr r1, .LCramflags /* R1=.bss/.data section MMU flags */
add r3, r3, r1 /* r3=flags + base */
/* Now setup the page tables for our normal mapped execution region.
/* Now setup the page tables for our normal mapped RAM region.
* We round NUTTX_RAM_VADDR down to the nearest megabyte boundary.
*/
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
add r0, r4, #(NUTTX_RAM_VADDR & 0xfff00000) >> 18
str r3, [r0], #4
@ -743,43 +752,60 @@ __start:
* end of memory. See g_idle_topstack below.
*/
.type .Linitparms, %object
.Linitparms:
.long _sbss
.long _ebss
.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
.size .Linitparms, . -.Linitparms
#if !defined(CONFIG_PAGING)
.type .LCnuttxptext, %object
.LCnuttxptext:
.long NUTTX_TEXT_PADDR & 0xfff00000
.size .LCnuttxptext, . -.LCnuttxptext
#ifdef CONFIG_BOOT_RUNFROMFLASH
.type .LCramflags, %object
.LCramflags:
.long MMU_MEMFLAGS /* MMU flags for RAM section */
.size .LCramflags, . -.LCramflags
.type .LCnuttxpram, %object
.LCnuttxpram:
.long NUTTX_RAM_PADDR & 0xfff00000
.size .LCnuttxpram, . -.LCnuttxpram
#endif
#endif
#ifdef CONFIG_PAGING
.type .Ldataspan, %object
.Ldataspan:
.long PG_L1_DATA_VADDR /* Virtual address in the L1 table */
.long PG_L2_DATA_PBASE /* Physical address of the start of the L2 page table */
.long PG_DATA_NPAGES /* Number of pages in the data region */
.long PG_L2_DATA_NPAGE1 /* The number of text pages in the first page table */
.long MMU_L1_DATAFLAGS /* L1 MMU flags to use */
.size .Ldataspan, . -.Ldataspan
.type .Ldatamap, %object
.Ldatamap:
.long PG_L2_DATA_VADDR /* Virtual address in the L2 table */
.long PG_DATA_PBASE /* Physical address of data memory */
.long PG_DATA_NPAGES /* Number of pages in the data region */
.long MMU_L2_DATAFLAGS /* L2 MMU flags to use */
.size .Ldatamap, . -.Ldatamap
#endif /* CONFIG_PAGING */
#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING)
.type .Ldatainit, %object
.Ldatainit:
.long _eronly /* Where .data defaults are stored in FLASH */
.long _sdata /* Where .data needs to reside in SDRAM */
.long _edata
.size .Ldatainit, . -.Ldatainit
#endif
.size .Lvstart, .-.Lvstart
@ -790,7 +816,7 @@ __start:
* above.
*/
.data
.section .rodata, "a"
.align 4
.globl g_idle_topstack
.type g_idle_topstack, object

74
arch/arm/src/sama5/chip/sama5d3x_memorymap.h
View file

@ -379,13 +379,85 @@
*/
#if defined(CONFIG_BOOT_RUNFROMFLASH)
/* Some sanity checks. If we are running from FLASH, then one of the
* external chip selects must be configured to boot from NOR flash.
* And, if so, then its size must agree with the configured size.
*/
#if defined(CONFIG_SAMA5_EBICS0) && defined(CONFIG_SAMA5_EBICS0_NOR) && \
defined (CONFIG_SAMA5_BOOT_CS0FLASH)
# if CONFIG_SAMA5_EBICS0_SIZE != CONFIG_FLASH_SIZE
# error CS0 FLASH size disagreement
# endif
# undef CONFIG_SAMA5_BOOT_CS1FLASH
# undef CONFIG_SAMA5_BOOT_CS2FLASH
# undef CONFIG_SAMA5_BOOT_CS3FLASH
#elif defined(CONFIG_SAMA5_EBICS1) && defined(CONFIG_SAMA5_EBICS1_NOR) && \
defined (CONFIG_SAMA5_BOOT_CS1FLASH)
# if CONFIG_SAMA5_EBICS1_SIZE != CONFIG_FLASH_SIZE
# error CS1 FLASH size disagreement
# endif
# undef CONFIG_SAMA5_BOOT_CS0FLASH
# undef CONFIG_SAMA5_BOOT_CS2FLASH
# undef CONFIG_SAMA5_BOOT_CS3FLASH
#elif defined(CONFIG_SAMA5_EBICS2) && defined(CONFIG_SAMA5_EBICS2_NOR) && \
defined (CONFIG_SAMA5_BOOT_CS2FLASH)
# if CONFIG_SAMA2_EBICS0_SIZE != CONFIG_FLASH_SIZE
# error CS2 FLASH size disagreement
# endif
# undef CONFIG_SAMA5_BOOT_CS0FLASH
# undef CONFIG_SAMA5_BOOT_CS1FLASH
# undef CONFIG_SAMA5_BOOT_CS3FLASH
#elif defined(CONFIG_SAMA5_EBICS3) && defined(CONFIG_SAMA5_EBICS3_NOR) && \
defined (CONFIG_SAMA5_BOOT_CS3FLASH)
# if CONFIG_SAMA5_EBICS3_SIZE != CONFIG_FLASH_SIZE
# error CS3 FLASH size disagreement
# endif
# undef CONFIG_SAMA5_BOOT_CS0FLASH
# undef CONFIG_SAMA5_BOOT_CS1FLASH
# undef CONFIG_SAMA5_BOOT_CS2FLASH
#else
# error CONFIG_BOOT_RUNFROMFLASH=y, but no bootable NOR flash defined
# undef CONFIG_SAMA5_BOOT_CS0FLASH
# undef CONFIG_SAMA5_BOOT_CS1FLASH
# undef CONFIG_SAMA5_BOOT_CS2FLASH
# undef CONFIG_SAMA5_BOOT_CS3FLASH
#endif
/* Set up the NOR FLASH region as the NUTTX .text region */
# define NUTTX_TEXT_VADDR (CONFIG_FLASH_VSTART & 0xfff00000)
# define NUTTX_TEXT_PADDR (CONFIG_FLASH_START & 0xfff00000)
# define NUTTX_TEXT_SIZE (CONFIG_FLASH_END - NUTTX_TEXT_VADDR)
/* In the default configuration, the primary RAM use for .bss and .data
* is the internal SRAM.
*/
# define NUTTX_RAM_VADDR (CONFIG_RAM_VSTART & 0xfff00000)
# define NUTTX_RAM_PADDR (CONFIG_RAM_START & 0xfff00000)
# define NUTTX_RAM_SIZE (CONFIG_RAM_END - NUTTX_RAM_PADDR)
#else /* Running from some kind of RAM */
#else
/* Otherwise we are running from some kind of RAM (ISRAM or SDRAM).
* Setup the RAM region as the NUTTX .txt, .bss, and .data region.
*/
# define NUTTX_TEXT_VADDR (CONFIG_RAM_VSTART & 0xfff00000)
# define NUTTX_TEXT_PADDR (CONFIG_RAM_START & 0xfff00000)
# define NUTTX_TEXT_SIZE (CONFIG_RAM_END - NUTTX_TEXT_VADDR)

9
arch/arm/src/sama5/sam_clockconfig.c
View file

@ -452,8 +452,15 @@ void sam_clockconfig(void)
* - Program and Start the PLL
* - Switch the system clock to the new value
*/
#error Missing logic
/* Enable the 32768 Hz oscillator */
/* REVISIT! */
/* Reprogram the SMC setup, cycle, hold, mode timing registers for EBI
* CS0, to adapt them to the new clock.
*/
board_norflash_config();
config = true;
}
#endif

41
arch/arm/src/sama5/sam_clockconfig.h
View file

@ -85,6 +85,47 @@ extern "C"
void sam_clockconfig(void);
/****************************************************************************
* Name: board_norflash_config
*
* Description:
* If CONFIG_SAMA5_BOOT_CS0FLASH, then the system is boot directly off
* CS0 NOR FLASH. In this case, we assume that we get here from the
* primary boot loader under these conditions:
*
* "If BMS signal is tied to 0, BMS_BIT is read at 1. The ROM Code
* allows execution of the code contained into the memory connected to
* Chip Select 0 of the External Bus Interface.
*
* "To achieve that, the following sequence is preformed by the ROM
* Code:
*
* - The main clock is the on-chip 12 MHz RC oscillator,
* - The Static Memory Controller is configured with timing allowing
* code execution inCS0 external memory at 12 MHz
* - AXI matrix is configured to remap EBI CS0 address at 0x0
* - 0x0 is loaded in the Program Counter register
*
* "The user software in the external memory must perform the next
* operation in order to complete the clocks and SMC timings
* configuration to run at a higher clock frequency:
*
* - Enable the 32768 Hz oscillator if best accuracy is needed
* - Reprogram the SMC setup, cycle, hold, mode timing registers
* for EBI CS0, to adapt them to the new clock
* - Program the PMC (Main Oscillator Enable or Bypass mode)
* - Program and Start the PLL
* - Switch the system clock to the new value"
*
* This function provides the board-specific implementation of the logic
* to reprogram the SMC.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_BOOT_CS0FLASH
void board_norflash_config(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}

8
configs/sama5d3x-ek/README.txt
View file

@ -729,6 +729,14 @@ Configurations
CONFIG_SAMA5_EBICS0_SIZE=134217728 : Memory size is 128KB
CONFIG_SAMA5_EBICS0_NOR=y : Memory type is NOR FLASH
CONFIG_FLASH_START=0x10000000 : Physical FLASH start address
CONFIG_FLASH_VSTART=0x10000000 : Virtual FLASH start address
CONFIG_FLASH_SIZE=134217728 : FLASH size (again)
CONFIG_RAM_START=0x00300400 : Data stored after page table
CONFIG_RAM_VSTART=0x00300400
CONFIG_RAM_SIZE=114688 : Available size of 128KB - 16KB for page table
NOTE: In order to boot in this configuration, you need to close the
BMS jumper.

2
configs/sama5d3x-ek/scripts/norflash.ld
View file

@ -46,7 +46,7 @@
MEMORY
{
norflash (W!RX) : ORIGIN = 0x10000000, LENGTH = 128M
isram (WRX!) : ORIGIN = 0x00304000, LENGTH = 128K - 16K
isram (WR) : ORIGIN = 0x00304000, LENGTH = 128K - 16K
}
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")

4
configs/sama5d3x-ek/src/Makefile
View file

@ -46,6 +46,10 @@ ifeq ($(CONFIG_HAVE_CXX),y)
CSRCS += sam_cxxinitialize.c
endif
ifeq ($(CONFIG_SAMA5_BOOT_CS0FLASH),y)
CSRCS += sam_norflash.c
endif
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += sam_autoleds.c
else

102
configs/sama5d3x-ek/src/sam_norflash.c Normal file
View file

@ -0,0 +1,102 @@
/************************************************************************************
* configs/sama5d3x-ek/src/sam_norflash.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include "sama5d3x-ek.h"
#ifdef CONFIG_SAMA5_BOOT_CS0FLASH
/************************************************************************************
* Definitions
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: board_norflash_config
*
* Description:
* If CONFIG_SAMA5_BOOT_CS0FLASH, then the system is boot directly off
* CS0 NOR FLASH. In this case, we assume that we get here from the
* primary boot loader under these conditions:
*
* "If BMS signal is tied to 0, BMS_BIT is read at 1. The ROM Code
* allows execution of the code contained into the memory connected to
* Chip Select 0 of the External Bus Interface.
*
* "To achieve that, the following sequence is preformed by the ROM
* Code:
*
* - The main clock is the on-chip 12 MHz RC oscillator,
* - The Static Memory Controller is configured with timing allowing
* code execution inCS0 external memory at 12 MHz
* - AXI matrix is configured to remap EBI CS0 address at 0x0
* - 0x0 is loaded in the Program Counter register
*
* "The user software in the external memory must perform the next
* operation in order to complete the clocks and SMC timings
* configuration to run at a higher clock frequency:
*
* - Enable the 32768 Hz oscillator if best accuracy is needed
* - Reprogram the SMC setup, cycle, hold, mode timing registers
* for EBI CS0, to adapt them to the new clock
* - Program the PMC (Main Oscillator Enable or Bypass mode)
* - Program and Start the PLL
* - Switch the system clock to the new value"
*
* This function provides the board-specific implementation of the logic
* to reprogram the SMC.
*
****************************************************************************/
void board_norflash_config(void)
{
#warning Missing logic
}
#endif /* CONFIG_SAMA5_BOOT_CS0FLASH */