From 48a541900546c918e470fc27f2ebea93125b031d Mon Sep 17 00:00:00 2001 From: chenzhijia Date: Thu, 11 Jul 2024 11:33:11 +0800 Subject: [PATCH] drivers/coresight:Add caps member to coresight_desc_s for etr Add caps member to coresight_desc_s for etr and fix etr compilation error Signed-off-by: chenzhijia --- drivers/coresight/coresight_tmc_core.c | 1 + drivers/coresight/coresight_tmc_core.h | 23 --------------------- drivers/coresight/coresight_tmc_etr.c | 4 ++-- include/nuttx/coresight/coresight.h | 1 + include/nuttx/coresight/coresight_tmc.h | 27 +++++++++++++++++++++++++ 5 files changed, 31 insertions(+), 25 deletions(-) diff --git a/drivers/coresight/coresight_tmc_core.c b/drivers/coresight/coresight_tmc_core.c index da5d4fb25c4..d6044692bbd 100644 --- a/drivers/coresight/coresight_tmc_core.c +++ b/drivers/coresight/coresight_tmc_core.c @@ -143,6 +143,7 @@ tmc_register(FAR const struct coresight_desc_s *desc) } tmc_init_arch_data(tmcdev, desc); + tmcdev->caps = desc->caps; switch (tmcdev->config_type) { diff --git a/drivers/coresight/coresight_tmc_core.h b/drivers/coresight/coresight_tmc_core.h index 7de33133b8d..991b1c4c4a2 100644 --- a/drivers/coresight/coresight_tmc_core.h +++ b/drivers/coresight/coresight_tmc_core.h @@ -120,29 +120,6 @@ #define TMC_DEVID_AXIAW_SHIFT 17 #define TMC_DEVID_AXIAW_MASK 0x7f -/* TMC ETR Capability bit definitions. These need to be set by software. */ - -#define TMC_ETR_SG (0x1U << 0) - -/* ETR has separate read/write cache encodings. */ - -#define TMC_ETR_AXI_ARCACHE (0x1U << 1) - -/* TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are - * retained when TMC leaves Disabled state, allowing us to continue - * the tracing from a point where we stopped. This also implies that - * the RRP/RWP/STS.Full should always be programmed to the correct - * value. Unfortunately this is not advertised by the hardware, - * so we have to rely on PID of the IP to detect the functionality. - */ - -#define TMC_ETR_SAVE_RESTORE (0x1U << 2) - -/* Coresight SoC-600 TMC-ETR unadvertised capabilities */ - -#define TMC_600_ETR_CAPS \ - (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) - #define TMC_MAX_NAME_LEN 32 /**************************************************************************** diff --git a/drivers/coresight/coresight_tmc_etr.c b/drivers/coresight/coresight_tmc_etr.c index 2643621684d..ac110dc5ab9 100644 --- a/drivers/coresight/coresight_tmc_etr.c +++ b/drivers/coresight/coresight_tmc_etr.c @@ -125,11 +125,11 @@ static int tmc_etr_hw_enable(FAR struct coresight_tmc_dev_s *tmcdev) if (tmcdev->caps & TMC_ETR_SAVE_RESTORE) { - coresight_put32((uint32_t)tmcdev->buf, tmcdev->csdev.addr + TMC_RRP); + coresight_put32((uintptr_t)tmcdev->buf, tmcdev->csdev.addr + TMC_RRP); coresight_put32(((uint64_t)(uintptr_t)tmcdev->buf >> 32), tmcdev->csdev.addr + TMC_RRPHI); - coresight_put32((uint32_t)tmcdev->buf, tmcdev->csdev.addr + TMC_RWP); + coresight_put32((uintptr_t)tmcdev->buf, tmcdev->csdev.addr + TMC_RWP); coresight_put32(((uint64_t)(uintptr_t)tmcdev->buf >> 32), tmcdev->csdev.addr + TMC_RWPHI); diff --git a/include/nuttx/coresight/coresight.h b/include/nuttx/coresight/coresight.h index dc4a445f485..9d9480cd667 100644 --- a/include/nuttx/coresight/coresight.h +++ b/include/nuttx/coresight/coresight.h @@ -151,6 +151,7 @@ struct coresight_desc_s uint32_t buffer_size; uint32_t burst_size; + uint32_t caps; /* Description of outports of current device. */ diff --git a/include/nuttx/coresight/coresight_tmc.h b/include/nuttx/coresight/coresight_tmc.h index 199c8ea1854..046f01c5382 100644 --- a/include/nuttx/coresight/coresight_tmc.h +++ b/include/nuttx/coresight/coresight_tmc.h @@ -30,6 +30,33 @@ #include #include +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TMC ETR Capability bit definitions. These need to be set by software. */ + +#define TMC_ETR_SG (0x1U << 0) + +/* ETR has separate read/write cache encodings. */ + +#define TMC_ETR_AXI_ARCACHE (0x1U << 1) + +/* TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are + * retained when TMC leaves Disabled state, allowing us to continue + * the tracing from a point where we stopped. This also implies that + * the RRP/RWP/STS.Full should always be programmed to the correct + * value. Unfortunately this is not advertised by the hardware, + * so we have to rely on PID of the IP to detect the functionality. + */ + +#define TMC_ETR_SAVE_RESTORE (0x1U << 2) + +/* Coresight SoC-600 TMC-ETR unadvertised capabilities */ + +#define TMC_600_ETR_CAPS \ + (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) + /**************************************************************************** * Public Types ****************************************************************************/