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arch/arm/stm32c0: Fix RCC CRS and HSIUSB48 bits

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APB1 bit 16 is CRS, not CRC (CRC is on AHB). RCC_CRRCR only holds the
HSIUSB48 calibration; the HSIUSB48 enable lives in RCC_CR.

Assisted-by: Claude Code
Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-09-14 12:54:11 +02:00 • committed by Alan C. Assis
parent 63ca8d1cbc
commit 47042a6014
2 changed files with 5 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

14
arch/arm/src/stm32c0/hardware/stm32c0_rcc.h
View file

@ -142,13 +142,9 @@
/* Clock recovery RC register */
#define RCC_CRRCR_HSI48ON (1 << 0) /* Bits 0: 48MHz HSI clock enable */
#define RCC_CRRCR_HSI48RDY (1 << 1) /* Bits 1: 48MHz HSI clock ready */
#define RCC_CRRCR_HSI48DIV6EN (1 << 2) /* Bits 2: 48MHz HSI clock divided by 6 output enable */
/* Bits 3-7: Reserved */
#define RCC_CRRCR_HSI48CAL_SHIFT (8) /* Bits 8: 48 MHz HSI reset calibration */
#define RCC_CRRCR_HSI48CAL_MASK (0xff << RCC_CRRCR_HSI48CAL_SHIFT)
/* Bits 16-31: Reserved */
#define RCC_CRRCR_HSIUSB48CAL_SHIFT (0) /* Bits 0-8: HSIUSB48 clock calibration */
#define RCC_CRRCR_HSIUSB48CAL_MASK (0x1ff << RCC_CRRCR_HSIUSB48CAL_SHIFT)
/* Bits 9-31: Reserved */
/* Clock configuration register */
@ -240,7 +236,7 @@
#define RCC_APB1RSTR_USBRST (1 << 13) /* Bit 13: USB reset */
#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
/* Bit 15: Reserved */
#define RCC_APB1RSTR_CRCRST (1 << 16) /* Bit 15: CRC reset */
#define RCC_APB1RSTR_CRSRST (1 << 16) /* Bit 16: CRS reset */
#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
#define RCC_APB1RSTR_USART4RST (1 << 19) /* Bit 19: USART 4 reset */
@ -293,7 +289,7 @@
#define RCC_APB1ENR_USBEN (1 << 13) /* Bit 13: USB clock enable */
#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */
/* Bit 15: Reserved */
#define RCC_APB1ENR_CRCEN (1 << 16) /* Bit 16: CRC clock enable */
#define RCC_APB1ENR_CRSEN (1 << 16) /* Bit 16: CRS clock enable */
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */
#define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART 4 clock enable */

6
arch/arm/src/stm32c0/stm32c0_rcc.c
View file

@ -195,12 +195,6 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_USBEN;
#endif
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_APB1ENR_CRCEN;
#endif
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */