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arch/arm/stm32h7: Dump FDCAN Rx/Tx FIFO status registers.

Browse source 
fdcan_dumpregs() printed the Rx FIFO 0 and Tx buffer configuration
registers (RXF0C, TXBC) but not their live status counterparts
(RXF0S, TXFQS), and did not print the Rx FIFO 1 configuration or
status registers (RXF1C, RXF1S) at all.

Add the missing RXF1C configuration line and the RXF0S, RXF1S, and
TXFQS status lines so every configured FIFO/buffer's fill-level
state is visible alongside its configuration, matching the existing
dump grouping.

Convert fdcan_dumpregs() from printf() to ninfo(), matching the
logging convention already used elsewhere in this file
(ninfo/nerr), per upstream review feedback.

Compile-tested: boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan
with CONFIG_STM32_FDCAN_REGDEBUG=y, CONFIG_DEBUG_INFO=y.

Assisted-by: Claude:claude-sonnet-4.5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
This commit is contained in:
jsanchez-2g 2026-09-25 10:43:57 -05:00 • committed by Xiang Xiao
parent f741c9369a
commit 463d8a71d7
1 changed files with 23 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

38
arch/arm/src/stm32h7/stm32_fdcan_sock.c
View file

@ -514,49 +514,57 @@ static void fdcan_errint(struct fdcan_driver_s *priv, bool enable);
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpregs(struct fdcan_driver_s *priv)
{
printf("-------------- FDCAN Reg Dump ----------------\n");
printf("CAN%d Base: 0x%lx\n", priv->iface_idx, priv->base);
ninfo("-------------- FDCAN Reg Dump ----------------\n");
ninfo("CAN%d Base: 0x%lx\n", priv->iface_idx, priv->base);
uint32_t regval;
regval = getreg32(priv->base + STM32_FDCAN_CCCR_OFFSET);
printf("CCCR = 0x%lx\n", regval);
ninfo("CCCR = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_ECR_OFFSET);
printf("ECR = 0x%lx\n", regval);
ninfo("ECR = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_NBTP_OFFSET);
printf("NBTP = 0x%lx\n", regval);
ninfo("NBTP = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_DBTP_OFFSET);
printf("DBTP = 0x%lx\n", regval);
ninfo("DBTP = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_TXBC_OFFSET);
printf("TXBC = 0x%lx\n", regval);
ninfo("TXBC = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_TXFQS_OFFSET);
ninfo("TXFQS = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_RXF0C_OFFSET);
printf("RXF0C = 0x%lx\n", regval);
ninfo("RXF0C = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_RXF0S_OFFSET);
ninfo("RXF0S = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_RXF1C_OFFSET);
ninfo("RXF1C = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_RXF1S_OFFSET);
ninfo("RXF1S = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_TXESC_OFFSET);
printf("TXESC = 0x%lx\n", regval);
ninfo("TXESC = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_RXESC_OFFSET);
printf("RXESC = 0x%lx\n", regval);
ninfo("RXESC = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_IE_OFFSET);
printf("IE = 0x%lx\n", regval);
ninfo("IE = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_ILE_OFFSET);
printf("ILE = 0x%lx\n", regval);
ninfo("ILE = 0x%lx\n", regval);
regval = getreg32(priv->base + STM32_FDCAN_ILS_OFFSET);
printf("ILS = 0x%lx\n", regval);
ninfo("ILS = 0x%lx\n", regval);
/* Print out some possibly interesting unhandled interrupts */
regval = getreg32(priv->base + STM32_FDCAN_IR_OFFSET);
printf("IR = 0x%lx\n", regval);
ninfo("IR = 0x%lx\n", regval);
if (regval & FDCAN_IR_PEA || regval & FDCAN_IR_PED)
{
/* Protocol error -- check protocol status register for details */
regval = getreg32(priv->base + STM32_FDCAN_PSR_OFFSET);
printf("--PSR.LEC = %" PRId32 "\n", regval & FDCAN_PSR_LEC_MASK);
ninfo("--PSR.LEC = %" PRId32 "\n", regval & FDCAN_PSR_LEC_MASK);
}
}
#endif