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Fix nxstyle warning

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2020-11-27 00:33:25 +08:00
parent b1d85d4978
commit 463457b001
4 changed files with 31 additions and 31 deletions
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2
libs/libc/machine/arm/armv8-m/arch_ceil.c
View file

@ -48,7 +48,7 @@
double ceil(double x)
{
double result;
asm volatile ( "vrintp.f64\t%P0, %P1" : "=w" (result) : "w" (x) );
asm volatile("vrintp.f64\t%P0, %P1" : "=w"(result) : "w"(x));
return result;
}

2
libs/libc/machine/arm/armv8-m/arch_ceilf.c
View file

@ -48,7 +48,7 @@
float ceilf(float x)
{
float result;
asm volatile ( "vrintp.f32\t%0, %1" : "=t" (result) : "t" (x) );
asm volatile("vrintp.f32\t%0, %1" : "=t"(result) : "t"(x));
return result;
}

56
libs/libc/machine/arm/armv8-m/arch_elf.c
View file

@ -210,23 +210,23 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
*
* upper_insn:
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +----------+---+-------------------------------+--------------+
* |1 1 1 |OP1| OP2 | | 32-Bit Instructions
* +----------+---+--+-----+----------------------+--------------+
* |1 1 1 | 1 0| S | imm10 | BL Instruction
* +----------+------+-----+-------------------------------------+
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-------+---+----------------------+-----------+
* |1 1 1|OP1| OP2 | | 32Bit Instruction
* +-------+---+-+---+----------------+-----------+
* |1 1 1| 1 0| S | imm10 | BL Instruction
* +-------+-----+---+----------------------------+
*
* lower_insn:
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +---+---------------------------------------------------------+
* |OP | | 32-Bit Instructions
* +---+--+---+---+---+------------------------------------------+
* |1 1 |J1 | 1 |J2 | imm11 | BL Instruction
* +------+---+---+---+------------------------------------------+
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +--+-------------------------------------------+
* |OP| | 32Bit Instruction
* +--+-+--+--+--+--------------------------------+
* |1 1|J1| 1|J2| imm11 | BL Instruction
* +----+--+--+--+--------------------------------+
*
* The branch target is encoded in these bits:
*
@ -385,23 +385,23 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
*
* upper_insn:
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +----------+---+-------------------------------+--------------+
* |1 1 1 |OP1| OP2 | | 32-Bit Instructions
* +----------+---+--+-----+----------------------+--------------+
* |1 1 1 | 1 0| i | 1 0 1 1 0 0 | imm4 | MOVT Instruction
* +----------+------+-----+----------------------+--------------+
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-------+---+-----------------------+----------+
* |1 1 1|OP1| OP2 | | 32Bit Instruction
* +-------+---+-+---+-----------------+----------+
* |1 1 1| 1 0| i | 1 0 1 1 0 0 | imm4 | MOVT Instruction
* +-------+-----+---+-----------------+----------+
*
* lower_insn:
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +---+---------------------------------------------------------+
* |OP | | 32-Bit Instructions
* +---+----------+--------------+-------------------------------+
* |0 | imm3 | Rd | imm8 | MOVT Instruction
* +---+----------+--------------+-------------------------------+
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +--+-------------------------------------------+
* |OP| | 32Bit Instruction
* +--+--------+----------+-----------------------+
* |0 | imm3 | Rd | imm8 | MOVT Instruction
* +--+--------+----------+-----------------------+
*
* The 16-bit immediate value is encoded in these bits:
*

2
libs/libc/machine/arm/armv8-m/arch_floorf.c
View file

@ -48,7 +48,7 @@
float floorf(float x)
{
float result;
asm volatile ( "vrintm.f32\t%0, %1" : "=t" (result) : "t" (x) );
asm volatile("vrintm.f32\t%0, %1" : "=t"(result) : "t"(x));
return result;
}