Aksal/nuttx
3
1
Fork 1
mirror of https://github.com/apache/nuttx.git synced 2026-08-01 20:28:58 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().

Browse source
This commit is contained in:
Gregory Nutt 2016-06-20 11:59:15 -06:00
parent d40a473f72
commit 43eb04bb8f
329 changed files with 2252 additions and 2478 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/src/arm/up_dataabort.c
View file

@ -107,7 +107,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* fatal error.
*/
pgllinfo("FSR: %08x FAR: %08x\n", fsr, far);
pginfo("FSR: %08x FAR: %08x\n", fsr, far);
if ((fsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
@ -118,7 +118,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* (It has not yet been saved in the register context save area).
*/
pgllinfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (far < PG_PAGED_VBASE || far >= PG_PAGED_VEND)
{
goto segfault;

4
arch/arm/src/arm/up_prefetchabort.c
View file

@ -99,8 +99,8 @@ void up_prefetchabort(uint32_t *regs)
* virtual addresses.
*/
pgllinfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{

2
arch/arm/src/arm/up_releasepending.c
View file

@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
sllinfo("From TCB=%p\n", rtcb);
sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */

2
arch/arm/src/arm/up_reprioritizertr.c
View file

@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
sllinfo("TCB=%p PRI=%d\n", tcb, priority);
sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just

32
arch/arm/src/armv6-m/up_dumpnvic.c
View file

@ -72,27 +72,27 @@ void up_dumpnvic(FAR const char *msg)
flags = enter_critical_section();
_llinfo("NVIC: %s\n", msg);
_llinfo(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
_info("NVIC: %s\n", msg);
_info(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
for (i = 0 ; i < 8; i += 4)
{
_llinfo(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
i, getreg32(ARMV6M_NVIC_IPR(i)),
i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
_info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
i, getreg32(ARMV6M_NVIC_IPR(i)),
i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
}
_llinfo("SYSCON:\n");
_llinfo(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
_llinfo(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
getreg32(ARMV6M_SYSCON_SHPR3));
_info("SYSCON:\n");
_info(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
_info(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
#endif

2
arch/arm/src/armv6-m/up_releasepending.c
View file

@ -66,7 +66,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
sllinfo("From TCB=%p\n", rtcb);
sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */

2
arch/arm/src/armv6-m/up_reprioritizertr.c
View file

@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
sllinfo("TCB=%p PRI=%d\n", tcb, priority);
sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just removed the head

58
arch/arm/src/armv6-m/up_svcall.c
View file

@ -147,19 +147,19 @@ int up_svcall(int irq, FAR void *context)
if (cmd > SYS_switch_context)
# endif
{
svcllinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef CONFIG_BUILD_PROTECTED
svcllinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
# else
svcllinfo(" PSR: %08x PRIMASK: %08x\n",
regs[REG_XPSR], regs[REG_PRIMASK]);
svcinfo(" PSR: %08x PRIMASK: %08x\n",
regs[REG_XPSR], regs[REG_PRIMASK]);
# endif
}
#endif
@ -444,7 +444,7 @@ int up_svcall(int irq, FAR void *context)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
}
break;
@ -459,30 +459,30 @@ int up_svcall(int irq, FAR void *context)
if (regs != CURRENT_REGS)
# endif
{
svcllinfo("SVCall Return:\n");
svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
svcinfo("SVCall Return:\n");
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
svcllinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
CURRENT_REGS[REG_EXC_RETURN]);
svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
CURRENT_REGS[REG_EXC_RETURN]);
#else
svcllinfo(" PSR: %08x PRIMASK: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
svcinfo(" PSR: %08x PRIMASK: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
}
# ifdef CONFIG_DEBUG_SVCALL
else
{
svcllinfo("SVCall Return: %d\n", regs[REG_R0]);
svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
#endif

14
arch/arm/src/armv7-a/arm_cpustart.c
View file

@ -64,19 +64,19 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb)
{
int regndx;
_llinfo("CPU%d:\n", up_cpu_index());
_info("CPU%d:\n", up_cpu_index());
/* Dump the startup registers */
for (regndx = REG_R0; regndx <= REG_R15; regndx += 8)
{
uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx];
_llinfo("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regndx, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
_info("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regndx, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
_llinfo("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
_info("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
}
#else
# define arm_registerdump(tcb)
@ -106,7 +106,7 @@ int arm_start_handler(int irq, FAR void *context)
{
FAR struct tcb_s *tcb;
sllinfo("CPU%d Started\n", up_cpu_index());
sinfo("CPU%d Started\n", up_cpu_index());
/* Reset scheduler parameters */
@ -155,7 +155,7 @@ int arm_start_handler(int irq, FAR void *context)
int up_cpu_start(int cpu)
{
sllinfo("Starting CPU%d\n", cpu);
sinfo("Starting CPU%d\n", cpu);
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());

4
arch/arm/src/armv7-a/arm_dataabort.c
View file

@ -104,7 +104,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
* fatal error.
*/
pgllinfo("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
pginfo("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
if ((dfsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
@ -115,7 +115,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
* (It has not yet been saved in the register context save area).
*/
pgllinfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND)
{
goto segfault;

2
arch/arm/src/armv7-a/arm_gicv2.c
View file

@ -387,7 +387,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
regval = getreg32(GIC_ICCIAR);
irq = (regval & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT;
irqllinfo("irq=%d\n", irq);
irqinfo("irq=%d\n", irq);
/* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending
* interrupt.

96
arch/arm/src/armv7-a/arm_gicv2_dump.c
View file

@ -69,22 +69,22 @@
static inline void arm_gic_dump_cpu(bool all, int irq, int nlines)
{
irqllinfo(" CPU Interface Registers:\n");
irqllinfo(" ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
irqllinfo(" RPR: %08x HPIR: %08x ABPR: %08x\n",
getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
getreg32(GIC_ICCABPR));
irqllinfo(" AIAR: %08x AHPIR: %08x IDR: %08x\n",
getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
getreg32(GIC_ICCIDR));
irqllinfo(" APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
irqllinfo(" NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
irqinfo(" CPU Interface Registers:\n");
irqinfo(" ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
irqinfo(" RPR: %08x HPIR: %08x ABPR: %08x\n",
getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
getreg32(GIC_ICCABPR));
irqinfo(" AIAR: %08x AHPIR: %08x IDR: %08x\n",
getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
getreg32(GIC_ICCIDR));
irqinfo(" APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
irqinfo(" NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
}
/****************************************************************************
@ -110,9 +110,9 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
incr <<= 2;
for (i = 0; i < nlines; i += incr, regaddr += 16)
{
irqllinfo(" %08x %08x %08x %08x\n",
getreg32(regaddr), getreg32(regaddr + 4),
getreg32(regaddr + 8), getreg32(regaddr + 12));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(regaddr), getreg32(regaddr + 4),
getreg32(regaddr + 8), getreg32(regaddr + 12));
}
}
@ -135,7 +135,7 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
int nlines)
{
irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 4);
}
@ -158,7 +158,7 @@ static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
int nlines)
{
irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 8);
}
@ -181,7 +181,7 @@ static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
int nlines)
{
irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 16);
}
@ -204,7 +204,7 @@ static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
int nlines)
{
irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 32);
}
@ -226,10 +226,10 @@ static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
{
irqllinfo(" Distributor Registers:\n");
irqllinfo(" DCR: %08x ICTR: %08x IIDR: %08x\n",
getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
getreg32(GIC_ICDIIDR));
irqinfo(" Distributor Registers:\n");
irqinfo(" DCR: %08x ICTR: %08x IIDR: %08x\n",
getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
getreg32(GIC_ICDIIDR));
if (all)
{
@ -246,27 +246,27 @@ static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
}
else
{
irqllinfo(" ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
irqllinfo(" IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
irqllinfo(" NSACR: %08x SCPR: %08x\n",
getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
irqinfo(" ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
irqinfo(" IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
irqinfo(" NSACR: %08x SCPR: %08x\n",
getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
}
irqllinfo(" PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
irqllinfo(" %08x %08x %08x %08x\n",
getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
irqllinfo(" %08x %08x %08x %08x\n",
getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
getreg32(GIC_ICDPIDR(6)));
irqllinfo(" CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
irqllinfo(" %08x %08x %08x %08x\n",
getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
irqinfo(" PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
getreg32(GIC_ICDPIDR(6)));
irqinfo(" CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
}
/****************************************************************************
@ -295,11 +295,11 @@ void arm_gic_dump(const char *msg, bool all, int irq)
if (all)
{
irqllinfo("GIC: %s NLINES=%u\n", msg, nlines);
irqinfo("GIC: %s NLINES=%u\n", msg, nlines);
}
else
{
irqllinfo("GIC: %s IRQ=%d\n", msg, irq);
irqinfo("GIC: %s IRQ=%d\n", msg, irq);
}
arm_gic_dump_cpu(all, irq, nlines);

4
arch/arm/src/armv7-a/arm_prefetchabort.c
View file

@ -86,8 +86,8 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
* virtual addresses.
*/
pgllinfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{

2
arch/arm/src/armv7-a/arm_releasepending.c
View file

@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
sllinfo("From TCB=%p\n", rtcb);
sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */

2
arch/arm/src/armv7-a/arm_reprioritizertr.c
View file

@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
sllinfo("TCB=%p PRI=%d\n", tcb, priority);
sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just

34
arch/arm/src/armv7-a/arm_syscall.c
View file

@ -156,14 +156,14 @@ uint32_t *arm_syscall(uint32_t *regs)
* and R1..R7 = variable number of arguments depending on the system call.
*/
svcllinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Handle the SVCall according to the command in R0 */
@ -456,7 +456,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@ -479,14 +479,14 @@ uint32_t *arm_syscall(uint32_t *regs)
/* Report what happened */
svcllinfo("SYSCALL Exit: regs: %p\n", regs);
svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
svcinfo("SYSCALL Exit: regs: %p\n", regs);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Return the last value of curent_regs. This supports context switches
* on return from the exception. That capability is only used with the

2
arch/arm/src/armv7-m/up_releasepending.c
View file

@ -66,7 +66,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
sllinfo("From TCB=%p\n", rtcb);
sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */

2
arch/arm/src/armv7-m/up_reprioritizertr.c
View file

@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
sllinfo("TCB=%p PRI=%d\n", tcb, priority);
sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just removed the head

52
arch/arm/src/armv7-m/up_svcall.c
View file

@ -142,18 +142,18 @@ int up_svcall(int irq, FAR void *context)
if (cmd > SYS_switch_context)
# endif
{
svcllinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef REG_EXC_RETURN
svcllinfo(" PSR: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_EXC_RETURN]);
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_EXC_RETURN]);
# else
svcllinfo(" PSR: %08x\n", regs[REG_XPSR]);
svcinfo(" PSR: %08x\n", regs[REG_XPSR]);
# endif
}
#endif
@ -446,7 +446,7 @@ int up_svcall(int irq, FAR void *context)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
}
break;
@ -461,28 +461,28 @@ int up_svcall(int irq, FAR void *context)
if (regs != CURRENT_REGS)
# endif
{
svcllinfo("SVCall Return:\n");
svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
svcinfo("SVCall Return:\n");
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
# ifdef REG_EXC_RETURN
svcllinfo(" PSR: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
# else
svcllinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
else
{
svcllinfo("SVCall Return: %d\n", regs[REG_R0]);
svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
#endif

2
arch/arm/src/armv7-r/arm_l2cc_pl310.c
View file

@ -411,7 +411,7 @@ void up_l2ccinitialize(void)
putreg32(L2CC_CR_L2CEN, L2CC_CR);
}
sllinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
}

2
arch/arm/src/armv7-r/arm_releasepending.c
View file

@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
sllinfo("From TCB=%p\n", rtcb);
sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */

2
arch/arm/src/armv7-r/arm_reprioritizertr.c
View file

@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
sllinfo("TCB=%p PRI=%d\n", tcb, priority);
sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just

34
arch/arm/src/armv7-r/arm_syscall.c
View file

@ -154,14 +154,14 @@ uint32_t *arm_syscall(uint32_t *regs)
* and R1..R7 = variable number of arguments depending on the system call.
*/
svcllinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Handle the SVCall according to the command in R0 */
@ -454,7 +454,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@ -477,14 +477,14 @@ uint32_t *arm_syscall(uint32_t *regs)
/* Report what happened */
svcllinfo("SYSCALL Exit: regs: %p\n", regs);
svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
svcinfo("SYSCALL Exit: regs: %p\n", regs);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Return the last value of curent_regs. This supports context switches
* on return from the exception. That capability is only used with the

4
arch/arm/src/c5471/c5471_ethernet.c
View file

@ -1267,7 +1267,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllinfo("IPv4 frame\n");
ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1310,7 +1310,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllinfo("Iv6 frame\n");
ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */

8
arch/arm/src/c5471/c5471_watchdog.c
View file

@ -234,17 +234,17 @@ static int wdt_setusec(uint32_t usec)
static int wdt_interrupt(int irq, void *context)
{
wdllinfo("expired\n");
wdinfo("expired\n");
#if defined(CONFIG_SOFTWARE_REBOOT)
# if defined(CONFIG_SOFTWARE_TEST)
wdllinfo(" Test only\n");
wdinfo(" Test only\n");
# else
wdllinfo(" Re-booting\n");
wdinfo(" Re-booting\n");
# warning "Add logic to reset CPU here"
# endif
#else
wdllinfo(" No reboot\n");
wdinfo(" No reboot\n");
#endif
return OK;
}

4
arch/arm/src/common/up_exit.c
View file

@ -146,10 +146,10 @@ void _exit(int status)
(void)up_irq_save();
sllinfo("TCB=%p exiting\n", this_task());
sinfo("TCB=%p exiting\n", this_task());
#ifdef CONFIG_DUMP_ON_EXIT
sllinfo("Other tasks:\n");
sinfo("Other tasks:\n");
sched_foreach(_up_dumponexit, NULL);
#endif

32
arch/arm/src/dm320/dm320_usbdev.c
View file

@ -443,7 +443,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
{
if (count == 4)
{
ullinfo("...\n");
uinfo("...\n");
}
return val;
@ -460,7 +460,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
ullinfo("[repeats %d more times]\n", count-3);
uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -472,7 +472,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
/* Show the register value read */
ullinfo("%08x->%02x\n", addr, val);
uinfo("%08x->%02x\n", addr, val);
return val;
}
#endif
@ -506,7 +506,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
{
if (count == 4)
{
ullinfo("...\n");
uinfo("...\n");
}
return val;
@ -523,7 +523,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
ullinfo("[repeats %d more times]\n", count-3);
uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -535,7 +535,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
/* Show the register value read */
ullinfo("%08x->%04x\n", addr, val);
uinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
@ -569,7 +569,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
{
if (count == 4)
{
ullinfo("...\n");
uinfo("...\n");
}
return val;
@ -586,7 +586,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
ullinfo("[repeats %d more times]\n", count-3);
uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -598,7 +598,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
/* Show the register value read */
ullinfo("%08x->%08x\n", addr, val);
uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@ -616,7 +616,7 @@ static void dm320_putreg8(uint8_t val, uint32_t addr)
{
/* Show the register value being written */
ullinfo("%08x<-%02x\n", addr, val);
uinfo("%08x<-%02x\n", addr, val);
/* Write the value */
@ -637,7 +637,7 @@ static void dm320_putreg16(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
ullinfo("%08x<-%04x\n", addr, val);
uinfo("%08x<-%04x\n", addr, val);
/* Write the value */
@ -658,7 +658,7 @@ static void dm320_putreg32(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
ullinfo("%08x<-%08x\n", addr, val);
uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@ -1216,8 +1216,8 @@ static inline void dm320_ep0setup(struct dm320_usbdev_s *priv)
value = GETUINT16(ctrl.value);
len = GETUINT16(ctrl.len);
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@ -1618,7 +1618,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context)
}
else
{
ullinfo("Pending data on OUT endpoint\n");
uinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@ -2417,7 +2417,7 @@ void up_usbinitialize(void)
#ifdef CONFIG_DEBUG_USB_INFO
chiprev = dm320_getreg16(DM320_BUSC_REVR);
ullinfo("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f);
uinfo("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f);
#endif
/* Enable USB clock & GIO clock */

2
arch/arm/src/efm32/efm32_idle.c
View file

@ -110,7 +110,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
_llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */

4
arch/arm/src/efm32/efm32_pwm.c
View file

@ -522,8 +522,8 @@ static int pwm_interrupt(struct efm32_pwmtimer_s *priv)
/* Now all of the time critical stuff is done so we can do some debug output */
pwmllinfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
regval, priv->prev, priv->curr, priv->count);
pwminfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
regval, priv->prev, priv->curr, priv->count);
return OK;
#else

38
arch/arm/src/efm32/efm32_usbdev.c
View file

@ -819,7 +819,7 @@ static uint32_t efm32_getreg(uint32_t addr)
{
if (count == 4)
{
ullinfo("...\n");
uinfo("...\n");
}
return val;
@ -836,7 +836,7 @@ static uint32_t efm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
ullinfo("[repeats %d more times]\n", count-3);
uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -848,7 +848,7 @@ static uint32_t efm32_getreg(uint32_t addr)
/* Show the register value read */
ullinfo("%08x->%08x\n", addr, val);
uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@ -866,7 +866,7 @@ static void efm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
ullinfo("%08x<-%08x\n", addr, val);
uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@ -1224,9 +1224,9 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv,
return;
}
ullinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
privep->epphy, privreq, privreq->req.len,
privreq->req.xfrd, privep->zlp);
uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
privep->epphy, privreq, privreq->req.len,
privreq->req.xfrd, privep->zlp);
/* Check for a special case: If we are just starting a request (xfrd==0) and
* the class driver is trying to send a zero-length packet (len==0). Then set
@ -1490,8 +1490,8 @@ static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv,
return;
}
ullinfo("EP%d: len=%d xfrd=%d\n",
privep->epphy, privreq->req.len, privreq->req.xfrd);
uinfo("EP%d: len=%d xfrd=%d\n",
privep->epphy, privreq->req.len, privreq->req.xfrd);
/* Return the completed read request to the class driver and mark the state
* IDLE.
@ -1525,7 +1525,7 @@ static inline void efm32_ep0out_receive(FAR struct efm32_ep_s *privep, int bcnt)
DEBUGASSERT(privep && privep->ep.priv);
priv = (FAR struct efm32_usbdev_s *)privep->ep.priv;
ullinfo("EP0: bcnt=%d\n", bcnt);
uinfo("EP0: bcnt=%d\n", bcnt);
usbtrace(TRACE_READ(EP0), bcnt);
/* Verify that an OUT SETUP request as received before this data was
@ -1618,7 +1618,8 @@ static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt)
return;
}
ullinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
uinfo("EP%d: len=%d xfrd=%d\n",
privep->epphy, privreq->req.len, privreq->req.xfrd);
usbtrace(TRACE_READ(privep->epphy), bcnt);
/* Get the number of bytes to transfer from the RxFIFO */
@ -1702,7 +1703,7 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv,
return;
}
ullinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
/* Ignore any attempt to receive a zero length packet (this really
* should not happen.
@ -2498,8 +2499,8 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv)
ctrlreq.index = GETUINT16(priv->ctrlreq.index);
ctrlreq.len = GETUINT16(priv->ctrlreq.len);
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
/* Check for a standard request */
@ -2633,7 +2634,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv)
if ((daint & 1) != 0)
{
regval = efm32_getreg(EFM32_USB_DOEPINT(epno));
ullinfo("DOEPINT(%d) = %08x\n", epno, regval);
uinfo("DOEPINT(%d) = %08x\n", epno, regval);
efm32_putreg(0xFF, EFM32_USB_DOEPINT(epno));
}
@ -2863,8 +2864,8 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv)
{
if ((daint & 1) != 0)
{
ullinfo("DIEPINT(%d) = %08x\n",
epno, efm32_getreg(EFM32_USB_DIEPINT(epno)));
uinfo("DIEPINT(%d) = %08x\n",
epno, efm32_getreg(EFM32_USB_DIEPINT(epno)));
efm32_putreg(0xFF, EFM32_USB_DIEPINT(epno));
}
@ -4337,7 +4338,8 @@ static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
uinfo("req=%p callback=%p buf=%p ep=%p\n",
req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

21
arch/arm/src/efm32/efm32_usbhost.c
View file

@ -582,7 +582,7 @@ static const struct efm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] =
#ifdef CONFIG_EFM32_USBHOST_REGDEBUG
static void efm32_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@ -632,7 +632,7 @@ static void efm32_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
ullinfo("[repeats %d more times]\n", count);
uinfo("[repeats %d more times]\n", count);
}
}
@ -2448,7 +2448,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@ -2709,7 +2709,7 @@ static inline void efm32_gint_hcoutisr(FAR struct efm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@ -3012,7 +3012,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
/* Read and pop the next status from the Rx FIFO */
grxsts = efm32_getreg(EFM32_USB_GRXSTSP);
ullinfo("GRXSTS: %08x\n", grxsts);
uinfo("GRXSTS: %08x\n", grxsts);
/* Isolate the channel number/index in the status word */
@ -3166,8 +3166,8 @@ static inline void efm32_gint_nptxfeisr(FAR struct efm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
ullinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@ -3254,8 +3254,8 @@ static inline void efm32_gint_ptxfeisr(FAR struct efm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
ullinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@ -4795,7 +4795,8 @@ static int efm32_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
uinfo("Hub port %d connected: %s\n",
hport->port, connected ? "YES" : "NO");
/* Report the connection event */

4
arch/arm/src/kinetis/kinetis_enet.c
View file

@ -557,7 +557,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllinfo("IPv4 frame\n");
ninfo("IPv4 frame\n");
NETDEV_RXIPV4(&priv->dev);
/* Handle ARP on input then give the IPv4 packet to the network
@ -598,7 +598,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllinfo("Iv6 frame\n");
ninfo("Iv6 frame\n");
NETDEV_RXIPV6(&priv->dev);
/* Give the IPv6 packet to the network layer */

28
arch/arm/src/kinetis/kinetis_sdhc.c
View file

@ -791,8 +791,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
* ready (BWR)
*/
mcllinfo("Entry: remaining: %d IRQSTAT: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
while (priv->remaining > 0 &&
(getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BWR) != 0)
@ -837,8 +837,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
putreg32(data.w, KINETIS_SDHC_DATPORT);
}
mcllinfo("Exit: remaining: %d IRQSTAT: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
mcinfo("Exit: remaining: %d IRQSTAT: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
}
#endif
@ -876,8 +876,8 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
* ready (BRR)
*/
mcllinfo("Entry: remaining: %d IRQSTAT: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
while (priv->remaining > 0 &&
(getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BRR) != 0)
@ -928,9 +928,9 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
putreg32(watermark << SDHC_WML_RD_SHIFT, KINETIS_SDHC_WML);
mcllinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT),
getreg32(KINETIS_SDHC_WML));
mcinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT),
getreg32(KINETIS_SDHC_WML));
}
#endif
@ -971,7 +971,7 @@ static void kinetis_eventtimeout(int argc, uint32_t arg)
/* Wake up any waiting threads */
kinetis_endwait(priv, SDIOWAIT_TIMEOUT);
mcllerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
}
}
@ -1103,8 +1103,8 @@ static int kinetis_interrupt(int irq, void *context)
regval = getreg32(KINETIS_SDHC_IRQSIGEN);
enabled = getreg32(KINETIS_SDHC_IRQSTAT) & regval;
mcllinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled);
mcinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled);
/* Disable card interrupts to clear the card interrupt to the host system. */
@ -1160,7 +1160,7 @@ static int kinetis_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
mcllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@ -1170,7 +1170,7 @@ static int kinetis_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
mcllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
}
}

2
arch/arm/src/kinetis/kinetis_serial.c
View file

@ -805,7 +805,7 @@ static int up_interrupt(int irq, void *context)
*/
regval = up_serialin(priv, KINETIS_UART_S1_OFFSET);
_llinfo("S1: %02x\n", regval);
_info("S1: %02x\n", regval);
UNUSED(regval);
regval = up_serialin(priv, KINETIS_UART_D_OFFSET);

62
arch/arm/src/kinetis/kinetis_usbdev.c
View file

@ -375,8 +375,8 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
/* CONFIG_KHCI_USBDEV_BDTDEBUG dumps most BDT settings */
#ifdef CONFIG_KHCI_USBDEV_BDTDEBUG
# define bdterr ullerr
# define bdtinfo ullinfo
# define bdterr uerr
# define bdtinfo uinfo
#else
# define bdterr(x...)
# define bdtinfo(x...)
@ -693,7 +693,7 @@ static uint16_t khci_getreg(uint32_t addr)
{
if (count == 4)
{
ullinfo("...\n");
uinfo("...\n");
}
return val;
}
@ -709,7 +709,7 @@ static uint16_t khci_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
ullinfo("[repeats %d more times]\n", count-3);
uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -721,7 +721,7 @@ static uint16_t khci_getreg(uint32_t addr)
/* Show the register value read */
ullinfo("%08x->%04x\n", addr, val);
uinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
@ -735,7 +735,7 @@ static void khci_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
ullinfo("%08x<-%04x\n", addr, val);
uinfo("%08x<-%04x\n", addr, val);
/* Write the value */
@ -966,15 +966,15 @@ static void khci_wrcomplete(struct khci_usbdev_s *priv,
epno = USB_EPNO(privep->ep.eplog);
#ifdef CONFIG_USBDEV_NOWRITEAHEAD
ullinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
uinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
#else
ullinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
epno, privreq->req.len, privreq->req.xfrd,
privreq->inflight[0], privreq->inflight[1]);
uinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
epno, privreq->req.len, privreq->req.xfrd,
privreq->inflight[0], privreq->inflight[1]);
#endif
bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
epno, bdtin, bdtin->status, bdtin->addr);
epno, bdtin, bdtin->status, bdtin->addr);
/* We should own the BDT that just completed. But NULLify the entire BDT IN.
* Why? So that we can tell later that the BDT available. No, it is not
@ -1282,8 +1282,8 @@ static int khci_wrstart(struct khci_usbdev_s *priv,
bytesleft = privreq->req.len;
}
ullinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
uinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
/* Get the number of bytes left to be sent in the packet */
@ -1396,10 +1396,10 @@ static int khci_rdcomplete(struct khci_usbdev_s *priv,
bdtout = privep->bdtout;
epno = USB_EPNO(privep->ep.eplog);
ullinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
uinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
epno, bdtout, bdtout->status, bdtout->addr);
epno, bdtout, bdtout->status, bdtout->addr);
/* We should own the BDT that just completed */
@ -1685,7 +1685,7 @@ static int khci_rdrequest(struct khci_usbdev_s *priv,
return OK;
}
ullinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
uinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
/* Ignore any attempt to receive a zero length packet */
@ -1975,8 +1975,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@ -2219,7 +2219,7 @@ static void khci_ep0setup(struct khci_usbdev_s *priv)
{
/* Special case recipient=device test mode */
ullinfo("test mode: %d\n", index.w);
uinfo("test mode: %d\n", index.w);
}
else
{
@ -2893,7 +2893,7 @@ x
if ((usbir & USB_INT_ERROR) != 0)
{
usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_UERR), usbir);
ullerr("ERROR: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
uerr("ERROR: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
/* Clear all pending USB error interrupts */
@ -3221,7 +3221,7 @@ static int khci_epconfigure(struct usbdev_ep_s *ep,
if (!ep || !desc)
{
usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
ullerr("ERROR: ep=%p desc=%p\n");
uerr("ERROR: ep=%p desc=%p\n");
return -EINVAL;
}
#endif
@ -3352,7 +3352,7 @@ static int khci_epdisable(struct usbdev_ep_s *ep)
if (!ep)
{
usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
ullerr("ERROR: ep=%p\n", ep);
uerr("ERROR: ep=%p\n", ep);
return -EINVAL;
}
#endif
@ -3451,8 +3451,8 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
req, req->callback, req->buf, ep);
uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@ -3464,7 +3464,7 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
ullerr("ERROR: driver=%p\n", priv->driver);
uerr("ERROR: driver=%p\n", priv->driver);
return -ESHUTDOWN;
}
#endif
@ -4233,10 +4233,10 @@ static void khci_hwreset(struct khci_usbdev_s *priv)
khci_putreg((uint8_t)((uint32_t)g_bdt >> 16), KINETIS_USB0_BDTPAGE2);
khci_putreg((uint8_t)(((uint32_t)g_bdt >> 8) & USB_BDTPAGE1_MASK), KINETIS_USB0_BDTPAGE1);
ullinfo("BDT Address %hhx \n" ,&g_bdt);
ullinfo("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3));
ullinfo("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2));
ullinfo("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1));
uinfo("BDT Address %hhx \n" ,&g_bdt);
uinfo("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3));
uinfo("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2));
uinfo("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1));
/* Clear any pending interrupts */

12
arch/arm/src/kl/kl_dumpgpio.c
View file

@ -118,12 +118,12 @@ void kl_dumpgpio(gpio_cfgset_t pinset, const char *msg)
flags = enter_critical_section();
_llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
_llinfo(" PDOR: %08x PDIR: %08x PDDR: %08x\n",
getreg32(base + KL_GPIO_PDOR_OFFSET),
getreg32(base + KL_GPIO_PDIR_OFFSET),
getreg32(base + KL_GPIO_PDDR_OFFSET));
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
_info(" PDOR: %08x PDIR: %08x PDDR: %08x\n",
getreg32(base + KL_GPIO_PDOR_OFFSET),
getreg32(base + KL_GPIO_PDIR_OFFSET),
getreg32(base + KL_GPIO_PDDR_OFFSET));
leave_critical_section(flags);
}

2
arch/arm/src/kl/kl_idle.c
View file

@ -103,7 +103,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
_llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */

26
arch/arm/src/lpc17xx/lpc17_can.c
View file

@ -308,7 +308,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
{
if (count == 4)
{
canllinfo("...\n");
caninfo("...\n");
}
return;
@ -325,7 +325,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
{
/* Yes.. then show how many times the value repeated */
canllinfo("[repeats %d more times]\n", count-3);
caninfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -337,7 +337,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
/* Show the register value read */
canllinfo("%08x->%08x\n", addr, value);
caninfo("%08x->%08x\n", addr, value);
}
#endif
@ -398,7 +398,7 @@ static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value)
/* Show the register value being written */
canllinfo("%08x<-%08x\n", addr, value);
caninfo("%08x<-%08x\n", addr, value);
/* Write the value */
@ -458,7 +458,7 @@ static void can_putcommon(uint32_t addr, uint32_t value)
{
/* Show the register value being written */
canllinfo("%08x<-%08x\n", addr, value);
caninfo("%08x<-%08x\n", addr, value);
/* Write the value */
@ -942,7 +942,7 @@ static void can_interrupt(FAR struct can_dev_s *dev)
/* Read the interrupt and capture register (also clearing most status bits) */
regval = can_getreg(priv, LPC17_CAN_ICR_OFFSET);
canllinfo("CAN%d ICR: %08x\n", priv->port, regval);
caninfo("CAN%d ICR: %08x\n", priv->port, regval);
/* Check for a receive interrupt */
@ -972,7 +972,7 @@ static void can_interrupt(FAR struct can_dev_s *dev)
if ((rfs & CAN_RFS_FF) != 0)
{
canllerr("ERROR: Received message with extended identifier. Dropped\n");
canerr("ERROR: Received message with extended identifier. Dropped\n");
}
else
#endif
@ -1049,7 +1049,7 @@ static int can12_interrupt(int irq, void *context)
{
/* Handle CAN1/2 interrupts */
canllinfo("irq: %d\n", irq);
caninfo("irq: %d\n", irq);
#ifdef CONFIG_LPC17_CAN1
can_interrupt(&g_can1dev);
@ -1126,8 +1126,8 @@ static int can_bittiming(struct up_dev_s *priv)
uint32_t ts2;
uint32_t sjw;
canllinfo("CAN%d PCLK: %d baud: %d\n", priv->port,
CAN_CLOCK_FREQUENCY(priv->divisor), priv->baud);
caninfo("CAN%d PCLK: %d baud: %d\n", priv->port,
CAN_CLOCK_FREQUENCY(priv->divisor), priv->baud);
/* Try to get CAN_BIT_QUANTA quanta in one bit_time.
*
@ -1179,7 +1179,7 @@ static int can_bittiming(struct up_dev_s *priv)
sjw = 1;
canllinfo("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
caninfo("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
/* Configure bit timing */
@ -1196,7 +1196,7 @@ static int can_bittiming(struct up_dev_s *priv)
btr |= CAN_BTR_SAM;
#endif
canllinfo("Setting CANxBTR= 0x%08x\n", btr);
caninfo("Setting CANxBTR= 0x%08x\n", btr);
can_putreg(priv, LPC17_CAN_BTR_OFFSET, btr); /* Set bit timing */
return OK;
}
@ -1224,7 +1224,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
irqstate_t flags;
uint32_t regval;
canllinfo("CAN%d\n", port);
caninfo("CAN%d\n", port);
flags = enter_critical_section();

24
arch/arm/src/lpc17xx/lpc17_usbdev.c
View file

@ -534,7 +534,7 @@ static struct lpc17_dmadesc_s g_usbddesc[CONFIG_LPC17_USBDEV_NDMADESCRIPTORS];
#ifdef CONFIG_LPC17_USBDEV_REGDEBUG
static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@ -584,7 +584,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
ullinfo("[repeats %d more times]\n", count);
uinfo("[repeats %d more times]\n", count);
}
}
@ -1079,8 +1079,9 @@ static int lpc17_wrrequest(struct lpc17_ep_s *privep)
return OK;
}
ullinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
uinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
privep->epphy, privreq, privreq->req.len, privreq->req.xfrd,
privep->txnullpkt);
/* Ignore any attempt to send a zero length packet on anything but EP0IN */
@ -1188,8 +1189,8 @@ static int lpc17_rdrequest(struct lpc17_ep_s *privep)
return OK;
}
ullinfo("len=%d xfrd=%d nullpkt=%d\n",
privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
uinfo("len=%d xfrd=%d nullpkt=%d\n",
privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to receive a zero length packet */
@ -1596,8 +1597,8 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@ -1742,7 +1743,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
ullinfo("test mode: %d\n", index);
uinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2324,7 +2325,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
}
else
{
ullinfo("Pending data on OUT endpoint\n");
uinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@ -2803,7 +2804,8 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
uinfo("req=%p callback=%p buf=%p ep=%p\n",
req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

20
arch/arm/src/lpc17xx/lpc17_usbhost.c
View file

@ -460,7 +460,7 @@ static struct lpc17_xfrinfo_s g_xfrbuffers[CONFIG_LPC17_USBHOST_NPREALLOC];
#ifdef CONFIG_LPC17_USBHOST_REGDEBUG
static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@ -510,7 +510,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
ullinfo("[repeats %d more times]\n", count);
uinfo("[repeats %d more times]\n", count);
}
}
@ -1646,7 +1646,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
intst = lpc17_getreg(LPC17_USBHOST_INTST);
regval = lpc17_getreg(LPC17_USBHOST_INTEN);
ullinfo("INST: %08x INTEN: %08x\n", intst, regval);
uinfo("INST: %08x INTEN: %08x\n", intst, regval);
pending = intst & regval;
if (pending != 0)
@ -1656,18 +1656,18 @@ static int lpc17_usbinterrupt(int irq, void *context)
if ((pending & OHCI_INT_RHSC) != 0)
{
uint32_t rhportst1 = lpc17_getreg(LPC17_USBHOST_RHPORTST1);
ullinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
uinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
if ((rhportst1 & OHCI_RHPORTST_CSC) != 0)
{
uint32_t rhstatus = lpc17_getreg(LPC17_USBHOST_RHSTATUS);
ullinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
uinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
/* If DRWE is set, Connect Status Change indicates a remote wake-up event */
if (rhstatus & OHCI_RHSTATUS_DRWE)
{
ullinfo("DRWE: Remote wake-up\n");
uinfo("DRWE: Remote wake-up\n");
}
/* Otherwise... Not a remote wake-up event */
@ -1684,7 +1684,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* Yes.. connected. */
ullinfo("Connected\n");
uinfo("Connected\n");
priv->connected = true;
priv->change = true;
@ -1714,7 +1714,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
priv->rhport.hport.speed = USB_SPEED_FULL;
}
ullinfo("Speed:%d\n", priv->rhport.hport.speed);
uinfo("Speed:%d\n", priv->rhport.hport.speed);
}
/* Check if we are now disconnected */
@ -1723,7 +1723,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* Yes.. disconnect the device */
ullinfo("Disconnected\n");
uinfo("Disconnected\n");
priv->connected = false;
priv->change = true;
@ -3458,7 +3458,7 @@ static int lpc17_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */

28
arch/arm/src/lpc214x/lpc214x_usbdev.c
View file

@ -539,7 +539,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
{
if (count == 4)
{
ullinfo("...\n");
uinfo("...\n");
}
return val;
@ -556,7 +556,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
ullinfo("[repeats %d more times]\n", count-3);
uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -568,7 +568,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
/* Show the register value read */
ullinfo("%08x->%08x\n", addr, val);
uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@ -586,7 +586,7 @@ static void lpc214x_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
ullinfo("%08x<-%08x\n", addr, val);
uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@ -1021,8 +1021,9 @@ static int lpc214x_wrrequest(struct lpc214x_ep_s *privep)
return OK;
}
ullinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
uinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
privep->epphy, privreq, privreq->req.len, privreq->req.xfrd,
privep->txnullpkt);
/* Ignore any attempt to send a zero length packet on anything but EP0IN */
@ -1130,8 +1131,8 @@ static int lpc214x_rdrequest(struct lpc214x_ep_s *privep)
return OK;
}
ullinfo("len=%d xfrd=%d nullpkt=%d\n",
privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
uinfo("len=%d xfrd=%d nullpkt=%d\n",
privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to receive a zero length packet */
@ -1552,8 +1553,8 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@ -1697,7 +1698,7 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
ullinfo("test mode: %d\n", index);
uinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2287,7 +2288,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context)
}
else
{
ullinfo("Pending data on OUT endpoint\n");
uinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@ -2763,7 +2764,8 @@ static int lpc214x_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
uinfo("req=%p callback=%p buf=%p ep=%p\n",
req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

8
arch/arm/src/lpc31xx/lpc31_ehci.c
View file

@ -826,7 +826,7 @@ static uint32_t lpc31_swap32(uint32_t value)
static void lpc31_printreg(volatile uint32_t *regaddr, uint32_t regval,
bool iswrite)
{
ullinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@ -877,7 +877,7 @@ static void lpc31_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw
{
/* No.. More than one. */
ullinfo("[repeats %d more times]\n", count);
uinfo("[repeats %d more times]\n", count);
}
}
@ -3370,7 +3370,7 @@ static int lpc31_ehci_interrupt(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@ -4680,7 +4680,7 @@ static int lpc31_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */

6
arch/arm/src/lpc31xx/lpc31_spi.c
View file

@ -207,7 +207,7 @@ static bool spi_checkreg(bool wr, uint32_t value, uint32_t address)
{
if (g_ntimes > 0)
{
spillinfo("...[Repeats %d times]...\n", g_ntimes);
spiinfo("...[Repeats %d times]...\n", g_ntimes);
}
g_wrlast = wr;
@ -239,7 +239,7 @@ static void spi_putreg(uint32_t value, uint32_t address)
{
if (spi_checkreg(true, value, address))
{
spillinfo("%08x<-%08x\n", address, value);
spiinfo("%08x<-%08x\n", address, value);
}
putreg32(value, address);
}
@ -265,7 +265,7 @@ static uint32_t spi_getreg(uint32_t address)
uint32_t value = getreg32(address);
if (spi_checkreg(false, value, address))
{
spillinfo("%08x->%08x\n", address, value);
spiinfo("%08x->%08x\n", address, value);
}
return value;
}

16
arch/arm/src/lpc31xx/lpc31_usbdev.c
View file

@ -501,7 +501,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
{
if (count == 4)
{
ullinfo("...\n");
uinfo("...\n");
}
return val;
@ -518,7 +518,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
ullinfo("[repeats %d more times]\n", count-3);
uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -530,7 +530,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
/* Show the register value read */
ullinfo("%08x->%08x\n", addr, val);
uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@ -548,7 +548,7 @@ static void lpc31_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
ullinfo("%08x<-%08x\n", addr, val);
uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@ -1183,8 +1183,8 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
if ((ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
@ -1323,7 +1323,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
ullinfo("test mode: %d\n", index);
uinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2083,7 +2083,7 @@ static int lpc31_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

8
arch/arm/src/lpc43xx/lpc43_ehci.c
View file

@ -817,7 +817,7 @@ static uint32_t lpc43_swap32(uint32_t value)
static void lpc43_printreg(volatile uint32_t *regaddr, uint32_t regval,
bool iswrite)
{
ullinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@ -868,7 +868,7 @@ static void lpc43_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw
{
/* No.. More than one. */
ullinfo("[repeats %d more times]\n", count);
uinfo("[repeats %d more times]\n", count);
}
}
@ -3207,7 +3207,7 @@ static int lpc43_ehci_interrupt(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@ -4511,7 +4511,7 @@ static int lpc43_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */

84
arch/arm/src/lpc43xx/lpc43_ethernet.c
View file

@ -704,7 +704,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
if (count == 4)
{
nllinfo("...\n");
ninfo("...\n");
}
return val;
@ -721,7 +721,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
nllinfo("[repeats %d more times]\n", count-3);
ninfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -733,7 +733,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
/* Show the register value read */
nllinfo("%08x->%08x\n", addr, val);
ninfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@ -760,7 +760,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
nllinfo("%08x<-%08x\n", addr, val);
ninfo("%08x<-%08x\n", addr, val);
/* Write the value */
@ -947,8 +947,8 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
txdesc = priv->txhead;
txfirst = txdesc;
nllinfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
@ -964,7 +964,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
bufcount = (priv->dev.d_len + (CONFIG_LPC43_ETH_BUFSIZE-1)) / CONFIG_LPC43_ETH_BUFSIZE;
lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_LPC43_ETH_BUFSIZE;
nllinfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
/* Set the first segment bit in the first TX descriptor */
@ -1074,8 +1074,8 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
priv->inflight++;
nllinfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
ninfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
/* If all TX descriptors are in-flight, then we have to disable receive interrupts
* too. This is because receive events can trigger more un-stoppable transmit
@ -1373,7 +1373,7 @@ static void lpc43_freesegment(FAR struct lpc43_ethmac_s *priv,
struct eth_rxdesc_s *rxdesc;
int i;
nllinfo("rxfirst: %p segments: %d\n", rxfirst, segments);
ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
/* Set OWN bit in RX descriptors. This gives the buffers back to DMA */
@ -1431,8 +1431,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
uint8_t *buffer;
int i;
nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
/* Check if there are free buffers. We cannot receive new frames in this
* design unless there is at least one free buffer.
@ -1440,7 +1440,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
if (!lpc43_isfreebuffer(priv))
{
nllerr("ERROR: No free buffers\n");
nerr("ERROR: No free buffers\n");
return -ENOMEM;
}
@ -1497,7 +1497,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
rxcurr = priv->rxcurr;
}
nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
/* Check if any errors are reported in the frame */
@ -1536,8 +1536,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3;
lpc43_freesegment(priv, rxcurr, priv->segments);
nllinfo("rxhead: %p d_buf: %p d_len: %d\n",
priv->rxhead, dev->d_buf, dev->d_len);
ninfo("rxhead: %p d_buf: %p d_len: %d\n",
priv->rxhead, dev->d_buf, dev->d_len);
return OK;
}
@ -1563,8 +1563,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
priv->rxhead = rxdesc;
nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
return -EAGAIN;
}
@ -1632,7 +1632,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllinfo("IPv4 frame\n");
ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1672,7 +1672,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllinfo("Iv6 frame\n");
ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1709,7 +1709,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllinfo("ARP frame\n");
ninfo("ARP frame\n");
/* Handle ARP packet */
@ -1768,8 +1768,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
int i;
nllinfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
ninfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
/* Scan for "in-flight" descriptors owned by the CPU */
@ -1784,8 +1784,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
* TX descriptors.
*/
nllinfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
ninfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
DEBUGASSERT(txdesc->tdes2 != 0);
@ -1837,8 +1837,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
priv->txtail = txdesc;
nllinfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
ninfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
}
}
@ -1975,7 +1975,7 @@ static inline void lpc43_interrupt_process(FAR struct lpc43_ethmac_s *priv)
{
/* Just let the user know what happened */
nllerr("ERROR: Abnormal event(s): %08x\n", dmasr);
nerr("ERROR: Abnormal event(s): %08x\n", dmasr);
/* Clear all pending abnormal events */
@ -2179,7 +2179,7 @@ static void lpc43_txtimeout_expiry(int argc, uint32_t arg, ...)
{
FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg;
nllinfo("Timeout!\n");
ninfo("Timeout!\n");
#ifdef CONFIG_NET_NOINTS
/* Disable further Ethernet interrupts. This will prevent some race
@ -2647,8 +2647,8 @@ static int lpc43_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Add the MAC address to the hardware multicast hash table */
@ -2704,8 +2704,8 @@ static int lpc43_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Remove the MAC address to the hardware multicast hash table */
@ -3718,11 +3718,11 @@ static void lpc43_macaddress(FAR struct lpc43_ethmac_s *priv)
FAR struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address high register */
@ -3925,12 +3925,12 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Reset the Ethernet block */
nllinfo("Reset the Ethernet block\n");
ninfo("Reset the Ethernet block\n");
lpc43_ethreset(priv);
/* Initialize the PHY */
nllinfo("Initialize the PHY\n");
ninfo("Initialize the PHY\n");
ret = lpc43_phyinit(priv);
if (ret < 0)
{
@ -3945,7 +3945,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Initialize the MAC and DMA */
nllinfo("Initialize the MAC and DMA\n");
ninfo("Initialize the MAC and DMA\n");
ret = lpc43_macconfig(priv);
if (ret < 0)
{
@ -3966,7 +3966,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Enable normal MAC operation */
nllinfo("Enable normal operation\n");
ninfo("Enable normal operation\n");
return lpc43_macenable(priv);
}

2
arch/arm/src/lpc43xx/lpc43_idle.c
View file

@ -98,7 +98,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
_llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */

4
arch/arm/src/lpc43xx/lpc43_rit.c
View file

@ -201,8 +201,8 @@ void up_timer_initialize(void)
mask_bits++;
}
tmrllinfo("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n",
mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int);
tmrinfo("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n",
mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int);
/* Set the mask and compare value so we get interrupts every
* RIT_TIMER_RESOLUTION cycles.

16
arch/arm/src/lpc43xx/lpc43_usb0dev.c
View file

@ -522,7 +522,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
if (count == 4)
{
usbllinfo("...\n");
usbinfo("...\n");
}
return val;
@ -539,7 +539,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
usbllinfo("[repeats %d more times]\n", count-3);
usbinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -551,7 +551,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
/* Show the register value read */
usbllinfo("%08x->%08x\n", addr, val);
usbinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@ -569,7 +569,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
usbllinfo("%08x<-%08x\n", addr, val);
usbinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@ -1228,8 +1228,8 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
priv->ep0buf_len = len;
ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl->type, ctrl->req, value, index, len);
uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
ctrl->type, ctrl->req, value, index, len);
/* Starting a control request - update state */
@ -1393,7 +1393,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
ullinfo("test mode: %d\n", index);
uinfo("test mode: %d\n", index);
}
else if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2206,7 +2206,7 @@ static int lpc43_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif

2
arch/arm/src/nuc1xx/nuc_idle.c
View file

@ -99,7 +99,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
_llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */

2
arch/arm/src/sam34/sam4cm_oneshot.c
View file

@ -91,7 +91,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
tmrllinfo("Expired...\n");
tmrinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.

32
arch/arm/src/sam34/sam4cm_tc.c
View file

@ -394,21 +394,21 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg)
uintptr_t base;
base = chan->base;
tmrllinfo("TC%d [%08x]: %s\n", chan->chan, (int)base, msg);
tmrllinfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET),
getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET));
tmrinfo("TC%d [%08x]: %s\n", chan->chan, (int)base, msg);
tmrinfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET),
getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET));
base = chan->base;
tmrllinfo("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg);
tmrllinfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET),
getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET));
tmrllinfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n",
getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET),
getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET));
tmrllinfo(" IMR: %08x\n",
getreg32(base+SAM_TC_IMR_OFFSET));
tmrinfo("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg);
tmrinfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET),
getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET));
tmrinfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n",
getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET),
getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET));
tmrinfo(" IMR: %08x\n",
getreg32(base+SAM_TC_IMR_OFFSET));
}
#endif
@ -451,7 +451,7 @@ static bool sam_checkreg(struct sam_chan_s *chan, bool wr, uint32_t regaddr,
{
/* Yes... show how many times we did it */
tmrllinfo("...[Repeats %d times]...\n", chan->ntimes);
tmrinfo("...[Repeats %d times]...\n", chan->ntimes);
}
/* Save information about the new access */
@ -485,7 +485,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAM34_TC_REGDEBUG
if (sam_checkreg(chan, false, regaddr, regval))
{
tmrllinfo("%08x->%08x\n", regaddr, regval);
tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -508,7 +508,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset,
#ifdef CONFIG_SAM34_TC_REGDEBUG
if (sam_checkreg(chan, true, regaddr, regval))
{
tmrllinfo("%08x<-%08x\n", regaddr, regval);
tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif

2
arch/arm/src/sam34/sam4cm_tickless.c
View file

@ -197,7 +197,7 @@ static struct sam_tickless_s g_tickless;
static void sam_oneshot_handler(void *arg)
{
tmrllinfo("Expired...\n");
tmrinfo("Expired...\n");
sched_timer_expiration();
}

30
arch/arm/src/sam34/sam_emac.c
View file

@ -490,7 +490,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
nllinfo("...[Repeats %d times]...\n", priv->ntimes);
ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -522,7 +522,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
if (sam_checkreg(priv, false, regval, address))
{
nllinfo("%08x->%08x\n", address, regval);
ninfo("%08x->%08x\n", address, regval);
}
return regval;
@ -543,7 +543,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address,
{
if (sam_checkreg(priv, true, regval, address))
{
nllinfo("%08x<-%08x\n", address, regval);
ninfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);
@ -753,7 +753,7 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
nllinfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
@ -830,7 +830,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
nllinfo("Disabling RX interrupts\n");
ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
}
@ -1010,7 +1010,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
sam_cmcc_invalidate((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
nllinfo("rxndx: %d\n", rxndx);
ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@ -1060,7 +1060,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
nllerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@ -1107,7 +1107,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@ -1132,7 +1132,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
@ -1167,7 +1167,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
nllinfo("rxndx: %d\n", priv->rxndx);
ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@ -1222,7 +1222,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllinfo("IPv4 frame\n");
ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1262,7 +1262,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllinfo("Iv6 frame\n");
ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1299,7 +1299,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllinfo("ARP frame\n");
ninfo("ARP frame\n");
/* Handle ARP packet */
@ -1442,7 +1442,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | EMAC_INT_UNUSED);
nllinfo("isr: %08x pending: %08x\n", isr, pending);
ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@ -2077,7 +2077,7 @@ static int sam_ifdown(struct net_driver_s *dev)
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
{
nllinfo("ifup: %d\n", priv->ifup);
ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */

6
arch/arm/src/sam34/sam_hsmci.c
View file

@ -1320,7 +1320,7 @@ static int sam_interrupt(int irq, void *context)
{
/* Yes.. Was the error some kind of timeout? */
mcllinfo("ERROR: events: %08x SR: %08x\n",
mcllerr("ERROR: events: %08x SR: %08x\n",
priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
@ -2628,7 +2628,7 @@ static void sam_callback(void *arg)
{
/* Yes.. queue it */
mcllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
@ -2743,7 +2743,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
mcllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */

10
arch/arm/src/sam34/sam_rtt.c
View file

@ -204,7 +204,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
if (count == 4)
{
tmrllinfo("...\n");
tmrinfo("...\n");
}
return val;
@ -221,7 +221,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
tmrllinfo("[repeats %d more times]\n", count-3);
tmrinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -233,7 +233,7 @@ static uint32_t sam34_getreg(uint32_t addr)
/* Show the register value read */
tmrllinfo("%08lx->%08lx\n", addr, val);
tmrinfo("%08lx->%08lx\n", addr, val);
return val;
}
#endif
@ -251,7 +251,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
tmrllinfo("%08lx<-%08lx\n", addr, val);
tmrinfo("%08lx<-%08lx\n", addr, val);
/* Write the value */
@ -277,7 +277,7 @@ static int sam34_interrupt(int irq, FAR void *context)
{
FAR struct sam34_lowerhalf_s *priv = &g_tcdev;
tmrllinfo("Entry\n");
tmrinfo("Entry\n");
DEBUGASSERT(irq == SAM_IRQ_RTT);
/* Check if the interrupt is really pending */

4
arch/arm/src/sam34/sam_spi.c
View file

@ -458,7 +458,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi,
#ifdef CONFIG_SAM34_SPI_REGDEBUG
if (spi_checkreg(spi, false, value, address))
{
spillinfo("%08x->%08x\n", address, value);
spiinfo("%08x->%08x\n", address, value);
}
#endif
@ -481,7 +481,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
#ifdef CONFIG_SAM34_SPI_REGDEBUG
if (spi_checkreg(spi, true, value, address))
{
spillinfo("%08x<-%08x\n", address, value);
spiinfo("%08x<-%08x\n", address, value);
}
#endif

8
arch/arm/src/sam34/sam_tc.c
View file

@ -185,7 +185,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
if (count == 4)
{
tmrllinfo("...\n");
tmrinfo("...\n");
}
return val;
@ -202,7 +202,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
tmrllinfo("[repeats %d more times]\n", count-3);
tmrinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -214,7 +214,7 @@ static uint32_t sam34_getreg(uint32_t addr)
/* Show the register value read */
tmrllinfo("%08lx->%08lx\n", addr, val);
tmrinfo("%08lx->%08lx\n", addr, val);
return val;
}
#endif
@ -232,7 +232,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
tmrllinfo("%08lx<-%08lx\n", addr, val);
tmrinfo("%08lx<-%08lx\n", addr, val);
/* Write the value */

12
arch/arm/src/sam34/sam_twi.c
View file

@ -277,7 +277,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
i2cllinfo("...[Repeats %d times]...\n", priv->ntimes);
i2cinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -309,7 +309,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address)
if (twi_checkreg(priv, false, value, address))
{
i2cllinfo("%08x->%08x\n", address, value);
i2cinfo("%08x->%08x\n", address, value);
}
return value;
@ -330,7 +330,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address,
{
if (twi_checkreg(priv, true, value, address))
{
i2cllinfo("%08x<-%08x\n", address, value);
i2cinfo("%08x<-%08x\n", address, value);
}
putreg32(value, address);
@ -390,9 +390,9 @@ static int twi_wait(struct twi_dev_s *priv)
do
{
i2cllinfo("TWI%d Waiting...\n", priv->twi);
i2cinfo("TWI%d Waiting...\n", priv->twi);
twi_takesem(&priv->waitsem);
i2cllinfo("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
i2cinfo("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
}
while (priv->result == -EBUSY);
@ -449,7 +449,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
imr = twi_getrel(priv, SAM_TWI_IMR_OFFSET);
pending = sr & imr;
i2cllinfo("TWI%d pending: %08x\n", priv->twi, pending);
i2cinfo("TWI%d pending: %08x\n", priv->twi, pending);
msg = priv->msg;

47
arch/arm/src/sam34/sam_udp.c
View file

@ -606,7 +606,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
#ifdef CONFIG_SAM34_UDP_REGDEBUG
static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
_llinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
_info("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@ -657,7 +657,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
/* No.. More than one. */
_llinfo("[repeats %d more times]\n", count);
_info("[repeats %d more times]\n", count);
}
}
@ -737,15 +737,15 @@ static void sam_dumpep(struct sam_usbdev_s *priv, uint8_t epno)
{
/* Global Registers */
_llinfo("Global Registers:\n");
_llinfo(" FRMNUM: %08x\n", sam_getreg(SAM_UDP_FRMNUM));
_llinfo("GLBSTAT: %08x\n", sam_getreg(SAM_UDP_GLBSTAT));
_llinfo(" FADDR: %08x\n", sam_getreg(SAM_UDP_FADDR));
_llinfo(" IMR: %08x\n", sam_getreg(SAM_UDP_IMR));
_llinfo(" ISR: %08x\n", sam_getreg(SAM_UDP_ISR));
_llinfo(" RSTEP: %08x\n", sam_getreg(SAM_UDP_RSTEP));
_llinfo(" TXVC: %08x\n", sam_getreg(SAM_UDP_TXVC));
_llinfo(" CSR[%d]: %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno)));
_info("Global Registers:\n");
_info(" FRMNUM: %08x\n", sam_getreg(SAM_UDP_FRMNUM));
_info("GLBSTAT: %08x\n", sam_getreg(SAM_UDP_GLBSTAT));
_info(" FADDR: %08x\n", sam_getreg(SAM_UDP_FADDR));
_info(" IMR: %08x\n", sam_getreg(SAM_UDP_IMR));
_info(" ISR: %08x\n", sam_getreg(SAM_UDP_ISR));
_info(" RSTEP: %08x\n", sam_getreg(SAM_UDP_RSTEP));
_info(" TXVC: %08x\n", sam_getreg(SAM_UDP_TXVC));
_info(" CSR[%d]: %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno)));
}
#endif
@ -968,9 +968,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
return -ENOENT;
}
ullinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
epno, privreq, privreq->req.len, privreq->req.xfrd,
privreq->inflight, privep->zlpneeded);
uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
epno, privreq, privreq->req.len, privreq->req.xfrd,
privreq->inflight, privep->zlpneeded);
/* Handle any bytes in flight. */
@ -1139,8 +1139,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
return -ENOENT;
}
ullinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
uinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
/* Ignore any attempt to receive a zero length packet */
@ -1408,8 +1408,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@ -1572,7 +1572,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
{
/* Special case recipient=device test mode */
ullinfo("test mode: %d\n", index.w);
uinfo("test mode: %d\n", index.w);
}
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -2946,7 +2946,7 @@ static int sam_ep_disable(struct usbdev_ep_s *ep)
if (!ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
ullerr("ERROR: ep=%p\n", ep);
uerr("ERROR: ep=%p\n", ep);
return -EINVAL;
}
#endif
@ -3079,7 +3079,8 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@ -3091,7 +3092,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
ullerr("ERROR: driver=%p\n", priv->driver);
uerr("ERROR: driver=%p\n", priv->driver);
return -ESHUTDOWN;
}
#endif
@ -3119,7 +3120,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
* queue. They will stay queuee until the stall is cleared.
*/
ullinfo("Pending stall clear\n");
uinfo("Pending stall clear\n");
sam_req_enqueue(&privep->pendq, privreq);
usbtrace(TRACE_INREQQUEUED(epno), req->len);
ret = OK;

8
arch/arm/src/sam34/sam_wdt.c
View file

@ -187,7 +187,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
if (count == 4)
{
wdllinfo("...\n");
wdinfo("...\n");
}
return val;
@ -204,7 +204,7 @@ static uint32_t sam34_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
wdllinfo("[repeats %d more times]\n", count-3);
wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -216,7 +216,7 @@ static uint32_t sam34_getreg(uint32_t addr)
/* Show the register value read */
wdllinfo("%08x->%08x\n", addr, val);
wdinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@ -234,7 +234,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
wdllinfo("%08x<-%08x\n", addr, val);
wdinfo("%08x<-%08x\n", addr, val);
/* Write the value */

8
arch/arm/src/sama5/sam_adc.c
View file

@ -548,7 +548,7 @@ static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr,
{
/* Yes... show how many times we did it */
allinfo("...[Repeats %d times]...\n", priv->ntimes);
ainfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -729,7 +729,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
struct sam_adc_s *priv = (struct sam_adc_s *)arg;
int ret;
allinfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
ainfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
DEBUGASSERT(priv->ready);
/* Check of the bottom half is keeping up with us.
@ -2191,7 +2191,7 @@ uint32_t sam_adc_getreg(struct sam_adc_s *priv, uintptr_t address)
if (sam_adc_checkreg(priv, false, regval, address))
{
allinfo("%08x->%08x\n", address, regval);
ainfo("%08x->%08x\n", address, regval);
}
return regval;
@ -2211,7 +2211,7 @@ void sam_adc_putreg(struct sam_adc_s *priv, uintptr_t address, uint32_t regval)
{
if (sam_adc_checkreg(priv, true, regval, address))
{
allinfo("%08x<-%08x\n", address, regval);
ainfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);

98
arch/arm/src/sama5/sam_can.c
View file

@ -371,7 +371,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset)
{
if (priv->count == 4)
{
canllinfo("...\n");
caninfo("...\n");
}
return regval;
@ -388,7 +388,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset)
{
/* Yes.. then show how many times the value repeated */
canllinfo("[repeats %d more times]\n", priv->count - 3);
caninfo("[repeats %d more times]\n", priv->count - 3);
}
/* Save the new address, value, and count */
@ -400,7 +400,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset)
/* Show the register value read */
canllinfo("%08x->%08x\n", regaddr, regval);
caninfo("%08x->%08x\n", regaddr, regval);
return regval;
}
@ -437,7 +437,7 @@ static void can_putreg(FAR struct sam_can_s *priv, int offset, uint32_t regval)
/* Show the register value being written */
canllinfo("%08x<-%08x\n", regaddr, regval);
caninfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */
@ -474,29 +474,29 @@ static void can_dumpctrlregs(FAR struct sam_can_s *priv, FAR const char *msg)
if (msg)
{
canllinfo("Control Registers: %s\n", msg);
caninfo("Control Registers: %s\n", msg);
}
else
{
canllinfo("Control Registers:\n");
caninfo("Control Registers:\n");
}
/* CAN control and status registers */
canllinfo(" MR: %08x IMR: %08x SR: %08x\n",
getreg32(config->base + SAM_CAN_MR_OFFSET),
getreg32(config->base + SAM_CAN_IMR_OFFSET),
getreg32(config->base + SAM_CAN_SR_OFFSET));
caninfo(" MR: %08x IMR: %08x SR: %08x\n",
getreg32(config->base + SAM_CAN_MR_OFFSET),
getreg32(config->base + SAM_CAN_IMR_OFFSET),
getreg32(config->base + SAM_CAN_SR_OFFSET));
canllinfo(" BR: %08x TIM: %08x TIMESTP: %08x\n",
getreg32(config->base + SAM_CAN_BR_OFFSET),
getreg32(config->base + SAM_CAN_TIM_OFFSET),
getreg32(config->base + SAM_CAN_TIMESTP_OFFSET));
caninfo(" BR: %08x TIM: %08x TIMESTP: %08x\n",
getreg32(config->base + SAM_CAN_BR_OFFSET),
getreg32(config->base + SAM_CAN_TIM_OFFSET),
getreg32(config->base + SAM_CAN_TIMESTP_OFFSET));
canllinfo(" ECR: %08x WPMR: %08x WPSR: %08x\n",
getreg32(config->base + SAM_CAN_ECR_OFFSET),
getreg32(config->base + SAM_CAN_TCR_OFFSET),
getreg32(config->base + SAM_CAN_ACR_OFFSET));
caninfo(" ECR: %08x WPMR: %08x WPSR: %08x\n",
getreg32(config->base + SAM_CAN_ECR_OFFSET),
getreg32(config->base + SAM_CAN_TCR_OFFSET),
getreg32(config->base + SAM_CAN_ACR_OFFSET));
}
#endif
@ -523,30 +523,30 @@ static void can_dumpmbregs(FAR struct sam_can_s *priv, FAR const char *msg)
if (msg)
{
canllinfo("Mailbox Registers: %s\n", msg);
caninfo("Mailbox Registers: %s\n", msg);
}
else
{
canllinfo("Mailbox Registers:\n");
caninfo("Mailbox Registers:\n");
}
for (i = 0; i < SAM_CAN_NMAILBOXES; i++)
{
mbbase = config->base + SAM_CAN_MBn_OFFSET(i);
canllinfo(" MB%d:\n", i);
caninfo(" MB%d:\n", i);
/* CAN mailbox registers */
canllinfo(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n",
getreg32(mbbase + SAM_CAN_MMR_OFFSET),
getreg32(mbbase + SAM_CAN_MAM_OFFSET),
getreg32(mbbase + SAM_CAN_MID_OFFSET),
getreg32(mbbase + SAM_CAN_MFID_OFFSET));
caninfo(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n",
getreg32(mbbase + SAM_CAN_MMR_OFFSET),
getreg32(mbbase + SAM_CAN_MAM_OFFSET),
getreg32(mbbase + SAM_CAN_MID_OFFSET),
getreg32(mbbase + SAM_CAN_MFID_OFFSET));
canllinfo(" MSR: %08x MDL: %08x MDH: %08x\n",
getreg32(mbbase + SAM_CAN_MSR_OFFSET),
getreg32(mbbase + SAM_CAN_MDL_OFFSET),
getreg32(mbbase + SAM_CAN_MDH_OFFSET));
caninfo(" MSR: %08x MDL: %08x MDH: %08x\n",
getreg32(mbbase + SAM_CAN_MSR_OFFSET),
getreg32(mbbase + SAM_CAN_MDL_OFFSET),
getreg32(mbbase + SAM_CAN_MDH_OFFSET));
}
}
#endif
@ -783,7 +783,7 @@ static void can_reset(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
canllinfo("CAN%d\n", config->port);
caninfo("CAN%d\n", config->port);
UNUSED(config);
/* Get exclusive access to the CAN peripheral */
@ -840,7 +840,7 @@ static int can_setup(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
canllinfo("CAN%d pid: %d\n", config->port, config->pid);
caninfo("CAN%d pid: %d\n", config->port, config->pid);
/* Get exclusive access to the CAN peripheral */
@ -851,7 +851,7 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = can_hwinitialize(priv);
if (ret < 0)
{
canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
return ret;
}
@ -863,7 +863,7 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = irq_attach(config->pid, config->handler);
if (ret < 0)
{
canllerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
canerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
return ret;
}
@ -872,7 +872,7 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = can_recvsetup(priv);
if (ret < 0)
{
canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
return ret;
}
@ -918,7 +918,7 @@ static void can_shutdown(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
canllinfo("CAN%d\n", config->port);
caninfo("CAN%d\n", config->port);
/* Get exclusive access to the CAN peripheral */
@ -957,7 +957,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
FAR struct sam_can_s *priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
canllinfo("CAN%d enable: %d\n", priv->config->port, enable);
caninfo("CAN%d enable: %d\n", priv->config->port, enable);
/* Enable/disable the mailbox interrupts from all receive mailboxes */
@ -990,7 +990,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
FAR struct sam_can_s *priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
canllinfo("CAN%d enable: %d\n", priv->config->port, enable);
caninfo("CAN%d enable: %d\n", priv->config->port, enable);
/* Get exclusive access to the CAN peripheral */
@ -1091,9 +1091,9 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
canllinfo("CAN%d\n", priv->config->port);
canllinfo("CAN%d ID: %d DLC: %d\n",
priv->config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
caninfo("CAN%d\n", priv->config->port);
caninfo("CAN%d ID: %d DLC: %d\n",
priv->config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
/* Get exclusive access to the CAN peripheral */
@ -1327,7 +1327,7 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx,
ret = can_receive(dev, &hdr, (FAR uint8_t *)md);
if (ret < 0)
{
canllerr("ERROR: can_receive failed: %d\n", ret);
canerr("ERROR: can_receive failed: %d\n", ret);
}
/* Set the MTCR flag in the CAN_MCRx register. This clears the
@ -1422,9 +1422,9 @@ static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx)
case CAN_MMR_MOT_CONSUMER: /* Consumer Mailbox */
case CAN_MMR_MOT_PRODUCER: /* Producer Mailbox */
case CAN_MMR_MOT_DISABLED: /* Mailbox is disabled */
canllerr("ERROR: CAN%d MB%d: Unsupported or invalid mailbox type\n",
priv->config->port, mbndx);
canllerr(" MSR: %08x MMR: %08x\n", msr, mmr);
canerr("ERROR: CAN%d MB%d: Unsupported or invalid mailbox type\n",
priv->config->port, mbndx);
canerr(" MSR: %08x MMR: %08x\n", msr, mmr);
break;
}
}
@ -1515,8 +1515,8 @@ static void can_interrupt(FAR struct can_dev_s *dev)
if ((pending & ~CAN_INT_MBALL) != 0)
{
canllerr("ERROR: CAN%d system interrupt, SR=%08x IMR=%08x\n",
priv->config->port, sr, imr);
canerr("ERROR: CAN%d system interrupt, SR=%08x IMR=%08x\n",
priv->config->port, sr, imr);
}
}
@ -1773,7 +1773,7 @@ static int can_autobaud(struct sam_can_s *priv)
uint32_t regval;
int ret;
canllinfo("CAN%d\n", config->port);
caninfo("CAN%d\n", config->port);
/* The CAN controller can start listening to the network in Autobaud Mode.
* In this case, the error counters are locked and a mailbox may be
@ -1843,7 +1843,7 @@ static int can_hwinitialize(struct sam_can_s *priv)
uint32_t mck;
int ret;
canllinfo("CAN%d\n", config->port);
caninfo("CAN%d\n", config->port);
/* Configure CAN pins */

8
arch/arm/src/sama5/sam_ehci.c
View file

@ -628,7 +628,7 @@ static uint32_t sam_swap32(uint32_t value)
static void sam_printreg(volatile uint32_t *regaddr, uint32_t regval,
bool iswrite)
{
ullinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@ -679,7 +679,7 @@ static void sam_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool iswri
{
/* No.. More than one. */
ullinfo("[repeats %d more times]\n", count);
uinfo("[repeats %d more times]\n", count);
}
}
@ -3180,7 +3180,7 @@ static int sam_ehci_tophalf(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@ -4493,7 +4493,7 @@ static int sam_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */

176
arch/arm/src/sama5/sam_emaca.c
View file

@ -461,7 +461,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
nllinfo("...[Repeats %d times]...\n", priv->ntimes);
ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -493,7 +493,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
if (sam_checkreg(priv, false, regval, address))
{
nllinfo("%08x->%08x\n", address, regval);
ninfo("%08x->%08x\n", address, regval);
}
return regval;
@ -514,7 +514,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address,
{
if (sam_checkreg(priv, true, regval, address))
{
nllinfo("%08x<-%08x\n", address, regval);
ninfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);
@ -607,7 +607,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
nllerr("ERROR: Failed to allocate TX descriptors\n");
nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@ -617,7 +617,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
nllerr("ERROR: Failed to allocate RX descriptors\n");
nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -628,7 +628,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
nllerr("ERROR: Failed to allocate TX buffer\n");
nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -637,7 +637,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
nllerr("ERROR: Failed to allocate RX buffer\n");
nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -725,14 +725,14 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
nllinfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > EMAC_TX_UNITSIZE)
{
nllerr("ERROR: Packet too big: %d\n", dev->d_len);
nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@ -744,7 +744,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
nllerr("ERROR: No free TX descriptors\n");
nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@ -806,7 +806,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
nllinfo("Disabling RX interrupts\n");
ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
}
@ -986,7 +986,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
nllinfo("rxndx: %d\n", rxndx);
ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@ -1042,7 +1042,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@ -1097,7 +1097,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@ -1128,11 +1128,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
nllerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
return -E2BIG;
}
@ -1172,7 +1172,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
nllinfo("rxndx: %d\n", priv->rxndx);
ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@ -1227,7 +1227,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllinfo("IPv4 frame\n");
ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1267,7 +1267,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllinfo("Iv6 frame\n");
ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1304,7 +1304,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllinfo("ARP frame\n");
ninfo("ARP frame\n");
/* Handle ARP packet */
@ -1449,7 +1449,7 @@ static int sam_emac_interrupt(int irq, void *context)
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | EMAC_INT_UNUSED);
nllinfo("isr: %08x pending: %08x\n", isr, pending);
ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@ -1475,7 +1475,7 @@ static int sam_emac_interrupt(int irq, void *context)
clrbits = EMAC_TSR_RLES | sam_txinuse(priv);
sam_txreset(priv);
nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_TE;
@ -1486,7 +1486,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((tsr & EMAC_TSR_COL) != 0)
{
nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_COL;
}
@ -1494,7 +1494,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((tsr & EMAC_TSR_BEX) != 0)
{
nllerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
nerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_BEX;
}
@ -1509,7 +1509,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((tsr & EMAC_TSR_UND) != 0)
{
nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_UND;
}
@ -1546,7 +1546,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((rsr & EMAC_RSR_OVR) != 0)
{
nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_OVR;
}
@ -1563,7 +1563,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((rsr & EMAC_RSR_BNA) != 0)
{
nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@ -1624,7 +1624,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
{
struct sam_emac_s *priv = (struct sam_emac_s *)arg;
nllerr("ERROR: Timeout!\n");
nerr("ERROR: Timeout!\n");
/* Then reset the hardware. Just take the interface down, then back
* up again.
@ -1705,7 +1705,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the EMAC interface for normal operation. */
nllinfo("Initialize the EMAC\n");
ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@ -1723,7 +1723,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phyinit failed: %d\n", ret);
nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@ -1732,16 +1732,16 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
nllinfo("Link detected \n");
ninfo("Link detected \n");
/* Enable normal MAC operation */
nllinfo("Enable normal operation\n");
ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@ -1825,7 +1825,7 @@ static int sam_txavail(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
nllinfo("ifup: %d\n", priv->ifup);
ninfo("ifup: %d\n", priv->ifup);
/* Disable interrupts because this function may be called from interrupt
* level processing.
@ -2003,8 +2003,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2077,8 +2077,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2273,21 +2273,21 @@ static void sam_phydump(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_NCR, regval);
#ifdef CONFIG_SAMA5_EMAC_RMII
nllinfo("RMII Registers (Address %02x)\n", priv->phyaddr);
ninfo("RMII Registers (Address %02x)\n", priv->phyaddr);
#else /* defined(CONFIG_SAMA5_EMAC_MII) */
nllinfo("MII Registers (Address %02x)\n", priv->phyaddr);
ninfo("MII Registers (Address %02x)\n", priv->phyaddr);
#endif
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
nllinfo(" MCR: %04x\n", phyval);
ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
nllinfo(" MSR: %04x\n", phyval);
ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
nllinfo(" ADVERTISE: %04x\n", phyval);
ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
nllinfo(" LPR: %04x\n", phyval);
ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
nllinfo(" PHYSR: %04x\n", phyval);
ninfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@ -2410,7 +2410,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
nllinfo(" sam_phyreset\n");
ninfo(" sam_phyreset\n");
/* Enable management port */
@ -2423,7 +2423,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
nllerr("ERROR: sam_phywrite failed: %d\n", ret);
nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@ -2435,7 +2435,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
@ -2477,7 +2477,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
nllinfo("Find a valid PHY address\n");
ninfo("Find a valid PHY address\n");
/* Enable management port */
@ -2500,8 +2500,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
else
{
nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
candidate, ret);
nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@ -2522,10 +2522,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@ -2566,7 +2566,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -2581,7 +2581,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -2621,7 +2621,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -2636,7 +2636,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -2680,32 +2680,32 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYID1\n");
nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYID2\n");
nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == MII_OUI_MSB &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
{
nllinfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
nllinfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
ninfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
ninfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
nllerr("ERROR: PHY not recognized\n");
nerr("ERROR: PHY not recognized\n");
}
/* Setup control register */
@ -2713,7 +2713,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MCR\n");
nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@ -2724,7 +2724,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR\n");
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@ -2739,7 +2739,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
nllerr("ERROR: Failed to write ANAR\n");
nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
@ -2748,7 +2748,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MCR\n");
nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@ -2756,7 +2756,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR\n");
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@ -2768,11 +2768,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR\n");
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
nllinfo(" MCR: %04x\n", mcr);
ninfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@ -2782,7 +2782,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MSR\n");
nerr("ERROR: Failed to read MSR\n");
goto errout;
}
@ -2792,7 +2792,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
nllinfo("AutoNegotiate complete\n");
ninfo("AutoNegotiate complete\n");
break;
}
@ -2800,7 +2800,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
nllerr("ERROR: TimeOut\n");
nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@ -2812,7 +2812,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
nllerr("ERROR: Failed to read ANLPAR\n");
nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
@ -2902,13 +2902,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MSR: %d\n", ret);
nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
nllerr("ERROR: MSR LinkStatus: %04x\n", msr);
nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
@ -2917,7 +2917,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &physr);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYSR: %d\n", ret);
nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
@ -2955,7 +2955,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
nllinfo("Link is up\n");
ninfo("Link is up\n");
linkup = true;
errout:
@ -3024,7 +3024,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
nllerr("ERROR: sam_phyfind failed: %d\n", ret);
nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@ -3276,11 +3276,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@ -3388,7 +3388,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
nllinfo("Entry\n");
ninfo("Entry\n");
/* Enable clocking to the EMAC peripheral */

176
arch/arm/src/sama5/sam_emacb.c
View file

@ -970,7 +970,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
nllerr("ERROR: Failed to allocate TX descriptors\n");
nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@ -980,7 +980,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
nllerr("ERROR: Failed to allocate RX descriptors\n");
nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -991,7 +991,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
nllerr("ERROR: Failed to allocate TX buffer\n");
nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -1000,7 +1000,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
nllerr("ERROR: Failed to allocate RX buffer\n");
nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -1088,14 +1088,14 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
nllinfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > EMAC_TX_UNITSIZE)
{
nllerr("ERROR: Packet too big: %d\n", dev->d_len);
nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@ -1107,7 +1107,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
nllerr("ERROR: No free TX descriptors\n");
nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@ -1169,7 +1169,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
nllinfo("Disabling RX interrupts\n");
ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_RCOMP);
}
@ -1349,7 +1349,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
nllinfo("rxndx: %d\n", rxndx);
ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@ -1405,7 +1405,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@ -1460,7 +1460,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@ -1491,11 +1491,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
nllerr("ERROR: Buffer size %d; frame size %d\n",
dev->d_len, pktlen);
nerr("ERROR: Buffer size %d; frame size %d\n",
dev->d_len, pktlen);
return -E2BIG;
}
@ -1535,7 +1535,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
nllinfo("rxndx: %d\n", priv->rxndx);
ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@ -1590,7 +1590,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllinfo("IPv4 frame\n");
ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1630,7 +1630,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllinfo("Iv6 frame\n");
ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1667,7 +1667,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllinfo("ARP frame\n");
ninfo("ARP frame\n");
/* Handle ARP packet */
@ -1836,7 +1836,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET);
pending = isr & ~(imr | EMAC_INT_UNUSED);
nllinfo("isr: %08x pending: %08x\n", isr, pending);
ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@ -1862,7 +1862,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
clrbits = EMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv);
nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
regval |= EMAC_NCR_TXEN;
@ -1873,7 +1873,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_COL) != 0)
{
nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_COL;
}
@ -1881,7 +1881,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_TFC) != 0)
{
nllerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
clrbits |= EMAC_TSR_TFC;
}
@ -1896,7 +1896,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_UND) != 0)
{
nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_UND;
}
@ -1933,7 +1933,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_RXOVR) != 0)
{
nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_RXOVR;
}
@ -1950,7 +1950,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_BNA) != 0)
{
nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@ -2147,7 +2147,7 @@ static int sam_emac1_interrupt(int irq, void *context)
static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
{
nllerr("ERROR: Timeout!\n");
nerr("ERROR: Timeout!\n");
/* Reset the hardware. Just take the interface down, then back up again. */
@ -2390,7 +2390,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the EMAC interface for normal operation. */
nllinfo("Initialize the EMAC\n");
ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@ -2408,7 +2408,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phyinit failed: %d\n", ret);
nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@ -2417,16 +2417,16 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
nllinfo("Link detected \n");
ninfo("Link detected \n");
/* Enable normal MAC operation */
nllinfo("Enable normal operation\n");
ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@ -2460,7 +2460,7 @@ static int sam_ifdown(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
nllinfo("Taking the network down\n");
ninfo("Taking the network down\n");
/* Disable the EMAC interrupt */
@ -2505,7 +2505,7 @@ static int sam_ifdown(struct net_driver_s *dev)
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
{
nllinfo("ifup: %d\n", priv->ifup);
ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
@ -2758,8 +2758,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2831,8 +2831,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -3026,19 +3026,19 @@ static void sam_phydump(struct sam_emac_s *priv)
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
nllinfo("%s Registers (Address %02x)\n",
priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
ninfo("%s Registers (Address %02x)\n",
priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
nllinfo(" MCR: %04x\n", phyval);
ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
nllinfo(" MSR: %04x\n", phyval);
ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
nllinfo(" ADVERTISE: %04x\n", phyval);
ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
nllinfo(" LPR: %04x\n", phyval);
ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, priv->attr->physr, &phyval);
nllinfo(" PHYSR: %04x\n", phyval);
ninfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@ -3262,7 +3262,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
nllinfo(" sam_phyreset\n");
ninfo(" sam_phyreset\n");
/* Enable management port */
@ -3275,7 +3275,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
nllerr("ERROR: sam_phywrite failed: %d\n", ret);
nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@ -3287,7 +3287,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
@ -3329,7 +3329,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
nllinfo("Find a valid PHY address\n");
ninfo("Find a valid PHY address\n");
/* Enable management port */
@ -3352,8 +3352,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
else
{
nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
candidate, ret);
nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@ -3374,10 +3374,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, priv->attr->physr, &phyval);
nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@ -3418,7 +3418,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -3443,7 +3443,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -3483,7 +3483,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -3508,7 +3508,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -3552,33 +3552,33 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYID1\n");
nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYID2\n");
nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == priv->attr->msoui &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) ==
(uint16_t)priv->attr->lsoui)
{
nllinfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
nllinfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
ninfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
ninfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
nllerr("ERROR: PHY not recognized\n");
nerr("ERROR: PHY not recognized\n");
}
/* Setup control register */
@ -3586,7 +3586,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MCR\n");
nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@ -3597,7 +3597,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR\n");
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@ -3612,7 +3612,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
nllerr("ERROR: Failed to write ANAR\n");
nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
@ -3621,7 +3621,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MCR\n");
nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@ -3629,7 +3629,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR\n");
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@ -3641,11 +3641,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR\n");
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
nllinfo(" MCR: %04x\n", mcr);
ninfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@ -3655,7 +3655,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MSR\n");
nerr("ERROR: Failed to read MSR\n");
goto errout;
}
@ -3665,7 +3665,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
nllinfo("AutoNegotiate complete\n");
ninfo("AutoNegotiate complete\n");
break;
}
@ -3673,7 +3673,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
nllerr("ERROR: TimeOut\n");
nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@ -3685,7 +3685,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
nllerr("ERROR: Failed to read ANLPAR\n");
nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
@ -3775,13 +3775,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MSR: %d\n", ret);
nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
nllerr("ERROR: MSR LinkStatus: %04x\n", msr);
nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
@ -3790,7 +3790,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, priv->attr->physr, &physr);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYSR: %d\n", ret);
nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
@ -3828,7 +3828,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
nllinfo("Link is up\n");
ninfo("Link is up\n");
linkup = true;
errout:
@ -3897,7 +3897,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
nllerr("ERROR: sam_phyfind failed: %d\n", ret);
nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@ -4012,7 +4012,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
else
#endif
{
ninfo("ERROR: emac=%d\n", priv->attr->emac);
nerr("ERROR: emac=%d\n", priv->attr->emac);
}
}
@ -4311,11 +4311,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@ -4423,7 +4423,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
nllinfo("Entry\n");
ninfo("Entry\n");
/* Enable clocking to the EMAC peripheral */

190
arch/arm/src/sama5/sam_gmac.c
View file

@ -392,7 +392,7 @@ static bool sam_checkreg(struct sam_gmac_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
nllinfo("...[Repeats %d times]...\n", priv->ntimes);
ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -424,7 +424,7 @@ static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t address)
if (sam_checkreg(priv, false, regval, address))
{
nllinfo("%08x->%08x\n", address, regval);
ninfo("%08x->%08x\n", address, regval);
}
return regval;
@ -445,7 +445,7 @@ static void sam_putreg(struct sam_gmac_s *priv, uintptr_t address,
{
if (sam_checkreg(priv, true, regval, address))
{
nllinfo("%08x<-%08x\n", address, regval);
ninfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);
@ -538,7 +538,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->txdesc = (struct gmac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
nllerr("ERROR: Failed to allocate TX descriptors\n");
nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@ -548,7 +548,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->rxdesc = (struct gmac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
nllerr("ERROR: Failed to allocate RX descriptors\n");
nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -559,7 +559,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
nllerr("ERROR: Failed to allocate TX buffer\n");
nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -568,7 +568,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
nllerr("ERROR: Failed to allocate RX buffer\n");
nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -656,15 +656,15 @@ static int sam_transmit(struct sam_gmac_s *priv)
uint32_t regval;
uint32_t status;
nllinfo("d_len: %d txhead: %d txtail: %d\n",
dev->d_len, priv->txhead, priv->txtail);
ninfo("d_len: %d txhead: %d txtail: %d\n",
dev->d_len, priv->txhead, priv->txtail);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > GMAC_TX_UNITSIZE)
{
nllerr("ERROR: Packet too big: %d\n", dev->d_len);
nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@ -676,7 +676,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
if (sam_txfree(priv) < 1)
{
nllerr("ERROR: No free TX descriptors\n");
nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@ -738,7 +738,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
if (sam_txfree(priv) < 1)
{
nllinfo("Disabling RX interrupts\n");
ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_RCOMP);
}
@ -918,7 +918,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s));
nllinfo("rxndx: %d\n", rxndx);
ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & GMACRXD_ADDR_OWNER) != 0)
{
@ -974,7 +974,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
{
if (rxndx == priv->rxndx)
{
nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the GMAC */
@ -1029,7 +1029,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Frame size from the GMAC */
dev->d_len = (rxdesc->status & GMACRXD_STA_FRLEN_MASK);
nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@ -1060,11 +1060,11 @@ static int sam_recvframe(struct sam_gmac_s *priv)
* all of the data.
*/
nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
nllerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
return -E2BIG;
}
@ -1102,7 +1102,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
nllinfo("rxndx: %d\n", priv->rxndx);
ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@ -1157,7 +1157,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllinfo("IPv4 frame\n");
ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1197,7 +1197,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllinfo("Iv6 frame\n");
ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1234,7 +1234,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllinfo("ARP frame\n");
ninfo("ARP frame\n");
/* Handle ARP packet */
@ -1377,7 +1377,7 @@ static int sam_gmac_interrupt(int irq, void *context)
imr = sam_getreg(priv, SAM_GMAC_IMR);
pending = isr & ~(imr | GMAC_INT_UNUSED);
nllinfo("isr: %08x pending: %08x\n", isr, pending);
ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@ -1403,7 +1403,7 @@ static int sam_gmac_interrupt(int irq, void *context)
clrbits = GMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv);
nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_GMAC_NCR);
regval |= GMAC_NCR_TXEN;
@ -1414,7 +1414,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_COL) != 0)
{
nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= GMAC_TSR_COL;
}
@ -1422,7 +1422,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_TFC) != 0)
{
nllerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
nerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
clrbits |= GMAC_TSR_TFC;
}
@ -1437,7 +1437,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_UND) != 0)
{
nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= GMAC_TSR_UND;
}
@ -1445,7 +1445,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_HRESP) != 0)
{
nllerr("ERROR: HRESP not OK: %08x\n", tsr);
nerr("ERROR: HRESP not OK: %08x\n", tsr);
clrbits |= GMAC_TSR_HRESP;
}
@ -1453,7 +1453,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_LCO) != 0)
{
nllerr("ERROR: Late collision: %08x\n", tsr);
nerr("ERROR: Late collision: %08x\n", tsr);
clrbits |= GMAC_TSR_LCO;
}
@ -1490,7 +1490,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((rsr & GMAC_RSR_RXOVR) != 0)
{
nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= GMAC_RSR_RXOVR;
}
@ -1507,7 +1507,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((rsr & GMAC_RSR_BNA) != 0)
{
nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= GMAC_RSR_BNA;
}
@ -1515,7 +1515,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((rsr & GMAC_RSR_HNO) != 0)
{
nllerr("ERROR: HRESP not OK: %08x\n", rsr);
nerr("ERROR: HRESP not OK: %08x\n", rsr);
clrbits |= GMAC_RSR_HNO;
}
@ -1576,7 +1576,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
{
struct sam_gmac_s *priv = (struct sam_gmac_s *)arg;
nllerr("ERROR: Timeout!\n");
nerr("ERROR: Timeout!\n");
/* Then reset the hardware. Just take the interface down, then back
* up again.
@ -1657,7 +1657,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the GMAC interface for normal operation. */
nllinfo("Initialize the GMAC\n");
ninfo("Initialize the GMAC\n");
sam_gmac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@ -1675,7 +1675,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phyinit failed: %d\n", ret);
nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@ -1685,7 +1685,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
#else
@ -1696,7 +1696,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Enable normal MAC operation */
nllinfo("Enable normal operation\n");
ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@ -1780,7 +1780,7 @@ static int sam_txavail(struct net_driver_s *dev)
struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
irqstate_t flags;
nllinfo("ifup: %d\n", priv->ifup);
ninfo("ifup: %d\n", priv->ifup);
/* Disable interrupts because this function may be called from interrupt
* level processing.
@ -1958,8 +1958,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2032,8 +2032,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -2220,21 +2220,21 @@ static void sam_phydump(struct sam_gmac_s *priv)
sam_enablemdio(priv);
nllinfo("GMII Registers (Address %02x)\n", priv->phyaddr);
ninfo("GMII Registers (Address %02x)\n", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
nllinfo(" MCR: %04x\n", phyval);
ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
nllinfo(" MSR: %04x\n", phyval);
ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_ADVERTISE, &phyval);
nllinfo(" ADVERTISE: %04x\n", phyval);
ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_LPA, &phyval);
nllinfo(" LPR: %04x\n", phyval);
ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_1000BTCR, &phyval);
nllinfo(" 1000BTCR: %04x\n", phyval);
ninfo(" 1000BTCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &phyval);
nllinfo(" 1000BTSR: %04x\n", phyval);
ninfo(" 1000BTSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_ESTATUS, &phyval);
nllinfo(" ESTATUS: %04x\n", phyval);
ninfo(" ESTATUS: %04x\n", phyval);
/* Disable management port */
@ -2418,7 +2418,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
int timeout;
int ret;
nllinfo(" sam_phyreset\n");
ninfo(" sam_phyreset\n");
/* Enable management port */
@ -2429,7 +2429,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, GMII_MCR_RESET);
if (ret < 0)
{
nllerr("ERROR: sam_phywrite failed: %d\n", ret);
nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@ -2441,7 +2441,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, GMII_MCR, &mcr);
if (result < 0)
{
nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & GMII_MCR_RESET) == 0)
@ -2480,7 +2480,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
nllinfo("Find a valid PHY address\n");
ninfo("Find a valid PHY address\n");
/* Enable management port */
@ -2501,8 +2501,8 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
else
{
nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
candidate, ret);
nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@ -2523,7 +2523,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
}
@ -2563,7 +2563,7 @@ static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -2578,7 +2578,7 @@ static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -2618,7 +2618,7 @@ static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -2633,7 +2633,7 @@ static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -2679,35 +2679,35 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID1, &phyid1);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYID1 register\n");
nerr("ERROR: Failed to read PHYID1 register\n");
goto errout;
}
nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
/* Read the LS bits of the OUI from Pthe PHYID2 register */
ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID2, &phyid2);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYID2 register\n");
nerr("ERROR: Failed to read PHYID2 register\n");
goto errout;
}
nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == GMII_OUI_MSB &&
(phyid2 & GMII_PHYID2_OUI_MASK) == GMII_OUI_LSB)
{
nllinfo(" Vendor Model Number: %04x\n",
(phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
nllinfo(" Model Revision Number: %04x\n",
(phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
ninfo(" Vendor Model Number: %04x\n",
(phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
ninfo(" Model Revision Number: %04x\n",
(phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
}
else
{
nllerr("ERROR: PHY not recognized: PHYID1=%04x PHYID2=%04x\n",
phyid1, phyid2);
nerr("ERROR: PHY not recognized: PHYID1=%04x PHYID2=%04x\n",
phyid1, phyid2);
}
#ifdef SAMA5_GMAC_PHY_KSZ90x1
@ -2735,7 +2735,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_ADVERTISE, advertise);
if (ret < 0)
{
nllerr("ERROR: Failed to write ADVERTISE register\n");
nerr("ERROR: Failed to write ADVERTISE register\n");
goto errout;
}
@ -2746,7 +2746,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTCR, &btcr);
if (ret < 0)
{
nllerr("ERROR: Failed to read 1000BTCR register: %d\n", ret);
nerr("ERROR: Failed to read 1000BTCR register: %d\n", ret);
goto errout;
}
@ -2755,7 +2755,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_1000BTCR, btcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write 1000BTCR register: %d\n", ret);
nerr("ERROR: Failed to write 1000BTCR register: %d\n", ret);
goto errout;
}
@ -2764,7 +2764,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
if (ret < 0)
{
nllerr("ERROR: Failed to read MCR register: %d\n", ret);
nerr("ERROR: Failed to read MCR register: %d\n", ret);
goto errout;
}
@ -2773,11 +2773,11 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, phyval);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR register: %d\n", ret);
nerr("ERROR: Failed to write MCR register: %d\n", ret);
goto errout;
}
nllinfo(" MCR: 0x%X\n", phyval);
ninfo(" MCR: 0x%X\n", phyval);
/* Wait for autonegotion to complete */
@ -2787,7 +2787,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
if (ret < 0)
{
nllerr("ERROR: Failed to read MSR register: %d\n", ret);
nerr("ERROR: Failed to read MSR register: %d\n", ret);
goto errout;
}
@ -2797,7 +2797,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
{
/* Yes.. break out of the loop */
nllinfo("AutoNegotiate complete\n");
ninfo("AutoNegotiate complete\n");
break;
}
@ -2805,7 +2805,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
nllerr("ERROR: TimeOut\n");
nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@ -2822,7 +2822,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &btsr);
if (ret < 0)
{
nllerr("ERROR: Failed to read 1000BTSR register: %d\n", ret);
nerr("ERROR: Failed to read 1000BTSR register: %d\n", ret);
goto errout;
}
@ -2850,7 +2850,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_LPA, &lpa);
if (ret < 0)
{
nllerr("ERROR: Failed to read LPA register: %d\n", ret);
nerr("ERROR: Failed to read LPA register: %d\n", ret);
goto errout;
}
@ -2892,7 +2892,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
nllerr("ERROR: TimeOut\n");
nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@ -3065,7 +3065,7 @@ static int sam_phyinit(struct sam_gmac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
nllerr("ERROR: sam_phyfind failed: %d\n", ret);
nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@ -3324,11 +3324,11 @@ static void sam_macaddress(struct sam_gmac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@ -3436,7 +3436,7 @@ static int sam_gmac_configure(struct sam_gmac_s *priv)
{
uint32_t regval;
nllinfo("Entry\n");
ninfo("Entry\n");
/* Enable clocking to the GMAC peripheral */
@ -3573,7 +3573,7 @@ int sam_gmac_initialize(void)
priv->txpoll = wd_create();
if (!priv->txpoll)
{
nllerr("ERROR: Failed to create periodic poll timer\n");
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
@ -3581,7 +3581,7 @@ int sam_gmac_initialize(void)
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
nllerr("ERROR: Failed to create periodic poll timer\n");
nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
@ -3595,7 +3595,7 @@ int sam_gmac_initialize(void)
ret = sam_buffer_initialize(priv);
if (ret < 0)
{
nllerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
}
@ -3606,7 +3606,7 @@ int sam_gmac_initialize(void)
ret = irq_attach(SAM_IRQ_GMAC, sam_gmac_interrupt);
if (ret < 0)
{
nllerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAC);
nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAC);
goto errout_with_buffers;
}
@ -3619,7 +3619,7 @@ int sam_gmac_initialize(void)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
nllerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
goto errout_with_buffers;
}
@ -3631,7 +3631,7 @@ int sam_gmac_initialize(void)
return ret;
}
nllerr("ERROR: netdev_register() failed: %d\n", ret);
nerr("ERROR: netdev_register() failed: %d\n", ret);
errout_with_buffers:
sam_buffer_free(priv);

12
arch/arm/src/sama5/sam_hsmci.c
View file

@ -729,7 +729,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
mcllinfo("...[Repeats %d times]...\n", priv->ntimes);
mcinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -762,7 +762,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG
if (sam_checkreg(priv, false, value, address))
{
mcllinfo("%08x->%08x\n", address, value);
mcinfo("%08x->%08x\n", address, value);
}
#endif
@ -785,7 +785,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value,
#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG
if (sam_checkreg(priv, true, value, address))
{
mcllinfo("%08x<-%08x\n", address, value);
mcinfo("%08x<-%08x\n", address, value);
}
#endif
@ -1613,7 +1613,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was the error some kind of timeout? */
fllinfo("ERROR: events: %08x SR: %08x\n",
fllerr("ERROR: events: %08x SR: %08x\n",
priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
@ -3157,7 +3157,7 @@ static void sam_callback(void *arg)
lcderr("ERROR: Failed to cancel work: %d\n", ret);
}
fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
finfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback,
priv->cbarg, 0);
if (ret < 0)
@ -3397,7 +3397,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
fllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
finfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */

6
arch/arm/src/sama5/sam_lcd.c
View file

@ -1017,7 +1017,7 @@ static bool sam_checkreg(bool wr, uint32_t regval, uintptr_t address)
{
/* Yes... show how many times we did it */
lcdllinfo("...[Repeats %d times]...\n", g_lcdc.ntimes);
lcdinfo("...[Repeats %d times]...\n", g_lcdc.ntimes);
}
/* Save information about the new access */
@ -1049,7 +1049,7 @@ static uint32_t sam_getreg(uintptr_t address)
if (sam_checkreg(false, regval, address))
{
lcdllinfo("%08x->%08x\n", address, regval);
lcdinfo("%08x->%08x\n", address, regval);
}
return regval;
@ -1069,7 +1069,7 @@ static void sam_putreg(uintptr_t address, uint32_t regval)
{
if (sam_checkreg(true, regval, address))
{
lcdllinfo("%08x<-%08x\n", address, regval);
lcdinfo("%08x<-%08x\n", address, regval);
}
putreg32(regval, address);

8
arch/arm/src/sama5/sam_nand.c
View file

@ -999,7 +999,7 @@ static uint32_t nand_nfc_poll(void)
sr = nand_getreg(SAM_HSMC_SR);
#ifndef CONFIG_SAMA5_NAND_REGDEBUG
// fllinfo("sr=%08x\n", sr);
// finfo("sr=%08x\n", sr);
#endif
/* When set to one, this XFRDONE indicates that the NFC has terminated
@ -1065,7 +1065,7 @@ static int hsmc_interrupt(int irq, void *context)
uint32_t pending = sr & imr;
#ifndef CONFIG_SAMA5_NAND_REGDEBUG
fllinfo("sr=%08x imr=%08x\n", sr, imr);
finfo("sr=%08x imr=%08x\n", sr, imr);
#endif
/* When set to one, this XFRDONE indicates that the NFC has terminated
@ -1163,7 +1163,7 @@ static void nand_dma_sampleinit(struct sam_nandcs_s *priv)
#ifdef CONFIG_SAMA5_NAND_DMADEBUG
static void nand_dma_sampledone(struct sam_nandcs_s *priv, int result)
{
fllinfo("result: %d\n", result);
finfo("result: %d\n", result);
/* Sample the final registers */
@ -3088,7 +3088,7 @@ bool nand_checkreg(bool wr, uintptr_t regaddr, uint32_t regval)
{
/* Yes... show how many times we did it */
fllinfo("...[Repeats %d times]...\n", g_nand.ntimes);
finfo("...[Repeats %d times]...\n", g_nand.ntimes);
}
/* Save information about the new access */

6
arch/arm/src/sama5/sam_ohci.c
View file

@ -520,7 +520,7 @@ static uint8_t g_bufalloc[SAM_BUFALLOC]
#ifdef CONFIG_SAMA5_OHCI_REGDEBUG
static void sam_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@ -570,7 +570,7 @@ static void sam_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
ullinfo("[repeats %d more times]\n", count);
uinfo("[repeats %d more times]\n", count);
}
}
@ -3784,7 +3784,7 @@ static int sam_connect(struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */

2
arch/arm/src/sama5/sam_oneshot.c
View file

@ -108,7 +108,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
tmrllinfo("Expired...\n");
tmrinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.

14
arch/arm/src/sama5/sam_pwm.c
View file

@ -694,7 +694,7 @@ static bool pwm_checkreg(FAR struct sam_pwm_s *pwm, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
pwmllinfo("...[Repeats %d times]...\n", pwm->count);
pwminfo("...[Repeats %d times]...\n", pwm->count);
}
/* Save information about the new access */
@ -738,7 +738,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset)
#ifdef CONFIG_SAMA5_PWM_REGDEBUG
if (pwm_checkreg(&g_pwm, false, regval, regaddr))
{
pwmllinfo("%08x->%08x\n", regaddr, regval);
pwminfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -755,7 +755,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset)
#ifdef CONFIG_SAMA5_PWM_REGDEBUG
if (pwm_checkreg(pwm, false, regval, regaddr))
{
pwmllinfo("%08x->%08x\n", regaddr, regval);
pwminfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -794,7 +794,7 @@ static uint32_t pwm_chan_getreg(struct sam_pwm_chan_s *chan, int offset)
if (pwm_checkreg(chan->pwm, false, regval, regaddr))
#endif
{
pwmllinfo("%08x->%08x\n", regaddr, regval);
pwminfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -825,7 +825,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset,
#ifdef CONFIG_SAMA5_PWM_REGDEBUG
if (pwm_checkreg(&g_pwm, true, regval, regaddr))
{
pwmllinfo("%08x<-%08x\n", regaddr, regval);
pwminfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@ -838,7 +838,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset,
#ifdef CONFIG_SAMA5_PWM_REGDEBUG
if (pwm_checkreg(pwm, true, regval, regaddr))
{
pwmllinfo("%08x<-%08x\n", regaddr, regval);
pwminfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@ -874,7 +874,7 @@ static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset,
if (pwm_checkreg(chan->pwm, true, regval, regaddr))
#endif
{
pwmllinfo("%08x<-%08x\n", regaddr, regval);
pwminfo("%08x<-%08x\n", regaddr, regval);
}
#endif

6
arch/arm/src/sama5/sam_spi.c
View file

@ -413,7 +413,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
spillinfo("...[Repeats %d times]...\n", spi->ntimes);
spiinfo("...[Repeats %d times]...\n", spi->ntimes);
}
/* Save information about the new access */
@ -447,7 +447,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi,
#ifdef CONFIG_SAMA5_SPI_REGDEBUG
if (spi_checkreg(spi, false, value, address))
{
spillinfo("%08x->%08x\n", address, value);
spiinfo("%08x->%08x\n", address, value);
}
#endif
@ -470,7 +470,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
#ifdef CONFIG_SAMA5_SPI_REGDEBUG
if (spi_checkreg(spi, true, value, address))
{
spillinfo("%08x<-%08x\n", address, value);
spiinfo("%08x<-%08x\n", address, value);
}
#endif

32
arch/arm/src/sama5/sam_ssc.c
View file

@ -703,7 +703,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
i2sllinfo("...[Repeats %d times]...\n", priv->count);
i2sinfo("...[Repeats %d times]...\n", priv->count);
}
/* Save information about the new access */
@ -737,7 +737,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv,
#ifdef CONFIG_SAMA5_SSC_REGDEBUG
if (ssc_checkreg(priv, false, regval, regaddr))
{
i2sllinfo("%08x->%08x\n", regaddr, regval);
i2sinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -760,7 +760,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset,
#ifdef CONFIG_SAMA5_SSC_REGDEBUG
if (ssc_checkreg(priv, true, regval, regaddr))
{
i2sllinfo("%08x<-%08x\n", regaddr, regval);
i2sinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@ -847,12 +847,12 @@ static void ssc_dump_queue(sq_queue_t *queue)
if (!apb)
{
i2sllinfo(" %p: No buffer\n", bfcontainer);
i2sinfo(" %p: No buffer\n", bfcontainer);
}
else
{
i2sllinfo(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
i2sinfo(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
}
}
}
@ -862,12 +862,12 @@ static void ssc_dump_queues(struct sam_transport_s *xpt, const char *msg)
irqstate_t flags;
flags = enter_critical_section();
i2sllinfo("%s\n", msg);
i2sllinfo(" Pending:\n");
i2sinfo("%s\n", msg);
i2sinfo(" Pending:\n");
ssc_dump_queue(&xpt->pend);
i2sllinfo(" Active:\n");
i2sinfo(" Active:\n");
ssc_dump_queue(&xpt->act);
i2sllinfo(" Done:\n");
i2sinfo(" Done:\n");
ssc_dump_queue(&xpt->done);
leave_critical_section(flags);
}
@ -1090,7 +1090,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv,
#if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_RX)
static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result)
{
i2sllinfo("result: %d\n", result);
i2sinfo("result: %d\n", result);
/* Sample the final registers */
@ -1155,7 +1155,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result)
#if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_TX)
static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result)
{
i2sllinfo("result: %d\n", result);
i2sinfo("result: %d\n", result);
/* Sample the final registers */
@ -1377,7 +1377,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
i2sllerr("ERROR: wd_start failed: %d\n", errno);
i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@ -1565,7 +1565,7 @@ static void ssc_rx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->rx.work, ssc_rx_worker, priv, 0);
if (ret != 0)
{
i2sllerr("ERROR: Failed to queue RX work: %d\n", ret);
i2serr("ERROR: Failed to queue RX work: %d\n", ret);
}
}
}
@ -1790,7 +1790,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
i2sllerr("ERROR: wd_start failed: %d\n", errno);
i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@ -1965,7 +1965,7 @@ static void ssc_tx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->tx.work, ssc_tx_worker, priv, 0);
if (ret != 0)
{
i2sllerr("ERROR: Failed to queue TX work: %d\n", ret);
i2serr("ERROR: Failed to queue TX work: %d\n", ret);
}
}
}

10
arch/arm/src/sama5/sam_tc.c
View file

@ -562,7 +562,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr,
{
/* Yes... show how many times we did it */
tmllinfo("...[Repeats %d times]...\n", tc->ntimes);
tmrinfo("...[Repeats %d times]...\n", tc->ntimes);
}
/* Save information about the new access */
@ -597,7 +597,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(tc, false, regaddr, regval))
{
tmllinfo("%08x->%08x\n", regaddr, regval);
tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -621,7 +621,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(tc, true, regaddr, regval))
{
tmllinfo("%08x<-%08x\n", regaddr, regval);
tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@ -645,7 +645,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(chan->tc, false, regaddr, regval))
{
tmllinfo("%08x->%08x\n", regaddr, regval);
tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -668,7 +668,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(chan->tc, true, regaddr, regval))
{
tmllinfo("%08x<-%08x\n", regaddr, regval);
tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif

2
arch/arm/src/sama5/sam_tickless.c
View file

@ -209,7 +209,7 @@ static struct sam_tickless_s g_tickless;
static void sam_oneshot_handler(void *arg)
{
tmrllinfo("Expired...\n");
tmrinfo("Expired...\n");
sched_timer_expiration();
}

8
arch/arm/src/sama5/sam_twi.c
View file

@ -373,7 +373,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
i2cllinfo("...[Repeats %d times]...\n", priv->ntimes);
i2cinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -405,7 +405,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address)
if (twi_checkreg(priv, false, value, address))
{
i2cllinfo("%08x->%08x\n", address, value);
i2cinfo("%08x->%08x\n", address, value);
}
return value;
@ -426,7 +426,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address,
{
if (twi_checkreg(priv, true, value, address))
{
i2cllinfo("%08x<-%08x\n", address, value);
i2cinfo("%08x<-%08x\n", address, value);
}
putreg32(value, address);
@ -563,7 +563,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
imr = twi_getrel(priv, SAM_TWI_IMR_OFFSET);
pending = sr & imr;
i2cllinfo("TWI%d pending: %08x\n", priv->attr->twi, pending);
i2cinfo("TWI%d pending: %08x\n", priv->attr->twi, pending);
/* Byte received */

61
arch/arm/src/sama5/sam_udphs.c
View file

@ -667,7 +667,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
#ifdef CONFIG_SAMA5_UDPHS_REGDEBUG
static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
ullinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
uinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@ -718,7 +718,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
/* No.. More than one. */
ullinfo("[repeats %d more times]\n", count);
uinfo("[repeats %d more times]\n", count);
}
}
@ -798,31 +798,31 @@ static void sam_dumpep(struct sam_usbdev_s *priv, int epno)
{
/* Global Registers */
ullinfo("Global Register:\n");
ullinfo(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL));
ullinfo(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM));
ullinfo(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN));
ullinfo(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA));
ullinfo(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST));
uinfo("Global Register:\n");
uinfo(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL));
uinfo(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM));
uinfo(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN));
uinfo(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA));
uinfo(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST));
/* Endpoint registers */
ullinfo("Endpoint %d Register:\n", epno);
ullinfo(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno)));
ullinfo(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno)));
ullinfo(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno)));
uinfo("Endpoint %d Register:\n", epno);
uinfo(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno)));
uinfo(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno)));
uinfo(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno)));
ullinfo("DMA %d Register:\n", epno);
uinfo("DMA %d Register:\n", epno);
if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0)
{
ullinfo(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno)));
ullinfo(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno)));
ullinfo(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno)));
ullinfo(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno)));
uinfo(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno)));
uinfo(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno)));
uinfo(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno)));
uinfo(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno)));
}
else
{
ullinfo(" None\n");
uinfo(" None\n");
}
}
#endif
@ -1353,9 +1353,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
return -ENOENT;
}
ullinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
epno, privreq, privreq->req.len, privreq->req.xfrd,
privreq->inflight, privep->zlpneeded);
uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
epno, privreq, privreq->req.len, privreq->req.xfrd,
privreq->inflight, privep->zlpneeded);
/* Handle any bytes in flight. */
@ -1596,8 +1596,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
return -ENOENT;
}
ullinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
uinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
/* Ignore any attempt to receive a zero length packet */
@ -1881,8 +1881,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@ -2045,7 +2045,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
{
/* Special case recipient=device test mode */
ullinfo("test mode: %d\n", index.w);
uinfo("test mode: %d\n", index.w);
}
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -3436,7 +3436,7 @@ static int sam_ep_disable(struct usbdev_ep_s *ep)
if (!ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
ullerr("ERROR: ep=%p\n", ep);
uerr("ERROR: ep=%p\n", ep);
return -EINVAL;
}
#endif
@ -3568,7 +3568,8 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@ -3580,7 +3581,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
ullerr("ERROR: driver=%p\n", priv->driver);
uerr("ERROR: driver=%p\n", priv->driver);
return -ESHUTDOWN;
}
#endif
@ -3607,7 +3608,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (privep->stalled)
{
sam_req_abort(privep, privreq, -EBUSY);
ullerr("ERROR: stalled\n");
uerr("ERROR: stalled\n");
ret = -EPERM;
}
else

8
arch/arm/src/sama5/sam_wdt.c
View file

@ -190,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
if (count == 4)
{
wdllinfo("...\n");
wdinfo("...\n");
}
return regval;
@ -207,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
/* Yes.. then show how many times the value repeated */
wdllinfo("[repeats %d more times]\n", count-3);
wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -219,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
/* Show the register value read */
wdllinfo("%08x->%048\n", regaddr, regval);
wdinfo("%08x->%048\n", regaddr, regval);
return regval;
}
#endif
@ -237,7 +237,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr)
{
/* Show the register value being written */
wdllinfo("%08x<-%08x\n", regaddr, regval);
wdinfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */

2
arch/arm/src/samdl/sam_idle.c
View file

@ -99,7 +99,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
_llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */

14
arch/arm/src/samdl/sam_spi.c
View file

@ -548,7 +548,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
spillinfo("...[Repeats %d times]...\n", priv->ntimes);
spiinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -581,7 +581,7 @@ static uint8_t spi_getreg8(struct sam_spidev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, false, (uint32_t)regval, regaddr))
{
spillinfo("%08x->%02x\n", regaddr, regval);
spiinfo("%08x->%02x\n", regaddr, regval);
}
#endif
@ -604,7 +604,7 @@ static void spi_putreg8(struct sam_spidev_s *priv, uint8_t regval,
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, true, (uint32_t)regval, regaddr))
{
spillinfo("%08x<-%02x\n", regaddr, regval);
spiinfo("%08x<-%02x\n", regaddr, regval);
}
#endif
@ -627,7 +627,7 @@ static uint16_t spi_getreg16(struct sam_spidev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, false, (uint32_t)regval, regaddr))
{
spillinfo("%08x->%04x\n", regaddr, regval);
spiinfo("%08x->%04x\n", regaddr, regval);
}
#endif
@ -650,7 +650,7 @@ static void spi_putreg16(struct sam_spidev_s *priv, uint16_t regval,
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, true, (uint32_t)regval, regaddr))
{
spillinfo("%08x<-%04x\n", regaddr, regval);
spiinfo("%08x<-%04x\n", regaddr, regval);
}
#endif
@ -673,7 +673,7 @@ static uint32_t spi_getreg32(struct sam_spidev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, false, regval, regaddr))
{
spillinfo("%08x->%08x\n", regaddr, regval);
spiinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -696,7 +696,7 @@ static void spi_putreg32(struct sam_spidev_s *priv, uint32_t regval,
#ifdef CONFIG_SAMDL_SPI_REGDEBUG
if (spi_checkreg(priv, true, regval, regaddr))
{
spillinfo("%08x<-%08x\n", regaddr, regval);
spiinfo("%08x<-%08x\n", regaddr, regval);
}
#endif

196
arch/arm/src/samv7/sam_emac.c
View file

@ -966,7 +966,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
nllinfo("...[Repeats %d times]...\n", priv->ntimes);
ninfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -999,7 +999,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset)
#ifdef CONFIG_SAMV7_EMAC_REGDEBUG
if (sam_checkreg(priv, false, regval, regaddr))
{
nllinfo("%08x->%08x\n", regaddr, regval);
ninfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -1023,7 +1023,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset,
#ifdef CONFIG_SAMV7_EMAC_REGDEBUG
if (sam_checkreg(priv, true, regval, regaddr))
{
nllinfo("%08x<-%08x\n", regaddr, regval);
ninfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@ -1147,7 +1147,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[0].txdesc = (struct emac_txdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].txdesc)
{
nllerr("ERROR: Failed to allocate TX descriptors\n");
nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@ -1158,7 +1158,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[0].rxdesc = (struct emac_rxdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].rxdesc)
{
nllerr("ERROR: Failed to allocate RX descriptors\n");
nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -1170,7 +1170,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[0].txbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].txbuffer)
{
nllerr("ERROR: Failed to allocate TX buffer\n");
nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -1181,7 +1181,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[0].rxbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].rxbuffer)
{
nllerr("ERROR: Failed to allocate RX buffer\n");
nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -1194,7 +1194,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[1].txdesc = (struct emac_txdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].txdesc)
{
nllerr("ERROR: Failed to allocate TX descriptors\n");
nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@ -1205,7 +1205,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[1].rxdesc = (struct emac_rxdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].rxdesc)
{
nllerr("ERROR: Failed to allocate RX descriptors\n");
nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -1217,7 +1217,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[1].txbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].txbuffer)
{
nllerr("ERROR: Failed to allocate TX buffer\n");
nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -1228,7 +1228,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[1].rxbuffer = (uint8_t *)kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].rxbuffer)
{
nllerr("ERROR: Failed to allocate RX buffer\n");
nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@ -1369,7 +1369,7 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
if (dev->d_len > EMAC_TX_UNITSIZE)
{
nllerr("ERROR: Packet too big: %d\n", dev->d_len);
nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@ -1379,14 +1379,14 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
txhead = xfrq->txhead;
txdesc = &xfrq->txdesc[txhead];
nllinfo("d_len: %d txhead[%d]: %d\n", dev->d_len, qid, xfrq->txhead);
ninfo("d_len: %d txhead[%d]: %d\n", dev->d_len, qid, xfrq->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* If no free TX descriptor, buffer can't be sent */
if (sam_txfree(priv, qid) < 1)
{
nllerr("ERROR: No free TX descriptors\n");
nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@ -1460,7 +1460,7 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
if (sam_txfree(priv, qid) < 1)
{
nllinfo("Disabling RX interrupts\n");
ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_RCOMP);
}
@ -1646,7 +1646,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
nllinfo("Entry rxndx[%d]: %d\n", qid, rxndx);
ninfo("Entry rxndx[%d]: %d\n", qid, rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@ -1709,7 +1709,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
{
if (rxndx == xfrq->rxndx)
{
nllinfo("ERROR: No EOF (Invalid or buffers too small)\n");
nerr("ERROR: No EOF (Invalid or buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@ -1767,7 +1767,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
nllinfo("packet %d-%d (%d)\n", xfrq->rxndx, rxndx, dev->d_len);
ninfo("packet %d-%d (%d)\n", xfrq->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor(s). Loop until all descriptors
@ -1801,12 +1801,12 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
* all of the data.
*/
nllinfo("rxndx: %d d_len: %d\n",
xfrq->rxndx, dev->d_len);
ninfo("rxndx: %d d_len: %d\n",
xfrq->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
nllerr("ERROR: Buffer size %d; frame size %d\n",
dev->d_len, pktlen);
nerr("ERROR: Buffer size %d; frame size %d\n",
dev->d_len, pktlen);
NETDEV_RXERRORS(&priv->dev);
return -E2BIG;
}
@ -1854,7 +1854,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid)
/* No packet was found */
xfrq->rxndx = rxndx;
nllinfo("Exit rxndx[%d]: %d\n", qid, xfrq->rxndx);
ninfo("Exit rxndx[%d]: %d\n", qid, xfrq->rxndx);
return -EAGAIN;
}
@ -1912,7 +1912,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllinfo("IPv4 frame\n");
ninfo("IPv4 frame\n");
NETDEV_RXIPV4(&priv->dev);
/* Handle ARP on input then give the IPv4 packet to the network
@ -1953,7 +1953,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllinfo("Iv6 frame\n");
ninfo("Iv6 frame\n");
NETDEV_RXIPV6(&priv->dev);
/* Give the IPv6 packet to the network layer */
@ -1991,7 +1991,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllinfo("ARP frame\n");
ninfo("ARP frame\n");
NETDEV_RXARP(&priv->dev);
/* Handle ARP packet */
@ -2286,7 +2286,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET);
pending = isr & ~(imr | EMAC_INT_UNUSED);
nllinfo("isr: %08x pending: %08x\n", isr, pending);
ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the receipt of an RX packet.
*
@ -2312,7 +2312,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((rsr & EMAC_RSR_RXOVR) != 0)
{
nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_RXOVR;
}
@ -2329,7 +2329,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((rsr & EMAC_RSR_BNA) != 0)
{
nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@ -2370,7 +2370,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
clrbits = EMAC_TSR_RLE | sam_txinuse(priv, qid);
sam_txreset(priv, qid);
nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
regval |= EMAC_NCR_TXEN;
@ -2381,7 +2381,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((tsr & EMAC_TSR_COL) != 0)
{
nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
NETDEV_TXERRORS(&priv->dev);
}
@ -2389,7 +2389,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((tsr & EMAC_TSR_TFC) != 0)
{
nllerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
NETDEV_TXERRORS(&priv->dev);
}
@ -2407,7 +2407,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((pending & EMAC_INT_HRESP) != 0)
{
nllerr("ERROR: Hresp not OK\n");
nerr("ERROR: Hresp not OK\n");
}
/* Check for PAUSE Frame received (PFRE).
@ -2418,7 +2418,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((pending & EMAC_INT_PFNZ) != 0)
{
nllinfo("Pause frame received\n");
ninfo("Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@ -2428,7 +2428,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid)
if ((pending & EMAC_INT_PTZ) != 0)
{
nllinfo("Pause TO!\n");
ninfo("Pause TO!\n");
}
#endif
}
@ -2593,7 +2593,7 @@ static int sam_emac1_interrupt(int irq, void *context)
static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
{
nllerr("ERROR: Timeout!\n");
nerr("ERROR: Timeout!\n");
NETDEV_TXTIMEOUTS(&priv->dev);
/* Reset the hardware. Just take the interface down, then back up again. */
@ -2837,7 +2837,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the EMAC interface for normal operation. */
nllinfo("Initialize the EMAC\n");
ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
sam_queue_configure(priv, EMAC_QUEUE_1);
sam_queue_configure(priv, EMAC_QUEUE_2);
@ -2858,7 +2858,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phyinit failed: %d\n", ret);
nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@ -2867,16 +2867,16 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
nllinfo("Link detected \n");
ninfo("Link detected \n");
/* Enable normal MAC operation */
nllinfo("Enable normal operation\n");
ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@ -2910,7 +2910,7 @@ static int sam_ifdown(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
nllinfo("Taking the network down\n");
ninfo("Taking the network down\n");
/* Disable the EMAC interrupt */
@ -2955,7 +2955,7 @@ static int sam_ifdown(struct net_driver_s *dev)
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
{
nllinfo("ifup: %d\n", priv->ifup);
ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
@ -3208,8 +3208,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -3281,8 +3281,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@ -3476,19 +3476,19 @@ static void sam_phydump(struct sam_emac_s *priv)
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
nllinfo("%s Registers (Address %02x)\n",
priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
ninfo("%s Registers (Address %02x)\n",
priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
nllinfo(" MCR: %04x\n", phyval);
ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
nllinfo(" MSR: %04x\n", phyval);
ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
nllinfo(" ADVERTISE: %04x\n", phyval);
ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
nllinfo(" LPR: %04x\n", phyval);
ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, priv->attr->physr, &phyval);
nllinfo(" PHYSR: %04x\n", phyval);
ninfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@ -3716,7 +3716,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
nllinfo(" sam_phyreset\n");
ninfo(" sam_phyreset\n");
/* Enable management port */
@ -3729,7 +3729,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
nllerr("ERROR: sam_phywrite failed: %d\n", ret);
nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@ -3741,7 +3741,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
@ -3783,7 +3783,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
nllinfo("Find a valid PHY address\n");
ninfo("Find a valid PHY address\n");
/* Enable management port */
@ -3806,8 +3806,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
else
{
nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
candidate, ret);
nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@ -3828,10 +3828,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, priv->attr->physr, &phyval);
nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@ -3872,7 +3872,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -3897,7 +3897,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -3937,7 +3937,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -3962,7 +3962,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
nllerr("ERROR: sam_phywait failed: %d\n", ret);
nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@ -4007,33 +4007,33 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYID1\n");
nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYID2\n");
nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == priv->attr->msoui &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) ==
(uint16_t)priv->attr->lsoui)
{
nllinfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
nllinfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
ninfo(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
ninfo(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
nllerr("ERROR: PHY not recognized\n");
nerr("ERROR: PHY not recognized\n");
}
/* Setup control register */
@ -4041,7 +4041,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MCR\n");
nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@ -4052,7 +4052,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR\n");
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@ -4067,7 +4067,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
nllerr("ERROR: Failed to write ANAR\n");
nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
@ -4076,7 +4076,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MCR\n");
nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@ -4084,7 +4084,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR\n");
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@ -4096,11 +4096,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
nllerr("ERROR: Failed to write MCR\n");
nerr("ERROR: Failed to write MCR\n");
goto errout;
}
nllinfo(" MCR: %04x\n", mcr);
ninfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@ -4110,7 +4110,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MSR\n");
nerr("ERROR: Failed to read MSR\n");
goto errout;
}
@ -4120,7 +4120,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
nllinfo("AutoNegotiate complete\n");
ninfo("AutoNegotiate complete\n");
break;
}
@ -4128,7 +4128,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
nllerr("ERROR: TimeOut\n");
nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@ -4140,7 +4140,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
nllerr("ERROR: Failed to read ANLPAR\n");
nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
@ -4235,13 +4235,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
nllerr("ERROR: Failed to read MSR: %d\n", ret);
nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
nllerr("ERROR: MSR LinkStatus: %04x\n", msr);
nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
@ -4250,7 +4250,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, priv->attr->physr, &physr);
if (ret < 0)
{
nllerr("ERROR: Failed to read PHYSR: %d\n", ret);
nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
@ -4288,7 +4288,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
nllinfo("Link is up\n");
ninfo("Link is up\n");
linkup = true;
errout:
@ -4365,7 +4365,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
nllerr("ERROR: sam_phyfind failed: %d\n", ret);
nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@ -4480,7 +4480,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
else
#endif
{
ninfo("ERROR: emac=%d\n", priv->attr->emac);
nerr("ERROR: emac=%d\n", priv->attr->emac);
}
}
@ -4803,11 +4803,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@ -5006,7 +5006,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
nllinfo("Entry\n");
ninfo("Entry\n");
/* Enable clocking to the EMAC peripheral */

20
arch/arm/src/samv7/sam_hsmci.c
View file

@ -657,7 +657,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
mcllinfo("...[Repeats %d times]...\n", priv->ntimes);
mcinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -690,7 +690,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMV7_HSMCI_REGDEBUG
if (sam_checkreg(priv, false, value, address))
{
mcllinfo("%08x->%08x\n", address, value);
mcinfo("%08x->%08x\n", address, value);
}
#endif
@ -713,7 +713,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value,
#ifdef CONFIG_SAMV7_HSMCI_REGDEBUG
if (sam_checkreg(priv, true, value, address))
{
mcllinfo("%08x<-%08x\n", address, value);
mcinfo("%08x<-%08x\n", address, value);
}
#endif
@ -1173,7 +1173,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result)
if (result < 0)
{
wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR);
mcllerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
mcerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
/* sam_endtransfer will terminate the transfer and wait up the waiting
* client in this case.
@ -1273,7 +1273,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
/* Yes.. wake up any waiting threads */
sam_endwait(priv, SDIOWAIT_TIMEOUT);
mcllerr("ERROR: Timeout\n");
mcerr("ERROR: Timeout\n");
}
}
@ -1473,7 +1473,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was it some kind of timeout error? */
mcllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
mcerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
{
/* Yes.. Terminate with a timeout. */
@ -1594,8 +1594,8 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was the error some kind of timeout? */
mcllinfo("ERROR: events: %08x SR: %08x\n",
priv->cmdrmask, enabled);
mcerr("ERROR: events: %08x SR: %08x\n",
priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
{
@ -3220,7 +3220,7 @@ static void sam_callback(void *arg)
mcerr("ERROR: Failed to cancel work: %d\n", ret);
}
mcllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback,
priv->cbarg, 0);
if (ret < 0)
@ -3418,7 +3418,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
mcllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */

50
arch/arm/src/samv7/sam_mcan.c
View file

@ -794,7 +794,7 @@
#endif
#ifdef CONFIG_SAMV7_MCAN_REGDEBUG
# define reginfo canllinfo
# define reginfo caninfo
#else
# define reginfo(x...)
#endif
@ -1195,7 +1195,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset)
{
if (priv->count == 4)
{
canllinfo("...\n");
caninfo("...\n");
}
return regval;
@ -1212,7 +1212,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset)
{
/* Yes.. then show how many times the value repeated */
canllinfo("[repeats %d more times]\n", priv->count - 3);
caninfo("[repeats %d more times]\n", priv->count - 3);
}
/* Save the new address, value, and count */
@ -1224,7 +1224,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset)
/* Show the register value read */
canllinfo("%08x->%08x\n", regaddr, regval);
caninfo("%08x->%08x\n", regaddr, regval);
return regval;
}
@ -1261,7 +1261,7 @@ static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval
/* Show the register value being written */
canllinfo("%08x<-%08x\n", regaddr, regval);
caninfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */
@ -2137,7 +2137,7 @@ static void mcan_reset(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
canllinfo("MCAN%d\n", config->port);
caninfo("MCAN%d\n", config->port);
UNUSED(config);
/* Get exclusive access to the MCAN peripheral */
@ -2194,7 +2194,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
canllinfo("MCAN%d pid: %d\n", config->port, config->pid);
caninfo("MCAN%d pid: %d\n", config->port, config->pid);
/* Get exclusive access to the MCAN peripheral */
@ -2205,7 +2205,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
ret = mcan_hw_initialize(priv);
if (ret < 0)
{
canllerr("ERROR: MCAN%d H/W initialization failed: %d\n", config->port, ret);
canerr("ERROR: MCAN%d H/W initialization failed: %d\n", config->port, ret);
return ret;
}
@ -2216,7 +2216,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
ret = irq_attach(config->irq0, config->handler);
if (ret < 0)
{
canllerr("ERROR: Failed to attach MCAN%d line 0 IRQ (%d)",
canerr("ERROR: Failed to attach MCAN%d line 0 IRQ (%d)",
config->port, config->irq0);
return ret;
}
@ -2224,7 +2224,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
ret = irq_attach(config->irq1, config->handler);
if (ret < 0)
{
canllerr("ERROR: Failed to attach MCAN%d line 1 IRQ (%d)",
canerr("ERROR: Failed to attach MCAN%d line 1 IRQ (%d)",
config->port, config->irq1);
return ret;
}
@ -2271,7 +2271,7 @@ static void mcan_shutdown(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
canllinfo("MCAN%d\n", config->port);
caninfo("MCAN%d\n", config->port);
/* Get exclusive access to the MCAN peripheral */
@ -2320,7 +2320,7 @@ static void mcan_rxint(FAR struct can_dev_s *dev, bool enable)
DEBUGASSERT(priv && priv->config);
canllinfo("MCAN%d enable: %d\n", priv->config->port, enable);
caninfo("MCAN%d enable: %d\n", priv->config->port, enable);
/* Enable/disable the receive interrupts */
@ -2362,7 +2362,7 @@ static void mcan_txint(FAR struct can_dev_s *dev, bool enable)
DEBUGASSERT(priv && priv->config);
canllinfo("MCAN%d enable: %d\n", priv->config->port, enable);
caninfo("MCAN%d enable: %d\n", priv->config->port, enable);
/* Enable/disable the receive interrupts */
@ -2669,9 +2669,9 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
DEBUGASSERT(priv && priv->config);
config = priv->config;
canllinfo("MCAN%d\n", config->port);
canllinfo("MCAN%d ID: %d DLC: %d\n",
config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
caninfo("MCAN%d\n", config->port);
caninfo("MCAN%d ID: %d DLC: %d\n",
config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
/* That that FIFO elements were configured.
*
@ -3141,7 +3141,7 @@ static void mcan_error(FAR struct can_dev_s *dev, uint32_t status,
ret = can_receive(dev, &hdr, data);
if (ret < 0)
{
canllerr("ERROR: can_receive failed: %d\n", ret);
canerr("ERROR: can_receive failed: %d\n", ret);
}
}
}
@ -3235,7 +3235,7 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
ret = can_receive(dev, &hdr, (FAR uint8_t *)rxbuffer);
if (ret < 0)
{
canllerr("ERROR: can_receive failed: %d\n", ret);
canerr("ERROR: can_receive failed: %d\n", ret);
}
}
@ -3288,7 +3288,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((pending & MCAN_CMNERR_INTS) != 0)
{
canllerr("ERROR: Common %08x\n", pending & MCAN_CMNERR_INTS);
canerr("ERROR: Common %08x\n", pending & MCAN_CMNERR_INTS);
/* Clear the error indications */
@ -3299,7 +3299,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((pending & MCAN_TXERR_INTS) != 0)
{
canllerr("ERROR: TX %08x\n", pending & MCAN_TXERR_INTS);
canerr("ERROR: TX %08x\n", pending & MCAN_TXERR_INTS);
/* Clear the error indications */
@ -3320,7 +3320,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((pending & MCAN_RXERR_INTS) != 0)
{
canllerr("ERROR: RX %08x\n", pending & MCAN_RXERR_INTS);
canerr("ERROR: RX %08x\n", pending & MCAN_RXERR_INTS);
/* Clear the error indications */
@ -3341,7 +3341,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
{
/* All (old) errors cleared */
canllerr("ERROR: CLEARED\n");
canerr("ERROR: CLEARED\n");
mcan_error(dev, 0, priv->olderrors);
@ -3466,7 +3466,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((regval & MCAN_RXF0S_RF0L) != 0)
{
canllerr("ERROR: Message lost: %08x\n", regval);
canerr("ERROR: Message lost: %08x\n", regval);
}
else
{
@ -3500,7 +3500,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
if ((regval & MCAN_RXF0S_RF0L) != 0)
{
canllerr("ERROR: Message lost: %08x\n", regval);
canerr("ERROR: Message lost: %08x\n", regval);
}
else
{
@ -3594,7 +3594,7 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv)
uint32_t cntr;
uint32_t cmr;
canllinfo("MCAN%d\n", config->port);
caninfo("MCAN%d\n", config->port);
/* Configure MCAN pins */

2
arch/arm/src/samv7/sam_oneshot.c
View file

@ -109,7 +109,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
tmrllinfo("Expired...\n");
tmrinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.

6
arch/arm/src/samv7/sam_qspi.c
View file

@ -378,7 +378,7 @@ static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
spillinfo("...[Repeats %d times]...\n", priv->ntimes);
spiinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -412,7 +412,7 @@ static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv,
#ifdef CONFIG_SAMV7_QSPI_REGDEBUG
if (qspi_checkreg(priv, false, value, address))
{
spillinfo("%08x->%08x\n", address, value);
spiinfo("%08x->%08x\n", address, value);
}
#endif
@ -435,7 +435,7 @@ static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value,
#ifdef CONFIG_SAMV7_QSPI_REGDEBUG
if (qspi_checkreg(priv, true, value, address))
{
spillinfo("%08x<-%08x\n", address, value);
spiinfo("%08x<-%08x\n", address, value);
}
#endif

6
arch/arm/src/samv7/sam_rswdt.c
View file

@ -190,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
if (count == 4)
{
wdllinfo("...\n");
wdinfo("...\n");
}
return regval;
@ -207,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
/* Yes.. then show how many times the value repeated */
wdllinfo("[repeats %d more times]\n", count-3);
wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -219,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
/* Show the register value read */
wdllinfo("%08x->%048\n", regaddr, regval);
wdinfo("%08x->%048\n", regaddr, regval);
return regval;
}
#endif

6
arch/arm/src/samv7/sam_spi.c
View file

@ -436,7 +436,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
spillinfo("...[Repeats %d times]...\n", spi->ntimes);
spiinfo("...[Repeats %d times]...\n", spi->ntimes);
}
/* Save information about the new access */
@ -470,7 +470,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi,
#ifdef CONFIG_SAMV7_SPI_REGDEBUG
if (spi_checkreg(spi, false, value, address))
{
spillinfo("%08x->%08x\n", address, value);
spiinfo("%08x->%08x\n", address, value);
}
#endif
@ -493,7 +493,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
#ifdef CONFIG_SAMV7_SPI_REGDEBUG
if (spi_checkreg(spi, true, value, address))
{
spillinfo("%08x<-%08x\n", address, value);
spiinfo("%08x<-%08x\n", address, value);
}
#endif

6
arch/arm/src/samv7/sam_spi_slave.c
View file

@ -252,7 +252,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
spillinfo("...[Repeats %d times]...\n", priv->ntimes);
spiinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -285,7 +285,7 @@ static uint32_t spi_getreg(struct sam_spidev_s *priv, unsigned int offset)
#ifdef CONFIG_SAMV7_SPI_REGDEBUG
if (spi_checkreg(priv, false, value, address))
{
spillinfo("%08x->%08x\n", address, value);
spiinfo("%08x->%08x\n", address, value);
}
#endif
@ -308,7 +308,7 @@ static void spi_putreg(struct sam_spidev_s *priv, uint32_t value,
#ifdef CONFIG_SAMV7_SPI_REGDEBUG
if (spi_checkreg(priv, true, value, address))
{
spillinfo("%08x<-%08x\n", address, value);
spiinfo("%08x<-%08x\n", address, value);
}
#endif

30
arch/arm/src/samv7/sam_ssc.c
View file

@ -678,7 +678,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval,
{
/* Yes... show how many times we did it */
i2sllinfo("...[Repeats %d times]...\n", priv->count);
i2sinfo("...[Repeats %d times]...\n", priv->count);
}
/* Save information about the new access */
@ -712,7 +712,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv,
#ifdef CONFIG_SAMV7_SSC_REGDEBUG
if (ssc_checkreg(priv, false, regval, regaddr))
{
i2sllinfo("%08x->%08x\n", regaddr, regval);
i2sinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -735,7 +735,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset,
#ifdef CONFIG_SAMV7_SSC_REGDEBUG
if (ssc_checkreg(priv, true, regval, regaddr))
{
i2sllinfo("%08x<-%08x\n", regaddr, regval);
i2sinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@ -821,12 +821,12 @@ static void ssc_dump_queue(sq_queue_t *queue)
if (!apb)
{
i2sllinfo(" %p: No buffer\n", bfcontainer);
i2sinfo(" %p: No buffer\n", bfcontainer);
}
else
{
i2sllinfo(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
i2sinfo(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
}
}
}
@ -836,12 +836,12 @@ static void ssc_dump_queues(struct sam_transport_s *xpt, const char *msg)
irqstate_t flags;
flags = enter_critical_section();
i2sllinfo("%s\n", msg);
i2sllinfo(" Pending:\n");
i2sinfo("%s\n", msg);
i2sinfo(" Pending:\n");
ssc_dump_queue(&xpt->pend);
i2sllinfo(" Active:\n");
i2sinfo(" Active:\n");
ssc_dump_queue(&xpt->act);
i2sllinfo(" Done:\n");
i2sinfo(" Done:\n");
ssc_dump_queue(&xpt->done);
leave_critical_section(flags);
}
@ -1129,7 +1129,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result)
#if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_TX)
static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result)
{
i2sllinfo("result: %d\n", result);
i2sinfo("result: %d\n", result);
/* Sample the final registers */
@ -1352,7 +1352,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
i2sllerr("ERROR: wd_start failed: %d\n", errno);
i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@ -1540,7 +1540,7 @@ static void ssc_rx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->rx.work, ssc_rx_worker, priv, 0);
if (ret != 0)
{
i2sllerr("ERROR: Failed to queue RX work: %d\n", ret);
i2serr("ERROR: Failed to queue RX work: %d\n", ret);
}
}
}
@ -1769,7 +1769,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
i2sllerr("ERROR: wd_start failed: %d\n", errno);
i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@ -1944,7 +1944,7 @@ static void ssc_tx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->tx.work, ssc_tx_worker, priv, 0);
if (ret != 0)
{
i2sllerr("ERROR: Failed to queue TX work: %d\n", ret);
i2serr("ERROR: Failed to queue TX work: %d\n", ret);
}
}
}

14
arch/arm/src/samv7/sam_tc.c
View file

@ -702,7 +702,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr,
{
/* Yes... show how many times we did it */
tmrllinfo("...[Repeats %d times]...\n", tc->ntimes);
tmrinfo("...[Repeats %d times]...\n", tc->ntimes);
}
/* Save information about the new access */
@ -737,7 +737,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMV7_TC_REGDEBUG
if (sam_checkreg(tc, false, regaddr, regval))
{
tmrllinfo("%08x->%08x\n", regaddr, regval);
tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -761,7 +761,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval,
#ifdef CONFIG_SAMV7_TC_REGDEBUG
if (sam_checkreg(tc, true, regaddr, regval))
{
tmrllinfo("%08x<-%08x\n", regaddr, regval);
tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@ -785,7 +785,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMV7_TC_REGDEBUG
if (sam_checkreg(chan->tc, false, regaddr, regval))
{
tmrllinfo("%08x->%08x\n", regaddr, regval);
tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -808,7 +808,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset,
#ifdef CONFIG_SAMV7_TC_REGDEBUG
if (sam_checkreg(chan->tc, true, regaddr, regval))
{
tmrllinfo("%08x<-%08x\n", regaddr, regval);
tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@ -845,8 +845,8 @@ static int sam_tc_interrupt(struct sam_tc_s *tc, struct sam_chan_s *chan)
imr = sam_chan_getreg(chan, SAM_TC_IMR_OFFSET);
pending = sr & imr;
tmrllinfo("TC%d Channel %d: pending=%08lx\n",
tc->tc, chan->chan, (unsigned long)pending);
tmrinfo("TC%d Channel %d: pending=%08lx\n",
tc->tc, chan->chan, (unsigned long)pending);
/* Are there any pending interrupts for this channel? */

2
arch/arm/src/samv7/sam_tickless.c
View file

@ -221,7 +221,7 @@ static struct sam_tickless_s g_tickless;
static void sam_oneshot_handler(void *arg)
{
tmrllinfo("Expired...\n");
tmrinfo("Expired...\n");
sched_timer_expiration();
}

8
arch/arm/src/samv7/sam_twihs.c
View file

@ -353,7 +353,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value,
{
/* Yes... show how many times we did it */
i2cllinfo("...[Repeats %d times]...\n", priv->ntimes);
i2cinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -385,7 +385,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address)
if (twi_checkreg(priv, false, value, address))
{
i2cllinfo("%08x->%08x\n", address, value);
i2cinfo("%08x->%08x\n", address, value);
}
return value;
@ -406,7 +406,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address,
{
if (twi_checkreg(priv, true, value, address))
{
i2cllinfo("%08x<-%08x\n", address, value);
i2cinfo("%08x<-%08x\n", address, value);
}
putreg32(value, address);
@ -543,7 +543,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
imr = twi_getrel(priv, SAM_TWIHS_IMR_OFFSET);
pending = sr & imr;
i2cllinfo("TWIHS%d pending: %08x\n", priv->attr->twi, pending);
i2cinfo("TWIHS%d pending: %08x\n", priv->attr->twi, pending);
/* Byte received */

22
arch/arm/src/samv7/sam_usbdevhs.c
View file

@ -736,7 +736,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
#ifdef CONFIG_SAMV7_USBHS_REGDEBUG
static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
ullinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
uinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@ -787,7 +787,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
/* No.. More than one. */
ullinfo("[repeats %d more times]\n", count);
uinfo("[repeats %d more times]\n", count);
}
}
@ -1405,9 +1405,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
return -ENOENT;
}
ullinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
epno, privreq, privreq->req.len, privreq->req.xfrd,
privreq->inflight, privep->zlpneeded);
uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
epno, privreq, privreq->req.len, privreq->req.xfrd,
privreq->inflight, privep->zlpneeded);
/* Handle any bytes in flight. */
@ -1640,8 +1640,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
return -ENOENT;
}
ullinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
uinfo("EP%d: len=%d xfrd=%d\n",
epno, privreq->req.len, privreq->req.xfrd);
/* Ignore any attempt to receive a zero length packet */
@ -1975,8 +1975,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@ -2139,7 +2139,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
{
/* Special case recipient=device test mode */
ullinfo("test mode: %d\n", index.w);
uinfo("test mode: %d\n", index.w);
}
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@ -3902,7 +3902,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (privep->stalled)
{
sam_req_abort(privep, privreq, -EBUSY);
ullerr("ERROR: stalled\n");
uerr("ERROR: stalled\n");
ret = -EPERM;
}
else

8
arch/arm/src/samv7/sam_wdt.c
View file

@ -190,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
if (count == 4)
{
wdllinfo("...\n");
wdinfo("...\n");
}
return regval;
@ -207,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
{
/* Yes.. then show how many times the value repeated */
wdllinfo("[repeats %d more times]\n", count-3);
wdinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -219,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr)
/* Show the register value read */
wdllinfo("%08x->%048\n", regaddr, regval);
wdinfo("%08x->%048\n", regaddr, regval);
return regval;
}
#endif
@ -237,7 +237,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr)
{
/* Show the register value being written */
wdllinfo("%08x<-%08x\n", regaddr, regval);
wdinfo("%08x<-%08x\n", regaddr, regval);
/* Write the value */

2
arch/arm/src/stm32/stm32_adc.c
View file

@ -1717,7 +1717,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
int ret;
#endif
allinfo("intf: %d\n", priv->intf);
ainfo("intf: %d\n", priv->intf);
flags = enter_critical_section();
#if defined(CONFIG_STM32_STM32L15XX) && \

30
arch/arm/src/stm32/stm32_can.c
View file

@ -540,7 +540,7 @@ static void can_reset(FAR struct can_dev_s *dev)
uint32_t regbit = 0;
irqstate_t flags;
canllinfo("CAN%d\n", priv->port);
caninfo("CAN%d\n", priv->port);
/* Get the bits in the AHB1RSTR register needed to reset this CAN device */
@ -602,8 +602,8 @@ static int can_setup(FAR struct can_dev_s *dev)
FAR struct stm32_can_s *priv = dev->cd_priv;
int ret;
canllinfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n",
priv->port, priv->canrx[0], priv->canrx[1], priv->cantx);
caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n",
priv->port, priv->canrx[0], priv->canrx[1], priv->cantx);
/* CAN cell initialization */
@ -685,7 +685,7 @@ static void can_shutdown(FAR struct can_dev_s *dev)
{
FAR struct stm32_can_s *priv = dev->cd_priv;
canllinfo("CAN%d\n", priv->port);
caninfo("CAN%d\n", priv->port);
/* Disable the RX FIFO 0/1 and TX interrupts */
@ -723,7 +723,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
FAR struct stm32_can_s *priv = dev->cd_priv;
uint32_t regval;
canllinfo("CAN%d enable: %d\n", priv->port, enable);
caninfo("CAN%d enable: %d\n", priv->port, enable);
/* Enable/disable the FIFO 0/1 message pending interrupt */
@ -758,7 +758,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
FAR struct stm32_can_s *priv = dev->cd_priv;
uint32_t regval;
canllinfo("CAN%d enable: %d\n", priv->port, enable);
caninfo("CAN%d enable: %d\n", priv->port, enable);
/* Support only disabling the transmit mailbox interrupt */
@ -843,8 +843,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
int dlc;
int txmb;
canllinfo("CAN%d ID: %d DLC: %d\n",
priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
caninfo("CAN%d ID: %d DLC: %d\n",
priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
/* Select one empty transmit mailbox */
@ -996,7 +996,7 @@ static bool can_txready(FAR struct can_dev_s *dev)
/* Return true if any mailbox is available */
regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
canllinfo("CAN%d TSR: %08x\n", priv->port, regval);
caninfo("CAN%d TSR: %08x\n", priv->port, regval);
return (regval & CAN_ALL_MAILBOXES) != 0;
}
@ -1027,7 +1027,7 @@ static bool can_txempty(FAR struct can_dev_s *dev)
/* Return true if all mailboxes are available */
regval = can_getreg(priv, STM32_CAN_TSR_OFFSET);
canllinfo("CAN%d TSR: %08x\n", priv->port, regval);
caninfo("CAN%d TSR: %08x\n", priv->port, regval);
return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES;
}
@ -1379,8 +1379,8 @@ static int can_bittiming(FAR struct stm32_can_s *priv)
uint32_t ts1;
uint32_t ts2;
canllinfo("CAN%d PCLK1: %d baud: %d\n",
priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
caninfo("CAN%d PCLK1: %d baud: %d\n",
priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
/* Try to get CAN_BIT_QUANTA quanta in one bit_time.
*
@ -1432,7 +1432,7 @@ static int can_bittiming(FAR struct stm32_can_s *priv)
DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
}
canllinfo("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
caninfo("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
/* Configure bit timing. This also does the following, less obvious
* things. Unless loopback mode is enabled, it:
@ -1475,7 +1475,7 @@ static int can_cellinit(FAR struct stm32_can_s *priv)
uint32_t regval;
int ret;
canllinfo("CAN%d\n", priv->port);
caninfo("CAN%d\n", priv->port);
/* Exit from sleep mode */
@ -1601,7 +1601,7 @@ static int can_filterinit(FAR struct stm32_can_s *priv)
uint32_t regval;
uint32_t bitmask;
canllinfo("CAN%d filter: %d\n", priv->port, priv->filter);
caninfo("CAN%d filter: %d\n", priv->port, priv->filter);
/* Get the bitmask associated with the filter used by this CAN block */

132
arch/arm/src/stm32/stm32_dumpgpio.c
View file

@ -120,107 +120,107 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
flags = enter_critical_section();
#if defined(CONFIG_STM32_STM32F10XX)
_llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
{
_llinfo(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
getreg32(base + STM32_GPIO_CRH_OFFSET),
getreg32(base + STM32_GPIO_CRL_OFFSET),
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
_llinfo(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
getreg32(STM32_AFIO_EXTICR1),
getreg32(STM32_AFIO_EXTICR2),
getreg32(STM32_AFIO_EXTICR3),
getreg32(STM32_AFIO_EXTICR4));
_info(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
getreg32(base + STM32_GPIO_CRH_OFFSET),
getreg32(base + STM32_GPIO_CRL_OFFSET),
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
_info(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
getreg32(STM32_AFIO_EXTICR1),
getreg32(STM32_AFIO_EXTICR2),
getreg32(STM32_AFIO_EXTICR3),
getreg32(STM32_AFIO_EXTICR4));
}
else
{
_llinfo(" GPIO%c not enabled: APB2ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_APB2ENR));
_info(" GPIO%c not enabled: APB2ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_APB2ENR));
}
#elif defined(CONFIG_STM32_STM32L15XX)
DEBUGASSERT(port < STM32_NGPIO_PORTS);
_llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0)
{
_llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
_llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
_llinfo(" AFRH: %08x AFRL: %08x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET));
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
_info(" AFRH: %08x AFRL: %08x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET));
}
else
{
_llinfo(" GPIO%c not enabled: AHBENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_AHBENR));
_info(" GPIO%c not enabled: AHBENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_AHBENR));
}
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
DEBUGASSERT(port < STM32_NGPIO_PORTS);
_llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
/* GPIOs are always enabled */
_llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
_llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
_llinfo(" AFRH: %08x AFRL: %08x BRR: %04x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET),
getreg32(base + STM32_GPIO_BRR_OFFSET));
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
_info(" AFRH: %08x AFRL: %08x BRR: %04x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET),
getreg32(base + STM32_GPIO_BRR_OFFSET));
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
DEBUGASSERT(port < STM32_NGPIO_PORTS);
_llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
{
_llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
_llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
_llinfo(" AFRH: %08x AFRL: %08x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET));
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
_info(" AFRH: %08x AFRL: %08x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET));
}
else
{
_llinfo(" GPIO%c not enabled: AHB1ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
_info(" GPIO%c not enabled: AHB1ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
}
#else
# error "Unsupported STM32 chip"

90
arch/arm/src/stm32/stm32_eth.c
View file

@ -769,7 +769,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
if (count == 4)
{
nllinfo("...\n");
ninfo("...\n");
}
return val;
@ -786,7 +786,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
nllinfo("[repeats %d more times]\n", count-3);
ninfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -798,7 +798,7 @@ static uint32_t stm32_getreg(uint32_t addr)
/* Show the register value read */
nllinfo("%08x->%08x\n", addr, val);
ninfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@ -825,7 +825,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
nllinfo("%08x<-%08x\n", addr, val);
ninfo("%08x<-%08x\n", addr, val);
/* Write the value */
@ -1012,8 +1012,8 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
txdesc = priv->txhead;
txfirst = txdesc;
nllinfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
@ -1029,7 +1029,7 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
bufcount = (priv->dev.d_len + (CONFIG_STM32_ETH_BUFSIZE-1)) / CONFIG_STM32_ETH_BUFSIZE;
lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_STM32_ETH_BUFSIZE;
nllinfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
/* Set the first segment bit in the first TX descriptor */
@ -1139,8 +1139,8 @@ static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
priv->inflight++;
nllinfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
ninfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
/* If all TX descriptors are in-flight, then we have to disable receive interrupts
* too. This is because receive events can trigger more un-stoppable transmit
@ -1438,7 +1438,7 @@ static void stm32_freesegment(FAR struct stm32_ethmac_s *priv,
struct eth_rxdesc_s *rxdesc;
int i;
nllinfo("rxfirst: %p segments: %d\n", rxfirst, segments);
ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
/* Set OWN bit in RX descriptors. This gives the buffers back to DMA */
@ -1496,8 +1496,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
uint8_t *buffer;
int i;
nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
/* Check if there are free buffers. We cannot receive new frames in this
* design unless there is at least one free buffer.
@ -1505,7 +1505,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
if (!stm32_isfreebuffer(priv))
{
nllerr("ERROR: No free buffers\n");
nerr("ERROR: No free buffers\n");
return -ENOMEM;
}
@ -1562,7 +1562,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
rxcurr = priv->rxcurr;
}
nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
/* Check if any errors are reported in the frame */
@ -1601,8 +1601,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3;
stm32_freesegment(priv, rxcurr, priv->segments);
nllinfo("rxhead: %p d_buf: %p d_len: %d\n",
priv->rxhead, dev->d_buf, dev->d_len);
ninfo("rxhead: %p d_buf: %p d_len: %d\n",
priv->rxhead, dev->d_buf, dev->d_len);
return OK;
}
@ -1612,7 +1612,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
* scanning logic, and continue scanning with the next frame.
*/
nllerr("ERROR: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0);
nerr("ERROR: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0);
stm32_freesegment(priv, rxcurr, priv->segments);
}
}
@ -1628,8 +1628,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
priv->rxhead = rxdesc;
nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
return -EAGAIN;
}
@ -1673,7 +1673,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
nllerr("ERROR: Dropped, Too big: %d\n", dev->d_len);
nerr("ERROR: Dropped, Too big: %d\n", dev->d_len);
/* Free dropped packet buffer */
@ -1698,7 +1698,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
nllinfo("IPv4 frame\n");
ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@ -1738,7 +1738,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
nllinfo("Iv6 frame\n");
ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@ -1775,7 +1775,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
nllinfo("ARP frame\n");
ninfo("ARP frame\n");
/* Handle ARP packet */
@ -1793,7 +1793,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
else
#endif
{
nllerr("ERROR: Dropped, Unknown type: %04x\n", BUF->type);
nerr("ERROR: Dropped, Unknown type: %04x\n", BUF->type);
}
/* We are finished with the RX buffer. NOTE: If the buffer is
@ -1834,8 +1834,8 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
int i;
nllinfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
ninfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
/* Scan for "in-flight" descriptors owned by the CPU */
@ -1850,8 +1850,8 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
* TX descriptors.
*/
nllinfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
ninfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
DEBUGASSERT(txdesc->tdes2 != 0);
@ -1903,8 +1903,8 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
priv->txtail = txdesc;
nllinfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
ninfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
}
}
@ -2042,7 +2042,7 @@ static inline void stm32_interrupt_process(FAR struct stm32_ethmac_s *priv)
{
/* Just let the user know what happened */
nllerr("ERROR: Abormal event(s): %08x\n", dmasr);
nerr("ERROR: Abormal event(s): %08x\n", dmasr);
/* Clear all pending abnormal events */
@ -2246,7 +2246,7 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...)
{
FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg;
nllerr("ERROR: Timeout!\n");
nerr("ERROR: Timeout!\n");
#ifdef CONFIG_NET_NOINTS
/* Disable further Ethernet interrupts. This will prevent some race
@ -2712,8 +2712,8 @@ static int stm32_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Add the MAC address to the hardware multicast hash table */
@ -2769,8 +2769,8 @@ static int stm32_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Remove the MAC address to the hardware multicast hash table */
@ -3853,11 +3853,11 @@ static void stm32_macaddress(FAR struct stm32_ethmac_s *priv)
FAR struct net_driver_s *dev = &priv->dev;
uint32_t regval;
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address high register */
@ -4059,12 +4059,12 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
/* Reset the Ethernet block */
nllinfo("Reset the Ethernet block\n");
ninfo("Reset the Ethernet block\n");
stm32_ethreset(priv);
/* Initialize the PHY */
nllinfo("Initialize the PHY\n");
ninfo("Initialize the PHY\n");
ret = stm32_phyinit(priv);
if (ret < 0)
{
@ -4073,7 +4073,7 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
/* Initialize the MAC and DMA */
nllinfo("Initialize the MAC and DMA\n");
ninfo("Initialize the MAC and DMA\n");
ret = stm32_macconfig(priv);
if (ret < 0)
{
@ -4094,7 +4094,7 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
/* Enable normal MAC operation */
nllinfo("Enable normal operation\n");
ninfo("Enable normal operation\n");
return stm32_macenable(priv);
}

Some files were not shown because too many files have changed in this diff Show more