diff --git a/arch/mips/src/mips32/Kconfig b/arch/mips/src/mips32/Kconfig
index d740b1b255e..d8ea58a3601 100644
--- a/arch/mips/src/mips32/Kconfig
+++ b/arch/mips/src/mips32/Kconfig
@@ -92,6 +92,10 @@ config MIPS32_FRAMEPOINTER
 		Register r30 may be a frame pointer in some ABIs.  Or may just be
 		saved register s8.  It makes a difference for fork handling.
 
+config MIPS32_USE_SYSCALL_INSTRUCTION
+	bool
+	default n
+
 config MIPS32_HAVE_ICACHE
 	bool
 	default n
diff --git a/arch/mips/src/mips32/mips_irq.c b/arch/mips/src/mips32/mips_irq.c
index 94eddd51436..2def6dd9803 100644
--- a/arch/mips/src/mips32/mips_irq.c
+++ b/arch/mips/src/mips32/mips_irq.c
@@ -56,7 +56,9 @@ irqstate_t up_irq_save(void)
   status  = cp0_getstatus();       /* Get CP0 status */
   ret     = status;                /* Save the status */
   status &= ~CP0_STATUS_INT_MASK;  /* Clear all interrupt mask bits */
+#ifndef CONFIG_MIPS32_USE_SYSCALL_INSTRUCTION
   status |= CP0_STATUS_INT_SW0;    /* Enable only the SW0 interrupt */
+#endif
   cp0_putstatus(status);           /* Disable the rest of interrupts */
   return ret;                      /* Return saved status */
 }
diff --git a/arch/mips/src/mips32/mips_schedulesigaction.c b/arch/mips/src/mips32/mips_schedulesigaction.c
index f0e25acd456..decd2d26e4e 100644
--- a/arch/mips/src/mips32/mips_schedulesigaction.c
+++ b/arch/mips/src/mips32/mips_schedulesigaction.c
@@ -106,7 +106,9 @@ void up_schedule_sigaction(struct tcb_s *tcb)
       up_current_regs()[REG_EPC] = (uint32_t)mips_sigdeliver;
       status  = up_current_regs()[REG_STATUS];
       status &= ~CP0_STATUS_INT_MASK;
+#ifndef CONFIG_MIPS32_USE_SYSCALL_INSTRUCTION
       status |= CP0_STATUS_INT_SW0;
+#endif
       up_current_regs()[REG_STATUS]  = status;
 
       /* And make sure that the saved context in the TCB
@@ -145,7 +147,9 @@ void up_schedule_sigaction(struct tcb_s *tcb)
       tcb->xcp.regs[REG_EPC]     = (uint32_t)mips_sigdeliver;
       status                     = tcb->xcp.regs[REG_STATUS];
       status                    &= ~CP0_STATUS_INT_MASK;
+#ifndef CONFIG_MIPS32_USE_SYSCALL_INSTRUCTION
       status                    |= CP0_STATUS_INT_SW0;
+#endif
       tcb->xcp.regs[REG_STATUS]  = status;
 
       sinfo("PC/STATUS Saved: %08" PRIx32 "/%08" PRIx32
diff --git a/arch/mips/src/mips32/mips_syscall0.S b/arch/mips/src/mips32/mips_syscall0.S
index c2db024df8b..9c8dda46d0a 100644
--- a/arch/mips/src/mips32/mips_syscall0.S
+++ b/arch/mips/src/mips32/mips_syscall0.S
@@ -51,6 +51,39 @@
  * Public Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: up_syscall0, up_syscall1, up_syscall2, up_syscall3
+ *
+ * Description:
+ *   up_syscall0 - System call SYS_ argument and no additional parameters.
+ *   up_syscall1 - System call SYS_ argument and one additional parameter.
+ *   up_syscall2 - System call SYS_ argument and two additional parameters.
+ *   up_syscall3 - System call SYS_ argument and three additional parameters.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MIPS32_USE_SYSCALL_INSTRUCTION
+
+	.text
+	.set	noreorder
+	.set	nomips16
+#ifdef CONFIG_MIPS_MICROMIPS
+	.set	micromips
+#endif
+	.ent	sys_call0
+
+sys_call0:
+sys_call1:
+sys_call2:
+sys_call3:
+
+	syscall
+
+	j		ra
+	nop
+
+#else
+
 /****************************************************************************
  * Name: up_syscall0, up_syscall1, up_syscall2, up_syscall3
  *
@@ -102,4 +135,6 @@ sys_call3:	/* r4 holds the syscall number, arguments in r5, r6, and r7 */
 
 	j		ra
 	nop
+#endif
+
 	.end	sys_call0