diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index 52ca4659746..f7262145932 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -107,6 +107,7 @@ void arm_gic0_initialize(void) /* Registers with 2-bits per interrupt */ + putreg32(0x5555ffff, GIC_ICDICFR(GIC_IRQ_SGI0)); /* SGIs are edge sensitive */ for (irq = GIC_IRQ_SPI; irq < nlines; irq += 16) { //putreg32(0xffffffff, GIC_ICDICFR(irq)); /* SPIs edge sensitive */ @@ -574,5 +575,4 @@ int arm_gic_irq_trigger(int irq, bool edge) return -EINVAL; } - #endif /* CONFIG_ARMV7A_HAVE_GICv2 */ diff --git a/arch/arm/src/stm32/chip/stm32_dac.h b/arch/arm/src/stm32/chip/stm32_dac.h index 81a69b71e68..61332080eab 100644 --- a/arch/arm/src/stm32/chip/stm32_dac.h +++ b/arch/arm/src/stm32/chip/stm32_dac.h @@ -51,17 +51,17 @@ #define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ #define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel1 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel1 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel1 8-bit right aligned data holding register */ -#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel2 12-bit right aligned data holding register */ -#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel2 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ #define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ #define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ #define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel1 data output register */ -#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel2 data output register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ #define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ /* Register Addresses ***************************************************************/ @@ -164,10 +164,10 @@ /* These definitions may be used with the full, 32-bit register */ -#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel1 enable */ -#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel1 trigger enable */ -#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel1 trigger selection */ +#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ +#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel 1 output buffer disable */ +#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel 1 trigger enable */ +#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel 1 trigger selection */ #define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT) # define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */ # define DAC_CR_TSEL1_TIM8 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 8 TRGO event */ @@ -177,12 +177,12 @@ # define DAC_CR_TSEL1_TIM4 (5 << DAC_CR_TSEL1_SHIFT) /* Timer 4 TRGO event */ # define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */ # define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */ -#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel1 noise/triangle wave generation */enable +#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */enable #define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT) # define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ # define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ # define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ -#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ #define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT) # define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ # define DAC_CR_MAMP1_AMP3 (1 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ @@ -196,13 +196,13 @@ # define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ # define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ # define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ -#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel1 DMA enable */ -#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel1 DMA Underrun Interrupt enable */ +#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ +#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */ -#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel2 enable */ -#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel2 trigger enable */ -#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel2 trigger selection */ +#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ +#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */ +#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */ +#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ #define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT) # define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */ # define DAC_CR_TSEL2_TIM8 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 8 TRGO event */ @@ -212,12 +212,12 @@ # define DAC_CR_TSEL2_TIM4 (5 << DAC_CR_TSEL2_SHIFT) /* Timer 4 TRGO event */ # define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */ # define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */ -#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel2 noise/triangle wave generation enable */ +#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */ #define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT) # define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ # define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ # define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ -#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel2 mask/amplitude selector */ +#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */ #define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT) # define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ # define DAC_CR_MAMP2_AMP3 (1 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ @@ -231,24 +231,24 @@ # define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ # define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ # define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ -#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel2 DMA enable */ -#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bits 29: DAC channel2 DMA underrun interrupt enable */ +#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ +#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bits 29: DAC channel 2 DMA underrun interrupt enable */ /* DAC software trigger register */ #define DAC_SWTRIGR_SWTRIG(n) (1 << ((n)-1)) -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel2 software trigger */ +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */ -/* DAC channel1/2 12-bit right-aligned data holding register */ +/* DAC channel 1/2 12-bit right-aligned data holding register */ #define DAC_DHR12R_MASK (0x0fff) -/* DAC channel1/2 12-bit left aligned data holding register */ +/* DAC channel 1/2 12-bit left aligned data holding register */ #define DAC_DHR12L_MASK (0xfff0) -/* DAC channel1/2 8-bit right aligned data holding register */ +/* DAC channel 1/2 8-bit right aligned data holding register */ #define DAC_DHR8R_MASK (0x00ff) @@ -257,9 +257,9 @@ #define DAC_DHR12RD_DACC_SHIFT(n) (1 << (((n)-1) << 4)) #define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n)) -#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel1 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */ #define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) -#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel2 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */ #define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) /* Dual DAC 12-bit left-aligned data holding register */ @@ -267,9 +267,9 @@ #define DAC_DHR12LD_DACC_SHIFT(n) ((1 << (((n)-1) << 4)) + 4) #define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n)) -#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */ #define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT) -#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel2 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */ #define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT) /* DUAL DAC 8-bit right aligned data holding register */ @@ -277,19 +277,19 @@ #define DAC_DHR8RD_DACC_SHIFT(n) (1 << (((n)-1) << 3)) #define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n)) -#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */ #define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT) -#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel2 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */ #define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT) -/* DAC channel1/2 data output register */ +/* DAC channel 1/2 data output register */ #define DAC_DOR_MASK (0x0fff) /* DAC status register */ #define DAC_SR_DMAUDR(n) ((1 << (((n)-1) << 4)) + 13) -#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel2 DMA underrun flag */ +#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c index fdcbaf050a9..796bb81d213 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/stm32/stm32_dac.c @@ -472,7 +472,7 @@ static struct dac_dev_s g_dac2dev = #endif #ifdef CONFIG_STM32_DAC2 -/* Channel 1 */ +/* Channel 3 */ static struct stm32_chan_s g_dac3priv = { @@ -514,9 +514,18 @@ static struct stm32_dac_s g_dacblock; static inline void stm32_dac_modify_cr(FAR struct stm32_chan_s *chan, uint32_t clearbits, uint32_t setbits) { - uint32_t shift; + unsigned int shift; - shift = chan->intf * 16; + /* DAC1 channels 1 and 2 share the STM32_DAC[1]_CR control register. DAC2 + * channel 1 (and perhaps channel 2) uses the STM32_DAC2_CR control + * register. In either case, bit 0 of the interface number provides the + * correct shift. + * + * Bit 0 = 0: Shift = 0 + * Bit 0 = 1: Shift = 16 + */ + + shift = (chan->intf & 1) << 4; modifyreg32(chan->cr, clearbits << shift, setbits << shift); }