From 3dad6b273e80287c01a57b120dfacffa41c98194 Mon Sep 17 00:00:00 2001 From: Lucas Saavedra Vaz Date: Wed, 28 Dec 2022 03:01:11 -0300 Subject: [PATCH] arch/xtensa/esp32s2: Add missing SENS and RTCCNTL registers --- .../src/esp32s2/hardware/esp32s2_rtccntl.h | 651 ++++++- .../src/esp32s2/hardware/esp32s2_sens.h | 1724 +++++++++++++++++ 2 files changed, 2363 insertions(+), 12 deletions(-) create mode 100644 arch/xtensa/src/esp32s2/hardware/esp32s2_sens.h diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h index 45f93ce4e40..205f262b330 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h @@ -4262,6 +4262,594 @@ #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0x0000000F #define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 +/* RTC_CNTL_ULP_CP_TIMER_REG register + * Description + */ + +#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xf8) + +/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W; bitpos: [31]; default: 0; + * ULP-coprocessor timer enable bit + */ + +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (RTC_CNTL_ULP_CP_SLP_TIMER_EN_V << RTC_CNTL_ULP_CP_SLP_TIMER_EN_S) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x00000001 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 + +/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO; bitpos: [30]; default: 0; + * ULP-coprocessor wakeup by GPIO state clear + */ + +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x00000001 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 + +/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W; bitpos: [29]; default: 0; + * ULP-coprocessor wakeup by GPIO enable + */ + +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x00000001 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 + +/* RTC_CNTL_ULP_CP_PC_INIT : R/W; bitpos: [10:0]; default: 0; + * ULP-coprocessor PC initial address + */ + +#define RTC_CNTL_ULP_CP_PC_INIT 0x000007ff +#define RTC_CNTL_ULP_CP_PC_INIT_M (RTC_CNTL_ULP_CP_PC_INIT_V << RTC_CNTL_ULP_CP_PC_INIT_S) +#define RTC_CNTL_ULP_CP_PC_INIT_V 0x000007ff +#define RTC_CNTL_ULP_CP_PC_INIT_S 0 + +/* RTC_CNTL_ULP_CP_CTRL_REG register + * Description + */ + +#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0xfc) + +/* RTC_CNTL_ULP_CP_START_TOP : R/W; bitpos: [31]; default: 0; + * Write 1 to start ULP-coprocessor + */ + +#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) +#define RTC_CNTL_ULP_CP_START_TOP_M (RTC_CNTL_ULP_CP_START_TOP_V << RTC_CNTL_ULP_CP_START_TOP_S) +#define RTC_CNTL_ULP_CP_START_TOP_V 0x00000001 +#define RTC_CNTL_ULP_CP_START_TOP_S 31 + +/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W; bitpos: [30]; default: 0; + * 1: ULP-coprocessor is started by SW + */ + +#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (RTC_CNTL_ULP_CP_FORCE_START_TOP_V << RTC_CNTL_ULP_CP_FORCE_START_TOP_S) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x00000001 +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 + +/* RTC_CNTL_ULP_CP_RESET : R/W; bitpos: [29]; default: 0; + * ulp coprocessor clk software reset + */ + +#define RTC_CNTL_ULP_CP_RESET (BIT(29)) +#define RTC_CNTL_ULP_CP_RESET_M (RTC_CNTL_ULP_CP_RESET_V << RTC_CNTL_ULP_CP_RESET_S) +#define RTC_CNTL_ULP_CP_RESET_V 0x00000001 +#define RTC_CNTL_ULP_CP_RESET_S 29 + +/* RTC_CNTL_ULP_CP_CLK_FO : R/W; bitpos: [28]; default: 0; + * ulp coprocessor clk force on + */ + +#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) +#define RTC_CNTL_ULP_CP_CLK_FO_M (RTC_CNTL_ULP_CP_CLK_FO_V << RTC_CNTL_ULP_CP_CLK_FO_S) +#define RTC_CNTL_ULP_CP_CLK_FO_V 0x00000001 +#define RTC_CNTL_ULP_CP_CLK_FO_S 28 + +/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO; bitpos: [22]; default: 0; */ + +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V << RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x00000001 +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 + +/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W; bitpos: [21:11]; default: 512; */ + +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007ff +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M (RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V << RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S) +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x000007ff +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 + +/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W; bitpos: [10:0]; default: 512; */ + +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007ff +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M (RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V << RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S) +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x000007ff +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 + +/* RTC_CNTL_COCPU_CTRL_REG register + * Description + */ + +#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100) + +/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO; bitpos: [26]; default: 0; + * trigger cocpu register interrupt + */ + +#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (RTC_CNTL_COCPU_SW_INT_TRIGGER_V << RTC_CNTL_COCPU_SW_INT_TRIGGER_S) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x00000001 +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 + +/* RTC_CNTL_COCPU_DONE : R/W; bitpos: [25]; default: 0; + * done signal used by riscv to control timer. + */ + +#define RTC_CNTL_COCPU_DONE (BIT(25)) +#define RTC_CNTL_COCPU_DONE_M (RTC_CNTL_COCPU_DONE_V << RTC_CNTL_COCPU_DONE_S) +#define RTC_CNTL_COCPU_DONE_V 0x00000001 +#define RTC_CNTL_COCPU_DONE_S 25 + +/* RTC_CNTL_COCPU_DONE_FORCE : R/W; bitpos: [24]; default: 0; + * 1: select riscv done 0: select ulp done + */ + +#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_M (RTC_CNTL_COCPU_DONE_FORCE_V << RTC_CNTL_COCPU_DONE_FORCE_S) +#define RTC_CNTL_COCPU_DONE_FORCE_V 0x00000001 +#define RTC_CNTL_COCPU_DONE_FORCE_S 24 + +/* RTC_CNTL_COCPU_SEL : R/W; bitpos: [23]; default: 1; + * 1: old ULP 0: new riscV + */ + +#define RTC_CNTL_COCPU_SEL (BIT(23)) +#define RTC_CNTL_COCPU_SEL_M (RTC_CNTL_COCPU_SEL_V << RTC_CNTL_COCPU_SEL_S) +#define RTC_CNTL_COCPU_SEL_V 0x00000001 +#define RTC_CNTL_COCPU_SEL_S 23 + +/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W; bitpos: [22]; default: 0; + * to reset cocpu + */ + +#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (RTC_CNTL_COCPU_SHUT_RESET_EN_V << RTC_CNTL_COCPU_SHUT_RESET_EN_S) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x00000001 +#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 + +/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W; bitpos: [21:14]; default: 40; + * time from shut cocpu to disable clk + */ + +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000ff +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M (RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V << RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S) +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0x000000ff +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 + +/* RTC_CNTL_COCPU_SHUT : R/W; bitpos: [13]; default: 0; + * to shut cocpu + */ + +#define RTC_CNTL_COCPU_SHUT (BIT(13)) +#define RTC_CNTL_COCPU_SHUT_M (RTC_CNTL_COCPU_SHUT_V << RTC_CNTL_COCPU_SHUT_S) +#define RTC_CNTL_COCPU_SHUT_V 0x00000001 +#define RTC_CNTL_COCPU_SHUT_S 13 + +/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W; bitpos: [12:7]; default: 16; + * time from start cocpu to give start interrupt + */ + +#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003f +#define RTC_CNTL_COCPU_START_2_INTR_EN_M (RTC_CNTL_COCPU_START_2_INTR_EN_V << RTC_CNTL_COCPU_START_2_INTR_EN_S) +#define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x0000003f +#define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 + +/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W; bitpos: [6:1]; default: 8; + * time from start cocpu to pull down reset + */ + +#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003f +#define RTC_CNTL_COCPU_START_2_RESET_DIS_M (RTC_CNTL_COCPU_START_2_RESET_DIS_V << RTC_CNTL_COCPU_START_2_RESET_DIS_S) +#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x0000003f +#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 + +/* RTC_CNTL_COCPU_CLK_FO : R/W; bitpos: [0]; default: 0; + * cocpu clk force on + */ + +#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) +#define RTC_CNTL_COCPU_CLK_FO_M (RTC_CNTL_COCPU_CLK_FO_V << RTC_CNTL_COCPU_CLK_FO_S) +#define RTC_CNTL_COCPU_CLK_FO_V 0x00000001 +#define RTC_CNTL_COCPU_CLK_FO_S 0 + +/* RTC_CNTL_TOUCH_CTRL1_REG register + * Description + */ + +#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x104) + +/* RTC_CNTL_TOUCH_MEAS_NUM : R/W; bitpos: [31:16]; default: 4096; + * the meas length (in 8MHz) + */ + +#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000ffff +#define RTC_CNTL_TOUCH_MEAS_NUM_M (RTC_CNTL_TOUCH_MEAS_NUM_V << RTC_CNTL_TOUCH_MEAS_NUM_S) +#define RTC_CNTL_TOUCH_MEAS_NUM_V 0x0000ffff +#define RTC_CNTL_TOUCH_MEAS_NUM_S 16 + +/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 256; + * sleep cycles for timer + */ + +#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000ffff +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M (RTC_CNTL_TOUCH_SLEEP_CYCLES_V << RTC_CNTL_TOUCH_SLEEP_CYCLES_S) +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0x0000ffff +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 + +/* RTC_CNTL_TOUCH_CTRL2_REG register + * Description + */ + +#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x108) + +/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W; bitpos: [31]; default: 0; + * touch clock enable + */ + +#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) +#define RTC_CNTL_TOUCH_CLKGATE_EN_M (RTC_CNTL_TOUCH_CLKGATE_EN_V << RTC_CNTL_TOUCH_CLKGATE_EN_S) +#define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x00000001 +#define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 + +/* RTC_CNTL_TOUCH_CLK_FO : R/W; bitpos: [30]; default: 0; + * touch clock force on + */ + +#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) +#define RTC_CNTL_TOUCH_CLK_FO_M (RTC_CNTL_TOUCH_CLK_FO_V << RTC_CNTL_TOUCH_CLK_FO_S) +#define RTC_CNTL_TOUCH_CLK_FO_V 0x00000001 +#define RTC_CNTL_TOUCH_CLK_FO_S 30 + +/* RTC_CNTL_TOUCH_RESET : R/W; bitpos: [29]; default: 0; + * reset upgrade touch + */ + +#define RTC_CNTL_TOUCH_RESET (BIT(29)) +#define RTC_CNTL_TOUCH_RESET_M (RTC_CNTL_TOUCH_RESET_V << RTC_CNTL_TOUCH_RESET_S) +#define RTC_CNTL_TOUCH_RESET_V 0x00000001 +#define RTC_CNTL_TOUCH_RESET_S 29 + +/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W; bitpos: [28:27]; default: 0; + * force touch timer done + */ + +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M (RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V << RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S) +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x00000003 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 + +/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W; bitpos: [26:25]; default: 0; + * when a touch pad is active, sleep cycle could be divided by this number + */ + +#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M (RTC_CNTL_TOUCH_SLP_CYC_DIV_V << RTC_CNTL_TOUCH_SLP_CYC_DIV_S) +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x00000003 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 + +/* RTC_CNTL_TOUCH_XPD_WAIT : R/W; bitpos: [24:17]; default: 4; + * the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD + */ + +#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000ff +#define RTC_CNTL_TOUCH_XPD_WAIT_M (RTC_CNTL_TOUCH_XPD_WAIT_V << RTC_CNTL_TOUCH_XPD_WAIT_S) +#define RTC_CNTL_TOUCH_XPD_WAIT_V 0x000000ff +#define RTC_CNTL_TOUCH_XPD_WAIT_S 17 + +/* RTC_CNTL_TOUCH_START_FORCE : R/W; bitpos: [16]; default: 0; + * 1: to start touch fsm by SW + */ + +#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) +#define RTC_CNTL_TOUCH_START_FORCE_M (RTC_CNTL_TOUCH_START_FORCE_V << RTC_CNTL_TOUCH_START_FORCE_S) +#define RTC_CNTL_TOUCH_START_FORCE_V 0x00000001 +#define RTC_CNTL_TOUCH_START_FORCE_S 16 + +/* RTC_CNTL_TOUCH_START_EN : R/W; bitpos: [15]; default: 0; + * 1: start touch fsm + */ + +#define RTC_CNTL_TOUCH_START_EN (BIT(15)) +#define RTC_CNTL_TOUCH_START_EN_M (RTC_CNTL_TOUCH_START_EN_V << RTC_CNTL_TOUCH_START_EN_S) +#define RTC_CNTL_TOUCH_START_EN_V 0x00000001 +#define RTC_CNTL_TOUCH_START_EN_S 15 + +/* RTC_CNTL_TOUCH_START_FSM_EN : R/W; bitpos: [14]; default: 1; + * 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm + */ + +#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) +#define RTC_CNTL_TOUCH_START_FSM_EN_M (RTC_CNTL_TOUCH_START_FSM_EN_V << RTC_CNTL_TOUCH_START_FSM_EN_S) +#define RTC_CNTL_TOUCH_START_FSM_EN_V 0x00000001 +#define RTC_CNTL_TOUCH_START_FSM_EN_S 14 + +/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W; bitpos: [13]; default: 0; + * touch timer enable bit + */ + +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (RTC_CNTL_TOUCH_SLP_TIMER_EN_V << RTC_CNTL_TOUCH_SLP_TIMER_EN_S) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x00000001 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 + +/* RTC_CNTL_TOUCH_DBIAS : R/W; bitpos: [12]; default: 0; + * 1:use self bias 0:use bandgap bias + */ + +#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_M (RTC_CNTL_TOUCH_DBIAS_V << RTC_CNTL_TOUCH_DBIAS_S) +#define RTC_CNTL_TOUCH_DBIAS_V 0x00000001 +#define RTC_CNTL_TOUCH_DBIAS_S 12 + +/* RTC_CNTL_TOUCH_REFC : R/W; bitpos: [11:9]; default: 0; + * TOUCH pad0 reference cap + */ + +#define RTC_CNTL_TOUCH_REFC 0x00000007 +#define RTC_CNTL_TOUCH_REFC_M (RTC_CNTL_TOUCH_REFC_V << RTC_CNTL_TOUCH_REFC_S) +#define RTC_CNTL_TOUCH_REFC_V 0x00000007 +#define RTC_CNTL_TOUCH_REFC_S 9 + +/* RTC_CNTL_TOUCH_XPD_BIAS : R/W; bitpos: [8]; default: 0; + * TOUCH_XPD_BIAS + */ + +#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) +#define RTC_CNTL_TOUCH_XPD_BIAS_M (RTC_CNTL_TOUCH_XPD_BIAS_V << RTC_CNTL_TOUCH_XPD_BIAS_S) +#define RTC_CNTL_TOUCH_XPD_BIAS_V 0x00000001 +#define RTC_CNTL_TOUCH_XPD_BIAS_S 8 + +/* RTC_CNTL_TOUCH_DREFH : R/W; bitpos: [7:6]; default: 3; + * TOUCH_DREFH + */ + +#define RTC_CNTL_TOUCH_DREFH 0x00000003 +#define RTC_CNTL_TOUCH_DREFH_M (RTC_CNTL_TOUCH_DREFH_V << RTC_CNTL_TOUCH_DREFH_S) +#define RTC_CNTL_TOUCH_DREFH_V 0x00000003 +#define RTC_CNTL_TOUCH_DREFH_S 6 + +/* RTC_CNTL_TOUCH_DREFL : R/W; bitpos: [5:4]; default: 0; + * TOUCH_DREFL + */ + +#define RTC_CNTL_TOUCH_DREFL 0x00000003 +#define RTC_CNTL_TOUCH_DREFL_M (RTC_CNTL_TOUCH_DREFL_V << RTC_CNTL_TOUCH_DREFL_S) +#define RTC_CNTL_TOUCH_DREFL_V 0x00000003 +#define RTC_CNTL_TOUCH_DREFL_S 4 + +/* RTC_CNTL_TOUCH_DRANGE : R/W; bitpos: [3:2]; default: 3; + * TOUCH_DRANGE + */ + +#define RTC_CNTL_TOUCH_DRANGE 0x00000003 +#define RTC_CNTL_TOUCH_DRANGE_M (RTC_CNTL_TOUCH_DRANGE_V << RTC_CNTL_TOUCH_DRANGE_S) +#define RTC_CNTL_TOUCH_DRANGE_V 0x00000003 +#define RTC_CNTL_TOUCH_DRANGE_S 2 + +/* RTC_CNTL_TOUCH_SCAN_CTRL_REG register + * Description + */ + +#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x10c) + +/* RTC_CNTL_TOUCH_OUT_RING : R/W; bitpos: [31:28]; default: 15; + * select out ring pad + */ + +#define RTC_CNTL_TOUCH_OUT_RING 0x0000000f +#define RTC_CNTL_TOUCH_OUT_RING_M (RTC_CNTL_TOUCH_OUT_RING_V << RTC_CNTL_TOUCH_OUT_RING_S) +#define RTC_CNTL_TOUCH_OUT_RING_V 0x0000000f +#define RTC_CNTL_TOUCH_OUT_RING_S 28 + +/* RTC_CNTL_TOUCH_BUFDRV : R/W; bitpos: [27:25]; default: 0; + * touch7 buffer driver strength + */ + +#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 +#define RTC_CNTL_TOUCH_BUFDRV_M (RTC_CNTL_TOUCH_BUFDRV_V << RTC_CNTL_TOUCH_BUFDRV_S) +#define RTC_CNTL_TOUCH_BUFDRV_V 0x00000007 +#define RTC_CNTL_TOUCH_BUFDRV_S 25 + +/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W; bitpos: [24:10]; default: 0; + * touch scan mode pad enable map + */ + +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007fff +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M (RTC_CNTL_TOUCH_SCAN_PAD_MAP_V << RTC_CNTL_TOUCH_SCAN_PAD_MAP_S) +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x00007fff +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 + +/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [9]; default: 0; + * touch pad14 will be used as shield + */ + +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (RTC_CNTL_TOUCH_SHIELD_PAD_EN_V << RTC_CNTL_TOUCH_SHIELD_PAD_EN_S) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x00000001 +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 + +/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W; bitpos: [8]; default: 1; + * inactive touch pads connect to 1: gnd 0: HighZ + */ + +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V << RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x00000001 +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 + +/* RTC_CNTL_TOUCH_DENOISE_EN : R/W; bitpos: [2]; default: 0; + * touch pad0 will be used to de-noise + */ + +#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) +#define RTC_CNTL_TOUCH_DENOISE_EN_M (RTC_CNTL_TOUCH_DENOISE_EN_V << RTC_CNTL_TOUCH_DENOISE_EN_S) +#define RTC_CNTL_TOUCH_DENOISE_EN_V 0x00000001 +#define RTC_CNTL_TOUCH_DENOISE_EN_S 2 + +/* RTC_CNTL_TOUCH_DENOISE_RES : R/W; bitpos: [1:0]; default: 2; + * De-noise resolution: 12/10/8/4 bit + */ + +#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 +#define RTC_CNTL_TOUCH_DENOISE_RES_M (RTC_CNTL_TOUCH_DENOISE_RES_V << RTC_CNTL_TOUCH_DENOISE_RES_S) +#define RTC_CNTL_TOUCH_DENOISE_RES_V 0x00000003 +#define RTC_CNTL_TOUCH_DENOISE_RES_S 0 + +/* RTC_CNTL_TOUCH_SLP_THRES_REG register + * Description + */ + +#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x110) + +/* RTC_CNTL_TOUCH_SLP_PAD : R/W; bitpos: [31:27]; default: 15; + * N/A + */ + +#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001f +#define RTC_CNTL_TOUCH_SLP_PAD_M (RTC_CNTL_TOUCH_SLP_PAD_V << RTC_CNTL_TOUCH_SLP_PAD_S) +#define RTC_CNTL_TOUCH_SLP_PAD_V 0x0000001f +#define RTC_CNTL_TOUCH_SLP_PAD_S 27 + +/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W; bitpos: [26]; default: 0; + * sleep pad approach function enable + */ + +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (RTC_CNTL_TOUCH_SLP_APPROACH_EN_V << RTC_CNTL_TOUCH_SLP_APPROACH_EN_S) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x00000001 +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 + +/* RTC_CNTL_TOUCH_SLP_TH : R/W; bitpos: [21:0]; default: 0; + * the threshold for sleep touch pad + */ + +#define RTC_CNTL_TOUCH_SLP_TH 0x003fffff +#define RTC_CNTL_TOUCH_SLP_TH_M (RTC_CNTL_TOUCH_SLP_TH_V << RTC_CNTL_TOUCH_SLP_TH_S) +#define RTC_CNTL_TOUCH_SLP_TH_V 0x003fffff +#define RTC_CNTL_TOUCH_SLP_TH_S 0 + +/* RTC_CNTL_TOUCH_APPROACH_REG register + * Description + */ + +#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x114) + +/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W; bitpos: [31:24]; default: 80; + * approach pads total meas times + */ + +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000ff +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M (RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V << RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S) +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0x000000ff +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 + +/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO; bitpos: [23]; default: 0; + * clear touch slp channel + */ + +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V << RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 + +/* RTC_CNTL_TOUCH_FILTER_CTRL_REG register + * Description + */ + +#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x118) + +/* RTC_CNTL_TOUCH_FILTER_EN : R/W; bitpos: [31]; default: 1; + * touch filter enable + */ + +#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) +#define RTC_CNTL_TOUCH_FILTER_EN_M (RTC_CNTL_TOUCH_FILTER_EN_V << RTC_CNTL_TOUCH_FILTER_EN_S) +#define RTC_CNTL_TOUCH_FILTER_EN_V 0x00000001 +#define RTC_CNTL_TOUCH_FILTER_EN_S 31 + +/* RTC_CNTL_TOUCH_FILTER_MODE : R/W; bitpos: [30:28]; default: 1; + * 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter + */ + +#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 +#define RTC_CNTL_TOUCH_FILTER_MODE_M (RTC_CNTL_TOUCH_FILTER_MODE_V << RTC_CNTL_TOUCH_FILTER_MODE_S) +#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x00000007 +#define RTC_CNTL_TOUCH_FILTER_MODE_S 28 + +/* RTC_CNTL_TOUCH_DEBOUNCE : R/W; bitpos: [27:25]; default: 3; + * debounce counter + */ + +#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 +#define RTC_CNTL_TOUCH_DEBOUNCE_M (RTC_CNTL_TOUCH_DEBOUNCE_V << RTC_CNTL_TOUCH_DEBOUNCE_S) +#define RTC_CNTL_TOUCH_DEBOUNCE_V 0x00000007 +#define RTC_CNTL_TOUCH_DEBOUNCE_S 25 + +/* RTC_CNTL_TOUCH_HYSTERESIS : R/W; bitpos: [24:23]; default: 1; + * N/A + */ + +#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 +#define RTC_CNTL_TOUCH_HYSTERESIS_M (RTC_CNTL_TOUCH_HYSTERESIS_V << RTC_CNTL_TOUCH_HYSTERESIS_S) +#define RTC_CNTL_TOUCH_HYSTERESIS_V 0x00000003 +#define RTC_CNTL_TOUCH_HYSTERESIS_S 23 + +/* RTC_CNTL_TOUCH_NOISE_THRES : R/W; bitpos: [22:21]; default: 1; + * N/A + */ + +#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 +#define RTC_CNTL_TOUCH_NOISE_THRES_M (RTC_CNTL_TOUCH_NOISE_THRES_V << RTC_CNTL_TOUCH_NOISE_THRES_S) +#define RTC_CNTL_TOUCH_NOISE_THRES_V 0x00000003 +#define RTC_CNTL_TOUCH_NOISE_THRES_S 21 + +/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W; bitpos: [20:19]; default: 1; + * N/A + */ + +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M (RTC_CNTL_TOUCH_NEG_NOISE_THRES_V << RTC_CNTL_TOUCH_NEG_NOISE_THRES_S) +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x00000003 +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19 + +/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W; bitpos: [18:15]; default: 5; + * negative threshold counter limit + */ + +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000f +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M (RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V << RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S) +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0x0000000f +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15 + +/* RTC_CNTL_TOUCH_JITTER_STEP : R/W; bitpos: [14:11]; default: 1; + * touch jitter step + */ + +#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000f +#define RTC_CNTL_TOUCH_JITTER_STEP_M (RTC_CNTL_TOUCH_JITTER_STEP_V << RTC_CNTL_TOUCH_JITTER_STEP_S) +#define RTC_CNTL_TOUCH_JITTER_STEP_V 0x0000000f +#define RTC_CNTL_TOUCH_JITTER_STEP_S 11 + +/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W; bitpos: [10:9]; default: 0; + * touch jitter step + */ + +#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_M (RTC_CNTL_TOUCH_SMOOTH_LVL_V << RTC_CNTL_TOUCH_SMOOTH_LVL_S) +#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x00000003 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 + /* RTC_CNTL_USB_CONF_REG register * configure usb control register */ @@ -4387,29 +4975,53 @@ #define RTC_CNTL_USB_VREFH_V 0x00000003 #define RTC_CNTL_USB_VREFH_S 0 +/* RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG register + * Description + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x120) + +/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W; bitpos: [22]; default: 1; + * N/A + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (RTC_CNTL_TOUCH_TIMEOUT_EN_V << RTC_CNTL_TOUCH_TIMEOUT_EN_S) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x00000001 +#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 + +/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:0]; default: 4194303; + * N/A + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003fffff +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M (RTC_CNTL_TOUCH_TIMEOUT_NUM_V << RTC_CNTL_TOUCH_TIMEOUT_NUM_S) +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x003fffff +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 + /* RTC_CNTL_SLP_REJECT_CAUSE_REG register - * sleep reject casue register + * Stores the reject-to-sleep cause. */ #define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x124) /* RTC_CNTL_REJECT_CAUSE : RO; bitpos: [16:0]; default: 0; - * sleep reject cause + * Stores the reject-to-sleep cause. */ -#define RTC_CNTL_REJECT_CAUSE 0x0001FFFF +#define RTC_CNTL_REJECT_CAUSE 0x0001ffff #define RTC_CNTL_REJECT_CAUSE_M (RTC_CNTL_REJECT_CAUSE_V << RTC_CNTL_REJECT_CAUSE_S) -#define RTC_CNTL_REJECT_CAUSE_V 0x0001FFFF +#define RTC_CNTL_REJECT_CAUSE_V 0x0001ffff #define RTC_CNTL_REJECT_CAUSE_S 0 /* RTC_CNTL_OPTION1_REG register - * configure rtc option + * RTC option register */ #define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x128) /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [0]; default: 0; - * force chip boot from download mode + * Set this bit to force the chip to boot from the download mode. */ #define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) @@ -4418,29 +5030,44 @@ #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 /* RTC_CNTL_SLP_WAKEUP_CAUSE_REG register - * sleep wakeup cause state register + * Stores the sleep-to-wakeup cause. */ #define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x12c) /* RTC_CNTL_WAKEUP_CAUSE : RO; bitpos: [16:0]; default: 0; - * sleep wakeup cause + * Stores the wakeup cause. */ -#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE 0x0001ffff #define RTC_CNTL_WAKEUP_CAUSE_M (RTC_CNTL_WAKEUP_CAUSE_V << RTC_CNTL_WAKEUP_CAUSE_S) -#define RTC_CNTL_WAKEUP_CAUSE_V 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_V 0x0001ffff #define RTC_CNTL_WAKEUP_CAUSE_S 0 +/* RTC_CNTL_ULP_CP_TIMER_1_REG register + * Description + */ + +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x130) + +/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W; bitpos: [31:8]; default: 200; + * sleep cycles for ULP-coprocessor timer + */ + +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00ffffff +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M (RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V << RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0x00ffffff +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 + /* RTC_CNTL_DATE_REG register */ #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x138) /* RTC_CNTL_CNTL_DATE : R/W; bitpos: [27:0]; default: 26239377; */ -#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE 0x0fffffff #define RTC_CNTL_CNTL_DATE_M (RTC_CNTL_CNTL_DATE_V << RTC_CNTL_CNTL_DATE_S) -#define RTC_CNTL_CNTL_DATE_V 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_V 0x0fffffff #define RTC_CNTL_CNTL_DATE_S 0 #endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCCNTL_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_sens.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_sens.h new file mode 100644 index 00000000000..127f96027ce --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_sens.h @@ -0,0 +1,1724 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_sens.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SENS_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SENS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SENS_SAR_READER1_CTRL_REG (DR_REG_SENS_BASE + 0x0000) + +/* SENS_SAR1_INT_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ + +#define SENS_SAR1_INT_EN (BIT(29)) +#define SENS_SAR1_INT_EN_M (BIT(29)) +#define SENS_SAR1_INT_EN_V 0x1 +#define SENS_SAR1_INT_EN_S 29 + +/* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */ + +#define SENS_SAR1_DATA_INV (BIT(28)) +#define SENS_SAR1_DATA_INV_M (BIT(28)) +#define SENS_SAR1_DATA_INV_V 0x1 +#define SENS_SAR1_DATA_INV_S 28 + +/* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ + +#define SENS_SAR1_SAMPLE_NUM 0x000000FF +#define SENS_SAR1_SAMPLE_NUM_M ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S)) +#define SENS_SAR1_SAMPLE_NUM_V 0xFF +#define SENS_SAR1_SAMPLE_NUM_S 19 + +/* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ + +#define SENS_SAR1_CLK_GATED (BIT(18)) +#define SENS_SAR1_CLK_GATED_M (BIT(18)) +#define SENS_SAR1_CLK_GATED_V 0x1 +#define SENS_SAR1_CLK_GATED_S 18 + +/* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ + +#define SENS_SAR1_CLK_DIV 0x000000FF +#define SENS_SAR1_CLK_DIV_M ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S)) +#define SENS_SAR1_CLK_DIV_V 0xFF +#define SENS_SAR1_CLK_DIV_S 0 + +#define SENS_SAR_READER1_STATUS_REG (DR_REG_SENS_BASE + 0x0004) + +/* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define SENS_SAR1_READER_STATUS 0xFFFFFFFF +#define SENS_SAR1_READER_STATUS_M ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S)) +#define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF +#define SENS_SAR1_READER_STATUS_S 0 + +#define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x0008) + +/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ + +#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S)) +#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_GND_FORCE_S 30 + +/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */ + +#define SENS_AMP_SHORT_REF_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S)) +#define SENS_AMP_SHORT_REF_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_FORCE_S 28 + +/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ + +#define SENS_AMP_RST_FB_FORCE 0x00000003 +#define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S)) +#define SENS_AMP_RST_FB_FORCE_V 0x3 +#define SENS_AMP_RST_FB_FORCE_S 26 + +/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ + +#define SENS_FORCE_XPD_AMP 0x00000003 +#define SENS_FORCE_XPD_AMP_M ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S)) +#define SENS_FORCE_XPD_AMP_V 0x3 +#define SENS_FORCE_XPD_AMP_S 24 +#define SENS_FORCE_XPD_AMP_FSM 0 +#define SENS_FORCE_XPD_AMP_PD 2 +#define SENS_FORCE_XPD_AMP_PU 3 + +/* SENS_RTC_CLKGATE_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ + +#define SENS_RTC_CLKGATE_EN (BIT(23)) +#define SENS_RTC_CLKGATE_EN_M (BIT(23)) +#define SENS_RTC_CLKGATE_EN_V 0x1 +#define SENS_RTC_CLKGATE_EN_S 23 + +/* SENS_RTC_RESET : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +#define SENS_RTC_RESET (BIT(22)) +#define SENS_RTC_RESET_M (BIT(22)) +#define SENS_RTC_RESET_V 0x1 +#define SENS_RTC_RESET_S 22 + +#define SENS_SAR_MEAS1_CTRL2_REG (DR_REG_SENS_BASE + 0x000c) + +/* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define SENS_SAR1_EN_PAD_FORCE (BIT(31)) +#define SENS_SAR1_EN_PAD_FORCE_M (BIT(31)) +#define SENS_SAR1_EN_PAD_FORCE_V 0x1 +#define SENS_SAR1_EN_PAD_FORCE_S 31 + +/* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ + +#define SENS_SAR1_EN_PAD 0x00000FFF +#define SENS_SAR1_EN_PAD_M ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S)) +#define SENS_SAR1_EN_PAD_V 0xFFF +#define SENS_SAR1_EN_PAD_S 19 + +/* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ + +#define SENS_MEAS1_START_FORCE (BIT(18)) +#define SENS_MEAS1_START_FORCE_M (BIT(18)) +#define SENS_MEAS1_START_FORCE_V 0x1 +#define SENS_MEAS1_START_FORCE_S 18 + +/* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +#define SENS_MEAS1_START_SAR (BIT(17)) +#define SENS_MEAS1_START_SAR_M (BIT(17)) +#define SENS_MEAS1_START_SAR_V 0x1 +#define SENS_MEAS1_START_SAR_S 17 + +/* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ + +#define SENS_MEAS1_DONE_SAR (BIT(16)) +#define SENS_MEAS1_DONE_SAR_M (BIT(16)) +#define SENS_MEAS1_DONE_SAR_V 0x1 +#define SENS_MEAS1_DONE_SAR_S 16 + +/* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ + +#define SENS_MEAS1_DATA_SAR 0x0000FFFF +#define SENS_MEAS1_DATA_SAR_M ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S)) +#define SENS_MEAS1_DATA_SAR_V 0xFFFF +#define SENS_MEAS1_DATA_SAR_S 0 + +#define SENS_SAR_MEAS1_MUX_REG (DR_REG_SENS_BASE + 0x0010) + +/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[31] ;default: 1'd0 ; */ + +#define SENS_SAR1_DIG_FORCE (BIT(31)) +#define SENS_SAR1_DIG_FORCE_M (BIT(31)) +#define SENS_SAR1_DIG_FORCE_V 0x1 +#define SENS_SAR1_DIG_FORCE_S 31 + +#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x0014) + +/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ + +#define SENS_SAR1_ATTEN 0xFFFFFFFF +#define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S)) +#define SENS_SAR1_ATTEN_V 0xFFFFFFFF +#define SENS_SAR1_ATTEN_S 0 + +#define SENS_SAR_AMP_CTRL1_REG (DR_REG_SENS_BASE + 0x0018) + +/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ + +#define SENS_SAR_AMP_WAIT2 0x0000FFFF +#define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S)) +#define SENS_SAR_AMP_WAIT2_V 0xFFFF +#define SENS_SAR_AMP_WAIT2_S 16 + +/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ + +#define SENS_SAR_AMP_WAIT1 0x0000FFFF +#define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S)) +#define SENS_SAR_AMP_WAIT1_V 0xFFFF +#define SENS_SAR_AMP_WAIT1_S 0 + +#define SENS_SAR_AMP_CTRL2_REG (DR_REG_SENS_BASE + 0x001c) + +/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ + +#define SENS_SAR_AMP_WAIT3 0x0000FFFF +#define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S)) +#define SENS_SAR_AMP_WAIT3_V 0xFFFF +#define SENS_SAR_AMP_WAIT3_S 16 + +/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define SENS_SAR_RSTB_FSM_IDLE (BIT(6)) +#define SENS_SAR_RSTB_FSM_IDLE_M (BIT(6)) +#define SENS_SAR_RSTB_FSM_IDLE_V 0x1 +#define SENS_SAR_RSTB_FSM_IDLE_S 6 + +/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define SENS_XPD_SAR_FSM_IDLE (BIT(5)) +#define SENS_XPD_SAR_FSM_IDLE_M (BIT(5)) +#define SENS_XPD_SAR_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_FSM_IDLE_S 5 + +/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(4)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(4)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 4 + +/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(3)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(3)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_FSM_IDLE_S 3 + +/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define SENS_AMP_RST_FB_FSM_IDLE (BIT(2)) +#define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(2)) +#define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 +#define SENS_AMP_RST_FB_FSM_IDLE_S 2 + +/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(1)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(1)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_AMP_FSM_IDLE_S 1 + +/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(0)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(0)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 +#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 0 + +#define SENS_SAR_AMP_CTRL3_REG (DR_REG_SENS_BASE + 0x0020) + +/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[27:24] ;default: 4'b0000 ; */ + +#define SENS_SAR_RSTB_FSM 0x0000000F +#define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S)) +#define SENS_SAR_RSTB_FSM_V 0xF +#define SENS_SAR_RSTB_FSM_S 24 + +/* SENS_XPD_SAR_FSM : R/W ;bitpos:[23:20] ;default: 4'b0111 ; */ + +#define SENS_XPD_SAR_FSM 0x0000000F +#define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S)) +#define SENS_XPD_SAR_FSM_V 0xF +#define SENS_XPD_SAR_FSM_S 20 + +/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[19:16] ;default: 4'b0011 ; */ + +#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S)) +#define SENS_AMP_SHORT_REF_GND_FSM_V 0xF +#define SENS_AMP_SHORT_REF_GND_FSM_S 16 + +/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ + +#define SENS_AMP_SHORT_REF_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S)) +#define SENS_AMP_SHORT_REF_FSM_V 0xF +#define SENS_AMP_SHORT_REF_FSM_S 12 + +/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[11:8] ;default: 4'b1000 ; */ + +#define SENS_AMP_RST_FB_FSM 0x0000000F +#define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S)) +#define SENS_AMP_RST_FB_FSM_V 0xF +#define SENS_AMP_RST_FB_FSM_S 8 + +/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[7:4] ;default: 4'b1111 ; */ + +#define SENS_XPD_SAR_AMP_FSM 0x0000000F +#define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S)) +#define SENS_XPD_SAR_AMP_FSM_V 0xF +#define SENS_XPD_SAR_AMP_FSM_S 4 + +/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ + +#define SENS_SAR1_DAC_XPD_FSM 0x0000000F +#define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S)) +#define SENS_SAR1_DAC_XPD_FSM_V 0xF +#define SENS_SAR1_DAC_XPD_FSM_S 0 + +#define SENS_SAR_READER2_CTRL_REG (DR_REG_SENS_BASE + 0x0024) + +/* SENS_SAR2_INT_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ + +#define SENS_SAR2_INT_EN (BIT(30)) +#define SENS_SAR2_INT_EN_M (BIT(30)) +#define SENS_SAR2_INT_EN_V 0x1 +#define SENS_SAR2_INT_EN_S 30 + +/* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +#define SENS_SAR2_DATA_INV (BIT(29)) +#define SENS_SAR2_DATA_INV_M (BIT(29)) +#define SENS_SAR2_DATA_INV_V 0x1 +#define SENS_SAR2_DATA_INV_S 29 + +/* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ + +#define SENS_SAR2_SAMPLE_NUM 0x000000FF +#define SENS_SAR2_SAMPLE_NUM_M ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S)) +#define SENS_SAR2_SAMPLE_NUM_V 0xFF +#define SENS_SAR2_SAMPLE_NUM_S 19 + +/* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ + +#define SENS_SAR2_CLK_GATED (BIT(18)) +#define SENS_SAR2_CLK_GATED_M (BIT(18)) +#define SENS_SAR2_CLK_GATED_V 0x1 +#define SENS_SAR2_CLK_GATED_S 18 + +/* SENS_SAR2_WAIT_ARB_CYCLE : R/W ;bitpos:[17:16] ;default: 2'b1 ; */ + +#define SENS_SAR2_WAIT_ARB_CYCLE 0x00000003 +#define SENS_SAR2_WAIT_ARB_CYCLE_M ((SENS_SAR2_WAIT_ARB_CYCLE_V)<<(SENS_SAR2_WAIT_ARB_CYCLE_S)) +#define SENS_SAR2_WAIT_ARB_CYCLE_V 0x3 +#define SENS_SAR2_WAIT_ARB_CYCLE_S 16 + +/* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ + +#define SENS_SAR2_CLK_DIV 0x000000FF +#define SENS_SAR2_CLK_DIV_M ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S)) +#define SENS_SAR2_CLK_DIV_V 0xFF +#define SENS_SAR2_CLK_DIV_S 0 + +#define SENS_SAR_READER2_STATUS_REG (DR_REG_SENS_BASE + 0x0028) + +/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define SENS_SAR2_READER_STATUS 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S)) +#define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_S 0 + +#define SENS_SAR_MEAS2_CTRL1_REG (DR_REG_SENS_BASE + 0x002c) + +/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ + +#define SENS_SAR2_XPD_WAIT 0x000000FF +#define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S)) +#define SENS_SAR2_XPD_WAIT_V 0xFF +#define SENS_SAR2_XPD_WAIT_S 24 + +/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[23:16] ;default: 8'd2 ; */ + +#define SENS_SAR2_RSTB_WAIT 0x000000FF +#define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S)) +#define SENS_SAR2_RSTB_WAIT_V 0xFF +#define SENS_SAR2_RSTB_WAIT_S 16 + +/* SENS_SAR2_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd2 ; */ + +#define SENS_SAR2_STANDBY_WAIT 0x000000FF +#define SENS_SAR2_STANDBY_WAIT_M ((SENS_SAR2_STANDBY_WAIT_V)<<(SENS_SAR2_STANDBY_WAIT_S)) +#define SENS_SAR2_STANDBY_WAIT_V 0xFF +#define SENS_SAR2_STANDBY_WAIT_S 8 + +/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ + +#define SENS_SAR2_RSTB_FORCE 0x00000003 +#define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S)) +#define SENS_SAR2_RSTB_FORCE_V 0x3 +#define SENS_SAR2_RSTB_FORCE_S 6 + +/* SENS_SAR2_EN_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define SENS_SAR2_EN_TEST (BIT(5)) +#define SENS_SAR2_EN_TEST_M (BIT(5)) +#define SENS_SAR2_EN_TEST_V 0x1 +#define SENS_SAR2_EN_TEST_S 5 + +/* SENS_SAR2_PKDET_CAL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +#define SENS_SAR2_PKDET_CAL_EN (BIT(4)) +#define SENS_SAR2_PKDET_CAL_EN_M (BIT(4)) +#define SENS_SAR2_PKDET_CAL_EN_V 0x1 +#define SENS_SAR2_PKDET_CAL_EN_S 4 + +/* SENS_SAR2_PWDET_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +#define SENS_SAR2_PWDET_CAL_EN (BIT(3)) +#define SENS_SAR2_PWDET_CAL_EN_M (BIT(3)) +#define SENS_SAR2_PWDET_CAL_EN_V 0x1 +#define SENS_SAR2_PWDET_CAL_EN_S 3 + +/* SENS_SAR2_CNTL_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ + +#define SENS_SAR2_CNTL_STATE 0x00000007 +#define SENS_SAR2_CNTL_STATE_M ((SENS_SAR2_CNTL_STATE_V)<<(SENS_SAR2_CNTL_STATE_S)) +#define SENS_SAR2_CNTL_STATE_V 0x7 +#define SENS_SAR2_CNTL_STATE_S 0 + +#define SENS_SAR_MEAS2_CTRL2_REG (DR_REG_SENS_BASE + 0x0030) + +/* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define SENS_SAR2_EN_PAD_FORCE (BIT(31)) +#define SENS_SAR2_EN_PAD_FORCE_M (BIT(31)) +#define SENS_SAR2_EN_PAD_FORCE_V 0x1 +#define SENS_SAR2_EN_PAD_FORCE_S 31 + +/* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ + +#define SENS_SAR2_EN_PAD 0x00000FFF +#define SENS_SAR2_EN_PAD_M ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S)) +#define SENS_SAR2_EN_PAD_V 0xFFF +#define SENS_SAR2_EN_PAD_S 19 + +/* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ + +#define SENS_MEAS2_START_FORCE (BIT(18)) +#define SENS_MEAS2_START_FORCE_M (BIT(18)) +#define SENS_MEAS2_START_FORCE_V 0x1 +#define SENS_MEAS2_START_FORCE_S 18 + +/* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +#define SENS_MEAS2_START_SAR (BIT(17)) +#define SENS_MEAS2_START_SAR_M (BIT(17)) +#define SENS_MEAS2_START_SAR_V 0x1 +#define SENS_MEAS2_START_SAR_S 17 + +/* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ + +#define SENS_MEAS2_DONE_SAR (BIT(16)) +#define SENS_MEAS2_DONE_SAR_M (BIT(16)) +#define SENS_MEAS2_DONE_SAR_V 0x1 +#define SENS_MEAS2_DONE_SAR_S 16 + +/* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ + +#define SENS_MEAS2_DATA_SAR 0x0000FFFF +#define SENS_MEAS2_DATA_SAR_M ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S)) +#define SENS_MEAS2_DATA_SAR_V 0xFFFF +#define SENS_MEAS2_DATA_SAR_S 0 + +#define SENS_SAR_MEAS2_MUX_REG (DR_REG_SENS_BASE + 0x0034) + +/* SENS_SAR2_RTC_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define SENS_SAR2_RTC_FORCE (BIT(31)) +#define SENS_SAR2_RTC_FORCE_M (BIT(31)) +#define SENS_SAR2_RTC_FORCE_V 0x1 +#define SENS_SAR2_RTC_FORCE_S 31 + +/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[30:28] ;default: 3'b0 ; */ + +#define SENS_SAR2_PWDET_CCT 0x00000007 +#define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S)) +#define SENS_SAR2_PWDET_CCT_V 0x7 +#define SENS_SAR2_PWDET_CCT_S 28 + +#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x0038) + +/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ + +#define SENS_SAR2_ATTEN 0xFFFFFFFF +#define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S)) +#define SENS_SAR2_ATTEN_V 0xFFFFFFFF +#define SENS_SAR2_ATTEN_S 0 + +#define SENS_SAR_POWER_XPD_SAR_REG (DR_REG_SENS_BASE + 0x003c) + +/* SENS_SARCLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define SENS_SARCLK_EN (BIT(31)) +#define SENS_SARCLK_EN_M (BIT(31)) +#define SENS_SARCLK_EN_V 0x1 +#define SENS_SARCLK_EN_S 31 + +/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ + +#define SENS_FORCE_XPD_SAR 0x00000003 +#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S)) +#define SENS_FORCE_XPD_SAR_V 0x3 +#define SENS_FORCE_XPD_SAR_S 29 +#define SENS_FORCE_XPD_SAR_SW_M (BIT1) +#define SENS_FORCE_XPD_SAR_FSM 0 +#define SENS_FORCE_XPD_SAR_PD 2 +#define SENS_FORCE_XPD_SAR_PU 3 + +#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x0040) + +/* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ + +#define SENS_MEAS_STATUS 0x000000FF +#define SENS_MEAS_STATUS_M ((SENS_MEAS_STATUS_V)<<(SENS_MEAS_STATUS_S)) +#define SENS_MEAS_STATUS_V 0xFF +#define SENS_MEAS_STATUS_S 22 + +/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ + +#define SENS_I2C_SLAVE_ADDR0 0x000007FF +#define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S)) +#define SENS_I2C_SLAVE_ADDR0_V 0x7FF +#define SENS_I2C_SLAVE_ADDR0_S 11 + +/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ + +#define SENS_I2C_SLAVE_ADDR1 0x000007FF +#define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S)) +#define SENS_I2C_SLAVE_ADDR1_V 0x7FF +#define SENS_I2C_SLAVE_ADDR1_S 0 + +#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x0044) + +/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ + +#define SENS_I2C_SLAVE_ADDR2 0x000007FF +#define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S)) +#define SENS_I2C_SLAVE_ADDR2_V 0x7FF +#define SENS_I2C_SLAVE_ADDR2_S 11 + +/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ + +#define SENS_I2C_SLAVE_ADDR3 0x000007FF +#define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S)) +#define SENS_I2C_SLAVE_ADDR3_V 0x7FF +#define SENS_I2C_SLAVE_ADDR3_S 0 + +#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x0048) + +/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ + +#define SENS_I2C_SLAVE_ADDR4 0x000007FF +#define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S)) +#define SENS_I2C_SLAVE_ADDR4_V 0x7FF +#define SENS_I2C_SLAVE_ADDR4_S 11 + +/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ + +#define SENS_I2C_SLAVE_ADDR5 0x000007FF +#define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S)) +#define SENS_I2C_SLAVE_ADDR5_V 0x7FF +#define SENS_I2C_SLAVE_ADDR5_S 0 + +#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x004c) + +/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ + +#define SENS_I2C_SLAVE_ADDR6 0x000007FF +#define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S)) +#define SENS_I2C_SLAVE_ADDR6_V 0x7FF +#define SENS_I2C_SLAVE_ADDR6_S 11 + +/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ + +#define SENS_I2C_SLAVE_ADDR7 0x000007FF +#define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S)) +#define SENS_I2C_SLAVE_ADDR7_V 0x7FF +#define SENS_I2C_SLAVE_ADDR7_S 0 + +#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x0050) + +/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +#define SENS_TSENS_DUMP_OUT (BIT(24)) +#define SENS_TSENS_DUMP_OUT_M (BIT(24)) +#define SENS_TSENS_DUMP_OUT_V 0x1 +#define SENS_TSENS_DUMP_OUT_S 24 + +/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[23] ;default: 1'b0 ; */ + +#define SENS_TSENS_POWER_UP_FORCE (BIT(23)) +#define SENS_TSENS_POWER_UP_FORCE_M (BIT(23)) +#define SENS_TSENS_POWER_UP_FORCE_V 0x1 +#define SENS_TSENS_POWER_UP_FORCE_S 23 + +/* SENS_TSENS_POWER_UP : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +#define SENS_TSENS_POWER_UP (BIT(22)) +#define SENS_TSENS_POWER_UP_M (BIT(22)) +#define SENS_TSENS_POWER_UP_V 0x1 +#define SENS_TSENS_POWER_UP_S 22 + +/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ + +#define SENS_TSENS_CLK_DIV 0x000000FF +#define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S)) +#define SENS_TSENS_CLK_DIV_V 0xFF +#define SENS_TSENS_CLK_DIV_S 14 + +/* SENS_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define SENS_TSENS_IN_INV (BIT(13)) +#define SENS_TSENS_IN_INV_M (BIT(13)) +#define SENS_TSENS_IN_INV_V 0x1 +#define SENS_TSENS_IN_INV_S 13 + +/* SENS_TSENS_INT_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ + +#define SENS_TSENS_INT_EN (BIT(12)) +#define SENS_TSENS_INT_EN_M (BIT(12)) +#define SENS_TSENS_INT_EN_V 0x1 +#define SENS_TSENS_INT_EN_S 12 + +/* SENS_TSENS_READY : RO ;bitpos:[8] ;default: 1'h0 ; */ + +#define SENS_TSENS_READY (BIT(8)) +#define SENS_TSENS_READY_M (BIT(8)) +#define SENS_TSENS_READY_V 0x1 +#define SENS_TSENS_READY_S 8 + +/* SENS_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ + +#define SENS_TSENS_OUT 0x000000FF +#define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S)) +#define SENS_TSENS_OUT_V 0xFF +#define SENS_TSENS_OUT_S 0 + +#define SENS_SAR_TSENS_CTRL2_REG (DR_REG_SENS_BASE + 0x0054) + +/* SENS_TSENS_RESET : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +#define SENS_TSENS_RESET (BIT(16)) +#define SENS_TSENS_RESET_M (BIT(16)) +#define SENS_TSENS_RESET_V 0x1 +#define SENS_TSENS_RESET_S 16 + +/* SENS_TSENS_CLKGATE_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +#define SENS_TSENS_CLKGATE_EN (BIT(15)) +#define SENS_TSENS_CLKGATE_EN_M (BIT(15)) +#define SENS_TSENS_CLKGATE_EN_V 0x1 +#define SENS_TSENS_CLKGATE_EN_S 15 + +/* SENS_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ + +#define SENS_TSENS_CLK_INV (BIT(14)) +#define SENS_TSENS_CLK_INV_M (BIT(14)) +#define SENS_TSENS_CLK_INV_V 0x1 +#define SENS_TSENS_CLK_INV_S 14 + +/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ + +#define SENS_TSENS_XPD_FORCE 0x00000003 +#define SENS_TSENS_XPD_FORCE_M ((SENS_TSENS_XPD_FORCE_V)<<(SENS_TSENS_XPD_FORCE_S)) +#define SENS_TSENS_XPD_FORCE_V 0x3 +#define SENS_TSENS_XPD_FORCE_S 12 + +/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ + +#define SENS_TSENS_XPD_WAIT 0x00000FFF +#define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S)) +#define SENS_TSENS_XPD_WAIT_V 0xFFF +#define SENS_TSENS_XPD_WAIT_S 0 + +#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x0058) + +/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +#define SENS_SAR_I2C_START_FORCE (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_M (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_V 0x1 +#define SENS_SAR_I2C_START_FORCE_S 29 + +/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +#define SENS_SAR_I2C_START (BIT(28)) +#define SENS_SAR_I2C_START_M (BIT(28)) +#define SENS_SAR_I2C_START_V 0x1 +#define SENS_SAR_I2C_START_S 28 + +/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ + +#define SENS_SAR_I2C_CTRL 0x0FFFFFFF +#define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S)) +#define SENS_SAR_I2C_CTRL_V 0xFFFFFFF +#define SENS_SAR_I2C_CTRL_S 0 + +#define SENS_SAR_TOUCH_CONF_REG (DR_REG_SENS_BASE + 0x005c) + +/* SENS_TOUCH_APPROACH_PAD0 : R/W ;bitpos:[31:28] ;default: 4'hF ; */ + +#define SENS_TOUCH_APPROACH_PAD0 0x0000000F +#define SENS_TOUCH_APPROACH_PAD0_M ((SENS_TOUCH_APPROACH_PAD0_V)<<(SENS_TOUCH_APPROACH_PAD0_S)) +#define SENS_TOUCH_APPROACH_PAD0_V 0xF +#define SENS_TOUCH_APPROACH_PAD0_S 28 + +/* SENS_TOUCH_APPROACH_PAD1 : R/W ;bitpos:[27:24] ;default: 4'hF ; */ + +#define SENS_TOUCH_APPROACH_PAD1 0x0000000F +#define SENS_TOUCH_APPROACH_PAD1_M ((SENS_TOUCH_APPROACH_PAD1_V)<<(SENS_TOUCH_APPROACH_PAD1_S)) +#define SENS_TOUCH_APPROACH_PAD1_V 0xF +#define SENS_TOUCH_APPROACH_PAD1_S 24 + +/* SENS_TOUCH_APPROACH_PAD2 : R/W ;bitpos:[23:20] ;default: 4'hF ; */ + +#define SENS_TOUCH_APPROACH_PAD2 0x0000000F +#define SENS_TOUCH_APPROACH_PAD2_M ((SENS_TOUCH_APPROACH_PAD2_V)<<(SENS_TOUCH_APPROACH_PAD2_S)) +#define SENS_TOUCH_APPROACH_PAD2_V 0xF +#define SENS_TOUCH_APPROACH_PAD2_S 20 + +/* SENS_TOUCH_UNIT_END : RO ;bitpos:[19] ;default: 1'd0 ; */ + +#define SENS_TOUCH_UNIT_END (BIT(19)) +#define SENS_TOUCH_UNIT_END_M (BIT(19)) +#define SENS_TOUCH_UNIT_END_V 0x1 +#define SENS_TOUCH_UNIT_END_S 19 + +/* SENS_TOUCH_DENOISE_END : RO ;bitpos:[18] ;default: 1'd0 ; */ + +#define SENS_TOUCH_DENOISE_END (BIT(18)) +#define SENS_TOUCH_DENOISE_END_M (BIT(18)) +#define SENS_TOUCH_DENOISE_END_V 0x1 +#define SENS_TOUCH_DENOISE_END_S 18 + +/* SENS_TOUCH_DATA_SEL : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ + +#define SENS_TOUCH_DATA_SEL 0x00000003 +#define SENS_TOUCH_DATA_SEL_M ((SENS_TOUCH_DATA_SEL_V)<<(SENS_TOUCH_DATA_SEL_S)) +#define SENS_TOUCH_DATA_SEL_V 0x3 +#define SENS_TOUCH_DATA_SEL_S 16 + +/* SENS_TOUCH_STATUS_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ + +#define SENS_TOUCH_STATUS_CLR (BIT(15)) +#define SENS_TOUCH_STATUS_CLR_M (BIT(15)) +#define SENS_TOUCH_STATUS_CLR_V 0x1 +#define SENS_TOUCH_STATUS_CLR_S 15 + +/* SENS_TOUCH_OUTEN : R/W ;bitpos:[14:0] ;default: 15'h7FFF ; */ + +#define SENS_TOUCH_OUTEN 0x00007FFF +#define SENS_TOUCH_OUTEN_M ((SENS_TOUCH_OUTEN_V)<<(SENS_TOUCH_OUTEN_S)) +#define SENS_TOUCH_OUTEN_V 0x7FFF +#define SENS_TOUCH_OUTEN_S 0 + +#define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x0060) + +/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH1 0x003FFFFF +#define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S)) +#define SENS_TOUCH_OUT_TH1_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH1_S 0 + +#define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x0064) + +/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH2 0x003FFFFF +#define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S)) +#define SENS_TOUCH_OUT_TH2_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH2_S 0 + +#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x0068) + +/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH3 0x003FFFFF +#define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S)) +#define SENS_TOUCH_OUT_TH3_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH3_S 0 + +#define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x006c) + +/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH4 0x003FFFFF +#define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S)) +#define SENS_TOUCH_OUT_TH4_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH4_S 0 + +#define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x0070) + +/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH5 0x003FFFFF +#define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S)) +#define SENS_TOUCH_OUT_TH5_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH5_S 0 + +#define SENS_SAR_TOUCH_THRES6_REG (DR_REG_SENS_BASE + 0x0074) + +/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH6 0x003FFFFF +#define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S)) +#define SENS_TOUCH_OUT_TH6_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH6_S 0 + +#define SENS_SAR_TOUCH_THRES7_REG (DR_REG_SENS_BASE + 0x0078) + +/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH7 0x003FFFFF +#define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S)) +#define SENS_TOUCH_OUT_TH7_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH7_S 0 + +#define SENS_SAR_TOUCH_THRES8_REG (DR_REG_SENS_BASE + 0x007c) + +/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH8 0x003FFFFF +#define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S)) +#define SENS_TOUCH_OUT_TH8_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH8_S 0 + +#define SENS_SAR_TOUCH_THRES9_REG (DR_REG_SENS_BASE + 0x0080) + +/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH9 0x003FFFFF +#define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S)) +#define SENS_TOUCH_OUT_TH9_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH9_S 0 + +#define SENS_SAR_TOUCH_THRES10_REG (DR_REG_SENS_BASE + 0x0084) + +/* SENS_TOUCH_OUT_TH10 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH10 0x003FFFFF +#define SENS_TOUCH_OUT_TH10_M ((SENS_TOUCH_OUT_TH10_V)<<(SENS_TOUCH_OUT_TH10_S)) +#define SENS_TOUCH_OUT_TH10_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH10_S 0 + +#define SENS_SAR_TOUCH_THRES11_REG (DR_REG_SENS_BASE + 0x0088) + +/* SENS_TOUCH_OUT_TH11 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH11 0x003FFFFF +#define SENS_TOUCH_OUT_TH11_M ((SENS_TOUCH_OUT_TH11_V)<<(SENS_TOUCH_OUT_TH11_S)) +#define SENS_TOUCH_OUT_TH11_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH11_S 0 + +#define SENS_SAR_TOUCH_THRES12_REG (DR_REG_SENS_BASE + 0x008c) + +/* SENS_TOUCH_OUT_TH12 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH12 0x003FFFFF +#define SENS_TOUCH_OUT_TH12_M ((SENS_TOUCH_OUT_TH12_V)<<(SENS_TOUCH_OUT_TH12_S)) +#define SENS_TOUCH_OUT_TH12_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH12_S 0 + +#define SENS_SAR_TOUCH_THRES13_REG (DR_REG_SENS_BASE + 0x0090) + +/* SENS_TOUCH_OUT_TH13 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH13 0x003FFFFF +#define SENS_TOUCH_OUT_TH13_M ((SENS_TOUCH_OUT_TH13_V)<<(SENS_TOUCH_OUT_TH13_S)) +#define SENS_TOUCH_OUT_TH13_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH13_S 0 + +#define SENS_SAR_TOUCH_THRES14_REG (DR_REG_SENS_BASE + 0x0094) + +/* SENS_TOUCH_OUT_TH14 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_OUT_TH14 0x003FFFFF +#define SENS_TOUCH_OUT_TH14_M ((SENS_TOUCH_OUT_TH14_V)<<(SENS_TOUCH_OUT_TH14_S)) +#define SENS_TOUCH_OUT_TH14_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH14_S 0 + +#define SENS_SAR_TOUCH_CHN_ST_REG (DR_REG_SENS_BASE + 0x00d4) + +/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ + +#define SENS_TOUCH_MEAS_DONE (BIT(31)) +#define SENS_TOUCH_MEAS_DONE_M (BIT(31)) +#define SENS_TOUCH_MEAS_DONE_V 0x1 +#define SENS_TOUCH_MEAS_DONE_S 31 + +/* SENS_TOUCH_CHANNEL_CLR : WO ;bitpos:[29:15] ;default: 15'd0 ; */ + +#define SENS_TOUCH_CHANNEL_CLR 0x00007FFF +#define SENS_TOUCH_CHANNEL_CLR_M ((SENS_TOUCH_CHANNEL_CLR_V)<<(SENS_TOUCH_CHANNEL_CLR_S)) +#define SENS_TOUCH_CHANNEL_CLR_V 0x7FFF +#define SENS_TOUCH_CHANNEL_CLR_S 15 + +/* SENS_TOUCH_PAD_ACTIVE : RO ;bitpos:[14:0] ;default: 15'd0 ; */ + +#define SENS_TOUCH_PAD_ACTIVE 0x00007FFF +#define SENS_TOUCH_PAD_ACTIVE_M ((SENS_TOUCH_PAD_ACTIVE_V)<<(SENS_TOUCH_PAD_ACTIVE_S)) +#define SENS_TOUCH_PAD_ACTIVE_V 0x7FFF +#define SENS_TOUCH_PAD_ACTIVE_S 0 + +#define SENS_SAR_TOUCH_STATUS0_REG (DR_REG_SENS_BASE + 0x00d8) + +/* SENS_TOUCH_SCAN_CURR : RO ;bitpos:[25:22] ;default: 4'd0 ; */ + +#define SENS_TOUCH_SCAN_CURR 0x0000000F +#define SENS_TOUCH_SCAN_CURR_M ((SENS_TOUCH_SCAN_CURR_V)<<(SENS_TOUCH_SCAN_CURR_S)) +#define SENS_TOUCH_SCAN_CURR_V 0xF +#define SENS_TOUCH_SCAN_CURR_S 22 + +/* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_DENOISE_DATA 0x003FFFFF +#define SENS_TOUCH_DENOISE_DATA_M ((SENS_TOUCH_DENOISE_DATA_V)<<(SENS_TOUCH_DENOISE_DATA_S)) +#define SENS_TOUCH_DENOISE_DATA_V 0x3FFFFF +#define SENS_TOUCH_DENOISE_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS1_REG (DR_REG_SENS_BASE + 0x00dc) + +/* SENS_TOUCH_PAD1_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD1_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD1_DEBOUNCE_M ((SENS_TOUCH_PAD1_DEBOUNCE_V)<<(SENS_TOUCH_PAD1_DEBOUNCE_S)) +#define SENS_TOUCH_PAD1_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD1_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD1_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD1_DATA 0x003FFFFF +#define SENS_TOUCH_PAD1_DATA_M ((SENS_TOUCH_PAD1_DATA_V)<<(SENS_TOUCH_PAD1_DATA_S)) +#define SENS_TOUCH_PAD1_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD1_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS2_REG (DR_REG_SENS_BASE + 0x00e0) + +/* SENS_TOUCH_PAD2_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD2_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD2_DEBOUNCE_M ((SENS_TOUCH_PAD2_DEBOUNCE_V)<<(SENS_TOUCH_PAD2_DEBOUNCE_S)) +#define SENS_TOUCH_PAD2_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD2_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD2_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD2_DATA 0x003FFFFF +#define SENS_TOUCH_PAD2_DATA_M ((SENS_TOUCH_PAD2_DATA_V)<<(SENS_TOUCH_PAD2_DATA_S)) +#define SENS_TOUCH_PAD2_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD2_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS3_REG (DR_REG_SENS_BASE + 0x00e4) + +/* SENS_TOUCH_PAD3_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD3_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD3_DEBOUNCE_M ((SENS_TOUCH_PAD3_DEBOUNCE_V)<<(SENS_TOUCH_PAD3_DEBOUNCE_S)) +#define SENS_TOUCH_PAD3_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD3_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD3_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD3_DATA 0x003FFFFF +#define SENS_TOUCH_PAD3_DATA_M ((SENS_TOUCH_PAD3_DATA_V)<<(SENS_TOUCH_PAD3_DATA_S)) +#define SENS_TOUCH_PAD3_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD3_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS4_REG (DR_REG_SENS_BASE + 0x00e8) + +/* SENS_TOUCH_PAD4_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD4_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD4_DEBOUNCE_M ((SENS_TOUCH_PAD4_DEBOUNCE_V)<<(SENS_TOUCH_PAD4_DEBOUNCE_S)) +#define SENS_TOUCH_PAD4_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD4_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD4_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD4_DATA 0x003FFFFF +#define SENS_TOUCH_PAD4_DATA_M ((SENS_TOUCH_PAD4_DATA_V)<<(SENS_TOUCH_PAD4_DATA_S)) +#define SENS_TOUCH_PAD4_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD4_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS5_REG (DR_REG_SENS_BASE + 0x00ec) + +/* SENS_TOUCH_PAD5_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD5_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD5_DEBOUNCE_M ((SENS_TOUCH_PAD5_DEBOUNCE_V)<<(SENS_TOUCH_PAD5_DEBOUNCE_S)) +#define SENS_TOUCH_PAD5_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD5_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD5_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD5_DATA 0x003FFFFF +#define SENS_TOUCH_PAD5_DATA_M ((SENS_TOUCH_PAD5_DATA_V)<<(SENS_TOUCH_PAD5_DATA_S)) +#define SENS_TOUCH_PAD5_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD5_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS6_REG (DR_REG_SENS_BASE + 0x00f0) + +/* SENS_TOUCH_PAD6_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD6_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD6_DEBOUNCE_M ((SENS_TOUCH_PAD6_DEBOUNCE_V)<<(SENS_TOUCH_PAD6_DEBOUNCE_S)) +#define SENS_TOUCH_PAD6_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD6_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD6_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD6_DATA 0x003FFFFF +#define SENS_TOUCH_PAD6_DATA_M ((SENS_TOUCH_PAD6_DATA_V)<<(SENS_TOUCH_PAD6_DATA_S)) +#define SENS_TOUCH_PAD6_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD6_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS7_REG (DR_REG_SENS_BASE + 0x00f4) + +/* SENS_TOUCH_PAD7_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD7_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD7_DEBOUNCE_M ((SENS_TOUCH_PAD7_DEBOUNCE_V)<<(SENS_TOUCH_PAD7_DEBOUNCE_S)) +#define SENS_TOUCH_PAD7_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD7_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD7_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD7_DATA 0x003FFFFF +#define SENS_TOUCH_PAD7_DATA_M ((SENS_TOUCH_PAD7_DATA_V)<<(SENS_TOUCH_PAD7_DATA_S)) +#define SENS_TOUCH_PAD7_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD7_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS8_REG (DR_REG_SENS_BASE + 0x00f8) + +/* SENS_TOUCH_PAD8_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD8_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD8_DEBOUNCE_M ((SENS_TOUCH_PAD8_DEBOUNCE_V)<<(SENS_TOUCH_PAD8_DEBOUNCE_S)) +#define SENS_TOUCH_PAD8_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD8_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD8_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD8_DATA 0x003FFFFF +#define SENS_TOUCH_PAD8_DATA_M ((SENS_TOUCH_PAD8_DATA_V)<<(SENS_TOUCH_PAD8_DATA_S)) +#define SENS_TOUCH_PAD8_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD8_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS9_REG (DR_REG_SENS_BASE + 0x00fc) + +/* SENS_TOUCH_PAD9_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD9_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD9_DEBOUNCE_M ((SENS_TOUCH_PAD9_DEBOUNCE_V)<<(SENS_TOUCH_PAD9_DEBOUNCE_S)) +#define SENS_TOUCH_PAD9_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD9_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD9_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD9_DATA 0x003FFFFF +#define SENS_TOUCH_PAD9_DATA_M ((SENS_TOUCH_PAD9_DATA_V)<<(SENS_TOUCH_PAD9_DATA_S)) +#define SENS_TOUCH_PAD9_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD9_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS10_REG (DR_REG_SENS_BASE + 0x0100) + +/* SENS_TOUCH_PAD10_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD10_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD10_DEBOUNCE_M ((SENS_TOUCH_PAD10_DEBOUNCE_V)<<(SENS_TOUCH_PAD10_DEBOUNCE_S)) +#define SENS_TOUCH_PAD10_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD10_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD10_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD10_DATA 0x003FFFFF +#define SENS_TOUCH_PAD10_DATA_M ((SENS_TOUCH_PAD10_DATA_V)<<(SENS_TOUCH_PAD10_DATA_S)) +#define SENS_TOUCH_PAD10_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD10_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS11_REG (DR_REG_SENS_BASE + 0x0104) + +/* SENS_TOUCH_PAD11_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD11_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD11_DEBOUNCE_M ((SENS_TOUCH_PAD11_DEBOUNCE_V)<<(SENS_TOUCH_PAD11_DEBOUNCE_S)) +#define SENS_TOUCH_PAD11_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD11_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD11_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD11_DATA 0x003FFFFF +#define SENS_TOUCH_PAD11_DATA_M ((SENS_TOUCH_PAD11_DATA_V)<<(SENS_TOUCH_PAD11_DATA_S)) +#define SENS_TOUCH_PAD11_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD11_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS12_REG (DR_REG_SENS_BASE + 0x0108) + +/* SENS_TOUCH_PAD12_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD12_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD12_DEBOUNCE_M ((SENS_TOUCH_PAD12_DEBOUNCE_V)<<(SENS_TOUCH_PAD12_DEBOUNCE_S)) +#define SENS_TOUCH_PAD12_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD12_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD12_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD12_DATA 0x003FFFFF +#define SENS_TOUCH_PAD12_DATA_M ((SENS_TOUCH_PAD12_DATA_V)<<(SENS_TOUCH_PAD12_DATA_S)) +#define SENS_TOUCH_PAD12_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD12_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS13_REG (DR_REG_SENS_BASE + 0x010c) + +/* SENS_TOUCH_PAD13_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD13_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD13_DEBOUNCE_M ((SENS_TOUCH_PAD13_DEBOUNCE_V)<<(SENS_TOUCH_PAD13_DEBOUNCE_S)) +#define SENS_TOUCH_PAD13_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD13_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD13_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD13_DATA 0x003FFFFF +#define SENS_TOUCH_PAD13_DATA_M ((SENS_TOUCH_PAD13_DATA_V)<<(SENS_TOUCH_PAD13_DATA_S)) +#define SENS_TOUCH_PAD13_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD13_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS14_REG (DR_REG_SENS_BASE + 0x0110) + +/* SENS_TOUCH_PAD14_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_PAD14_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD14_DEBOUNCE_M ((SENS_TOUCH_PAD14_DEBOUNCE_V)<<(SENS_TOUCH_PAD14_DEBOUNCE_S)) +#define SENS_TOUCH_PAD14_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD14_DEBOUNCE_S 29 + +/* SENS_TOUCH_PAD14_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_PAD14_DATA 0x003FFFFF +#define SENS_TOUCH_PAD14_DATA_M ((SENS_TOUCH_PAD14_DATA_V)<<(SENS_TOUCH_PAD14_DATA_S)) +#define SENS_TOUCH_PAD14_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD14_DATA_S 0 + +#define SENS_SAR_TOUCH_SLP_STATUS_REG (DR_REG_SENS_BASE + 0x0114) + +/* SENS_TOUCH_SLP_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ + +#define SENS_TOUCH_SLP_DEBOUNCE 0x00000007 +#define SENS_TOUCH_SLP_DEBOUNCE_M ((SENS_TOUCH_SLP_DEBOUNCE_V)<<(SENS_TOUCH_SLP_DEBOUNCE_S)) +#define SENS_TOUCH_SLP_DEBOUNCE_V 0x7 +#define SENS_TOUCH_SLP_DEBOUNCE_S 29 + +/* SENS_TOUCH_SLP_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define SENS_TOUCH_SLP_DATA 0x003FFFFF +#define SENS_TOUCH_SLP_DATA_M ((SENS_TOUCH_SLP_DATA_V)<<(SENS_TOUCH_SLP_DATA_S)) +#define SENS_TOUCH_SLP_DATA_V 0x3FFFFF +#define SENS_TOUCH_SLP_DATA_S 0 + +#define SENS_SAR_TOUCH_APPR_STATUS_REG (DR_REG_SENS_BASE + 0x0118) + +/* SENS_TOUCH_SLP_APPROACH_CNT : RO ;bitpos:[31:24] ;default: 8'd0 ; */ + +#define SENS_TOUCH_SLP_APPROACH_CNT 0x000000FF +#define SENS_TOUCH_SLP_APPROACH_CNT_M ((SENS_TOUCH_SLP_APPROACH_CNT_V)<<(SENS_TOUCH_SLP_APPROACH_CNT_S)) +#define SENS_TOUCH_SLP_APPROACH_CNT_V 0xFF +#define SENS_TOUCH_SLP_APPROACH_CNT_S 24 + +/* SENS_TOUCH_APPROACH_PAD0_CNT : RO ;bitpos:[23:16] ;default: 8'd0 ; */ + +#define SENS_TOUCH_APPROACH_PAD0_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD0_CNT_M ((SENS_TOUCH_APPROACH_PAD0_CNT_V)<<(SENS_TOUCH_APPROACH_PAD0_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD0_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD0_CNT_S 16 + +/* SENS_TOUCH_APPROACH_PAD1_CNT : RO ;bitpos:[15:8] ;default: 8'd0 ; */ + +#define SENS_TOUCH_APPROACH_PAD1_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD1_CNT_M ((SENS_TOUCH_APPROACH_PAD1_CNT_V)<<(SENS_TOUCH_APPROACH_PAD1_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD1_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD1_CNT_S 8 + +/* SENS_TOUCH_APPROACH_PAD2_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */ + +#define SENS_TOUCH_APPROACH_PAD2_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD2_CNT_M ((SENS_TOUCH_APPROACH_PAD2_CNT_V)<<(SENS_TOUCH_APPROACH_PAD2_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD2_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD2_CNT_S 0 + +#define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x011c) + +/* SENS_DAC_CLKGATE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +#define SENS_DAC_CLKGATE_EN (BIT(27)) +#define SENS_DAC_CLKGATE_EN_M (BIT(27)) +#define SENS_DAC_CLKGATE_EN_V 0x1 +#define SENS_DAC_CLKGATE_EN_S 27 + +/* SENS_DAC_RESET : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +#define SENS_DAC_RESET (BIT(26)) +#define SENS_DAC_RESET_M (BIT(26)) +#define SENS_DAC_RESET_V 0x1 +#define SENS_DAC_RESET_S 26 + +/* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +#define SENS_DAC_CLK_INV (BIT(25)) +#define SENS_DAC_CLK_INV_M (BIT(25)) +#define SENS_DAC_CLK_INV_V 0x1 +#define SENS_DAC_CLK_INV_S 25 + +/* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +#define SENS_DAC_CLK_FORCE_HIGH (BIT(24)) +#define SENS_DAC_CLK_FORCE_HIGH_M (BIT(24)) +#define SENS_DAC_CLK_FORCE_HIGH_V 0x1 +#define SENS_DAC_CLK_FORCE_HIGH_S 24 + +/* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */ + +#define SENS_DAC_CLK_FORCE_LOW (BIT(23)) +#define SENS_DAC_CLK_FORCE_LOW_M (BIT(23)) +#define SENS_DAC_CLK_FORCE_LOW_V 0x1 +#define SENS_DAC_CLK_FORCE_LOW_S 23 + +/* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +#define SENS_DAC_DIG_FORCE (BIT(22)) +#define SENS_DAC_DIG_FORCE_M (BIT(22)) +#define SENS_DAC_DIG_FORCE_V 0x1 +#define SENS_DAC_DIG_FORCE_S 22 + +/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ + +#define SENS_DEBUG_BIT_SEL 0x0000001F +#define SENS_DEBUG_BIT_SEL_M ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S)) +#define SENS_DEBUG_BIT_SEL_V 0x1F +#define SENS_DEBUG_BIT_SEL_S 17 + +/* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +#define SENS_SW_TONE_EN (BIT(16)) +#define SENS_SW_TONE_EN_M (BIT(16)) +#define SENS_SW_TONE_EN_V 0x1 +#define SENS_SW_TONE_EN_S 16 + +/* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ + +#define SENS_SW_FSTEP 0x0000FFFF +#define SENS_SW_FSTEP_M ((SENS_SW_FSTEP_V)<<(SENS_SW_FSTEP_S)) +#define SENS_SW_FSTEP_V 0xFFFF +#define SENS_SW_FSTEP_S 0 + +#define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x0120) + +/* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */ + +#define SENS_DAC_CW_EN2 (BIT(25)) +#define SENS_DAC_CW_EN2_M (BIT(25)) +#define SENS_DAC_CW_EN2_V 0x1 +#define SENS_DAC_CW_EN2_S 25 + +/* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */ + +#define SENS_DAC_CW_EN1 (BIT(24)) +#define SENS_DAC_CW_EN1_M (BIT(24)) +#define SENS_DAC_CW_EN1_V 0x1 +#define SENS_DAC_CW_EN1_S 24 + +/* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ + +#define SENS_DAC_INV2 0x00000003 +#define SENS_DAC_INV2_M ((SENS_DAC_INV2_V)<<(SENS_DAC_INV2_S)) +#define SENS_DAC_INV2_V 0x3 +#define SENS_DAC_INV2_S 22 + +/* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */ + +#define SENS_DAC_INV1 0x00000003 +#define SENS_DAC_INV1_M ((SENS_DAC_INV1_V)<<(SENS_DAC_INV1_S)) +#define SENS_DAC_INV1_V 0x3 +#define SENS_DAC_INV1_S 20 + +/* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ + +#define SENS_DAC_SCALE2 0x00000003 +#define SENS_DAC_SCALE2_M ((SENS_DAC_SCALE2_V)<<(SENS_DAC_SCALE2_S)) +#define SENS_DAC_SCALE2_V 0x3 +#define SENS_DAC_SCALE2_S 18 + +/* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ + +#define SENS_DAC_SCALE1 0x00000003 +#define SENS_DAC_SCALE1_M ((SENS_DAC_SCALE1_V)<<(SENS_DAC_SCALE1_S)) +#define SENS_DAC_SCALE1_V 0x3 +#define SENS_DAC_SCALE1_S 16 + +/* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ + +#define SENS_DAC_DC2 0x000000FF +#define SENS_DAC_DC2_M ((SENS_DAC_DC2_V)<<(SENS_DAC_DC2_S)) +#define SENS_DAC_DC2_V 0xFF +#define SENS_DAC_DC2_S 8 + +/* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ + +#define SENS_DAC_DC1 0x000000FF +#define SENS_DAC_DC1_M ((SENS_DAC_DC1_V)<<(SENS_DAC_DC1_S)) +#define SENS_DAC_DC1_V 0xFF +#define SENS_DAC_DC1_S 0 + +#define SENS_SAR_COCPU_STATE_REG (DR_REG_SENS_BASE + 0x0124) + +/* SENS_COCPU_EBREAK : RO ;bitpos:[30] ;default: 1'b0 ; */ + +#define SENS_COCPU_EBREAK (BIT(30)) +#define SENS_COCPU_EBREAK_M (BIT(30)) +#define SENS_COCPU_EBREAK_V 0x1 +#define SENS_COCPU_EBREAK_S 30 + +/* SENS_COCPU_TRAP : RO ;bitpos:[29] ;default: 1'b0 ; */ + +#define SENS_COCPU_TRAP (BIT(29)) +#define SENS_COCPU_TRAP_M (BIT(29)) +#define SENS_COCPU_TRAP_V 0x1 +#define SENS_COCPU_TRAP_S 29 + +/* SENS_COCPU_EOI : RO ;bitpos:[28] ;default: 1'b0 ; */ + +#define SENS_COCPU_EOI (BIT(28)) +#define SENS_COCPU_EOI_M (BIT(28)) +#define SENS_COCPU_EOI_V 0x1 +#define SENS_COCPU_EOI_S 28 + +/* SENS_COCPU_RESET_N : RO ;bitpos:[27] ;default: 1'b0 ; */ + +#define SENS_COCPU_RESET_N (BIT(27)) +#define SENS_COCPU_RESET_N_M (BIT(27)) +#define SENS_COCPU_RESET_N_V 0x1 +#define SENS_COCPU_RESET_N_S 27 + +/* SENS_COCPU_CLK_EN : RO ;bitpos:[26] ;default: 1'b0 ; */ + +#define SENS_COCPU_CLK_EN (BIT(26)) +#define SENS_COCPU_CLK_EN_M (BIT(26)) +#define SENS_COCPU_CLK_EN_V 0x1 +#define SENS_COCPU_CLK_EN_S 26 + +/* SENS_COCPU_DBG_TRIGGER : WO ;bitpos:[25] ;default: 1'b0 ; */ + +#define SENS_COCPU_DBG_TRIGGER (BIT(25)) +#define SENS_COCPU_DBG_TRIGGER_M (BIT(25)) +#define SENS_COCPU_DBG_TRIGGER_V 0x1 +#define SENS_COCPU_DBG_TRIGGER_S 25 + +#define SENS_SAR_COCPU_INT_RAW_REG (DR_REG_SENS_BASE + 0x0128) + +/* SENS_COCPU_SWD_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ + +#define SENS_COCPU_SWD_INT_RAW (BIT(8)) +#define SENS_COCPU_SWD_INT_RAW_M (BIT(8)) +#define SENS_COCPU_SWD_INT_RAW_V 0x1 +#define SENS_COCPU_SWD_INT_RAW_S 8 + +/* SENS_COCPU_SW_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ + +#define SENS_COCPU_SW_INT_RAW (BIT(7)) +#define SENS_COCPU_SW_INT_RAW_M (BIT(7)) +#define SENS_COCPU_SW_INT_RAW_V 0x1 +#define SENS_COCPU_SW_INT_RAW_S 7 + +/* SENS_COCPU_START_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ + +#define SENS_COCPU_START_INT_RAW (BIT(6)) +#define SENS_COCPU_START_INT_RAW_M (BIT(6)) +#define SENS_COCPU_START_INT_RAW_V 0x1 +#define SENS_COCPU_START_INT_RAW_S 6 + +/* SENS_COCPU_TSENS_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ + +#define SENS_COCPU_TSENS_INT_RAW (BIT(5)) +#define SENS_COCPU_TSENS_INT_RAW_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_RAW_V 0x1 +#define SENS_COCPU_TSENS_INT_RAW_S 5 + +/* SENS_COCPU_SENS2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ + +#define SENS_COCPU_SENS2_INT_RAW (BIT(4)) +#define SENS_COCPU_SENS2_INT_RAW_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_RAW_V 0x1 +#define SENS_COCPU_SENS2_INT_RAW_S 4 + +/* SENS_COCPU_SENS1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ + +#define SENS_COCPU_SENS1_INT_RAW (BIT(3)) +#define SENS_COCPU_SENS1_INT_RAW_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_RAW_V 0x1 +#define SENS_COCPU_SENS1_INT_RAW_S 3 + +/* SENS_COCPU_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_S 2 + +/* SENS_COCPU_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_S 1 + +/* SENS_COCPU_TOUCH_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_DONE_INT_RAW (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_RAW_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_RAW_S 0 + +#define SENS_SAR_COCPU_INT_ENA_REG (DR_REG_SENS_BASE + 0x012c) + +/* SENS_COCPU_SWD_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +#define SENS_COCPU_SWD_INT_ENA (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_V 0x1 +#define SENS_COCPU_SWD_INT_ENA_S 8 + +/* SENS_COCPU_SW_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +#define SENS_COCPU_SW_INT_ENA (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_M (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_V 0x1 +#define SENS_COCPU_SW_INT_ENA_S 7 + +/* SENS_COCPU_START_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define SENS_COCPU_START_INT_ENA (BIT(6)) +#define SENS_COCPU_START_INT_ENA_M (BIT(6)) +#define SENS_COCPU_START_INT_ENA_V 0x1 +#define SENS_COCPU_START_INT_ENA_S 6 + +/* SENS_COCPU_TSENS_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define SENS_COCPU_TSENS_INT_ENA (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_V 0x1 +#define SENS_COCPU_TSENS_INT_ENA_S 5 + +/* SENS_COCPU_SENS2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +#define SENS_COCPU_SENS2_INT_ENA (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_V 0x1 +#define SENS_COCPU_SENS2_INT_ENA_S 4 + +/* SENS_COCPU_SENS1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +#define SENS_COCPU_SENS1_INT_ENA (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_V 0x1 +#define SENS_COCPU_SENS1_INT_ENA_S 3 + +/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_S 2 + +/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S 1 + +/* SENS_COCPU_TOUCH_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_DONE_INT_ENA (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ENA_S 0 + +#define SENS_SAR_COCPU_INT_ST_REG (DR_REG_SENS_BASE + 0x0130) + +/* SENS_COCPU_SWD_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ + +#define SENS_COCPU_SWD_INT_ST (BIT(8)) +#define SENS_COCPU_SWD_INT_ST_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ST_V 0x1 +#define SENS_COCPU_SWD_INT_ST_S 8 + +/* SENS_COCPU_SW_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ + +#define SENS_COCPU_SW_INT_ST (BIT(7)) +#define SENS_COCPU_SW_INT_ST_M (BIT(7)) +#define SENS_COCPU_SW_INT_ST_V 0x1 +#define SENS_COCPU_SW_INT_ST_S 7 + +/* SENS_COCPU_START_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ + +#define SENS_COCPU_START_INT_ST (BIT(6)) +#define SENS_COCPU_START_INT_ST_M (BIT(6)) +#define SENS_COCPU_START_INT_ST_V 0x1 +#define SENS_COCPU_START_INT_ST_S 6 + +/* SENS_COCPU_TSENS_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ + +#define SENS_COCPU_TSENS_INT_ST (BIT(5)) +#define SENS_COCPU_TSENS_INT_ST_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ST_V 0x1 +#define SENS_COCPU_TSENS_INT_ST_S 5 + +/* SENS_COCPU_SENS2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ + +#define SENS_COCPU_SENS2_INT_ST (BIT(4)) +#define SENS_COCPU_SENS2_INT_ST_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_ST_V 0x1 +#define SENS_COCPU_SENS2_INT_ST_S 4 + +/* SENS_COCPU_SENS1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ + +#define SENS_COCPU_SENS1_INT_ST (BIT(3)) +#define SENS_COCPU_SENS1_INT_ST_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_ST_V 0x1 +#define SENS_COCPU_SENS1_INT_ST_S 3 + +/* SENS_COCPU_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_S 2 + +/* SENS_COCPU_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_S 1 + +/* SENS_COCPU_TOUCH_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_DONE_INT_ST (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ST_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ST_S 0 + +#define SENS_SAR_COCPU_INT_CLR_REG (DR_REG_SENS_BASE + 0x0134) + +/* SENS_COCPU_SWD_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ + +#define SENS_COCPU_SWD_INT_CLR (BIT(8)) +#define SENS_COCPU_SWD_INT_CLR_M (BIT(8)) +#define SENS_COCPU_SWD_INT_CLR_V 0x1 +#define SENS_COCPU_SWD_INT_CLR_S 8 + +/* SENS_COCPU_SW_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ + +#define SENS_COCPU_SW_INT_CLR (BIT(7)) +#define SENS_COCPU_SW_INT_CLR_M (BIT(7)) +#define SENS_COCPU_SW_INT_CLR_V 0x1 +#define SENS_COCPU_SW_INT_CLR_S 7 + +/* SENS_COCPU_START_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ + +#define SENS_COCPU_START_INT_CLR (BIT(6)) +#define SENS_COCPU_START_INT_CLR_M (BIT(6)) +#define SENS_COCPU_START_INT_CLR_V 0x1 +#define SENS_COCPU_START_INT_CLR_S 6 + +/* SENS_COCPU_TSENS_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ + +#define SENS_COCPU_TSENS_INT_CLR (BIT(5)) +#define SENS_COCPU_TSENS_INT_CLR_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_CLR_V 0x1 +#define SENS_COCPU_TSENS_INT_CLR_S 5 + +/* SENS_COCPU_SENS2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ + +#define SENS_COCPU_SENS2_INT_CLR (BIT(4)) +#define SENS_COCPU_SENS2_INT_CLR_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_CLR_V 0x1 +#define SENS_COCPU_SENS2_INT_CLR_S 4 + +/* SENS_COCPU_SENS1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ + +#define SENS_COCPU_SENS1_INT_CLR (BIT(3)) +#define SENS_COCPU_SENS1_INT_CLR_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_CLR_V 0x1 +#define SENS_COCPU_SENS1_INT_CLR_S 3 + +/* SENS_COCPU_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_S 2 + +/* SENS_COCPU_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S 1 + +/* SENS_COCPU_TOUCH_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ + +#define SENS_COCPU_TOUCH_DONE_INT_CLR (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_CLR_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_CLR_S 0 + +#define SENS_SAR_COCPU_DEBUG_REG (DR_REG_SENS_BASE + 0x0138) + +/* SENS_COCPU_MEM_ADDR : RO ;bitpos:[31:19] ;default: 13'd0 ; */ + +#define SENS_COCPU_MEM_ADDR 0x00001FFF +#define SENS_COCPU_MEM_ADDR_M ((SENS_COCPU_MEM_ADDR_V)<<(SENS_COCPU_MEM_ADDR_S)) +#define SENS_COCPU_MEM_ADDR_V 0x1FFF +#define SENS_COCPU_MEM_ADDR_S 19 + +/* SENS_COCPU_MEM_WEN : RO ;bitpos:[18:15] ;default: 4'd0 ; */ + +#define SENS_COCPU_MEM_WEN 0x0000000F +#define SENS_COCPU_MEM_WEN_M ((SENS_COCPU_MEM_WEN_V)<<(SENS_COCPU_MEM_WEN_S)) +#define SENS_COCPU_MEM_WEN_V 0xF +#define SENS_COCPU_MEM_WEN_S 15 + +/* SENS_COCPU_MEM_RDY : RO ;bitpos:[14] ;default: 1'b0 ; */ + +#define SENS_COCPU_MEM_RDY (BIT(14)) +#define SENS_COCPU_MEM_RDY_M (BIT(14)) +#define SENS_COCPU_MEM_RDY_V 0x1 +#define SENS_COCPU_MEM_RDY_S 14 + +/* SENS_COCPU_MEM_VLD : RO ;bitpos:[13] ;default: 1'b0 ; */ + +#define SENS_COCPU_MEM_VLD (BIT(13)) +#define SENS_COCPU_MEM_VLD_M (BIT(13)) +#define SENS_COCPU_MEM_VLD_V 0x1 +#define SENS_COCPU_MEM_VLD_S 13 + +/* SENS_COCPU_PC : RO ;bitpos:[12:0] ;default: 13'd0 ; */ + +#define SENS_COCPU_PC 0x00001FFF +#define SENS_COCPU_PC_M ((SENS_COCPU_PC_V)<<(SENS_COCPU_PC_S)) +#define SENS_COCPU_PC_V 0x1FFF +#define SENS_COCPU_PC_S 0 + +#define SENS_SAR_HALL_CTRL_REG (DR_REG_SENS_BASE + 0x013c) + +/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[31] ;default: 1'b1 ; */ + +#define SENS_HALL_PHASE_FORCE (BIT(31)) +#define SENS_HALL_PHASE_FORCE_M (BIT(31)) +#define SENS_HALL_PHASE_FORCE_V 0x1 +#define SENS_HALL_PHASE_FORCE_S 31 + +/* SENS_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +#define SENS_HALL_PHASE (BIT(30)) +#define SENS_HALL_PHASE_M (BIT(30)) +#define SENS_HALL_PHASE_V 0x1 +#define SENS_HALL_PHASE_S 30 + +/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[29] ;default: 1'b1 ; */ + +#define SENS_XPD_HALL_FORCE (BIT(29)) +#define SENS_XPD_HALL_FORCE_M (BIT(29)) +#define SENS_XPD_HALL_FORCE_V 0x1 +#define SENS_XPD_HALL_FORCE_S 29 + +/* SENS_XPD_HALL : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +#define SENS_XPD_HALL (BIT(28)) +#define SENS_XPD_HALL_M (BIT(28)) +#define SENS_XPD_HALL_V 0x1 +#define SENS_XPD_HALL_S 28 + +#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x0140) + +/* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define SENS_SAR_NOUSE 0xFFFFFFFF +#define SENS_SAR_NOUSE_M ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S)) +#define SENS_SAR_NOUSE_V 0xFFFFFFFF +#define SENS_SAR_NOUSE_S 0 + +#define SENS_SAR_IO_MUX_CONF_REG (DR_REG_SENS_BASE + 0x0144) + +/* SENS_IOMUX_CLK_GATE_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ + +#define SENS_IOMUX_CLK_GATE_EN (BIT(31)) +#define SENS_IOMUX_CLK_GATE_EN_M (BIT(31)) +#define SENS_IOMUX_CLK_GATE_EN_V 0x1 +#define SENS_IOMUX_CLK_GATE_EN_S 31 + +/* SENS_IOMUX_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +#define SENS_IOMUX_RESET (BIT(30)) +#define SENS_IOMUX_RESET_M (BIT(30)) +#define SENS_IOMUX_RESET_V 0x1 +#define SENS_IOMUX_RESET_S 30 + +#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x0148) + +/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1906140 ; */ + +#define SENS_SAR_DATE 0x0FFFFFFF +#define SENS_SAR_DATE_M ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S)) +#define SENS_SAR_DATE_V 0xFFFFFFF +#define SENS_SAR_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SENS_H */