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https://github.com/apache/nuttx.git
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arch/arm/stm32h5: implement flash driver for progmem
H5 implementation of functions defined in include/nuttx/progmem.h. The driver supports a subset of the flash peripheral functions. - Assumes non-secure memory accesses. Does not check for memory protection mechanisms. References implementation in arch/arm/src/stm32h7/stm32h743xx_flash.c
This commit is contained in:
stbenn
Alan C. Assis
parent
97155ae09d
commit
3abdec8af1
7 changed files with 894 additions and 71 deletions
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@ -14,6 +14,7 @@ choice
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config ARCH_CHIP_STM32H563ZI
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bool "STM32H563ZI"
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select ARCH_CORTEXM33
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select STM32H5_STM32H5XXXX
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select STM32H5_STM32H56XXX
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select STM32H5_STM32H563XX
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@ -135,7 +136,7 @@ config STM32H5_FLASH_CONFIG_E
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config STM32H5_FLASH_CONFIG_G
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bool
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default n
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depends on STM32H5_STM32H6XXX
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depends on STM32H5_STM32H56XXX
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config STM32H5_FLASH_CONFIG_I
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bool
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@ -200,6 +201,13 @@ config STM32H5_SRAM2_INIT
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case, the board should handle the initialization itself at the appropriate
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time.
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config STM32H5_PROGMEM
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bool "Flash progmem support"
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default n
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---help---
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Add progmem support, start block and end block options are provided to
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obtain a uniform flash memory mapping.
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comment "STM32H5 Peripherals"
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menu "STM32H5 Peripheral Selection"
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@ -25,16 +25,20 @@
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HEAD_ASRC =
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# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
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# Common ARM and Cortex-M33 files
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include armv8-m/Make.defs
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ifeq ($(CONFIG_STM32H5_PROGMEM),y)
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CHIP_CSRCS += stm32_flash.c
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endif
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# Required STM32H5 files
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CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c
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CHIP_CSRCS += stm32_serial.c stm32_start.c stm32_pwr.c stm32_timerisr.c
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CHIP_CSRCS += stm32_lse.c stm32_lsi.c
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CHIP_CSRCS += stm32_uid.c stm32_ethernet.c
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CHIP_CSRCS += stm32_uid.c
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ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
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CHIP_CSRCS += stm32_idle.c
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@ -80,6 +84,10 @@ ifeq ($(CONFIG_STM32H5_USBFS),y)
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CHIP_CSRCS += stm32_usbfs.c
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endif
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ifeq ($(CONFIG_STM32H5_ETHMAC),y)
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CHIP_CSRCS += stm32_ethernet.c
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endif
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# Required chip type specific files
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ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)
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@ -33,71 +33,6 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* Flash size is known from the chip selection:
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*
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* When CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT is set the
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* CONFIG_STM32H5_FLASH_CONFIG_x selects the default FLASH size based on
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* the chip part number. This value can be overridden with
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* CONFIG_STM32H5_FLASH_OVERRIDE_x
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*
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* Parts STM32H552xC and STM32H562xC have 256Kb of FLASH
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* Parts STM32H552xE and STM32H562xE have 512Kb of FLASH
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*
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* N.B. Only Single bank mode is supported
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*/
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#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_B) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_G) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_I) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_B) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_C) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_E) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_G) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_I)
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# define CONFIG_STM32H5_FLASH_OVERRIDE_E
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# warning "Flash size not defined defaulting to 512KiB (E)"
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#endif
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/* Override of the Flash has been chosen */
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#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT)
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# undef CONFIG_STM32H5_FLASH_CONFIG_C
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# undef CONFIG_STM32H5_FLASH_CONFIG_E
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# if defined(CONFIG_STM32H5_FLASH_OVERRIDE_C)
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# define CONFIG_STM32H5_FLASH_CONFIG_C
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# elif defined(CONFIG_STM32H5_FLASH_OVERRIDE_E)
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# define CONFIG_STM32H5_FLASH_CONFIG_E
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# endif
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#endif
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/* Define the valid configuration */
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#if defined(CONFIG_STM32H5_FLASH_CONFIG_B) /* 128 kB */
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# define STM32_FLASH_NPAGES 32
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# define STM32_FLASH_PAGESIZE 4096
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#elif defined(CONFIG_STM32H5_FLASH_CONFIG_C) /* 256 kB */
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# define STM32_FLASH_NPAGES 64
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# define STM32_FLASH_PAGESIZE 4096
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#elif defined(CONFIG_STM32H5_FLASH_CONFIG_E) /* 512 kB */
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# define STM32_FLASH_NPAGES 128
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# define STM32_FLASH_PAGESIZE 4096
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#elif defined(CONFIG_STM32H5_FLASH_CONFIG_G) /* 1 MB */
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# define STM32_FLASH_NPAGES 256
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# define STM32_FLASH_PAGESIZE 4096
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#elif defined(CONFIG_STM32H5_FLASH_CONFIG_I) /* 2 MB */
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# define STM32_FLASH_NPAGES 512
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# define STM32_FLASH_PAGESIZE 4096
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#else
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# error "unknown flash configuration!"
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#endif
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#ifdef STM32_FLASH_PAGESIZE
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# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
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#endif
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/* Register Offsets *********************************************************/
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#define STM32_FLASH_ACR_OFFSET 0x0000
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@ -316,7 +251,7 @@
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#define FLASH_NSCR_FW (1 << 4)
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#define FLASH_NSCR_STRT (1 << 5)
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#define FLASH_NSCR_SNB_SHIFT (1 << 6)
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#define FLASH_NSCR_SNB_SHIFT (6)
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#define FLASH_NSCR_SNB_MASK (0x7f << FLASH_NSCR_SNB_SHIFT)
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# define FLASH_NSCR_SNB(n) ((n) << FLASH_NSCR_SNB_SHIFT)
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@ -340,7 +275,7 @@
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#define FLASH_SECCR_FW (1 << 4)
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#define FLASH_SECCR_STRT (1 << 5)
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#define FLASH_SECCR_SNB_SHIFT (1 << 6)
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#define FLASH_SECCR_SNB_SHIFT (6)
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#define FLASH_SECCR_SNB_MASK (0x7f << FLASH_SECCR_SNB_SHIFT)
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# define FLASH_SECCR_SNB(n) ((n) << FLASH_SECCR_SNB_SHIFT)
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@ -46,7 +46,9 @@
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/* Code Base Addresses ******************************************************/
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#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
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#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */
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#define STM32_FLASH_BANK1 0x08000000 /* 0x08000000-0x080fffff: Bank 1 (562/563/573xx devices) */
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#define STM32_FLASH_BANK2 0x08100000 /* 0x08100000-0x081fffff: Bank 2 (562/563/573xx devices) */
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#define STM32_FLASH_BASE STM32_FLASH_BANK1
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#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */
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#define STM32_SRAM2_BASE 0x20040000 /* 0x20040000-0x2004ffff: 64k SRAM2 */
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#define STM32_SRAM3_BASE 0x20050000 /* 0x20050000-0x2008ffff: 320k SRAM3 */
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@ -54,6 +56,7 @@
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/* System Memory Addresses **************************************************/
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#define STM32_SYSMEM_MEM 0x0bf80000
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#define STM32_SYSMEM_UID 0x08FFF800 /* The 96-bit unique device identifier */
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#define STM32_SYSMEM_FSIZE 0x08FFF80C /* Size of Flash memory in Kbytes. */
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#define STM32_SYSMEM_PACKAGE 0x08FFF80E /* Indicates the device's package type. */
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37
arch/arm/src/stm32h5/stm32_flash.c
Normal file
37
arch/arm/src/stm32h5/stm32_flash.c
Normal file
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@ -0,0 +1,37 @@
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/****************************************************************************
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* arch/arm/src/stm32h5/stm32_flash.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#if defined(CONFIG_STM32H5_STM32H563XX)
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# include "stm32h563xx_flash.c"
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#else
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# error "Unsupported STM32 H5 chip"
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -34,4 +34,33 @@
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2);
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int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1,
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uint32_t clear2, uint32_t set2);
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int stm32h5_flash_swapbanks(void);
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void stm32h5_flash_lock(void);
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void stm32h5_flash_unlock(void);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_STM32H5_STM32_FLASH_H */
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803
arch/arm/src/stm32h5/stm32h563xx_flash.c
Normal file
803
arch/arm/src/stm32h5/stm32h563xx_flash.c
Normal file
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@ -0,0 +1,803 @@
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/****************************************************************************
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* arch/arm/src/stm32h5/stm32h563xx_flash.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Provides standard flash access functions, to be used by the flash mtd
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* driver. The interface is defined in the include/nuttx/progmem.h
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*
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* Requirements during write/erase operations on FLASH:
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* - HSI must be ON.
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* - Low Power Modes are not permitted during write/erase
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*
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* Notes:
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* - RM0481 refers to erase blocks as "Sectors". This file uses block.
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* - This file assumes dual bank flash memory.
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*
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <nuttx/mutex.h>
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#include <arch/barriers.h>
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#include <stdbool.h>
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#include <assert.h>
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#include <errno.h>
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#include "hardware/stm32_flash.h"
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#include "hardware/stm32_memorymap.h"
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#include "arm_internal.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define _K(x) ((x)*1024)
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#define FLASH_BLOCK_SIZE _K(8)
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#define FLASH_PAGE_SIZE 16
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#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_B) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_G) && \
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!defined(CONFIG_STM32H5_FLASH_OVERRIDE_I) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_B) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_C) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_E) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_G) && \
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!defined(CONFIG_STM32H5_FLASH_CONFIG_I)
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# define CONFIG_STM32H5_FLASH_OVERRIDE_E
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# warning "Flash size not defined defaulting to 512KiB (E)"
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#endif
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/* Override of the Flash has been chosen */
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#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT)
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# undef CONFIG_STM32H5_FLASH_CONFIG_C
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# undef CONFIG_STM32H5_FLASH_CONFIG_E
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# if defined(CONFIG_STM32H5_FLASH_OVERRIDE_C)
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# define CONFIG_STM32H5_FLASH_CONFIG_C
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# elif defined(CONFIG_STM32H5_FLASH_OVERRIDE_E)
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# define CONFIG_STM32H5_FLASH_CONFIG_E
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# endif
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#endif
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#if defined(CONFIG_STM32H5_FLASH_CONFIG_I)
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# define H5_FLASH_BANK_NBLOCKS 128
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#elif defined(CONFIG_STM32H5_FLASH_CONFIG_G)
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# define H5_FLASH_BANK_NBLOCKS 64
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#elif defined(CONFIG_STM32H5_FLASH_CONFIG_E)
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# define H5_FLASH_BANK_NBLOCKS 32
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#elif defined(CONFIG_STM32H5_FLASH_CONFIG_C)
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# define H5_FLASH_BANK_NBLOCKS 16
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#elif defined(CONFIG_STM32H5_FLASH_CONFIG_B)
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# define H5_FLASH_BANK_NBLOCKS 8
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#else
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# warning "No valid STM32H5_FLASH_CONFIG_x defined."
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#endif
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#define H5_FLASH_BANKSIZE (FLASH_BLOCK_SIZE * H5_FLASH_BANK_NBLOCKS)
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#define H5_FLASH_NBLOCKS (2 * H5_FLASH_BANK_NBLOCKS)
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#define H5_FLASH_TOTALSIZE (2 * H5_FLASH_BANKSIZE)
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#define H5_FLASH_NPAGES (H5_FLASH_TOTALSIZE / FLASH_PAGE_SIZE)
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#define FLASH_KEY1 0x45670123
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#define FLASH_KEY2 0xCDEF89AB
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#define FLASH_OPTKEY1 0x08192A3B
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#define FLASH_OPTKEY2 0x4C5D6E7F
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#define FLASH_OBKKEY1 0x192A083B
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#define FLASH_OBKKEY2 0x5E7F4C5D
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#define FLASH_ERASEDVALUE 0xffu
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#define FLASH_ERASEDVALUE_DW 0xffffffffu
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#define FLASH_TIMEOUT_VALUE 5000000 /* 5s */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct stm32h5_flash_priv_s
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{
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uint32_t base; /* FLASH base address */
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uint32_t stblock; /* The first block number */
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uint32_t stpage; /* The first page number */
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static struct stm32h5_flash_priv_s flash_bank1_priv =
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{
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.base = STM32_FLASH_BANK1,
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.stblock = 0,
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.stpage = 0
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};
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static struct stm32h5_flash_priv_s flash_bank2_priv =
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{
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.base = STM32_FLASH_BANK2,
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.stblock = (H5_FLASH_NBLOCKS / 2),
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.stpage = (H5_FLASH_NPAGES / 2),
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};
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static mutex_t g_lock = NXMUTEX_INITIALIZER;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: flash_bank
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*
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* Description:
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* Returns the priv pointer to the correct bank
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*
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****************************************************************************/
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static inline
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struct stm32h5_flash_priv_s * flash_bank(size_t address)
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{
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struct stm32h5_flash_priv_s *priv = NULL;
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if (address >= flash_bank1_priv.base &&
|
||||
address < flash_bank1_priv.base + H5_FLASH_BANKSIZE)
|
||||
{
|
||||
priv = &flash_bank1_priv;
|
||||
}
|
||||
else if (address >= flash_bank2_priv.base &&
|
||||
address < flash_bank2_priv.base + H5_FLASH_BANKSIZE)
|
||||
{
|
||||
priv = &flash_bank2_priv;
|
||||
}
|
||||
|
||||
return priv;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: flash_unlock_nscr
|
||||
*
|
||||
* Description:
|
||||
* Unlock the non-secure control register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void flash_unlock_nscr(void)
|
||||
{
|
||||
while (getreg32(STM32_FLASH_NSSR) & FLASH_NSSR_BSY)
|
||||
{
|
||||
}
|
||||
|
||||
if (getreg32(STM32_FLASH_NSCR) & FLASH_NSCR_LOCK)
|
||||
{
|
||||
putreg32(FLASH_KEY1, STM32_FLASH_NSKEYR);
|
||||
putreg32(FLASH_KEY2, STM32_FLASH_NSKEYR);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: flash_lock_nscr
|
||||
*
|
||||
* Description:
|
||||
* Lock the non-secure control register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void flash_lock_nscr(void)
|
||||
{
|
||||
modifyreg32(STM32_FLASH_NSCR, 0, FLASH_NSCR_LOCK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_israngeerased
|
||||
*
|
||||
* Description:
|
||||
* Returns count of non-erased words
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32h5_israngeerased(size_t startaddress, size_t size)
|
||||
{
|
||||
uint32_t *addr;
|
||||
uint8_t *baddr;
|
||||
size_t count = 0;
|
||||
size_t bwritten = 0;
|
||||
|
||||
if (!flash_bank(startaddress) || !flash_bank(startaddress + size - 1))
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
addr = (uint32_t *)startaddress;
|
||||
while (count + 4 <= size)
|
||||
{
|
||||
if (getreg32(addr) != FLASH_ERASEDVALUE_DW)
|
||||
{
|
||||
bwritten++;
|
||||
}
|
||||
|
||||
addr++;
|
||||
count += 4;
|
||||
}
|
||||
|
||||
baddr = (uint8_t *)addr;
|
||||
while (count < size)
|
||||
{
|
||||
if (getreg8(baddr) != FLASH_ERASEDVALUE)
|
||||
{
|
||||
bwritten++;
|
||||
}
|
||||
|
||||
baddr++;
|
||||
count++;
|
||||
}
|
||||
|
||||
return bwritten;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: flash_wait_for_operation()
|
||||
*
|
||||
* Description:
|
||||
* Wait for last write/erase operation to finish
|
||||
* Return error in case of timeout
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero or error value
|
||||
*
|
||||
* -EBUSY: Timeout while waiting for previous write/erase operation to
|
||||
* complete
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int flash_wait_for_operation(void)
|
||||
{
|
||||
int i;
|
||||
bool timeout = true;
|
||||
|
||||
UP_DSB();
|
||||
|
||||
for (i = 0; i < FLASH_TIMEOUT_VALUE; i++)
|
||||
{
|
||||
if (!(getreg32(STM32_FLASH_NSSR) &
|
||||
(FLASH_NSSR_BSY | FLASH_NSSR_DBNE | FLASH_NSSR_WBNE)))
|
||||
{
|
||||
timeout = false;
|
||||
break;
|
||||
}
|
||||
|
||||
up_udelay(1);
|
||||
}
|
||||
|
||||
if (timeout)
|
||||
{
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: flash_unlock_opt
|
||||
*
|
||||
* Description:
|
||||
* Unlock the flash option bytes
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static bool flash_unlock_opt(void)
|
||||
{
|
||||
bool was_locked = false;
|
||||
|
||||
while (getreg32(STM32_FLASH_NSSR) & FLASH_NSSR_BSY)
|
||||
{
|
||||
}
|
||||
|
||||
if (getreg32(STM32_FLASH_OPTCR) & FLASH_OPTCR_OPTLOCK)
|
||||
{
|
||||
was_locked = true;
|
||||
|
||||
putreg32(FLASH_OPTKEY1, STM32_FLASH_OPTKEYR);
|
||||
putreg32(FLASH_OPTKEY2, STM32_FLASH_OPTKEYR);
|
||||
}
|
||||
|
||||
return was_locked;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: flash_lock_opt
|
||||
*
|
||||
* Description:
|
||||
* Lock the flash option bytes
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void flash_lock_opt(void)
|
||||
{
|
||||
modifyreg32(STM32_FLASH_OPTCR, 0, FLASH_OPTCR_OPTLOCK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_flash_unlock
|
||||
*
|
||||
* Description:
|
||||
* Unlock non-secure flash control
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h5_flash_unlock(void)
|
||||
{
|
||||
nxmutex_lock(&g_lock);
|
||||
flash_unlock_nscr();
|
||||
nxmutex_unlock(&g_lock);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_flash_lock
|
||||
*
|
||||
* Description:
|
||||
* Lock non-secure flash control
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h5_flash_lock(void)
|
||||
{
|
||||
nxmutex_lock(&g_lock);
|
||||
flash_lock_nscr();
|
||||
nxmutex_unlock(&g_lock);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_flash_getopt
|
||||
*
|
||||
* Description:
|
||||
* Read the current flash option bytes from FLASH_OPTSR_CUR and
|
||||
* FLASH_OPTSR2_CUR registers.
|
||||
*
|
||||
* Input Parameters:
|
||||
* opt1 - result from FLASH_OPTSR_CUR
|
||||
* opt2 - result from FLASH_OPTSR2_CUR
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2)
|
||||
{
|
||||
*opt1 = getreg32(STM32_FLASH_OPTSR_CUR);
|
||||
*opt2 = getreg32(STM32_FLASH_OPTSR2_CUR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_flash_optmodify
|
||||
*
|
||||
* Description:
|
||||
* Modifies the current flash option bytes, given bits to set and clear.
|
||||
*
|
||||
* Input Parameters:
|
||||
* clear1 - clear bits for FLASH_OPTSR
|
||||
* set1 - set bits for FLASH_OPTSR
|
||||
* clear2 - clear bits for FLASH_OPTSR2
|
||||
* set2 - set bits for FLASH_OPTSR2
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero or error value
|
||||
*
|
||||
* -EBUSY: Timeout waiting for previous FLASH operation to occur, or
|
||||
* there was data in the flash data buffer.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1,
|
||||
uint32_t clear2, uint32_t set2)
|
||||
{
|
||||
int ret;
|
||||
uint32_t reg;
|
||||
bool was_locked;
|
||||
|
||||
ret = flash_wait_for_operation();
|
||||
if (ret != 0)
|
||||
{
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
reg = getreg32(STM32_FLASH_NSSR);
|
||||
if (reg & FLASH_NSSR_DBNE)
|
||||
{
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
was_locked = flash_unlock_opt();
|
||||
|
||||
modifyreg32(STM32_FLASH_OPTSR_PRG, clear1, set1);
|
||||
modifyreg32(STM32_FLASH_OPTSR2_PRG, clear2, set2);
|
||||
|
||||
modifyreg32(STM32_FLASH_OPTCR, 0, FLASH_OPTCR_OPTSTRT);
|
||||
|
||||
while (getreg32(STM32_FLASH_NSSR) & FLASH_NSSR_BSY)
|
||||
{
|
||||
}
|
||||
|
||||
if (was_locked)
|
||||
{
|
||||
flash_lock_opt();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_flash_swapbanks
|
||||
*
|
||||
* Description:
|
||||
* Swaps banks 1 and 2 in the processor's memory map. Takes effect
|
||||
* the next time the system is reset.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero or error value
|
||||
*
|
||||
* -ETIMEDOUT: Timeout occurred waiting for previous operation to occur.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32h5_flash_swapbanks(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
bool was_locked;
|
||||
|
||||
if (flash_wait_for_operation())
|
||||
{
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
was_locked = flash_unlock_opt();
|
||||
|
||||
reg = getreg32(STM32_FLASH_OPTSR_PRG);
|
||||
reg ^= FLASH_OPTSR_PRG_SWAP_BANK;
|
||||
putreg32(reg, STM32_FLASH_OPTSR_PRG);
|
||||
|
||||
modifyreg32(STM32_FLASH_OPTCR, 0, FLASH_OPTCR_OPTSTRT);
|
||||
|
||||
while ((getreg32(STM32_FLASH_OPTSR_CUR) >> 31) != (reg >> 31))
|
||||
{
|
||||
}
|
||||
|
||||
if (was_locked)
|
||||
{
|
||||
flash_lock_opt();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_HAVE_PROGMEM
|
||||
|
||||
/* up_progmem_x functions defined in nuttx/include/nuttx/progmem.h
|
||||
*
|
||||
* Notes on Implementation:
|
||||
* - The driver implementations DO NOT enforce memory address boundaries.
|
||||
* For processors with less than 2MB flash, the user is responsible for
|
||||
* not writing to memory between banks.
|
||||
*
|
||||
*/
|
||||
|
||||
size_t up_progmem_pagesize(size_t page)
|
||||
{
|
||||
return FLASH_PAGE_SIZE;
|
||||
}
|
||||
|
||||
ssize_t up_progmem_getpage(size_t addr)
|
||||
{
|
||||
struct stm32h5_flash_priv_s *priv;
|
||||
|
||||
priv = flash_bank(addr);
|
||||
|
||||
if (priv == NULL)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return priv->stpage + ((addr - priv->base) / FLASH_PAGE_SIZE);
|
||||
}
|
||||
|
||||
size_t up_progmem_getaddress(size_t page)
|
||||
{
|
||||
struct stm32h5_flash_priv_s *priv;
|
||||
if (page >= H5_FLASH_NPAGES)
|
||||
{
|
||||
return SIZE_MAX;
|
||||
}
|
||||
|
||||
priv = flash_bank(STM32_FLASH_BASE + (page * FLASH_PAGE_SIZE));
|
||||
return priv->base + (page - priv->stpage) * FLASH_PAGE_SIZE;
|
||||
}
|
||||
|
||||
size_t up_progmem_neraseblocks(void)
|
||||
{
|
||||
return H5_FLASH_NBLOCKS;
|
||||
}
|
||||
|
||||
bool up_progmem_isuniform(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
ssize_t up_progmem_ispageerased(size_t page)
|
||||
{
|
||||
size_t addr;
|
||||
size_t count;
|
||||
size_t bwritten = 0;
|
||||
|
||||
if (page >= H5_FLASH_NPAGES)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* Verify */
|
||||
|
||||
for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page);
|
||||
count; count--, addr++)
|
||||
{
|
||||
if (getreg8(addr) != FLASH_ERASEDVALUE)
|
||||
{
|
||||
bwritten++;
|
||||
}
|
||||
}
|
||||
|
||||
return bwritten;
|
||||
}
|
||||
|
||||
size_t up_progmem_erasesize(size_t block)
|
||||
{
|
||||
return FLASH_BLOCK_SIZE;
|
||||
}
|
||||
|
||||
ssize_t up_progmem_eraseblock(size_t block)
|
||||
{
|
||||
struct stm32h5_flash_priv_s *priv;
|
||||
int ret;
|
||||
size_t block_address = STM32_FLASH_BASE + (block * FLASH_BLOCK_SIZE);
|
||||
|
||||
if (block >= H5_FLASH_NBLOCKS)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
priv = flash_bank(block_address);
|
||||
|
||||
ret = nxmutex_lock(&g_lock);
|
||||
if (ret < 0)
|
||||
{
|
||||
return (ssize_t)ret;
|
||||
}
|
||||
|
||||
if (flash_wait_for_operation())
|
||||
{
|
||||
ret = -EIO;
|
||||
goto exit_with_lock;
|
||||
}
|
||||
|
||||
/* Get flash ready and begin erasing single block */
|
||||
|
||||
flash_unlock_nscr();
|
||||
|
||||
if (priv->base == STM32_FLASH_BANK1)
|
||||
{
|
||||
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_BKSEL, FLASH_NSCR_SER);
|
||||
}
|
||||
else
|
||||
{
|
||||
modifyreg32(STM32_FLASH_NSCR, 0, FLASH_NSCR_BKSEL | FLASH_NSCR_SER);
|
||||
}
|
||||
|
||||
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_SNB_MASK,
|
||||
FLASH_NSCR_SNB(block - priv->stblock));
|
||||
|
||||
modifyreg32(STM32_FLASH_NSCR, 0, FLASH_NSCR_STRT);
|
||||
|
||||
/* Wait for erase operation to complete */
|
||||
|
||||
if (flash_wait_for_operation())
|
||||
{
|
||||
ret = -EIO;
|
||||
goto exit_with_unlock;
|
||||
}
|
||||
|
||||
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_SER, 0);
|
||||
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_SNB_MASK, 0);
|
||||
|
||||
ret = 0;
|
||||
up_invalidate_dcache(block_address, block_address + FLASH_BLOCK_SIZE);
|
||||
|
||||
exit_with_unlock:
|
||||
flash_lock_nscr();
|
||||
|
||||
exit_with_lock:
|
||||
nxmutex_unlock(&g_lock);
|
||||
|
||||
/* Verify */
|
||||
|
||||
if (ret == 0 &&
|
||||
stm32h5_israngeerased(block_address, up_progmem_erasesize(block)) == 0)
|
||||
{
|
||||
ret = up_progmem_erasesize(block); /* Success */
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = -EIO; /* Failure */
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
|
||||
{
|
||||
struct stm32h5_flash_priv_s *priv;
|
||||
uint32_t *fp;
|
||||
uint32_t *rp;
|
||||
uint32_t *ll = (uint32_t *)buf;
|
||||
size_t faddr;
|
||||
size_t written = count;
|
||||
int ret;
|
||||
const size_t pagesize = up_progmem_pagesize(0); /* 128bit, 16 bytes per page */
|
||||
const size_t llperpage = pagesize / sizeof(uint32_t);
|
||||
size_t pcount = count / pagesize;
|
||||
|
||||
priv = flash_bank(addr);
|
||||
|
||||
if (priv == NULL)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* Check for valid address range */
|
||||
|
||||
if (addr < priv->base ||
|
||||
addr + count > priv->base + (H5_FLASH_TOTALSIZE / 2))
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
ret = nxmutex_lock(&g_lock);
|
||||
if (ret < 0)
|
||||
{
|
||||
return (ssize_t)ret;
|
||||
}
|
||||
|
||||
/* Check address and count alignment */
|
||||
|
||||
DEBUGASSERT(!(addr % pagesize));
|
||||
DEBUGASSERT(!(count % pagesize));
|
||||
|
||||
if (flash_wait_for_operation())
|
||||
{
|
||||
written = -EIO;
|
||||
goto exit_with_lock;
|
||||
}
|
||||
|
||||
/* Get flash ready for write */
|
||||
|
||||
flash_unlock_nscr();
|
||||
|
||||
if (priv->base == STM32_FLASH_BANK1)
|
||||
{
|
||||
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_BKSEL, FLASH_NSCR_PG);
|
||||
}
|
||||
else
|
||||
{
|
||||
modifyreg32(STM32_FLASH_NSCR, 0, FLASH_NSCR_BKSEL | FLASH_NSCR_PG);
|
||||
}
|
||||
|
||||
/* Write */
|
||||
|
||||
for (ll = (uint32_t *)buf, faddr = addr; pcount;
|
||||
pcount -= 1, ll += llperpage, faddr += pagesize)
|
||||
{
|
||||
fp = (uint32_t *)faddr;
|
||||
rp = ll;
|
||||
|
||||
UP_MB();
|
||||
|
||||
/* Write 4 32 bit word and wait to complete */
|
||||
|
||||
*fp++ = *rp++;
|
||||
*fp++ = *rp++;
|
||||
*fp++ = *rp++;
|
||||
*fp++ = *rp++;
|
||||
|
||||
/* Data synchronous Barrier (DSB) just after the write operation. This
|
||||
* will force the CPU to respect the sequence of instruction (no
|
||||
* optimization).
|
||||
*/
|
||||
|
||||
UP_MB();
|
||||
|
||||
if (flash_wait_for_operation())
|
||||
{
|
||||
written = -EIO;
|
||||
goto exit_with_unlock;
|
||||
}
|
||||
|
||||
/* H5 corrects single ECC errors, so only check double errors */
|
||||
|
||||
if (getreg32(STM32_FLASH_ECCDETR) & FLASH_ECCDETR_ECCD)
|
||||
{
|
||||
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_PG, 0);
|
||||
modifyreg32(STM32_FLASH_ECCDETR, 0, FLASH_ECCDETR_ECCD);
|
||||
ret = -EIO;
|
||||
goto exit_with_unlock;
|
||||
}
|
||||
}
|
||||
|
||||
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_PG, 0);
|
||||
modifyreg32(STM32_FLASH_NSCCR, 0, ~0);
|
||||
|
||||
exit_with_unlock:
|
||||
flash_lock_nscr();
|
||||
|
||||
if (written > 0)
|
||||
{
|
||||
for (ll = (uint32_t *)buf, faddr = addr, pcount = count / pagesize;
|
||||
pcount; pcount -= 1, ll += llperpage, faddr += pagesize)
|
||||
{
|
||||
fp = (uint32_t *)faddr;
|
||||
rp = ll;
|
||||
|
||||
modifyreg32(STM32_FLASH_NSCCR, 0, ~0);
|
||||
|
||||
if ((*fp++ != *rp++) ||
|
||||
(*fp++ != *rp++) ||
|
||||
(*fp++ != *rp++) ||
|
||||
(*fp++ != *rp++))
|
||||
{
|
||||
written = -EIO;
|
||||
break;
|
||||
}
|
||||
|
||||
if (getreg32(STM32_FLASH_ECCDETR) & FLASH_ECCDETR_ECCD)
|
||||
{
|
||||
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_PG, 0);
|
||||
modifyreg32(STM32_FLASH_ECCDETR, 0, FLASH_ECCDETR_ECCD);
|
||||
written = -EIO;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
modifyreg32(STM32_FLASH_NSCCR, 0, ~0);
|
||||
}
|
||||
|
||||
exit_with_lock:
|
||||
nxmutex_unlock(&g_lock);
|
||||
return written;
|
||||
}
|
||||
|
||||
uint8_t up_progmem_erasestate(void)
|
||||
{
|
||||
return FLASH_ERASEDVALUE;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARCH_HAVE_PROGMEM */
|
||||
Loading…
Add table
Add a link
Reference in a new issue