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84
ChangeLog
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@ -11729,3 +11729,87 @@
STM32F746ZG MCU. From Kconstantin Berezenko (2015-05-12).
* arch/arm-src/armv7-a: Complete re-design of logic to initialize each
CPUn, n > 0, when CONFIG_SMP=y (2016-05-13).
* arch/arm/src/imx6 and configs/sabre-6quad: The basic i.MX6 port is
complete. This is a very minimal port at present and probably still
has some as-of-yet-undiscovered issues (2016-05-17).
* arch/*/Makefile: Add definitions that can be overrided to use GCC
instead of LD in the final link. From Paul Alexander Patience
(2016-05-18) .
* arch/arm/src/stm32, stm32l4, and stm32f7 serial: Add support for
compliant BSD-style breaks. From David Sidrane (2016-05-18).
* enter/leave_critical_section() may attempt to access task lists before
they have been initialized in the SMP configuration (2016-05-18).
* configs/stm32f103-minimum: Add support for this minimual STM32F103CBT6
"blue" board. From Alan Carvalho de Assis (2016-05-18).
* arch/arm/src/sam* Watchdogs: Rename up_wdginitialize() to something
more appropriate for an internal, MCU-specific function (2016-05-18).
* configs/*/src/*_watchdog.c: Remove all implementations of
up_wdginitialize() which was only used by apps/examples/watchdog.
That internal OS function is no longer called from application code.
If you want to use the watchdog example, you will need to configure
the watchdog driver by calling the appropriate, MCU-specific driver
configuration function from your board initialization logic
(2016-05-18).
* arch/srm/src/stm32l4: Add CAN support for STM32L4. From Sebastien
Lorquet (2016-05-19).
* arch/arm/src/samv7: Adds a JTAG config and ERASE config to Kconfig to
set the CCFG_SYSIO SYSIO Pins. From Davide Sidrane (2016-05-19).
* arch/sim/src: Enhance networking support for the simulation under Linux.
Includes updated support for Linux TUN/TAP, and the addition of support
for Linux bridge devices. From Steve (2016-05-20).
* configs/stm32f411e-disco: Add basic configuration for stm32f411e-disco
board with STM32F411VE chip. From Konstantin Berezenko (2016-05-20).
* i.MX6 Sabre-6Quad: Basic SMP NSH configuration is now working. But
this is probably only because the SMP NSH case does not stress the
logic. There are know outstanding SMP issues as noted in the
Sabre-6Quad README.txt file (2016-05-22).
* configs/sabre-6quad: Add an SMP configuration; Enable procfs in all
configurations (2016-05-22).
* include/nuttx/crypto/aes.h: Modifications to the crypto API needed
for LPC43xx. From Alexander Vasiljev (2016-05-23).
* arch/arm/src/lpc32xx: Add AES support. From Alexander Vasiljev
(2016-05-24).
* configs/*/src/tiva_timer.c: Tiva boards: Fix a naming collision,
rename board-specific function from tiva_timer_initialize() to
tiva_timer_configure() to remove conflict (2016-05-23).
* arch/arm/src/sam*: Ensure that the TWIHS (i2c) hw get's its clock
set when the sequence of sam_i2cbus_initialize(),
sam_i2cbus_uninitialize(), then sam_i2cbus_initialize() or twi_reset()
is called. I found this a while back in the stm32 family, so there
may be more arch-es with this sort of bug. I suppose any driver that
has the notion of "do not set the freq if it is already set" could be
suspect. From David Sidrane (2016-05-23).
* arch/arm/src/samv7: Add the up_systemreset interface to the samv7
arch. The approach is slightly different in that: 1) It enables
ARCH_HAVE_RESET and allows the user to set if, and for how long, to
drive External nRST signal. It also does not contain a default
board_reset, as that really should be done in the config's src if
CONFIG_BOARDCTL_RESET is defined. From David Sidrane (2016-05-23).
* arch/arm/include/lpc43xx and src/lpc43xx: Adds definitions for the
LPC4337jet100 chip. From Alexander Vasiljev (2016-05-24).
* Many files: board_app_initialize() now accepts an argument that may
be used to support initialization in different configurations
(2016-05-24).
* arch/arm/src/samv7: Remove disabling of whole USB on suspend of USBHS.
This fix removes the disabling of the whole USB peripheral on suspend
interrupt. Its enough to freeze the clock instead. When disabling the
whole peripheral, the next wakeup-interrupt comes up with an disabled
clocking. The unfreeze clock has no effect, because the master clock
is disabled. This makes all registers, including the IDR unwriteable
and the IRQ falls in an endless loop blocking the whole system.
Furthermore the disabling of the peripheral clock prevents hotplugging
or reconnecting the USB. From Frank Benkert (2015-05-25).
* drivers/lcd: Add support for PCF8574 LCD Backpack driver. This driver
supports an interface board that is based on the PCF8574 io expander
and supports the HD44780-based (or compatible) LCD modules. There
are a myriad of different vendors of such, but they are principally
the same, save wiring and minor features like jumpers for I2C
addresses. This driver supports known and unknown variants. From
Dave (ziggurat29, 2013-6-26).
* arch/arm/stm32: Add support for a custom 1-wire driver. The serial
driver already supports a 1-wire interface, but this driver uses the
same serial logic to implement a lower half driver much like the I2C
lower half driver. From Aleksandr Vyhovanec (2015-05-25).
* fs/: Add logic to detach a file structure from a file descriptor.
This is for use only within the OS. It permits an open file or driver
to be used across multiple threads (2016-05-26).

9
Documentation/README.html
View file

@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
<p>Last Updated: May 12, 2016</p>
<p>Last Updated: May 26, 2016</p>
</td>
</tr>
</table>
@ -251,10 +251,14 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm3240g-eval/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- stm32_tiny/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32_tiny/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- stm32f103-minumum/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f103-minumum/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- stm32f3discovery/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f3discovery/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- stm32f4discovery/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f4discovery/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- stm32f411e-disco/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f411e-disco/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- stm32f429i-disco/
| | |- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f429i-disco/ide/ltcd/uvision/README.txt" target="_blank"><b><i>ide/ltcd/uvision/README.txt</i></b></a>
| | |- <a href="https://bitbucket.org/nuttx/nuttx/configs/src/master/stm32f429i-disco/ltdc/README.txt" target="_blank"><b><i>ltdc/README.txt</i></b></a>
@ -312,7 +316,8 @@ nuttx/
| |- eeprom/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/eeprom/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- lcd/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/lcd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| | |- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/lcd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/lcd/pcf8574_lcd_backpack_readme.txt" target="_blank"><b><i>pcf8574_lcd_backpack_readme.txt</i></b></a>
| |- mtd/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/mtd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- sensors/

7
README.txt
View file

@ -1426,10 +1426,14 @@ nuttx/
| | `- README.txt
| |- stm32_tiny/
| | `- README.txt
| |- stm32f103-minumum/
| | `- README.txt
| |- stm32f3discovery/
| | `- README.txt
| |- stm32f4discovery/
| | `- README.txt
| |- stm32f411e-disco/
| | `- README.txt
| |- stm32f429i-disco/
| | |- ide/ltcd/uvision/README.txt
| | |- ltdc/README.txt
@ -1487,7 +1491,8 @@ nuttx/
| |- eeprom/
| | `- README.txt
| |- lcd/
| | `- README.txt
| | | README.txt
| | `- pcf8574_lcd_backpack_readme.txt
| |- mtd/
| | `- README.txt
| |- sensors/

129
TODO
View file

@ -1,20 +1,20 @@
NuttX TODO List (Last updated March 31, 2016)
NuttX TODO List (Last updated May 28, 2016)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
standards, things that could be improved, and ideas for enhancements. This
TODO list does not include issues associated with individual boar ports. See
altheso individual README.txt files in the configs/ sub-directories for
issues reated to each board port.
also the individual README.txt files in the configs/ sub-directories for
issues related to each board port.
nuttx/
nuttx/:
(13) Task/Scheduler (sched/)
(1) Memory Management (mm/)
(3) Signals (sched/signal, arch/)
(2) pthreads (sched/pthread)
(0) Message Queues (sched/mqueue)
(8) Kernel/Protected Build
(9) Kernel/Protected Build
(3) C++ Support
(6) Binary loaders (binfmt/)
(12) Network (net/, drivers/net)
@ -23,16 +23,16 @@ nuttx/
(11) Libraries (libc/, libm/)
(11) File system/Generic drivers (fs/, drivers/)
(8) Graphics subsystem (graphics/)
(1) Pascal add-on (pcode/)
(1) Build system / Toolchains
(4) Linux/Cywgin simulation (arch/sim)
(3) Linux/Cywgin simulation (arch/sim)
(4) ARM (arch/arm/)
apps/
apps/ and other Add-Ons:
(3) Network Utilities (apps/netutils/)
(2) NuttShell (NSH) (apps/nshlib)
(1) System libraries apps/system (apps/system)
(1) Pascal add-on (pcode/)
(4) Other Applications & Tests (apps/examples/)
o Task/Scheduler (sched/)
@ -70,7 +70,7 @@ o Task/Scheduler (sched/)
Title: GET_ENVIRON_PTR()
Description: get_environ_ptr() (sched/sched_getenvironptr.c) is not implemented.
The representation of the environment strings selected for
NutX is not compatible with the operation. Some significant
NuttX is not compatible with the operation. Some significant
re-design would be required to implement this function and that
effort is thought to be not worth the result.
Status: Open. No change is planned.
@ -81,7 +81,7 @@ o Task/Scheduler (sched/)
Status: Open
Priority: Low -- There is no plan to implement this.
Title: INCOMPATIBILITES WITH execv() AND execl()
Title: INCOMPATIBILITIES WITH execv() AND execl()
Description: Simplified 'execl()' and 'execv()' functions are provided by
NuttX. NuttX does not support processes and hence the concept
of overlaying a tasks process image with a new process image
@ -175,7 +175,7 @@ o Task/Scheduler (sched/)
Yahoo! Groups message 7726: "I think that the system
should be required to handle pthread_cancel safely in
all cases. In the NuttX model, a task is like a Unix
process and a pthread is like a Unix thread. Cancelling
process and a pthread is like a Unix thread. Canceling
threads should always be safe (or at least as unsafe) as
under Unix because the model is complete for pthreads...
@ -188,7 +188,7 @@ o Task/Scheduler (sched/)
"The patch I just incorporated is also insufficient. It
works only if the serial driver is shut down when the
thread is cancelled. But what if there are other open
thread is canceled. But what if there are other open
references to the driver? Then the driver will not be
shut down, the semaphores will not be re-initialized, and
the semaphore counts will still be off by one.
@ -202,7 +202,7 @@ o Task/Scheduler (sched/)
hooks so that given a semaphore it can traverse all
holders. What is needed would be logic so that given
a task, you can traverse all semaphores held by the task,
releasing each semaphore cound held by the exiting task.
releasing each semaphore count held by the exiting task.
Nothing like this exists now so that solution is not
imminent.
@ -228,16 +228,15 @@ o Task/Scheduler (sched/)
hidden behind simple accessor functions and so the internal
data structures can be changed if need with very little impact.
Explicity refereence to the list strucutre are hidden behnid
Explicitly reference to the list structure are hidden behind
the macro this_task().
Status: Open
Priority: Low. Things are just the way that we want them for the way
that NuttX is used today.
o Memory Managment (mm/)
^^^^^^^^^^^^^^^^^^^^^^
o Memory Management (mm/)
^^^^^^^^^^^^^^^^^^^^^^^
Title: FREE MEMORY ON TASK EXIT
Description: Add an option to free all memory allocated by a task when the
@ -390,7 +389,7 @@ o pthreads (sched/pthreads)
Priority: Low -- about zero, probably not that useful. Priority inheritance is
already supported and is a much better solution. And it turns out
that priority protection is just about as complex as priority inheritance.
Exerpted from my post in a Linked-In discussion:
Excerpted from my post in a Linked-In discussion:
"I started to implement this HLS/"PCP" semaphore in an RTOS that I
work with (http://www.nuttx.org) and I discovered after doing the
@ -589,8 +588,21 @@ o Kernel/Protected Build
interrupt level callbacks into applications. This, of course,
will never work in anything but a non-secure, flat build.
Status: Open
Priority: Medium. The driver is only usable with all of its features in a FLAT build.
Priority: Medium. The driver is only usable with all of its features
in a FLAT build.
Title: USER MODE TASKS CAN MODIFY PRIVILEGED TASKS
Description: Certain interfaces, such as sched_setparam(),
sched_setscheduler(), etc. can be used by user mode tasks to
modify the behavior of priviledged kernel threads.
task_delete() could even be used to kill a kernel thread.
For a truly secure system. Privileges need to be checked in
every interface that permits one thread to modify the
properties of another thread.
Status: Open
Priority: Low for most embedded systems but would be a critical need if
NuttX were used in a secure system.
o C++ Support
^^^^^^^^^^^
@ -784,7 +796,7 @@ o Binary loaders (binfmt/)
to get fixed as needed for Windows native tool builds.
Title: TOOLCHAIN COMPATIBILITY PROBLEM
Descripton: The older 4.3.3 compiler generates GOTOFF relocations to the constant
Description: The older 4.3.3 compiler generates GOTOFF relocations to the constant
strings, like:
.L3:
@ -794,7 +806,7 @@ o Binary loaders (binfmt/)
.word .LC3(GOTOFF)
.word .LC4(GOTOFF)
Where .LC0, LC1, LC2, LC3, and .LC4 are the labels correponding to strings in
Where .LC0, LC1, LC2, LC3, and .LC4 are the labels corresponding to strings in
the .rodata.str1.1 section. One consequence of this is that .rodata must reside
in D-Space since it will addressed relative to the GOT (see the section entitled
"Read-Only Data in RAM" at
@ -880,7 +892,7 @@ o Network (net/, drivers/net)
RFC3678 (IGMPv3) suggests ioctl() commands to do this (SIOCSIPMSFILTER) but
also status that those APIs are historic. NuttX implements these ioctl
commands, but is non-standard because: (1) It does not support IGMPv3, and
(2) it looks up drivers by their device name (eg., "eth0") vs IP address.
(2) it looks up drivers by their device name (e.g., "eth0") vs IP address.
Linux uses setsockopt() to control multicast group membership using the
IP_ADD_MEMBERSHIP and IP_DROP_MEMBERSHIP options. It also looks up drivers
@ -896,7 +908,7 @@ o Network (net/, drivers/net)
that connection may time out. How should this be handled? Should the
connection be removed from the backlog if it is times out or is closed?
Or should it remain in the backlog with a status indication so that accept()
can fail when it encounteres the invalid connection?
can fail when it encounters the invalid connection?
Status: Open
Priority: Medium. Important on slow applications that will not accept
connections promptly.
@ -975,7 +987,7 @@ o Network (net/, drivers/net)
it is no longer needed. Perhaps there should be a delayed
call to unlink() (using a watchdog or the work queue). If
the driver is re-opened, the delayed unlink could be
cancelled? Needs more thought.
canceled? Needs more thought.
NOTE: This is not an issue for Unix domain streams sockets:
The end-of-life of the FIFO is well determined when sockets
are disconnected and support for that case is fully implemented.
@ -1020,7 +1032,7 @@ o USB (drivers/usbdev, drivers/usbhost)
that involves delays. This needs to be redesigned to eliminate these
delays. See logic conditioned on CONFIG_USBMSC_RACEWAR.
If queuing of stall requests is supported by DCD then this workaround
If queuing of stall requests is supported by the DCD then this workaround
is not required. In this case, (1) the stall is not sent until all
write requests preceding the stall request are sent, (2) the stall is
sent, and then after the stall is cleared, (3) all write requests
@ -1135,7 +1147,7 @@ o USB (drivers/usbdev, drivers/usbhost)
Priority: Medium-Low
Title: USB CDC/ACM HOST CLASS DRIVER
Desciption: A CDC/ACM host class driver has been added. This has been
Description: A CDC/ACM host class driver has been added. This has been
testing by running the USB CDC/ACM host on an Olimex
LPC1766STK and using the configs/stm3210e-eval/usbserial
configuration (using the CDC/ACM device side driver). There
@ -1374,7 +1386,7 @@ o File system / Generic drivers (fs/, drivers/)
Priority: Medium
Title: UNIFIED DESCRIPTOR REPRESENTATION
Descripton: There are two separate ranges of descriptors for file and
Description: There are two separate ranges of descriptors for file and
socket descriptors: if a descriptor is in one range then it is
recognized as a file descriptor; if it is in another range
then it is recognized as a socket descriptor. These separate
@ -1410,7 +1422,7 @@ o File system / Generic drivers (fs/, drivers/)
Status: Open
Priority: Low
Title: FAT LONG FILENAME COMPATIBILTY
Title: FAT LONG FILENAME COMPATIBILITY
Description: Recently there have been reports that file with long file
names created by NuttX don't have long file names when viewed
on Windows. The long file name support has been around for a
@ -1423,7 +1435,7 @@ o File system / Generic drivers (fs/, drivers/)
Description: I have seen cases where (1) long file names are enabled,
but (2) a short file name is created like:
nsh> echo "This is another thest" >/mnt/sdcard/another.txt
nsh> echo "This is another test" >/mnt/sdcard/another.txt
But then on subsequent 'ls' operations, the file does not appear:
@ -1472,7 +1484,7 @@ o File system / Generic drivers (fs/, drivers/)
4) When comparing the checksum in the long file name
entry with the checksum of the short file name, the
checksum fails and the entire directlry sequence is
checksum fails and the entire directory sequence is
ignored by readder() logic. This the file does not
appear in the 'ls'.
@ -1539,7 +1551,7 @@ o Graphics subsystem (graphics/)
Priority: Low, the need has not yet arisen.
Title: PER-WINDOW FRAMEBUFFERS
Description: One of the most awkard things to handle in the NX windowing
Description: One of the most awkward things to handle in the NX windowing
system is the re-draw callback. This is difficult because it
requires ad hoc, custom logic to be able to do the redrawing
in most cases.
@ -1567,26 +1579,6 @@ o Graphics subsystem (graphics/)
Priority: Low, not a serious issue but worth noting. There is no plan
to change this behavior.
o Pascal Add-On (pcode/)
^^^^^^^^^^^^^^^^^^^^^^
Title: P-CODES IN MEMORY UNTESTED
Description: Need APIs to verify execution of P-Code from memory buffer.
Status: Open
Priority: Low
Title: SMALLER LOADER AND OBJECT FORMAT
Description: Loader and object format may be too large for some small
memory systems. Consider ways to reduce memory footprint.
Status: Open
Priority: Medium
Title: PDBG
Description: Move the the pascal p-code debugger into the NuttX apps/ tree
where it can be used from the NSH command line.
Status: Open
Priority: Low
o Build system
^^^^^^^^^^^^
@ -1609,15 +1601,6 @@ o Other drivers (drivers/)
o Linux/Cywgin simulation (arch/sim)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Title: SIMULATOR NETWORKING SUPPORT
Description: I never did get networking to work on the sim Linux target. On Linux,
it tries to use the tap device (/dev/net/tun) to emulate an Ethernet
NIC, but I never got it correctly integrated with the NuttX networking.
NOTE: On Cygwin, the build uses the Cygwin WPCAP library and is, at
least, partially functional (it has never been rigorously tested).
Status: Open
Priority: Low (unless you want to test networking features on the simulation).
Title: SIMULATOR HAS NO INTERRUPTS (NON-PREMPTIBLE)
Description: The current simulator implementation is has no interrupts and, hence,
is non-preemptible. Also, without simulated interrupt, there can
@ -1765,7 +1748,7 @@ o ARM (arch/arm/)
But this has not been proven to be a solution.
UPDATE: Other ARM architectures have a similer issue.
UPDATE: Other ARM architectures have a similar issue.
Status: Open
Priority: Low. The conditions of continuous interrupts is really the problem.
@ -1823,7 +1806,7 @@ o NuttShell (NSH) (apps/nshlib)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Title: IFCONFIG AND MULTIPLE NETWORK INTERFACES
Descripton: The ifconfig command will not behave correctly if an interface
Description: The ifconfig command will not behave correctly if an interface
is provided and there are multiple interfaces. It should only
show status for the single interface on the command line; it will
still show status for all interfaces.
@ -1848,6 +1831,26 @@ o System libraries apps/system (apps/system)
Priority: Low (unless you are using mixed C-buffered I/O with readline and
fgetc, for example).
o Pascal Add-On (pcode/)
^^^^^^^^^^^^^^^^^^^^^^
Title: P-CODES IN MEMORY UNTESTED
Description: Need APIs to verify execution of P-Code from memory buffer.
Status: Open
Priority: Low
Title: SMALLER LOADER AND OBJECT FORMAT
Description: Loader and object format may be too large for some small
memory systems. Consider ways to reduce memory footprint.
Status: Open
Priority: Medium
Title: PDBG
Description: Move the the pascal p-code debugger into the NuttX apps/ tree
where it can be used from the NSH command line.
Status: Open
Priority: Low
o Other Applications & Tests (apps/examples/)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

4
arch/arm/Kconfig
View file

@ -27,7 +27,7 @@ config ARCH_CHIP_C5471
bool "TMS320 C5471"
select ARCH_ARM7TDMI
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_OTHER_UART
select OTHER_UART_SERIALDRIVER
---help---
TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
@ -36,7 +36,7 @@ config ARCH_CHIP_CALYPSO
select ARCH_ARM7TDMI
select ARCH_HAVE_HEAP2
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_OTHER_UART
select OTHER_UART_SERIALDRIVER
select ARCH_HAVE_POWEROFF
---help---
TI Calypso-based cell phones (ARM7TDMI)

59
arch/arm/include/lpc43xx/chip.h
View file

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/lpc43xx/chip.h
*
* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -167,7 +167,7 @@
# warning "Data sheet and user manual are consistement for the LPC4320"
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -194,7 +194,7 @@
# warning "Data sheet and user manual are consistement for the LPC4320"
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -220,7 +220,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -246,7 +246,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET100)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -272,7 +272,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET180)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -298,7 +298,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET256)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -324,7 +324,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -350,7 +350,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -376,7 +376,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET180)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -402,7 +402,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET256)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -428,7 +428,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (256*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -454,7 +454,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (256*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -480,7 +480,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (256*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -506,7 +506,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -532,7 +532,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -558,7 +558,7 @@
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
@ -632,6 +632,31 @@
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels (per ADC)*/
# define LPC43_NADC12 (1) /* ONne 12-bit ADC controllers (ADCHS)*/
#elif defined(CONFIG_ARCH_CHIP_LPC4337JET100)
# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1024)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (0) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (0) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (0) /* One PWM interface */
# define LPC43_QEI (0) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (4) /* Four ADC channels */
#else
# error "Unsupported LPC43xx chip"
#endif

40
arch/arm/include/stm32/chip.h
View file

@ -1568,7 +1568,7 @@
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
# define STM32_NSPI 4 /* SPI1-4 */
# define STM32_NSPI 5 /* SPI1-5 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
# define STM32_NI2C 3 /* I2C1-3 */
@ -1585,6 +1585,44 @@
# define STM32_NRNG 0 /* No Random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F411VE) /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
# define STM32_NSPI 5 /* SPI1-5 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 1 /* One SDIO interface */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
# define STM32_NGPIO 81 /* GPIOA-H */
# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* No CRC */
# define STM32_NETHERNET 0 /* No Ethernet MAC */
# define STM32_NRNG 0 /* No Random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */

2
arch/arm/include/stm32/stm32f10xxx_irq.h
View file

@ -120,7 +120,7 @@
# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
# define STM32_IRQ_UART5 (69) /* 53: USART5 global interrupt */
# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */
# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */

9
arch/arm/src/Makefile
View file

@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/Makefile
#
# Copyright (C) 2007-2009, 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
# Copyright (C) 2007-2009, 2011-2012, 2014-2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
@ -127,6 +127,11 @@ BIN = libarch$(LIBEXT)
LDFLAGS += $(ARCHSCRIPT)
# Override in Make.defs if linker is not 'ld'
LDSTARTGROUP ?= --start-group
LDENDGROUP ?= --end-group
EXTRA_LIBS ?=
EXTRA_LIBPATHS ?=
LINKLIBS ?=
@ -198,7 +203,7 @@ nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT)
$(Q) echo "LD: nuttx"
$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \
-o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \
--start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
$(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP)
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
$(Q) $(NM) $(NUTTX) | \
grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \

16
arch/arm/src/a1x/Kconfig
View file

@ -21,49 +21,49 @@ menu "Allwinner A1X Peripheral Support"
config A1X_UART0
bool "UART 0"
default n
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config A1X_UART1
bool "UART 1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config A1X_UART2
bool "UART 2"
default n
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config A1X_UART3
bool "UART 3"
default n
select ARCH_HAVE_UART3
select UART3_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config A1X_UART4
bool "UART 4"
default n
select ARCH_HAVE_UART4
select UART4_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config A1X_UART5
bool "UART 5"
default n
select ARCH_HAVE_UART5
select UART5_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config A1X_UART6
bool "UART 6"
default n
select ARCH_HAVE_UART6
select UART6_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config A1X_UART7
bool "UART 7"
default n
select ARCH_HAVE_UART7
select UART7_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config A1X_IR0

4
arch/arm/src/armv7-a/arm_addrenv.c
View file

@ -141,10 +141,6 @@
# error CONFIG_ARCH_HEAP_VBASE not aligned to section boundary
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_addrenv_kstack.c
View file

@ -121,18 +121,6 @@
#if defined(CONFIG_ARCH_ADDRENV) && defined(CONFIG_ARCH_KERNEL_STACK)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_addrenv_shm.c
View file

@ -55,18 +55,6 @@
#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_SHM)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

8
arch/arm/src/armv7-a/arm_addrenv_ustack.c
View file

@ -116,14 +116,6 @@
# error CONFIG_ARCH_STACK_VBASE not aligned to section boundary
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_addrenv_utils.c
View file

@ -53,18 +53,6 @@
#ifdef CONFIG_ARCH_ADDRENV
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

8
arch/arm/src/armv7-a/arm_allocpage.c
View file

@ -54,10 +54,6 @@
#include "pg_macros.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
@ -108,10 +104,6 @@ static L1ndx_t g_ptemap[CONFIG_PAGING_NPPAGED];
static bool g_pgwrap;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

8
arch/arm/src/armv7-a/arm_assert.c
View file

@ -334,7 +334,13 @@ static void up_dumpstate(void)
}
#endif
/* Then dump the registers (if available) */
#ifdef CONFIG_SMP
/* Show the CPU number */
lldbg("CPU%d:\n", up_cpu_index());
#endif
/* Then dump the CPU registers (if available) */
up_registerdump();

12
arch/arm/src/armv7-a/arm_checkmapping.c
View file

@ -51,18 +51,6 @@
#ifdef CONFIG_PAGING
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_coherent_dcache.c
View file

@ -46,18 +46,6 @@
#include <nuttx/arch.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_copyfullstate.c
View file

@ -44,18 +44,6 @@
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

8
arch/arm/src/armv7-a/arm_cpuidlestack.c
View file

@ -47,7 +47,7 @@
#include "smp.h"
#include "up_internal.h"
#if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1
#ifdef CONFIG_SMP
/****************************************************************************
* Pre-processor Definitions
@ -61,6 +61,7 @@
* Private Data
****************************************************************************/
#if CONFIG_SMP_NCPUS > 1
static FAR const uint32_t *g_cpu_stackalloc[CONFIG_SMP_NCPUS] =
{
0
@ -72,6 +73,7 @@ static FAR const uint32_t *g_cpu_stackalloc[CONFIG_SMP_NCPUS] =
#endif /* CONFIG_SMP_NCPUS > 3 */
#endif /* CONFIG_SMP_NCPUS > 2 */
};
#endif
/****************************************************************************
* Public Functions
@ -122,6 +124,7 @@ static FAR const uint32_t *g_cpu_stackalloc[CONFIG_SMP_NCPUS] =
int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
{
#if CONFIG_SMP_NCPUS > 1
uintptr_t stack_alloc;
uintptr_t top_of_stack;
@ -138,8 +141,9 @@ int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
tcb->adj_stack_size = SMP_STACK_SIZE;
tcb->stack_alloc_ptr = (FAR uint32_t *)stack_alloc;
tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack;
#endif
return OK;
}
#endif /* CONFIG_SMP && CONFIG_SMP_NCPUS > 1 */
#endif /* CONFIG_SMP */

47
arch/arm/src/armv7-a/arm_cpustart.c
View file

@ -46,10 +46,42 @@
#include "up_internal.h"
#include "gic.h"
#include "cp15_cacheops.h"
#include "sched/sched.h"
#ifdef CONFIG_SMP
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: arm_registerdump
****************************************************************************/
#if 0 /* Was useful in solving some startup problems */
static inline void arm_registerdump(FAR struct tcb_s *tcb)
{
int regndx;
lldbg("CPU%d:\n", up_cpu_index());
/* Dump the startup registers */
for (regndx = REG_R0; regndx <= REG_R15; regndx += 8)
{
uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx];
lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regndx, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
lldbg("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
}
#else
# define arm_registerdump(tcb)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -72,12 +104,19 @@
int arm_start_handler(int irq, FAR void *context)
{
FAR struct tcb_s *tcb = this_task();
FAR struct tcb_s *tcb;
sllvdbg("CPU%d Started\n", up_cpu_index());
/* Reset scheduler parameters */
tcb = this_task();
sched_resume_scheduler(tcb);
/* Dump registers so that we can see what is going to happen on return */
arm_registerdump(tcb);
/* Then switch contexts. This instantiates the exception context of the
* tcb at the head of the assigned task list. In this case, this should
* be the CPUs NULL task.
@ -116,8 +155,14 @@ int arm_start_handler(int irq, FAR void *context)
int up_cpu_start(int cpu)
{
sllvdbg("Starting CPU%d\n", cpu);
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
/* Make the content of CPU0 L1 cache has been written to coherent L2 */
cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1);
/* Execute SGI1 */
return arm_cpu_sgi(GIC_IRQ_SGI1, (1 << cpu));

16
arch/arm/src/armv7-a/arm_doirq.c
View file

@ -52,22 +52,6 @@
#include "group/group.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_elf.c
View file

@ -48,18 +48,6 @@
#include <nuttx/arch.h>
#include <nuttx/binfmt/elf.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

16
arch/arm/src/armv7-a/arm_fullcontextrestore.S
View file

@ -44,28 +44,12 @@
.file "arm_fullcontextrestore.S"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.globl up_fullcontextrestore
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

101
arch/arm/src/armv7-a/arm_gicv2.c
View file

@ -166,12 +166,12 @@ void arm_gic_initialize(void)
/* Registers with 8-bits per interrupt */
putreg32(0x80808080, GIC_ICDIPR(0)); /* SGI[3:0] priority */
putreg32(0x80808080, GIC_ICDIPR(4)); /* SGI[4:7] priority */
putreg32(0x80808080, GIC_ICDIPR(8)); /* SGI[8:11] priority */
putreg32(0x80808080, GIC_ICDIPR(12)); /* SGI[12:15] priority */
putreg32(0x80000000, GIC_ICDIPR(24)); /* PPI[0] priority */
putreg32(0x80808080, GIC_ICDIPR(28)); /* PPI[1:4] priority */
putreg32(0x80808080, GIC_ICDIPR(0)); /* SGI[3:0] priority */
putreg32(0x80808080, GIC_ICDIPR(4)); /* SGI[4:7] priority */
putreg32(0x80808080, GIC_ICDIPR(8)); /* SGI[8:11] priority */
putreg32(0x80808080, GIC_ICDIPR(12)); /* SGI[12:15] priority */
putreg32(0x80000000, GIC_ICDIPR(24)); /* PPI[0] priority */
putreg32(0x80808080, GIC_ICDIPR(28)); /* PPI[1:4] priority */
/* Set the binary point register.
*
@ -211,7 +211,16 @@ void arm_gic_initialize(void)
#endif
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_BOTH)
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
/* Set FIQn=1 if secure interrupts are to signal using nfiq_c.
*
* NOTE: Only for processors that operate in secure state.
* REVISIT: Do I need to do this?
*/
//iccicr |= GIC_ICCICRS_FIQEN;
#elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
/* Set FIQn=1 if secure interrupts are to signal using nfiq_c.
*
* NOTE: Only for processors that operate in secure state.
@ -221,25 +230,35 @@ void arm_gic_initialize(void)
iccicr |= GIC_ICCICRS_FIQEN;
#endif
#if defined(ONFIG_ARCH_TRUSTZONE_BOTH)
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE)
/* Program the AckCtl bit to select the required interrupt acknowledge
* behavior.
*
* NOTE: Only for processors that operate in both secure and non-secure
* state.
* REVISIT: I don't yet fully understand this setting.
* REVISIT: This is here only for superstituous reasons. I don't think
* I need this setting in this configuration.
*/
// iccicr |= GIC_ICCICRS_ACKTCTL;
iccicr |= GIC_ICCICRS_ACKTCTL;
#elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
/* Program the AckCtl bit to select the required interrupt acknowledge
* behavior.
*
* NOTE: Only for processors that operate in both secure and non-secure
* state.
*/
iccicr |= GIC_ICCICRS_ACKTCTL;
/* Program the SBPR bit to select the required binary pointer behavior.
*
* NOTE: Only for processors that operate in both secure and non-secure
* state.
* REVISIT: I don't yet fully understand this setting.
*/
// iccicr |= GIC_ICCICRS_CBPR;
iccicr |= GIC_ICCICRS_CBPR;
#endif
#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_BOTH)
@ -291,9 +310,15 @@ void arm_gic_initialize(void)
* bypass.
*/
#if 0 /* REVISIT -- I don't know why this needs to be like this */
iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_FIQBYPDISGRP0 |
GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 |
GIC_ICCICRS_IRQBYPDISGRP1);
#else
iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 |
GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 |
GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1);
#endif
icddcr = GIC_ICDDCR_ENABLEGRP0;
#elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
@ -498,4 +523,56 @@ int up_prioritize_irq(int irq, int priority)
return -EINVAL;
}
/****************************************************************************
* Name: arm_gic_irq_trigger
*
* Description:
* Set the trigger type for the specified IRQ source and the current CPU.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
* Input Paramters:
* irq - The interrupt request to modify.
* edge - False: Active HIGH level sensitive, True: Rising edge sensitive
*
* Returned Value:
* Zero (OK) on success; a negated errno value is returned on any failure.
*
****************************************************************************/
int arm_gic_irq_trigger(int irq, bool edge)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t intcfg;
if (irq > GIC_IRQ_SGI15 && irq < NR_IRQS)
{
/* Get the address of the Interrupt Configuration Register for this
* irq.
*/
regaddr = GIC_ICDICFR(irq);
/* Get the new Interrupt configuration bit setting */
intcfg = (edge ? (INT_ICDICFR_EDGE | INT_ICDICFR_1N) : INT_ICDICFR_1N);
/* Write the correct interrupt trigger to the Interrupt Configuration
* Register.
*/
regval = getreg32(regaddr);
regval &= ~GIC_ICDICFR_ID_MASK(irq);
regval |= GIC_ICDICFR_ID(irq, intcfg);
putreg32(regval, regaddr);
return OK;
}
return -EINVAL;
}
#endif /* CONFIG_ARMV7A_HAVE_GICv2 */

12
arch/arm/src/armv7-a/arm_initialstate.c
View file

@ -48,18 +48,6 @@
#include "up_internal.h"
#include "up_arch.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_mmu.c
View file

@ -44,18 +44,6 @@
#include "cache.h"
#include "mmu.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

7
arch/arm/src/armv7-a/arm_pgalloc.c
View file

@ -54,13 +54,6 @@
#ifdef CONFIG_BUILD_KERNEL
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions

12
arch/arm/src/armv7-a/arm_pginitialize.c
View file

@ -49,18 +49,6 @@
#ifdef CONFIG_PAGING
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

11
arch/arm/src/armv7-a/arm_physpgaddr.c
View file

@ -55,17 +55,6 @@
#ifdef CONFIG_MM_PGALLOC
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_prefetchabort.c
View file

@ -61,18 +61,6 @@
#include "sched/sched.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_schedulesigaction.c
View file

@ -53,18 +53,6 @@
#ifndef CONFIG_DISABLE_SIGNALS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_signal_dispatch.c
View file

@ -47,18 +47,6 @@
#if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_SIGNALS)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

2
arch/arm/src/armv7-a/arm_syscall.c
View file

@ -77,7 +77,7 @@
#endif
/****************************************************************************
* Private Data
* Private Functions
****************************************************************************/
/****************************************************************************

12
arch/arm/src/armv7-a/arm_unblocktask.c
View file

@ -49,18 +49,6 @@
#include "clock/clock.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_undefinedinsn.c
View file

@ -58,18 +58,6 @@
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

12
arch/arm/src/armv7-a/arm_va2pte.c
View file

@ -52,18 +52,6 @@
#ifdef CONFIG_PAGING
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

8
arch/arm/src/armv7-a/arm_vectors.S
View file

@ -45,10 +45,6 @@
.file "arm_vectors.S"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Private Data
************************************************************************************/
@ -69,10 +65,6 @@ g_fiqtmp:
.word 0 /* Saved spsr */
#endif
/************************************************************************************
* Assembly Macros
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/

12
arch/arm/src/armv7-a/arm_virtpgaddr.c
View file

@ -43,18 +43,6 @@
#if defined(CONFIG_MM_PGALLOC) && defined(CONFIG_ARCH_PGPOOL_MAPPING)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/

8
arch/arm/src/armv7-a/crt0.c
View file

@ -46,14 +46,6 @@
#ifdef CONFIG_BUILD_KERNEL
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/

22
arch/arm/src/armv7-a/gic.h
View file

@ -495,7 +495,7 @@
#define INT_ICDICFR_EDGE 2 /* Bit n+2: 1=Edge sensitive */
#define GIC_ICDICFR_ID_SHIFT(n) GIC_SHIFT16(n)
#define GIC_ICDICFR_ID_MASK(n) GIC_MASK16(n
#define GIC_ICDICFR_ID_MASK(n) GIC_MASK16(n)
# define GIC_ICDICFR_ID(n,c) ((uint32_t)(c) << GIC_SHIFT16(n))
/* PPI Status Register */
@ -720,6 +720,26 @@ void arm_gic0_initialize(void);
void arm_gic_initialize(void);
/****************************************************************************
* Name: arm_gic_irq_trigger
*
* Description:
* Set the trigger type for the specificd IRQ source and the current CPU.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
* Input Paramters:
* irq - The interrupt request to modify.
* edge - False: Active HIGH level sensitive, True: Rising edge sensitive
*
* Returned Value:
* Zero (OK) on success; a negated errno value is returned on any failure.
*
****************************************************************************/
int arm_gic_irq_trigger(int irq, bool edge);
/****************************************************************************
* Name: arm_decodeirq
*

4
arch/arm/src/common/up_createstack.c
View file

@ -220,7 +220,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
if (tcb->stack_alloc_ptr)
{
#if defined(CONFIG_TLS) && defined(CONFIG_STACK_COLORATION)
uinptr_t stack_base;
uintptr_t stack_base;
#endif
size_t top_of_stack;
size_t size_of_stack;
@ -264,7 +264,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
* water marks.
*/
stackbase = (uintptr_t)tcb->stack_alloc_ptr + sizeof(struct tls_info_s);
stack_base = (uintptr_t)tcb->stack_alloc_ptr + sizeof(struct tls_info_s);
stack_size = tcb->adj_stack_size - sizeof(struct tls_info_s);
up_stack_color((FAR void *)stack_base, stack_size);

8
arch/arm/src/common/up_usestack.c
View file

@ -174,7 +174,13 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
* value that we can use later to test for high water marks.
*/
# warning Missing logic
#ifdef CONFIG_TLS
up_stack_color(
(FAR void *)((uintptr_t)tcb->stack_alloc_ptr + sizeof(struct tls_info_s)),
tcb->adj_stack_size - sizeof(struct tls_info_s));
#else
up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
#endif
#endif
return OK;

4
arch/arm/src/dm320/Kconfig
View file

@ -11,12 +11,12 @@ menu "DM320 Peripheral Selections"
config DM320_UART0
bool
default y
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
config DM320_UART1
bool
default y
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
endmenu # DM320 Peripheral Selections
endif # ARCH_CHIP_DM320

17
arch/arm/src/efm32/Kconfig
View file

@ -157,45 +157,42 @@ config EFM32_BITBAND
config EFM32_USART0
bool "USART0"
default n
select ARCH_HAVE_USART0
select ARCH_HAVE_SERIAL_TERMIOS
config EFM32_USART1
bool "USART1"
default n
select ARCH_HAVE_USART1
select ARCH_HAVE_SERIAL_TERMIOS
config EFM32_USART2
bool "USART2"
default n
depends on EFM32_HAVE_USART2
select ARCH_HAVE_USART2
select ARCH_HAVE_SERIAL_TERMIOS
config EFM32_UART0
bool "UART0"
default n
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
select EFM32_UART
config EFM32_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
select EFM32_UART
config EFM32_LEUART0
bool "Low energy UART0"
default n
select ARCH_HAVE_OTHER_UART
select OTHER_UART_SERIALDRIVER
select EFM32_LEUART
config EFM32_LEUART1
bool "Low energy UART1"
default n
depends on EFM32_HAVE_LEUART1
select ARCH_HAVE_OTHER_UART
select OTHER_UART_SERIALDRIVER
select EFM32_LEUART
config EFM32_OTGFS
@ -261,7 +258,7 @@ choice
config EFM32_USART0_ISUART
bool "USART0 is a UART"
select USART0_ISUART
select USART0_SERIALDRIVER
select EFM32_USART_ISUART
config EFM32_USART0_ISSPI
@ -277,7 +274,7 @@ choice
config EFM32_USART1_ISUART
bool "USART1 is a UART"
select USART1_ISUART
select USART1_SERIALDRIVER
select EFM32_USART_ISUART
config EFM32_USART1_ISSPI
@ -293,7 +290,7 @@ choice
config EFM32_USART2_ISUART
bool "USART2 is a UART"
select USART2_ISUART
select USART2_SERIALDRIVER
select EFM32_USART_ISUART
config EFM32_USART2_ISSPI

57
arch/arm/src/efm32/efm32_adc.c
View file

@ -2,7 +2,9 @@
* arch/arm/src/efm32/efm32_adc.c
*
* Copyright (C) 2014 Bouteville Pierre-Noel. All rights reserved.
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Bouteville Pierre-Noel <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -63,9 +65,9 @@
#include "efm32.h"
#include "efm32_adc.h"
/* ADC "upper half" support must be enabled */
/* ADC "lower half" support must be enabled */
#ifdef CONFIG_ADC
#ifdef CONFIG_EFM32_ADC
/* Some ADC peripheral must be enabled */
@ -100,6 +102,7 @@
struct efm32_dev_s
{
FAR const struct adc_callback_s *cb;
uint8_t irq; /* Interrupt generated by this ADC block */
uint8_t nchannels; /* Number of channels */
uint8_t current; /* Current ADC channel being converted */
@ -124,6 +127,8 @@ static int adc_interrupt(FAR struct adc_dev_s *dev);
/* ADC Driver Methods */
static int adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback);
static void adc_reset(FAR struct adc_dev_s *dev);
static int adc_setup(FAR struct adc_dev_s *dev);
static void adc_shutdown(FAR struct adc_dev_s *dev);
@ -148,6 +153,7 @@ static void adc_startconv(FAR struct efm32_dev_s *priv, bool enable);
static const struct adc_ops_s g_adcops =
{
.ao_bind = adc_bind,
.ao_reset = adc_reset,
.ao_setup = adc_setup,
.ao_shutdown = adc_shutdown,
@ -790,7 +796,7 @@ static void adc_startconv(struct efm32_dev_s *priv, bool enable)
#endif
/****************************************************************************
* Name: adc_reset
* Name: adc_hw_reset
*
* Description:
* Deinitializes the ADCx peripheral registers to their default
@ -873,6 +879,25 @@ static void adc_enable(FAR struct efm32_dev_s *priv, bool enable)
adc_putreg(priv, EFM32_ADC_CR2_OFFSET, regval);
}
/****************************************************************************
* Name: adc_bind
*
* Description:
* Bind the upper-half driver callbacks to the lower-half implementation. This
* must be called early in order to receive ADC event notifications.
*
****************************************************************************/
static int adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback)
{
FAR struct efm32_dev_s *priv = (FAR struct efm32_dev_s *)dev->ad_priv;
DEBUGASSERT(priv != NULL);
priv->cb = callback;
return OK;
}
/****************************************************************************
* Name: adc_reset
*
@ -1180,14 +1205,21 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
value = adc_getreg(priv, EFM32_ADC_DR_OFFSET);
value &= ADC_DR_DATA_MASK;
/* Give the ADC data to the ADC driver. adc_receive accepts 3 parameters:
*
* 1) The first is the ADC device instance for this ADC block.
* 2) The second is the channel number for the data, and
* 3) The third is the converted data for the channel.
*/
/* Verify that the upper-half driver has bound its callback functions */
adc_receive(dev, priv->chanlist[priv->current], value);
if (priv->cb != NULL)
{
/* Give the ADC data to the ADC driver. The ADC receive method
* accepts 3 parameters:
*
* 1) The first is the ADC device instance for this ADC block.
* 2) The second is the channel number for the data, and
* 3) The third is the converted data for the channel.
*/
DEBUGASSERT(priv->cb->au_receive != NULL);
priv->cb->au_receive(dev, priv->chanlist[priv->current], value);
}
/* Set the channel number of the next channel that will complete conversion */
@ -1272,7 +1304,8 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
/* Configure the selected ADC */
priv = dev->ad_priv;
priv = dev->ad_priv;
priv->cb = NULL;
DEBUGASSERT(nchannels <= ADC_MAX_SAMPLES);
priv->nchannels = nchannels;
@ -1283,4 +1316,4 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
#endif /* CONFIG_EFM32_EFM32GG */
#endif /* CONFIG_EFM32_ADC1 */
#endif /* CONFIG_ADC */
#endif /* CONFIG_EFM32_ADC */

6
arch/arm/src/imx1/Kconfig
View file

@ -12,17 +12,17 @@ menu "iMX.1 Peripheral Selection"
config IMX1_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
config IMX1_UART2
bool "UART2"
default n
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
config IMX1_UART3
bool "UART3"
default n
select ARCH_HAVE_UART3
select UART3_SERIALDRIVER
config IMX1_SPI1
bool "SPI1"

4
arch/arm/src/imx1/imx_cspi.h
View file

@ -74,7 +74,7 @@
#define IMX_CSPI1_SPIDMA (IMX_CSPI1_VBASE + CSPI_DMA_OFFSET)
#define IMX_CSPI1_SPIRESET (IMX_CSPI1_VBASE + CSPI_RESET_OFFSET)
/* CSPI1 */
/* CSPI2 */
#define IMX_CSPI2_RXD (IMX_CSPI2_VBASE + CSPI_RXD_OFFSET)
#define IMX_CSPI2_TXD (IMX_CSPI2_VBASE + CSPI_TXD_OFFSET)
@ -138,7 +138,7 @@
/* CSPI Sample Period Control Register */
#define CSPI_SPCR_WAIT_SHIFT 0
#define CSPI_SPCR_WAIT_MASK (0x7ff << CSPI_CTRL_DATARATE_SHIFT)
#define CSPI_SPCR_WAIT_MASK (0x7ff << CSPI_SPCR_WAIT_SHIFT)
#define CSPI_SPCR_CSRC (1 << 15) /* Bit 15: 1:32768 or 32 kHz clock source */
/* CSPI DMA Control Register */

39
arch/arm/src/imx6/Kconfig
View file

@ -54,32 +54,61 @@ config IMX6_HAVE_HDCP
endmenu # "iMX.6 Chip Selection"
config IMX6_ECSPI
bool
default n
menu "iMX.6 Peripheral Selection"
config IMX6_ECSPI1
bool "ECSPI1"
default n
select IMX6_ECSPI
config IMX6_ECSPI2
bool "ECSPI2"
default n
select IMX6_ECSPI
config IMX6_ECSPI3
bool "ECSPI3"
default n
select IMX6_ECSPI
config IMX6_ECSPI4
bool "ECSPI4"
default n
select IMX6_ECSPI
config IMX6_ECSPI5
bool "ECSPI5"
default n
select IMX6_ECSPI
config IMX6_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
config IMX6_UART2
bool "UART2"
default n
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
config IMX6_UART3
bool "UART3"
default n
select ARCH_HAVE_UART3
select UART3_SERIALDRIVER
config IMX6_UART4
bool "UART4"
default n
select ARCH_HAVE_UART4
select UART4_SERIALDRIVER
config IMX6_UART5
bool "UART5"
default n
select ARCH_HAVE_UART5
select UART5_SERIALDRIVER
config IMX6_SPI1
bool "SPI1"

290
arch/arm/src/imx6/chip/imx_ecspi.h Normal file
View file

@ -0,0 +1,290 @@
/************************************************************************************
* arch/arm/src/imx6/imx_ecspi.h
*
* Copyright (C) 2009-2010, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX6_CHIP_ECSPI_H
#define __ARCH_ARM_IMX6_CHIP_ECSPI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/imx_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* ECSPI Register Offsets ***********************************************************/
#define ECSPI_RXDATA_OFFSET 0x0000 /* Receive Data Register */
#define ECSPI_TXDATA_OFFSET 0x0004 /* Transmit Data Register */
#define ECSPI_CONREG_OFFSET 0x0008 /* Control Register */
#define ECSPI_CONFIGREG_OFFSET 0x000c /* Configuration Register */
#define ECSPI_INTREG_OFFSET 0x0010 /* Interrupt Control Register */
#define ECSPI_DMAREG_OFFSET 0x0014 /* DMA Control Register */
#define ECSPI_STATREG_OFFSET 0x0018 /* Status Register */
#define ECSPI_PERIODREG_OFFSET 0x001c /* Sample Period Control Register */
#define ECSPI_TESTREG_OFFSET 0x0020 /* Test Control Register */
#define ECSPI_MSGDATA_OFFSET 0x0040 /* Message Data Register */
/* ECSPI Register Addresses *********************************************************/
/* ECSPI1 */
#define IMX_ECSPI1_RXDATA (IMX_ECSPI1_VBASE + ECSPI_RXDATA_OFFSET)
#define IMX_ECSPI1_TXDATA (IMX_ECSPI1_VBASE + ECSPI_TXDATA_OFFSET)
#define IMX_ECSPI1_CONREG (IMX_ECSPI1_VBASE + ECSPI_CONREG_OFFSET)
#define IMX_ECSPI1_CONFIGREG (IMX_ECSPI1_VBASE + ECSPI_CONFIGREG_OFFSET)
#define IMX_ECSPI1_INTREG (IMX_ECSPI1_VBASE + ECSPI_INTREG_OFFSET)
#define IMX_ECSPI1_DMAREG (IMX_ECSPI1_VBASE + ECSPI_DMAREG_OFFSET)
#define IMX_ECSPI1_STATREG (IMX_ECSPI1_VBASE + ECSPI_STATREG_OFFSET)
#define IMX_ECSPI1_PERIODREG (IMX_ECSPI1_VBASE + ECSPI_PERIODREG_OFFSET)
#define IMX_ECSPI1_TESTREG (IMX_ECSPI1_VBASE + ECSPI_TESTREG_OFFSET)
#define IMX_ECSPI1_MSGDATA (IMX_ECSPI1_VBASE + ECSPI_MSGDATA_OFFSET)
/* ECSPI2 */
#define IMX_ECSPI2_RXDATA (IMX_ECSPI2_VBASE + ECSPI_RXDATA_OFFSET)
#define IMX_ECSPI2_TXDATA (IMX_ECSPI2_VBASE + ECSPI_TXDATA_OFFSET)
#define IMX_ECSPI2_CONREG (IMX_ECSPI2_VBASE + ECSPI_CONREG_OFFSET)
#define IMX_ECSPI2_CONFIGREG (IMX_ECSPI2_VBASE + ECSPI_CONFIGREG_OFFSET)
#define IMX_ECSPI2_INTREG (IMX_ECSPI2_VBASE + ECSPI_INTREG_OFFSET)
#define IMX_ECSPI2_DMAREG (IMX_ECSPI2_VBASE + ECSPI_DMAREG_OFFSET)
#define IMX_ECSPI2_STATREG (IMX_ECSPI2_VBASE + ECSPI_STATREG_OFFSET)
#define IMX_ECSPI2_PERIODREG (IMX_ECSPI2_VBASE + ECSPI_PERIODREG_OFFSET)
#define IMX_ECSPI2_TESTREG (IMX_ECSPI2_VBASE + ECSPI_TESTREG_OFFSET)
#define IMX_ECSPI2_MSGDATA (IMX_ECSPI2_VBASE + ECSPI_MSGDATA_OFFSET)
/* ECSPI3 */
#define IMX_ECSPI3_RXDATA (IMX_ECSPI3_VBASE + ECSPI_RXDATA_OFFSET)
#define IMX_ECSPI3_TXDATA (IMX_ECSPI3_VBASE + ECSPI_TXDATA_OFFSET)
#define IMX_ECSPI3_CONREG (IMX_ECSPI3_VBASE + ECSPI_CONREG_OFFSET)
#define IMX_ECSPI3_CONFIGREG (IMX_ECSPI3_VBASE + ECSPI_CONFIGREG_OFFSET)
#define IMX_ECSPI3_INTREG (IMX_ECSPI3_VBASE + ECSPI_INTREG_OFFSET)
#define IMX_ECSPI3_DMAREG (IMX_ECSPI3_VBASE + ECSPI_DMAREG_OFFSET)
#define IMX_ECSPI3_STATREG (IMX_ECSPI3_VBASE + ECSPI_STATREG_OFFSET)
#define IMX_ECSPI3_PERIODREG (IMX_ECSPI3_VBASE + ECSPI_PERIODREG_OFFSET)
#define IMX_ECSPI3_TESTREG (IMX_ECSPI3_VBASE + ECSPI_TESTREG_OFFSET)
#define IMX_ECSPI3_MSGDATA (IMX_ECSPI3_VBASE + ECSPI_MSGDATA_OFFSET)
/* ECSPI4 */
#define IMX_ECSPI4_RXDATA (IMX_ECSPI4_VBASE + ECSPI_RXDATA_OFFSET)
#define IMX_ECSPI4_TXDATA (IMX_ECSPI4_VBASE + ECSPI_TXDATA_OFFSET)
#define IMX_ECSPI4_CONREG (IMX_ECSPI4_VBASE + ECSPI_CONREG_OFFSET)
#define IMX_ECSPI4_CONFIGREG (IMX_ECSPI4_VBASE + ECSPI_CONFIGREG_OFFSET)
#define IMX_ECSPI4_INTREG (IMX_ECSPI4_VBASE + ECSPI_INTREG_OFFSET)
#define IMX_ECSPI4_DMAREG (IMX_ECSPI4_VBASE + ECSPI_DMAREG_OFFSET)
#define IMX_ECSPI4_STATREG (IMX_ECSPI4_VBASE + ECSPI_STATREG_OFFSET)
#define IMX_ECSPI4_PERIODREG (IMX_ECSPI4_VBASE + ECSPI_PERIODREG_OFFSET)
#define IMX_ECSPI4_TESTREG (IMX_ECSPI4_VBASE + ECSPI_TESTREG_OFFSET)
#define IMX_ECSPI4_MSGDATA (IMX_ECSPI4_VBASE + ECSPI_MSGDATA_OFFSET)
/* ECSPI5 */
#define IMX_ECSPI5_RXDATA (IMX_ECSPI5_VBASE + ECSPI_RXDATA_OFFSET)
#define IMX_ECSPI5_TXDATA (IMX_ECSPI5_VBASE + ECSPI_TXDATA_OFFSET)
#define IMX_ECSPI5_CONREG (IMX_ECSPI5_VBASE + ECSPI_CONREG_OFFSET)
#define IMX_ECSPI5_CONFIGREG (IMX_ECSPI5_VBASE + ECSPI_CONFIGREG_OFFSET)
#define IMX_ECSPI5_INTREG (IMX_ECSPI5_VBASE + ECSPI_INTREG_OFFSET)
#define IMX_ECSPI5_DMAREG (IMX_ECSPI5_VBASE + ECSPI_DMAREG_OFFSET)
#define IMX_ECSPI5_STATREG (IMX_ECSPI5_VBASE + ECSPI_STATREG_OFFSET)
#define IMX_ECSPI5_PERIODREG (IMX_ECSPI5_VBASE + ECSPI_PERIODREG_OFFSET)
#define IMX_ECSPI5_TESTREG (IMX_ECSPI5_VBASE + ECSPI_TESTREG_OFFSET)
#define IMX_ECSPI5_MSGDATA (IMX_ECSPI5_VBASE + ECSPI_MSGDATA_OFFSET)
/* ECSPI Register Bit Definitions ***************************************************/
/* Control Register */
#define ECSPI_CONREG_EN (1 << 0) /* Bit 0: SPI Block enable control */
#define ECSPI_CONREG_HT (1 << 1) /* Bit 1: Hardware trigger enable */
#define ECSPI_CONREG_XCH (1 << 2) /* Bit 2: SPI Exchange bit */
#define ECSPI_CONREG_SMC (1 << 3) /* Bit 3: Start mode control */
#define ECSPI_CONREG_CHMODE_SHIFT (4) /* Bits 4-7: SPI Channel mode */
#define ECSPI_CONREG_CHMODE_MASK (15 << ECSPI_CONREG_CHMODE_SHIFT)
# define ECSPI_CONREG_CH0MASTER (1 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 0 master mode */
# define ECSPI_CONREG_CH1MASTER (2 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 1 master mode */
# define ECSPI_CONREG_CH2MASTER (4 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 2 master mode */
# define ECSPI_CONREG_CH3MASTER (8 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 3 master mode */
#define ECSPI_CONREG_POSTDIV_SHIFT (8) /* Bits 8-11: SPI Post divider (exponent) */
#define ECSPI_CONREG_POSTDIV_MASK (15 << ECSPI_CONREG_POSTDIV_SHIFT)
# define ECSPI_CONREG_POSTDIV_EXP(n) ((uint32_t)(n) << ECSPI_CONREG_POSTDIV_SHIFT)
# define ECSPI_CONREG_POSTDIV_1 (0 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*0 */
# define ECSPI_CONREG_POSTDIV_2 (1 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*1 */
# define ECSPI_CONREG_POSTDIV_4 (2 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*2 */
# define ECSPI_CONREG_POSTDIV_8 (3 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*3 */
# define ECSPI_CONREG_POSTDIV_16 (4 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*4 */
# define ECSPI_CONREG_POSTDIV_32 (5 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*5 */
# define ECSPI_CONREG_POSTDIV_64 (6 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*6 */
# define ECSPI_CONREG_POSTDIV_128 (7 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*7 */
# define ECSPI_CONREG_POSTDIV_256 (8 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*8 */
# define ECSPI_CONREG_POSTDIV_512 (9 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*9 */
# define ECSPI_CONREG_POSTDIV_1024 (10 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*10 */
# define ECSPI_CONREG_POSTDIV_2048 (11 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*11 */
# define ECSPI_CONREG_POSTDIV_4096 (12 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*12 */
# define ECSPI_CONREG_POSTDIV_8192 (13 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*13 */
# define ECSPI_CONREG_POSTDIV_16384 (14 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*14 */
# define ECSPI_CONREG_POSTDIV_32768 (15 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*15 */
#define ECSPI_CONREG_PREDIV_SHIFT (12) /* Bits 12-15: SPI Pre divider (minus 1) */
#define ECSPI_CONREG_PREDIV_MASK (15 << ECSPI_CONREG_PREDIV_SHIFT)
# define ECSPI_CONREG_PREDIV(n) ((uint32_t)(n) << ECSPI_CONREG_PREDIV_SHIFT)
#define ECSPI_CONREG_DRCTL_SHIFT 16 /* Bits 16-17: SPI Data ready control */
#define ECSPI_CONREG_DRCTL_MASK (3 << ECSPI_CONREG_DRCTL_SHIFT)
# define ECSPI_CONREG_DRCTL_IGNRDY (0 << ECSPI_CONREG_DRCTL_SHIFT)
# define ECSPI_CONREG_DRCTL_FALLING (1 << ECSPI_CONREG_DRCTL_SHIFT)
# define ECSPI_CONREG_DRCTL_ACTVLOW (2 << ECSPI_CONREG_DRCTL_SHIFT)
#define ECSPI_CONREG_CHSEL_SHIFT (18) /* Bits 18-19: SPI Channel select bits */
#define ECSPI_CONREG_CHSEL_MASK (3 << ECSPI_CONREG_CHSEL_SHIFT)
# define ECSPI_CONREG_CHSEL_SS0 (0 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 0 select (SS0) */
# define ECSPI_CONREG_CHSEL_SS1 (1 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 1 select (SS1) */
# define ECSPI_CONREG_CHSEL_SS2 (2 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 2 select (SS2) */
# define ECSPI_CONREG_CHSEL_SS3 (3 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 3 select (SS3) */
#define ECSPI_CONREG_BURSTLEN_SHIFT (20) /* Bits 20-31: Burst length */
#define ECSPI_CONREG_BURSTLEN_MASK (0xfff << ECSPI_CONREG_BURSTLEN_SHIFT)
# define ECSPI_CONREG_BURSTLEN(n) ((uint32_t)(n) << ECSPI_CONREG_BURSTLEN_SHIFT)
/* Configuration Register */
#define ECSPI_CONFIGREG_SCLKPHA_SHIFT (0) /* Bits 0-3: SPI Clock/Data Phase Control */
#define ECSPI_CONFIGREG_SCLKPHA_MASK (15 << ECSPI_CONFIGREG_SCLKPHA_SHIFT)
# define ECSPI_CONFIGREG_CH0PHA (1 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 0 SCLK Phase */
# define ECSPI_CONFIGREG_CH1PHA (2 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 1 SCLK Phase */
# define ECSPI_CONFIGREG_CH2PHA (4 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 2 SCLK Phase */
# define ECSPI_CONFIGREG_CH3PHA (8 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 3 SCLK Phase */
#define ECSPI_CONFIGREG_SCLKPOL_SHIFT (4) /* Bits 4-7: SPI Clock polarity control */
#define ECSPI_CONFIGREG_SCLKPOL_MASK (15 << ECSPI_CONFIGREG_SCLKPOL_SHIFT)
# define ECSPI_CONFIGREG_CH0POL (1 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 0 SCLK polarity */
# define ECSPI_CONFIGREG_CH1POL (2 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 1 SCLK polarity */
# define ECSPI_CONFIGREG_CH2POL (4 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 2 SCLK polarity */
# define ECSPI_CONFIGREG_CH3POL (8 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 3 SCLK polarity */
#define ECSPI_CONFIGREG_SSCTL_SHIFT (8) /* Bits 8-11: SPI SS Wave form select */
#define ECSPI_CONFIGREG_SSCTL_MASK (15 << ECSPI_CONFIGREG_SSCTL_SHIFT)
# define ECSPI_CONFIGREG_CH0SSCTRL (1 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 0 SS control */
# define ECSPI_CONFIGREG_CH1SSCTRL (2 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 1 SS control */
# define ECSPI_CONFIGREG_CH2SSCTRL (4 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 2 SS control */
# define ECSPI_CONFIGREG_CH3SSCTRL (8 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 3 SS control */
#define ECSPI_CONFIGREG_SSPOL_SHIFT (12) /* Bits 12-15: SPI SS Polarity select */
#define ECSPI_CONFIGREG_SSPOL_MASK (15 << ECSPI_CONFIGREG_SSPOL_SHIFT)
# define ECSPI_CONFIGREG_CH0SSPOL (1 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 0 SS polarity */
# define ECSPI_CONFIGREG_CH1SSPOL (2 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 1 SS polarity */
# define ECSPI_CONFIGREG_CH2SSPOL (4 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 2 SS polarity */
# define ECSPI_CONFIGREG_CH3SSPOL (8 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 3 SS polarity */
#define ECSPI_CONFIGREG_DATCTL_SHIFT (16) /* Bits 16-19: Data control */
#define ECSPI_CONFIGREG_DATCTL_MASK (15 << ECSPI_CONFIGREG_DATCTL_SHIFT)
# define ECSPI_CONFIGREG_CH0DATLOW (1 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 0 SS low when inactive */
# define ECSPI_CONFIGREG_CH1DATLOW (2 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 1 SS low when inactive */
# define ECSPI_CONFIGREG_CH2DATLOW (4 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 2 SS low when inactive */
# define ECSPI_CONFIGREG_CH3DATLOW (8 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 3 SS low when inactive */
#define ECSPI_CONFIGREG_SCLKCTL_SHIFT (20) /* Bits 20-23: SCLK Control */
#define ECSPI_CONFIGREG_SCLKCTL_MASK (15 << ECSPI_CONFIGREG_SCLKCTL_SHIFT)
# define ECSPI_CONFIGREG_CH0SCLKLOW (1 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 0 SCLK low when inactive */
# define ECSPI_CONFIGREG_CH1SCLKLOW (2 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 1 SCLK low when inactive */
# define ECSPI_CONFIGREG_CH2SCLKLOW (4 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 2 SCLK low when inactive */
# define ECSPI_CONFIGREG_CH3SCLKLOW (8 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 3 SCLK low when inactive */
#define ECSPI_CONFIGREG_HTLEN_SHIFT (24) /* Bits 24-28: HT Length */
#define ECSPI_CONFIGREG_HTLEN_MASK (15 << ECSPI_CONFIGREG_HTLEN_SHIFT)
# define ECSPI_CONFIGREG_HTLEN(n) ((uint32_t)(n) << ECSPI_CONFIGREG_HTLEN_SHIFT)
/* Bits 29-31: Reserved */
/* Common Interrupt Control Register and Status Register */
#define ECSPI_INT_TE (1 << 0) /* Bit 0: TXFIFO Empty Interrupt */
#define ECSPI_INT_TDR (1 << 1) /* Bit 1: TXFIFO Data Request Interrupt */
#define ECSPI_INT_TF (1 << 2) /* Bit 2: TXFIFO Full Interrupt */
#define ECSPI_INT_RR (1 << 3) /* Bit 3: RXFIFO Data Ready Interrupt */
#define ECSPI_INT_RDR (1 << 4) /* Bit 4: RXFIFO Data Request Interrupt enable */
#define ECSPI_INT_RF (1 << 5) /* Bit 5: RXFIFO Full Interrupt */
#define ECSPI_INT_RO (1 << 6) /* Bit 6: RXFIFO Overflow Interrupt */
#define ECSPI_INT_TC (1 << 7) /* Bit 7: Transfer Completed Interrupt enable */
/* Bits 8-31: Reserved */
#define ECSPI_INT_ALL 0x000000ff
/* ECSPI DMA Control Register */
#define ECSPI_DMAREG_TXTHRES_SHIFT (0) /* Bits 0-5: TX Threshold */
#define ECSPI_DMAREG_TXTHRES_MASK (0x3f << ECSPI_DMAREG_TXTHRES_SHIFT)
# define ECSPI_DMAREG_TXTHRES(n) ((uint32_t)(n) << ECSPI_DMAREG_TXTHRES_SHIFT)
/* Bit 6: Reserved */
#define ECSPI_DMAREG_TEDEN (1 << 7) /* Bit 7: TXFIFO Empty DMA request enable */
/* Bits 8-15: Reserved */
#define ECSPI_DMAREG_RXTHRES_SHIFT (16) /* Bits 16-21: RX Threshold */
#define ECSPI_DMAREG_RXTHRES_MASK (0x3f << ECSPI_DMAREG_RXTHRES_SHIFT)
# define ECSPI_DMAREG_RXTHRES(n) ((uint32_t)(n) << ECSPI_DMAREG_RXTHRES_SHIFT)
/* Bit 22: Reserved */
#define ECSPI_DMAREG_RXDEN (1 << 23) /* Bit 23: RXFIFO DMA request enable */
#define ECSPI_DMAREG_RXLEN_SHIFT (24) /* Bits 24-29: RX DMA length */
#define ECSPI_DMAREG_RXLEN_MASK (0x3f << ECSPI_DMAREG_RXLEN_SHIFT)
# define ECSPI_DMAREG_RXLEN(n) ((uint32_t)(n) << ECSPI_DMAREG_RXLEN_SHIFT)
/* Bit 30: Reserved */
#define ECSPI_DMAREG_RXTDEN (1 << 31) /* Bit 31: RXFIFO Tail DMA request enable */
/* ECSPI Sample Period Control Register */
#define ECSPI_PERIODREG_PERIOD_SHIFT (0) /* Bits 0-14: Sample Period Control */
#define ECSPI_PERIODREG_PERIOD_MASK (0x7fff << ECSPI_PERIODREG_PERIOD_SHIFT)
# define ECSPI_PERIODREG_PERIOD(n) ((uint32_t)(n) << ECSPI_PERIODREG_PERIOD_SHIFT)
#define ECSPI_PERIODREG_CSRC (1 << 15) /* Bit 15: Clock source control */
#define ECSPI_PERIODREG_CSDCTL_SHIFT (16) /* Bits 16-21: Chip Select delay control */
#define ECSPI_PERIODREG_CSDCTL_MASK (0x3f << ECSPI_PERIODREG_CSDCTL_SHIFT)
# define ECSPI_PERIODREG_CSDCTL(n) ((uint32_t)(n) << ECSPI_PERIODREG_CSDCTL_SHIFT)
/* Bits 22-31: Reserved */
/* Test Control Register */
#define ECSPI_TESTREG_TXCNT_SHIFT (0) /* Bits 0-6: TXFIFO Counter */
#define ECSPI_TESTREG_TXCNT_MASK (0x7f << ECSPI_TESTREG_TXCNT_SHIFT)
# define ECSPI_TESTREG_TXCNT(n) ((uint32_t)(n) << ECSPI_TESTREG_TXCNT_SHIFT)
/* Bit 7: Reserved */
#define ECSPI_TESTREG_RXCNT_SHIFT (8) /* Bits 8-14: RXFIFO Counter */
#define ECSPI_TESTREG_RXCNT_MASK (0x7f << ECSPI_TESTREG_RXCNT_SHIFT)
# define ECSPI_TESTREG_RXCNT(n) ((uint32_t)(n) << ECSPI_TESTREG_RXCNT_SHIFT)
/* Bits 15-30: Reserved */
#define ECSPI_TESTREG_LBC (1 << 31) /* Bit 31: Loop Back Control */
/* Message Data Register (32-bit message data) */
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_IMX6_CHIP_ECSPI_H */

8
arch/arm/src/imx6/chip/imx_uart.h
View file

@ -195,10 +195,10 @@
#define UART_UCR1_RRDYEN (1 << 9) /* Bit 9: Receiver ready interrupt enable */
#define UART_UCR1_ICD_SHIFT 10 /* Bit 10-11: Idle condition detect */
#define UART_UCR1_ICD_MASK (3 << UART_UCR1_ICD_SHIFT)
# define UART_UCR1_ICD_4FRMS (0 << UART_UCR1_ICD_SHIFT) /* Idle for more than 4 frames */
# define UART_UCR1_ICD_8FRMS (1 << UART_UCR1_ICD_SHIFT) /* Idle for more than 8 frames */
# define UART_UCR1_ICD_16FRMS (2 << UART_UCR1_ICD_SHIFT) /* Idle for more than 16 frames */
# define UART_UCR1_ICD_32FRMS (3 << UART_UCR1_ICD_SHIFT) /* Idle for more than 32 frames */
# define UART_UCR1_ICD_4FRMS (0 << UART_UCR1_ICD_SHIFT) /* Idle for more than 4 frames */
# define UART_UCR1_ICD_8FRMS (1 << UART_UCR1_ICD_SHIFT) /* Idle for more than 8 frames */
# define UART_UCR1_ICD_16FRMS (2 << UART_UCR1_ICD_SHIFT) /* Idle for more than 16 frames */
# define UART_UCR1_ICD_32FRMS (3 << UART_UCR1_ICD_SHIFT) /* Idle for more than 32 frames */
#define UART_UCR1_IDEN (1 << 12) /* Bit 12: Idle condition detected interrupt enable */
#define UART_UCR1_TRDYEN (1 << 13) /* Bit 13: Transmitter ready interrupt enable */
#define UART_UCR1_ADBR (1 << 14) /* Bit 14: Automatic detection of baud rate */

36
arch/arm/src/imx6/imx_cpuboot.c
View file

@ -51,7 +51,9 @@
#include "chip/imx_src.h"
#include "sctlr.h"
#include "smp.h"
#include "fpu.h"
#include "gic.h"
#include "cp15_cacheops.h"
#ifdef CONFIG_SMP
@ -68,44 +70,44 @@ typedef CODE void (*cpu_start_t)(void);
#if 0 /* Not used */
static const uint32_t g_cpu_reset[CONFIG_SMP_NCPUS] =
{
0,
SRC_SCR_CORE0_RST
#if CONFIG_SMP_NCPUS > 1
SRC_SCR_CORE1_RST,
, SRC_SCR_CORE1_RST
#endif
#if CONFIG_SMP_NCPUS > 2
SRC_SCR_CORE2_RST,
, SRC_SCR_CORE2_RST
#endif
#if CONFIG_SMP_NCPUS > 3
SRC_SCR_CORE3_RST
, SRC_SCR_CORE3_RST
#endif
};
#endif
static const uint32_t g_cpu_ctrl[CONFIG_SMP_NCPUS] =
{
0,
0
#if CONFIG_SMP_NCPUS > 1
SRC_SCR_CORE1_ENABLE,
, SRC_SCR_CORE1_ENABLE
#endif
#if CONFIG_SMP_NCPUS > 2
SRC_SCR_CORE2_ENABLE,
, SRC_SCR_CORE2_ENABLE
#endif
#if CONFIG_SMP_NCPUS > 3
SRC_SCR_CORE3_ENABLE
, SRC_SCR_CORE3_ENABLE
#endif
};
static const uintptr_t g_cpu_gpr[CONFIG_SMP_NCPUS] =
{
0,
IMX_SRC_GPR1
#if CONFIG_SMP_NCPUS > 1
IMX_SRC_GPR3,
, IMX_SRC_GPR3
#endif
#if CONFIG_SMP_NCPUS > 2
IMX_SRC_GPR5,
, IMX_SRC_GPR5
#endif
#if CONFIG_SMP_NCPUS > 3
IMX_SRC_GPR7
, IMX_SRC_GPR7
#endif
};
@ -258,6 +260,12 @@ void imx_cpu_enable(void)
void arm_cpu_boot(int cpu)
{
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
#endif
/* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */
arm_gic_initialize();
@ -289,6 +297,10 @@ void arm_cpu_boot(int cpu)
(void)up_irq_enable();
#endif
/* Invalidate CPUn L1 so that is will be reloaded from coherent L2. */
cp15_invalidate_dcache_all();
/* The next thing that we expect to happen is for logic running on CPU0
* to call up_cpu_start() which generate an SGI and a context switch to
* the configured NuttX IDLE task.

166
arch/arm/src/imx6/imx_ecspi.h Normal file
View file

@ -0,0 +1,166 @@
/************************************************************************************
* arch/arm/src/imx6/imx_ecspi.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX6_ECSPI_H
#define __ARCH_ARM_IMX6_ECSPI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <nuttx/spi/spi.h>
#include "chip/imx_ecspi.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif /* __cplusplus */
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
struct spi_dev_s; /* Forward reference */
enum spi_dev_e; /* Forward reference */
/************************************************************************************
* Name: imx_spibus_initialize
*
* Description:
* Initialize common parts the selected SPI port. Initialization of
* chip select GPIOs must have been performed by board specific logic
* prior to calling this function. Specifically: GPIOs should have
* been configured for output, and all chip selects disabled.
*
* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However,
* If multiple devices on on the bus, then multiple chip selects will be
* required. Theregore, all GPIO chip management is deferred to board-
* specific logic.
*
* Input Parameter:
* Port number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structre reference on succcess; a NULL on failure
*
************************************************************************************/
FAR struct spi_dev_s *imx_spibus_initialize(int port);
/************************************************************************************
* The external functions, imx_spiselect, imx_spistatus, and imx_cmddaa must be
* provided by board-specific logic. These are implementations of the select and
* status methods of the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including imx_spibus_initialize()) are
* provided by common logic. To use this common SPI logic on your board:
*
* 1. Provide imx_spiselect() and imx_spistatus() functions in your board-specific
* logic. This function will perform chip selection and status operations using
* GPIOs in the way your board is configured.
* 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide the
* imx_spicmddata() function in your board-specific logic. This function will
* perform cmd/data selection operations using GPIOs in the way your board is
* configured.
* 3. Add a call to imx_spibus_initialize() in your low level initialization logic
* 4. The handle returned by imx_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(),
* for example, will bind the SPI driver to the SPI MMC/SD driver).
*
************************************************************************************/
#ifdef CONFIG_IMX6_ECSPI1
void imx_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t imx_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif
#ifdef CONFIG_IMX6_ECSPI2
void imx_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t imx_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif
#ifdef CONFIG_IMX6_ECSPI3
void imx_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t imx_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif
#ifdef CONFIG_IMX6_ECSPI4
void imx_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t imx_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif
#ifdef CONFIG_IMX6_ECSPI5
void imx_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t imx_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_IMX6_ECSPI_H */

39
arch/arm/src/imx6/imx_serial.c
View file

@ -50,6 +50,7 @@
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/init.h>
#include <nuttx/serial/serial.h>
#include <arch/serial.h>
@ -57,6 +58,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "gic.h"
#include "chip/imx_uart.h"
#include "imx_config.h"
#include "imx_lowputc.h"
@ -258,6 +260,12 @@ static bool imx_txempty(struct uart_dev_s *dev);
* Private Data
****************************************************************************/
/* Used to assure mutually exclusive access up_putc() */
static sem_t g_putc_lock = SEM_INITIALIZER(1);
/* Serial driver UART operations */
static const struct uart_ops_s g_uart_ops =
{
.setup = imx_setup,
@ -613,6 +621,10 @@ static int imx_attach(struct uart_dev_s *dev)
ret = irq_attach(priv->irq, priv->handler);
if (ret == OK)
{
/* Configure as a (high) level interrupt */
(void)arm_gic_irq_trigger(priv->irq, false);
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the UART
*/
@ -1001,6 +1013,27 @@ int up_putc(int ch)
{
struct imx_uart_s *priv = (struct imx_uart_s *)CONSOLE_DEV.priv;
uint32_t ier;
bool locked;
int ret;
/* Only one thread may enter up_putc at a time. */
locked = false;
if (!up_interrupt_context() && g_os_initstate >= OSINIT_HARDWARE)
{
ret = sem_wait(&g_putc_lock);
if (ret < 0)
{
return ERROR;
}
locked = true;
}
/* Disable UART interrupts and wait until the hardware is ready to send
* a byte.
*/
imx_disableuartint(priv, &ier);
imx_waittxready(priv);
@ -1018,6 +1051,12 @@ int up_putc(int ch)
imx_serialout(priv, UART_TXD_OFFSET, (uint32_t)ch);
imx_waittxready(priv);
imx_restoreuartint(priv, ier);
if (locked)
{
sem_post(&g_putc_lock);
}
return ch;
}

32
arch/arm/src/imx6/imx_timerisr.c
View file

@ -46,6 +46,7 @@
#include <arch/irq.h>
#include "up_arch.h"
#include "gic.h"
#include "chip/imx_ccm.h"
#include "chip/imx_gpt.h"
@ -76,10 +77,25 @@
* We should be able to use a prescaler of 1.
*/
#define GPT_PR_VALUE 1
#define GPT_OCR3_VALUE ((GPT_CLOCK + ((1*CLK_TCK) >> 1)) / (1*CLK_TCK))
#define GPT_OCR2_VALUE ((GPT_CLOCK + ((2*CLK_TCK) >> 1)) / (2*CLK_TCK))
#define GPT_OCR1_VALUE ((GPT_CLOCK + ((3*CLK_TCK) >> 1)) / (3*CLK_TCK))
#define GPT_PR_VALUE 1
/* Timer counter comparison settings:
*
* - OCR3 will interrupt at CLK_TCK ticks/second after the timer counter
* has been reset.
* - OCR2 will interrupt at 2*CLK_TCK ticks/second after the timer counter
* has been reset.
* - OCR2 will interrupt at 3*CLK_TCK ticks/second after the timer counter
* has been reset and then will reset the timer, starting the 3 interrupt
* sequence again.
*
* Using three comparisons virtually eliminates the possibility of timer
* interrupt overrun.
*/
#define GPT_OCR3_VALUE ((1 * GPT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)
#define GPT_OCR2_VALUE ((2 * GPT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)
#define GPT_OCR1_VALUE ((3 * GPT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)
/****************************************************************************
* Private Functions
@ -164,7 +180,7 @@ void up_timer_initialize(void)
/* Disable GPT by setting EN=0 in GPT_CR register */
cr = getreg32(IMX_GPT_CR);
cr = getreg32(IMX_GPT_CR);
cr &= ~GPT_CR_EN;
putreg32(cr, IMX_GPT_CR);
@ -220,7 +236,7 @@ void up_timer_initialize(void)
*/
cr &= ~GPT_CR_FFR;
putreg32(cr | GPT_CR_SWR, IMX_GPT_CR);
putreg32(cr, IMX_GPT_CR);
/* Set ENMOD=1 in GPT_CR register, to bring GPT counter to 0x00000000. If
* the ENMOD bit is 1, then the Main Counter and Prescaler Counter values
@ -235,6 +251,10 @@ void up_timer_initialize(void)
cr |= GPT_CR_EN;
putreg32(cr, IMX_GPT_CR);
/* Configure as a (rising) edge-triggered interrupt */
(void)arm_gic_irq_trigger(IMX_IRQ_GPT, true);
/* Attach the timer interrupt vector */
(void)irq_attach(IMX_IRQ_GPT, (xcpt_t)up_timerisr);

12
arch/arm/src/kinetis/Kconfig
View file

@ -131,42 +131,42 @@ config KINETIS_FLEXBUS
config KINETIS_UART0
bool "UART0"
default n
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
---help---
Support UART0
config KINETIS_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
---help---
Support UART1
config KINETIS_UART2
bool "UART2"
default n
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
---help---
Support UART2
config KINETIS_UART3
bool "UART3"
default n
select ARCH_HAVE_UART3
select UART3_SERIALDRIVER
---help---
Support UART3
config KINETIS_UART4
bool "UART4"
default n
select ARCH_HAVE_UART4
select UART4_SERIALDRIVER
---help---
Support UART4
config KINETIS_UART5
bool "UART5"
default n
select ARCH_HAVE_UART5
select UART5_SERIALDRIVER
---help---
Support UART5

6
arch/arm/src/kl/Kconfig
View file

@ -47,21 +47,21 @@ config KL_FLEXBUS
config KL_UART0
bool "UART0"
default n
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
---help---
Support UART0
config KL_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
---help---
Support UART1
config KL_UART2
bool "UART2"
default n
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
---help---
Support UART2

2
arch/arm/src/lpc11xx/Kconfig
View file

@ -55,7 +55,7 @@ config LPC11_PLL
config LPC11_UART0
bool "UART0"
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
default y
config LPC11_CAN0

12
arch/arm/src/lpc17xx/Kconfig
View file

@ -172,36 +172,36 @@ config LPC17_SDCARD
config LPC17_UART0
bool "UART0"
default n
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config LPC17_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config LPC17_UART2
bool "UART2"
default n
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config LPC17_UART3
bool "UART3"
default n
select ARCH_HAVE_UART3
select UART3_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config LPC17_UART4
bool "UART4"
default n
select ARCH_HAVE_UART4
select UART4_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config LPC17_CAN1
bool "CAN1"
select ARCH_HAVE_UART4
select UART4_SERIALDRIVER
default n
config LPC17_CAN2

70
arch/arm/src/lpc17xx/lpc17_adc.c
View file

@ -2,8 +2,9 @@
* arch/arm/src/lpc17xx/lpc17_adc.c
*
* Copyright (C) 2011 Li Zhuoyi. All rights reserved.
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Li Zhuoyi <lzyy.cn@gmail.com>
* History: 0.1 2011-08-05 initial version
* Gregory Nutt <gnutt@nuttx.org>
*
* This file is a part of NuttX:
*
@ -50,6 +51,7 @@
#include <stdbool.h>
#include <semaphore.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
@ -87,6 +89,7 @@
struct up_dev_s
{
FAR const struct adc_callback_s *cb;
uint8_t mask;
uint32_t sps;
int irq;
@ -98,8 +101,12 @@ struct up_dev_s
* Private Function Prototypes
****************************************************************************/
static void adc_receive(FAR struct up_dev_s *priv, uint8_t ch, int32_t data);
/* ADC methods */
static int adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback);
static void adc_reset(FAR struct adc_dev_s *dev);
static int adc_setup(FAR struct adc_dev_s *dev);
static void adc_shutdown(FAR struct adc_dev_s *dev);
@ -113,6 +120,7 @@ static int adc_interrupt(int irq, void *context);
static const struct adc_ops_s g_adcops =
{
.ao_bind = adc_bind,
.ao_reset = adc_reset,
.ao_setup = adc_setup,
.ao_shutdown = adc_shutdown,
@ -137,6 +145,46 @@ static struct adc_dev_s g_adcdev =
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: adc_receive
*
* Description:
* Provide received ADC dat to the upper-half driver.
*
****************************************************************************/
static void adc_receive(FAR struct up_dev_s *priv, uint8_t ch, int32_t data)
{
/* Verify that the upper-half driver has bound its callback functions. */
if (priv->cb != NULL)
{
/* Perform the data received callback */
DEBUGASSERT(priv->cb->au_receive != NULL);
priv->cb->au_receive(&g_adcdev, ch, data);
}
}
/****************************************************************************
* Name: adc_bind
*
* Description:
* Bind the upper-half driver callbacks to the lower-half implementation. This
* must be called early in order to receive ADC event notifications.
*
****************************************************************************/
static int adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback)
{
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
DEBUGASSERT(priv != NULL);
priv->cb = callback;
return OK;
}
/****************************************************************************
* Name: adc_reset
*
@ -384,7 +432,7 @@ static int adc_interrupt(int irq, void *context)
{
value = priv->buf[ch] / priv->count[ch];
value <<= 15;
adc_receive(&g_adcdev, ch, value);
adc_receive(priv, ch, value);
priv->buf[ch] = 0;
priv->count[ch] = 0;
}
@ -409,7 +457,7 @@ static int adc_interrupt(int irq, void *context)
{
value = priv->buf[ch] / priv->count[ch];
value <<= 15;
adc_receive(&g_adcdev, ch, value);
adc_receive(priv, ch, value);
priv->buf[ch] = 0;
priv->count[ch] = 0;
}
@ -446,7 +494,7 @@ static int adc_interrupt(int irq, void *context)
#else /* CONFIG_ADC_WORKER_THREAD */
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 0, (regVal >> 4) & 0xFFF);
adc_receive(priv, 0, (regVal >> 4) & 0xFFF);
}
#endif /* CONFIG_ADC_WORKER_THREAD */
@ -473,7 +521,7 @@ static int adc_interrupt(int irq, void *context)
#else /* CONFIG_ADC_WORKER_THREAD */
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 1, (regVal >> 4) & 0xFFF);
adc_receive(priv, 1, (regVal >> 4) & 0xFFF);
}
#endif /* CONFIG_ADC_WORKER_THREAD */
@ -500,7 +548,7 @@ static int adc_interrupt(int irq, void *context)
#else /* CONFIG_ADC_WORKER_THREAD */
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 2, (regVal >> 4) & 0xFFF);
adc_receive(priv, 2, (regVal >> 4) & 0xFFF);
}
#endif /* CONFIG_ADC_WORKER_THREAD */
@ -512,7 +560,7 @@ static int adc_interrupt(int irq, void *context)
regVal = getreg32(LPC17_ADC_DR3);
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 3, (regVal >> 4) & 0xFFF);
adc_receive(priv, 3, (regVal >> 4) & 0xFFF);
}
}
@ -521,7 +569,7 @@ static int adc_interrupt(int irq, void *context)
regVal = getreg32(LPC17_ADC_DR4);
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 4, (regVal >> 4) & 0xFFF);
adc_receive(priv, 4, (regVal >> 4) & 0xFFF);
}
}
@ -530,7 +578,7 @@ static int adc_interrupt(int irq, void *context)
regVal = getreg32(LPC17_ADC_DR5);
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 5, (regVal >> 4) & 0xFFF);
adc_receive(priv, 5, (regVal >> 4) & 0xFFF);
}
}
@ -539,7 +587,7 @@ static int adc_interrupt(int irq, void *context)
regVal = getreg32(LPC17_ADC_DR6);
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 6, (regVal >> 4) & 0xFFF);
adc_receive(priv, 6, (regVal >> 4) & 0xFFF);
}
}
@ -548,7 +596,7 @@ static int adc_interrupt(int irq, void *context)
regVal = getreg32(LPC17_ADC_DR7);
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 7, (regVal >> 4) & 0xFFF);
adc_receive(priv, 7, (regVal >> 4) & 0xFFF);
}
}

4
arch/arm/src/lpc214x/Kconfig
View file

@ -92,12 +92,12 @@ menu "LPC214x Peripheral Support"
config LPC214X_UART0
bool
default y
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
config LPC214X_UART1
bool
default y
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
config LPC214X_USBDEV
bool "USB Device"

8
arch/arm/src/lpc2378/Kconfig
View file

@ -118,22 +118,22 @@ menu "LPC2378 Peripheral Support"
config LPC2378_UART0
bool "UART0"
default n
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
config LPC2378_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
config LPC2378_UART2
bool "UART2"
default n
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
config LPC2378_UART3
bool "UART3"
default n
select ARCH_HAVE_UART3
select UART3_SERIALDRIVER
config LPC2378_USBDEV
bool "USB Device"

2
arch/arm/src/lpc31xx/Kconfig
View file

@ -51,7 +51,7 @@ menu "LPC31xx Peripheral Support"
config LPC31_UART
bool "UART"
default n
select ARCH_HAVE_UART
select UART_SERIALDRIVER
config LPC31_SPI
bool "SPI"

13
arch/arm/src/lpc43xx/Kconfig
View file

@ -37,6 +37,9 @@ config ARCH_CHIP_LPC4330FET256
config ARCH_CHIP_LPC4337JBD144
bool "LPC4337JBD144"
config ARCH_CHIP_LPC4337JET100
bool "LPC4337JET100"
config ARCH_CHIP_LPC4350FBD208
bool "LPC4350FBD208"
@ -81,7 +84,7 @@ config ARCH_FAMILY_LPC4320
config ARCH_FAMILY_LPC4330
bool
default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256
default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256 || ARCH_CHIP_LPC4337JET100
select ARCH_HAVE_TICKLESS
config ARCH_FAMILY_LPC4337
@ -271,25 +274,25 @@ config LPC43_TMR3
config LPC43_USART0
bool "USART0"
default n
select ARCH_HAVE_USART0
select USART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config LPC43_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config LPC43_USART2
bool "USART2"
default n
select ARCH_HAVE_USART2
select USART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config LPC43_USART3
bool "USART3"
default n
select ARCH_HAVE_USART3
select USART3_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config LPC43_USBOTG

4
arch/arm/src/lpc43xx/Make.defs
View file

@ -182,6 +182,10 @@ ifeq ($(CONFIG_LPC43_USBOTG),y)
CHIP_CSRCS += lpc43_ehci.c
endif
ifeq ($(CONFIG_CRYPTO_AES),y)
CHIP_CSRCS += lpc43_aes.c
endif
ifeq ($(CONFIG_LPC43_USB0),y)
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += lpc43_usb0dev.c

4
arch/arm/src/lpc43xx/chip.h
View file

@ -141,6 +141,10 @@
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc435357_memorymap.h"
# include "chip/lpc4357fet256_pinconfig.h"
#elif defined(CONFIG_ARCH_CHIP_LPC4337JET100)
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc435357_memorymap.h"
# include "chip/lpc4337jet100_pinconfig.h"
#else
# error "Unsupported LPC43xx chip"
#endif

982
arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h Normal file
View file

@ -0,0 +1,982 @@
/****************************************************************************************************
* arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4337JET100_PINCONF_H
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4337JET100_PINCONF_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* NOTES:
*
* 1. These settings were taken from the LPC43_10_20_30_50 data sheet and may not be applicable to
* any other family members.
*
* 2. Settings taken from the data sheet include only function, pin set, and pin number. Additional
* settings must be verified before using these pin configurations (like pull-ups, open-drain,
* drive strength, input buffering, etc.).
*
* 3. Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers,
* however, will use the pin selection without the numeric suffix. Additional definitions are
* required in the board.h file to select between the alternative pins. For example, if CAN1_RD
* connects via Pins1[18], then the following definition should appear in the board.h header file
* for that board:
*
* 4. For ADC pins (PINCONF_ADCNpM), the pin must first be configured configured as a GPIO input.
* Then SCU's ADC function select register can be used to select the ADC.
*
* #define PINCONF_CAN1_RD PINCONF_CAN1_RD_1
*
* The driver will then automatically configre Pins1[18] as the CAN1 RD pin.
*/
#define PINCONF_ADC0p0 (PINCONF_FUNC0|PINCONF_PINS4|PINCONF_PIN_3)
#define PINCONF_ADC0p1 (PINCONF_FUNC0|PINCONF_PINS4|PINCONF_PIN_1)
#define PINCONF_ADC0p2 (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_8)
#define PINCONF_ADC0p3 (PINCONF_FUNC0|PINCONF_PINS7|PINCONF_PIN_5)
#define PINCONF_ADC0p4 (PINCONF_FUNC0|PINCONF_PINS7|PINCONF_PIN_4)
#define PINCONF_ADC0p5 (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_10)
#define PINCONF_ADC0p6 (PINCONF_FUNC0|PINCONF_PINSB|PINCONF_PIN_6)
#define PINCONF_ADC1p0 (PINCONF_FUNC4|PINCONF_PINSC|PINCONF_PIN_3)
#define PINCONF_ADC1p1 (PINCONF_FUNC0|PINCONF_PINSC|PINCONF_PIN_0)
#define PINCONF_ADC1p2 (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_9)
#define PINCONF_ADC1p3 (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_6)
#define PINCONF_ADC1p4 (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_5)
#define PINCONF_ADC1p5 (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_11)
#define PINCONF_ADC1p6 (PINCONF_FUNC0|PINCONF_PINS7|PINCONF_PIN_7)
#define PINCONF_ADC1p7 (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_7)
#define PINCONF_ADCTRIG0 (PINCONF_FUNC0|PINCONF_PINSE|PINCONF_PIN_2)
#define PINCONF_ADCTRIG1_1 (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_3)
#define PINCONF_ADCTRIG1_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_5)
#define PINCONF_CAN0_RD_1 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_2)
#define PINCONF_CAN0_RD_2 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_1)
#define PINCONF_CAN0_TD_1 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_3)
#define PINCONF_CAN0_TD_2 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_2)
#define PINCONF_CAN1_RD_1 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_18)
#define PINCONF_CAN1_RD_2 (PINCONF_FUNC5|PINCONF_PINSE|PINCONF_PIN_1)
#define PINCONF_CAN1_RD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_9)
#define PINCONF_CAN1_TD_1 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_17)
#define PINCONF_CAN1_TD_2 (PINCONF_FUNC5|PINCONF_PINSE|PINCONF_PIN_0)
#define PINCONF_CAN1_TD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_8)
#define PINCONF_CGU_OUT0 (PINCONF_FUNC6|PINCONF_PINS8|PINCONF_PIN_8)
#define PINCONF_CGU_OUT1_1 (PINCONF_FUNC4|PINCONF_PINS3|PINCONF_PIN_3)
#define PINCONF_CGU_OUT1_2 (PINCONF_FUNC6|PINCONF_PINSA|PINCONF_PIN_0)
#define PINCONF_CLKOUT (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_19)
#define PINCONF_CTIN0_1 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_13)
#define PINCONF_CTIN0_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_4)
#define PINCONF_CTIN1_1 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_10)
#define PINCONF_CTIN1_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_3)
#define PINCONF_CTIN2_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_5)
#define PINCONF_CTIN2_2 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_10)
#define PINCONF_CTIN2_3 (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_8)
#define PINCONF_CTIN3_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_0)
#define PINCONF_CTIN3_2 (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_3)
#define PINCONF_CTIN3_3 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_10)
#define PINCONF_CTIN4_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_13)
#define PINCONF_CTIN4_2 (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_2)
#define PINCONF_CTIN4_3 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_9)
#define PINCONF_CTIN5_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_6)
#define PINCONF_CTIN5_2 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_8)
#define PINCONF_CTIN5_3 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_7)
#define PINCONF_CTIN5_4 (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_4)
#define PINCONF_CTIN6_1 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_9)
#define PINCONF_CTIN6_2 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_4)
#define PINCONF_CTIN6_3 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_8)
#define PINCONF_CTIN6_4 (PINCONF_FUNC5|PINCONF_PINS2|PINCONF_PIN_2)
#define PINCONF_CTIN6_5 (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_6)
#define PINCONF_CTIN7_1 (PINCONF_FUNC5|PINCONF_PINS2|PINCONF_PIN_6)
#define PINCONF_CTIN7_2 (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_5)
#define PINCONF_CTOUT0_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_8)
#define PINCONF_CTOUT0_2 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_2)
#define PINCONF_CTOUT0_3 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_15)
#define PINCONF_CTOUT1_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_7)
#define PINCONF_CTOUT1_2 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_1)
#define PINCONF_CTOUT1_3 (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_9)
#define PINCONF_CTOUT2_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_10)
#define PINCONF_CTOUT2_2 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_4)
#define PINCONF_CTOUT2_3 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_6)
#define PINCONF_CTOUT3_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_9)
#define PINCONF_CTOUT3_2 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_3)
#define PINCONF_CTOUT3_3 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_5)
#define PINCONF_CTOUT4_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_12)
#define PINCONF_CTOUT4_2 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_6)
#define PINCONF_CTOUT4_3 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_8)
#define PINCONF_CTOUT5_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_11)
#define PINCONF_CTOUT5_2 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_5)
#define PINCONF_CTOUT5_3 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_7)
#define PINCONF_CTOUT6_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_2)
#define PINCONF_CTOUT6_2 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_5)
#define PINCONF_CTOUT6_3 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_3)
#define PINCONF_CTOUT6_4 (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_1)
#define PINCONF_CTOUT7_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_1)
#define PINCONF_CTOUT7_2 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_12)
#define PINCONF_CTOUT7_3 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_2)
#define PINCONF_CTOUT7_4 (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_2)
#define PINCONF_CTOUT8_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_3)
#define PINCONF_CTOUT8_2 (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_7)
#define PINCONF_CTOUT8_3 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_4)
#define PINCONF_CTOUT8_4 (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_3)
#define PINCONF_CTOUT8_5 (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_15)
#define PINCONF_CTOUT9_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_4)
#define PINCONF_CTOUT9_2 (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_4)
#define PINCONF_CTOUT9_3 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_5)
#define PINCONF_CTOUT10_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_5)
#define PINCONF_CTOUT10_2 (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_0)
#define PINCONF_CTOUT10_3 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_6)
#define PINCONF_CTOUT10_4 (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_12)
#define PINCONF_CTOUT11_1 (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_6)
#define PINCONF_CTOUT11_2 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_12)
#define PINCONF_CTOUT11_3 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_9)
#define PINCONF_CTOUT11_4 (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_14)
#define PINCONF_CTOUT12_1 (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_5)
#define PINCONF_CTOUT12_2 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_11)
#define PINCONF_CTOUT12_3 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_8)
#define PINCONF_CTOUT12_4 (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_16)
#define PINCONF_CTOUT13_1 (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_4)
#define PINCONF_CTOUT13_2 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_9)
#define PINCONF_CTOUT13_3 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_7)
#define PINCONF_CTOUT13_4 (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_13)
#define PINCONF_CTOUT14_1 (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_0)
#define PINCONF_CTOUT14_2 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_13)
#define PINCONF_CTOUT14_3 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_10)
#define PINCONF_CTOUT14_4 (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_11)
#define PINCONF_CTOUT15_1 (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_1)
#define PINCONF_CTOUT15_2 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_0)
#define PINCONF_CTOUT15_3 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_11)
#define PINCONF_EMC_A0 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_9)
#define PINCONF_EMC_A1 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_10)
#define PINCONF_EMC_A2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_11)
#define PINCONF_EMC_A3 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_12)
#define PINCONF_EMC_A4 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_13)
#define PINCONF_EMC_A5 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_0)
#define PINCONF_EMC_A6 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_1)
#define PINCONF_EMC_A7 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_2)
#define PINCONF_EMC_A8 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_8)
#define PINCONF_EMC_A9 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_7)
#define PINCONF_EMC_A10 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_6)
#define PINCONF_EMC_A11 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_2)
#define PINCONF_EMC_A12 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_1)
#define PINCONF_EMC_A13 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_0)
#define PINCONF_EMC_A14 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_8)
#define PINCONF_EMC_A15 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_7)
#define PINCONF_EMC_A16 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_16)
#define PINCONF_EMC_A17 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_15)
#define PINCONF_EMC_A18 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_0)
#define PINCONF_EMC_A19 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_1)
#define PINCONF_EMC_A20 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_2)
#define PINCONF_EMC_A21 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_3)
#define PINCONF_EMC_A22 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_4)
#define PINCONF_EMC_A23 (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_4)
#define PINCONF_EMC_BLS0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_4)
#define PINCONF_EMC_BLS1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_6)
#define PINCONF_EMC_BLS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_13)
#define PINCONF_EMC_BLS3 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_10)
#define PINCONF_EMC_CAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_4)
#define PINCONF_EMC_CKEOUT0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_11)
#define PINCONF_EMC_CKEOUT1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_2)
#define PINCONF_EMC_CKEOUT2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_1)
#define PINCONF_EMC_CKEOUT3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_15)
#define PINCONF_EMC_CS0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_5)
#define PINCONF_EMC_CS1 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_3)
#define PINCONF_EMC_CS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_12)
#define PINCONF_EMC_CS3 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_11)
#define PINCONF_EMC_D0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_7)
#define PINCONF_EMC_D1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_8)
#define PINCONF_EMC_D2 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_9)
#define PINCONF_EMC_D3 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_10)
#define PINCONF_EMC_D4 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_11)
#define PINCONF_EMC_D5 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_12)
#define PINCONF_EMC_D6 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_13)
#define PINCONF_EMC_D7 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_14)
#define PINCONF_EMC_D8 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_4)
#define PINCONF_EMC_D9 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_5)
#define PINCONF_EMC_D10 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_6)
#define PINCONF_EMC_D11 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_7)
#define PINCONF_EMC_D12 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_0)
#define PINCONF_EMC_D13 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_1)
#define PINCONF_EMC_D14 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_2)
#define PINCONF_EMC_D15 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_3)
#define PINCONF_EMC_D16 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_2)
#define PINCONF_EMC_D17 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_3)
#define PINCONF_EMC_D18 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_4)
#define PINCONF_EMC_D19 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_5)
#define PINCONF_EMC_D20 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_6)
#define PINCONF_EMC_D21 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_7)
#define PINCONF_EMC_D22 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_8)
#define PINCONF_EMC_D23 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_9)
#define PINCONF_EMC_D24 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_5)
#define PINCONF_EMC_D25 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_6)
#define PINCONF_EMC_D26 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_7)
#define PINCONF_EMC_D27 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_8)
#define PINCONF_EMC_D28 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_9)
#define PINCONF_EMC_D29 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_10)
#define PINCONF_EMC_D30 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_11)
#define PINCONF_EMC_D31 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_12)
#define PINCONF_EMC_DQMOUT0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_12)
#define PINCONF_EMC_DQMOUT1 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_10)
#define PINCONF_EMC_DQMOUT2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_0)
#define PINCONF_EMC_DQMOUT3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_13)
#define PINCONF_EMC_DYCS0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_9)
#define PINCONF_EMC_DYCS1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_1)
#define PINCONF_EMC_DYCS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_14)
#define PINCONF_EMC_DYCS3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_14)
#define PINCONF_EMC_OE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_3)
#define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_5)
#define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_6)
#define PINCONF_ENET_COL_1 (PINCONF_FUNC2|PINCONF_PINS0|PINCONF_PIN_1)
#define PINCONF_ENET_COL_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_6)
#define PINCONF_ENET_COL_3 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_1)
#define PINCONF_ENET_CRS_1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_16)
#define PINCONF_ENET_CRS_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_0)
#define PINCONF_ENET_MDC_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_1)
#define PINCONF_ENET_MDC_2 (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_7)
#define PINCONF_ENET_MDC_3 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_0)
#define PINCONF_ENET_MDIO (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_17|PINCONF_FLOAT|PINCONF_INBUFFER|PINCONF_GLITCH)
#define PINCONF_ENET_REF_CLK (PINCONF_FUNC0|PINCONF_PINS1|PINCONF_PIN_19|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_FLOAT)
#define PINCONF_ENET_RXD0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_15|PINCONF_FLOAT|PINCONF_INBUFFER|PINCONF_GLITCH)
#define PINCONF_ENET_RXD1 (PINCONF_FUNC2|PINCONF_PINS0|PINCONF_PIN_0|PINCONF_FLOAT|PINCONF_INBUFFER|PINCONF_GLITCH)
#define PINCONF_ENET_RXD2_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_6)
#define PINCONF_ENET_RXD2_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_3)
#define PINCONF_ENET_RXD3_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_7)
#define PINCONF_ENET_RXD3_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_2)
#define PINCONF_ENET_RX_CLK (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_0)
#define PINCONF_ENET_RX_DV_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_8)
#define PINCONF_ENET_RX_DV_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_16|PINCONF_FLOAT|PINCONF_INBUFFER|PINCONF_GLITCH)
#define PINCONF_ENET_RX_ER_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_9)
#define PINCONF_ENET_RX_ER_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_1)
#define PINCONF_ENET_TXD0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_18|PINCONF_FLOAT|PINCONF_GLITCH)
#define PINCONF_ENET_TXD1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_20|PINCONF_FLOAT|PINCONF_GLITCH)
#define PINCONF_ENET_TXD2_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_2)
#define PINCONF_ENET_TXD2_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_4)
#define PINCONF_ENET_TXD3_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_3)
#define PINCONF_ENET_TXD3_2 (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_5)
#define PINCONF_ENET_TXEN (PINCONF_FUNC6|PINCONF_PINS0|PINCONF_PIN_1|PINCONF_FLOAT|PINCONF_GLITCH)
#define PINCONF_ENET_TX_CLK (PINCONF_FUNC0|PINCONF_PINS1|PINCONF_PIN_19)
#define PINCONF_ENET_TX_EN (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_4)
#define PINCONF_ENET_TX_ER_1 (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_5)
#define PINCONF_ENET_TX_ER_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_14)
#define PINCONF_GPIO0p0 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_0)
#define PINCONF_GPIO0p1 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_1)
#define PINCONF_GPIO0p2 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_15)
#define PINCONF_GPIO0p3 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_16)
#define PINCONF_GPIO0p4 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_0)
#define PINCONF_GPIO0p5 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_6)
#define PINCONF_GPIO0p6 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_6)
#define PINCONF_GPIO0p7 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_7)
#define PINCONF_GPIO0p8 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_1)
#define PINCONF_GPIO0p9 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_2)
#define PINCONF_GPIO0p10 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_3)
#define PINCONF_GPIO0p11 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_4)
#define PINCONF_GPIO0p12 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_17)
#define PINCONF_GPIO0p13 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_18)
#define PINCONF_GPIO0p14 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_10)
#define PINCONF_GPIO0p15 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_20)
#define PINCONF_GPIO1p0 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_7)
#define PINCONF_GPIO1p1 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_8)
#define PINCONF_GPIO1p2 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_9)
#define PINCONF_GPIO1p3 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_10)
#define PINCONF_GPIO1p4 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_11)
#define PINCONF_GPIO1p5 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_12)
#define PINCONF_GPIO1p6 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_13)
#define PINCONF_GPIO1p7 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_14)
#define PINCONF_GPIO1p8 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_5)
#define PINCONF_GPIO1p9 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_6)
#define PINCONF_GPIO1p10 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_9)
#define PINCONF_GPIO1p11 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_11)
#define PINCONF_GPIO1p12 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_12)
#define PINCONF_GPIO1p13 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_13)
#define PINCONF_GPIO1p14 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_4)
#define PINCONF_GPIO1p15 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_5)
#define PINCONF_GPIO2p0 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_0)
#define PINCONF_GPIO2p1 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_1)
#define PINCONF_GPIO2p2 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_2)
#define PINCONF_GPIO2p3 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_3)
#define PINCONF_GPIO2p4 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_4)
#define PINCONF_GPIO2p5 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_5)
#define PINCONF_GPIO2p6 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_6)
#define PINCONF_GPIO2p7 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_7)
#define PINCONF_GPIO2p8 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_12)
#define PINCONF_GPIO2p9 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_0)
#define PINCONF_GPIO2p10 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_1)
#define PINCONF_GPIO2p11 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_2)
#define PINCONF_GPIO2p12 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_3)
#define PINCONF_GPIO2p13 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_4)
#define PINCONF_GPIO2p14 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_5)
#define PINCONF_GPIO2p15 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_6)
#define PINCONF_GPIO3p0 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_1)
#define PINCONF_GPIO3p1 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_2)
#define PINCONF_GPIO3p2 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_3)
#define PINCONF_GPIO3p3 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_4)
#define PINCONF_GPIO3p4 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_5)
#define PINCONF_GPIO3p5 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_9)
#define PINCONF_GPIO3p6 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_10)
#define PINCONF_GPIO3p7 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_11)
#define PINCONF_GPIO3p8 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_0)
#define PINCONF_GPIO3p9 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_1)
#define PINCONF_GPIO3p10 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_2)
#define PINCONF_GPIO3p11 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_3)
#define PINCONF_GPIO3p12 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_4)
#define PINCONF_GPIO3p13 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_5)
#define PINCONF_GPIO3p14 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_6)
#define PINCONF_GPIO3p15 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_7)
#define PINCONF_GPIO4p0 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_0)
#define PINCONF_GPIO4p1 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_1)
#define PINCONF_GPIO4p2 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_2)
#define PINCONF_GPIO4p3 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_3)
#define PINCONF_GPIO4p4 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_4)
#define PINCONF_GPIO4p5 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_5)
#define PINCONF_GPIO4p6 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_6)
#define PINCONF_GPIO4p7 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_7)
#define PINCONF_GPIO4p8 (PINCONF_FUNC0|PINCONF_PINSA|PINCONF_PIN_1)
#define PINCONF_GPIO4p9 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINSA|PINCONF_PIN_2)
#define PINCONF_GPIO4p10 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINSA|PINCONF_PIN_3)
#define PINCONF_GPIO4p11 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_6)
#define PINCONF_GPIO4p12 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_0)
#define PINCONF_GPIO4p13 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_1)
#define PINCONF_GPIO4p14 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_2)
#define PINCONF_GPIO4p15 (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_3)
#define PINCONF_GPIO5p0 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_0)
#define PINCONF_GPIO5p1 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_1)
#define PINCONF_GPIO5p2 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_2)
#define PINCONF_GPIO5p3 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_3)
#define PINCONF_GPIO5p4 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_4)
#define PINCONF_GPIO5p5 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_5)
#define PINCONF_GPIO5p6 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_6)
#define PINCONF_GPIO5p7 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_8)
#define PINCONF_GPIO5p8 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_1)
#define PINCONF_GPIO5p9 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_2)
#define PINCONF_GPIO5p10 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_7)
#define PINCONF_GPIO5p11 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_8)
#define PINCONF_GPIO5p12 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_8)
#define PINCONF_GPIO5p13 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_9)
#define PINCONF_GPIO5p14 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_10)
#define PINCONF_GPIO5p15 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_7)
#define PINCONF_GPIO5p16 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_8)
#define PINCONF_GPIO5p17 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_4)
#define PINCONF_GPIO5p18 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_5)
#define PINCONF_GPIO5p19 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSA|PINCONF_PIN_4)
#define PINCONF_GPIO5p20 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_0)
#define PINCONF_GPIO5p21 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_1)
#define PINCONF_GPIO5p22 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_2)
#define PINCONF_GPIO5p23 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_3)
#define PINCONF_GPIO5p24 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_4)
#define PINCONF_GPIO5p25 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_5)
#define PINCONF_GPIO5p26 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_6)
#define PINCONF_GPIO6p0 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_1)
#define PINCONF_GPIO6p1 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_2)
#define PINCONF_GPIO6p2 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_3)
#define PINCONF_GPIO6p3 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_4)
#define PINCONF_GPIO6p4 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_5)
#define PINCONF_GPIO6p5 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_6)
#define PINCONF_GPIO6p6 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_7)
#define PINCONF_GPIO6p7 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_8)
#define PINCONF_GPIO6p8 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_9)
#define PINCONF_GPIO6p9 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_10)
#define PINCONF_GPIO6p10 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_11)
#define PINCONF_GPIO6p11 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_12)
#define PINCONF_GPIO6p12 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_13)
#define PINCONF_GPIO6p13 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_14)
#define PINCONF_GPIO6p14 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_0)
#define PINCONF_GPIO6p15 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_1)
#define PINCONF_GPIO6p16 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_2)
#define PINCONF_GPIO6p17 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_3)
#define PINCONF_GPIO6p18 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_4)
#define PINCONF_GPIO6p19 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_5)
#define PINCONF_GPIO6p20 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_6)
#define PINCONF_GPIO6p21 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_7)
#define PINCONF_GPIO6p22 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_8)
#define PINCONF_GPIO6p23 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_9)
#define PINCONF_GPIO6p24 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_10)
#define PINCONF_GPIO6p25 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_11)
#define PINCONF_GPIO6p26 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_12)
#define PINCONF_GPIO6p27 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_13)
#define PINCONF_GPIO6p28 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_14)
#define PINCONF_GPIO6p29 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_15)
#define PINCONF_GPIO6p30 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_16)
#define PINCONF_GPIO7p0 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_0)
#define PINCONF_GPIO7p1 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_1)
#define PINCONF_GPIO7p2 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_2)
#define PINCONF_GPIO7p3 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_3)
#define PINCONF_GPIO7p4 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_4)
#define PINCONF_GPIO7p5 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_5)
#define PINCONF_GPIO7p6 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_6)
#define PINCONF_GPIO7p7 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_7)
#define PINCONF_GPIO7p8 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_8)
#define PINCONF_GPIO7p9 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_9)
#define PINCONF_GPIO7p10 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_10)
#define PINCONF_GPIO7p11 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_11)
#define PINCONF_GPIO7p12 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_12)
#define PINCONF_GPIO7p13 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_13)
#define PINCONF_GPIO7p14 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_14)
#define PINCONF_GPIO7p15 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_15)
#define PINCONF_GPIO7p16 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_1)
#define PINCONF_GPIO7p17 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_2)
#define PINCONF_GPIO7p18 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_3)
#define PINCONF_GPIO7p19 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_5)
#define PINCONF_GPIO7p20 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_6)
#define PINCONF_GPIO7p21 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_7)
#define PINCONF_GPIO7p22 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_8)
#define PINCONF_GPIO7p23 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_9)
#define PINCONF_GPIO7p24 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_10)
#define PINCONF_GPIO7p25 (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_11)
#define PINCONF_GP_CLKIN_1 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_7)
#define PINCONF_GP_CLKIN_2 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_0)
#define PINCONF_GP_CLKIN_3 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_4)
#define PINCONF_I2C1_SCL_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_4)
#define PINCONF_I2C1_SCL_2 (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_15)
#define PINCONF_I2C1_SDA_1 (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_3)
#define PINCONF_I2C1_SDA_2 (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_13)
#define PINCONF_I2S0_RX_MCLK_1 (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_0)
#define PINCONF_I2S0_RX_MCLK_2 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_0)
#define PINCONF_I2S0_RX_MCLK_3 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_19)
#define PINCONF_I2S0_RX_SCK_1 (PINCONF_FUNC0|PINCONF_PINS3|PINCONF_PIN_0)
#define PINCONF_I2S0_RX_SCK_2 (PINCONF_FUNC4|PINCONF_PINS6|PINCONF_PIN_0)
#define PINCONF_I2S0_RX_SCK_3 (PINCONF_FUNC7|PINCONF_PINSF|PINCONF_PIN_4)
#define PINCONF_I2S0_RX_SDA_1 (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_2)
#define PINCONF_I2S0_RX_SDA_2 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_2)
#define PINCONF_I2S0_RX_WS_1 (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_1)
#define PINCONF_I2S0_RX_WS_2 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_1)
#define PINCONF_I2S0_TXWS (PINCONF_FUNC6|PINCONF_PINS0|PINCONF_PIN_0)
#define PINCONF_I2S0_TX_MCLK_1 (PINCONF_FUNC3|PINCONF_PINS3|PINCONF_PIN_0)
#define PINCONF_I2S0_TX_MCLK_2 (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_3)
#define PINCONF_I2S0_TX_MCLK_3 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_4)
#define PINCONF_I2S0_TX_SCK_1 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_0)
#define PINCONF_I2S0_TX_SCK_2 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_7)
#define PINCONF_I2S0_TX_SDA_1 (PINCONF_FUNC0|PINCONF_PINS3|PINCONF_PIN_2)
#define PINCONF_I2S0_TX_SDA_2 (PINCONF_FUNC2|PINCONF_PINS7|PINCONF_PIN_2)
#define PINCONF_I2S0_TX_SDA_3 (PINCONF_FUNC4|PINCONF_PINS9|PINCONF_PIN_2)
#define PINCONF_I2S0_TX_SDA_4 (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_5)
#define PINCONF_I2S0_TX_SDA_5 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_12)
#define PINCONF_I2S0_TX_WS_1 (PINCONF_FUNC0|PINCONF_PINS3|PINCONF_PIN_1)
#define PINCONF_I2S0_TX_WS_2 (PINCONF_FUNC2|PINCONF_PINS7|PINCONF_PIN_1)
#define PINCONF_I2S0_TX_WS_3 (PINCONF_FUNC4|PINCONF_PINS9|PINCONF_PIN_1)
#define PINCONF_I2S0_TX_WS_4 (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_4)
#define PINCONF_I2S0_TX_WS_5 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_13)
#define PINCONF_I2S1_RX_MCLK (PINCONF_FUNC5|PINCONF_PINSA|PINCONF_PIN_0)
#define PINCONF_I2S1_RX_SDA (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_4)
#define PINCONF_I2S1_RX_WS (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_5)
#define PINCONF_I2S1_TXSDA (PINCONF_FUNC7|PINCONF_PINS0|PINCONF_PIN_1)
#define PINCONF_I2S1_TXWS (PINCONF_FUNC7|PINCONF_PINS0|PINCONF_PIN_0)
#define PINCONF_I2S1_TX_MCLK_1 (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_8)
#define PINCONF_I2S1_TX_MCLK_2 (PINCONF_FUNC7|PINCONF_PINSF|PINCONF_PIN_0)
#define PINCONF_I2S1_TX_SCK_1 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_7)
#define PINCONF_I2S1_TX_SCK_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_19)
#define PINCONF_I2S1_TX_SCK_3 (PINCONF_FUNC7|PINCONF_PINS3|PINCONF_PIN_3)
#define PINCONF_I2S1_TX_SDA (PINCONF_FUNC7|PINCONF_PINSF|PINCONF_PIN_6)
#define PINCONF_I2S1_TX_WS (PINCONF_FUNC7|PINCONF_PINSF|PINCONF_PIN_7)
#define PINCONF_LCD_DCLK_1 (PINCONF_FUNC0|PINCONF_PINS4|PINCONF_PIN_7)
#define PINCONF_LCD_DCLK_2 (PINCONF_FUNC4|PINCONF_PINSC|PINCONF_PIN_0)
#define PINCONF_LCD_ENAB (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_6)
#define PINCONF_LCD_FP (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_5)
#define PINCONF_LCD_LCDM (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_6)
#define PINCONF_LCD_LE (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_0)
#define PINCONF_LCD_LP_1 (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_6)
#define PINCONF_LCD_LP_2 (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_6)
#define PINCONF_LCD_PWR_1 (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_7)
#define PINCONF_LCD_PWR_2 (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_7)
#define PINCONF_LCD_PWR_3 (PINCONF_FUNC6|PINCONF_PINSB|PINCONF_PIN_5)
#define PINCONF_LCD_VD0 (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_1)
#define PINCONF_LCD_VD1 (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_4)
#define PINCONF_LCD_VD2 (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_3)
#define PINCONF_LCD_VD3 (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_2)
#define PINCONF_LCD_VD4_1 (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_7)
#define PINCONF_LCD_VD4_2 (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_4)
#define PINCONF_LCD_VD5_1 (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_6)
#define PINCONF_LCD_VD5_2 (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_3)
#define PINCONF_LCD_VD6_1 (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_5)
#define PINCONF_LCD_VD6_2 (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_2)
#define PINCONF_LCD_VD7_1 (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_4)
#define PINCONF_LCD_VD7_2 (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_1)
#define PINCONF_LCD_VD8_1 (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_5)
#define PINCONF_LCD_VD8_2 (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_5)
#define PINCONF_LCD_VD9 (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_8)
#define PINCONF_LCD_VD10 (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_10)
#define PINCONF_LCD_VD11 (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_9)
#define PINCONF_LCD_VD12_1 (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_3)
#define PINCONF_LCD_VD12_2 (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_2)
#define PINCONF_LCD_VD12_3 (PINCONF_FUNC7|PINCONF_PINS3|PINCONF_PIN_5)
#define PINCONF_LCD_VD13_1 (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_6)
#define PINCONF_LCD_VD13_2 (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_0)
#define PINCONF_LCD_VD13_3 (PINCONF_FUNC7|PINCONF_PINS3|PINCONF_PIN_4)
#define PINCONF_LCD_VD14_1 (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_5)
#define PINCONF_LCD_VD14_2 (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_10)
#define PINCONF_LCD_VD14_3 (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_2)
#define PINCONF_LCD_VD15_1 (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_4)
#define PINCONF_LCD_VD15_2 (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_9)
#define PINCONF_LCD_VD15_3 (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_1)
#define PINCONF_LCD_VD16_1 (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_4)
#define PINCONF_LCD_VD16_2 (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_4)
#define PINCONF_LCD_VD17 (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_3)
#define PINCONF_LCD_VD18 (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_2)
#define PINCONF_LCD_VD19_1 (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_1)
#define PINCONF_LCD_VD19_2 (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_3)
#define PINCONF_LCD_VD19_3 (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_1)
#define PINCONF_LCD_VD19_4 (PINCONF_FUNC6|PINCONF_PINSB|PINCONF_PIN_6)
#define PINCONF_LCD_VD20_1 (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_3)
#define PINCONF_LCD_VD20_2 (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_4)
#define PINCONF_LCD_VD21_1 (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_2)
#define PINCONF_LCD_VD21_2 (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_3)
#define PINCONF_LCD_VD22_1 (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_1)
#define PINCONF_LCD_VD22_2 (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_8)
#define PINCONF_LCD_VD23_1 (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_0)
#define PINCONF_LCD_VD23_2 (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_5)
#define PINCONF_MCABORT_1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_10)
#define PINCONF_MCABORT_2 (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_0)
#define PINCONF_MCI0_1 (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_3)
#define PINCONF_MCI0_2 (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_2)
#define PINCONF_MCI1_1 (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_2)
#define PINCONF_MCI1_2 (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_1)
#define PINCONF_MCI2_1 (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_1)
#define PINCONF_MCI2_2 (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_0)
#define PINCONF_MCOA0_1 (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_0)
#define PINCONF_MCOA0_2 (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_3)
#define PINCONF_MCOA1_1 (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_5)
#define PINCONF_MCOA1_2 (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_5)
#define PINCONF_MCOA2_1 (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_7)
#define PINCONF_MCOA2_2 (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_1)
#define PINCONF_MCOB0_1 (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_4)
#define PINCONF_MCOB0_2 (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_4)
#define PINCONF_MCOB1_1 (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_6)
#define PINCONF_MCOB1_2 (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_6)
#define PINCONF_MCOB2_1 (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_0)
#define PINCONF_MCOB2_2 (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_2)
#define PINCONF_NMI_1 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_4)
#define PINCONF_NMI_2 (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_0)
#define PINCONF_QEI_IDX (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_1)
#define PINCONF_QEI_PHA (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_3)
#define PINCONF_QEI_PHB (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_2)
#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_13)
#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_8)
#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_0)
#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_6)
#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_10)
#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_9)
#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_4)
#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_10)
#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_5)
#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_11)
#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_6)
#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_12)
#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_7)
#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_11)
#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_12)
#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_13)
#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_14)
#define PINCONF_SD_POW_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1)
#define PINCONF_SD_POW_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5)
#define PINCONF_SD_POW_3 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_9)
#define PINCONF_SD_RST_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_3)
#define PINCONF_SD_RST_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_2)
#define PINCONF_SD_VOLT0_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_8)
#define PINCONF_SD_VOLT0_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_1)
#define PINCONF_SD_VOLT1_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_4)
#define PINCONF_SD_VOLT1_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_3)
#define PINCONF_SD_VOLT2_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_16)
#define PINCONF_SD_VOLT2_2 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_11)
#define PINCONF_SD_WP_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_15)
#define PINCONF_SD_WP_2 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_10)
#define PINCONF_SGPIO0_1 (PINCONF_FUNC3|PINCONF_PINS0|PINCONF_PIN_0)
#define PINCONF_SGPIO0_2 (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_0)
#define PINCONF_SGPIO0_3 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_1)
#define PINCONF_SGPIO1_1 (PINCONF_FUNC3|PINCONF_PINS0|PINCONF_PIN_1)
#define PINCONF_SGPIO1_2 (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_1)
#define PINCONF_SGPIO1_3 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_2)
#define PINCONF_SGPIO2_1 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_15)
#define PINCONF_SGPIO2_2 (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_2)
#define PINCONF_SGPIO2_3 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_3)
#define PINCONF_SGPIO3_1 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_16)
#define PINCONF_SGPIO3_2 (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_5)
#define PINCONF_SGPIO3_3 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_9)
#define PINCONF_SGPIO4_1 (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_0)
#define PINCONF_SGPIO4_2 (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_3)
#define PINCONF_SGPIO4_3 (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_4)
#define PINCONF_SGPIO4_4 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_5)
#define PINCONF_SGPIO4_5 (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_0)
#define PINCONF_SGPIO4_6 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_0)
#define PINCONF_SGPIO5_1 (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_1)
#define PINCONF_SGPIO5_2 (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_6)
#define PINCONF_SGPIO5_3 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_6)
#define PINCONF_SGPIO5_4 (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_1)
#define PINCONF_SGPIO5_5 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_1)
#define PINCONF_SGPIO6_1 (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_2)
#define PINCONF_SGPIO6_2 (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_7)
#define PINCONF_SGPIO6_3 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_7)
#define PINCONF_SGPIO6_4 (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_2)
#define PINCONF_SGPIO6_5 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_2)
#define PINCONF_SGPIO7_1 (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_6)
#define PINCONF_SGPIO7_2 (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_8)
#define PINCONF_SGPIO7_3 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_0)
#define PINCONF_SGPIO7_4 (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_8)
#define PINCONF_SGPIO7_5 (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_7)
#define PINCONF_SGPIO7_6 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_3)
#define PINCONF_SGPIO8_1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_1)
#define PINCONF_SGPIO8_2 (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_0)
#define PINCONF_SGPIO8_3 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_12)
#define PINCONF_SGPIO8_4 (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_6)
#define PINCONF_SGPIO8_5 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_2)
#define PINCONF_SGPIO8_6 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_4)
#define PINCONF_SGPIO9_1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_2)
#define PINCONF_SGPIO9_2 (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_1)
#define PINCONF_SGPIO9_3 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_13)
#define PINCONF_SGPIO9_4 (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_3)
#define PINCONF_SGPIO9_5 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_3)
#define PINCONF_SGPIO9_6 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_5)
#define PINCONF_SGPIO10_1 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_3)
#define PINCONF_SGPIO10_2 (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_2)
#define PINCONF_SGPIO10_3 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_14)
#define PINCONF_SGPIO10_4 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_4)
#define PINCONF_SGPIO10_5 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_6)
#define PINCONF_SGPIO11_1 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_4)
#define PINCONF_SGPIO11_2 (PINCONF_FUNC5|PINCONF_PINSC|PINCONF_PIN_12)
#define PINCONF_SGPIO11_3 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_17)
#define PINCONF_SGPIO11_4 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_5)
#define PINCONF_SGPIO11_5 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_7)
#define PINCONF_SGPIO12_1 (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_3)
#define PINCONF_SGPIO12_2 (PINCONF_FUNC5|PINCONF_PINSC|PINCONF_PIN_13)
#define PINCONF_SGPIO12_3 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_18)
#define PINCONF_SGPIO12_4 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_6)
#define PINCONF_SGPIO12_5 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_8)
#define PINCONF_SGPIO13_1 (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_4)
#define PINCONF_SGPIO13_2 (PINCONF_FUNC5|PINCONF_PINSC|PINCONF_PIN_14)
#define PINCONF_SGPIO13_3 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_20)
#define PINCONF_SGPIO13_4 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_8)
#define PINCONF_SGPIO13_5 (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_9)
#define PINCONF_SGPIO14_1 (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_5)
#define PINCONF_SGPIO14_2 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_6)
#define PINCONF_SGPIO14_3 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_9)
#define PINCONF_SGPIO15_1 (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_8)
#define PINCONF_SGPIO15_2 (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_5)
#define PINCONF_SGPIO15_3 (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_10)
#define PINCONF_SPIFI_CS (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINS3|PINCONF_PIN_8)
#define PINCONF_SPIFI_MISO (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_6)
#define PINCONF_SPIFI_MOSI (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_7)
#define PINCONF_SPIFI_SCK (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_3)
#define PINCONF_SPIFI_SIO2 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_5)
#define PINCONF_SPIFI_SIO3 (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_4)
#define PINCONF_SPI_MISO (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_6)
#define PINCONF_SPI_MOSI (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_7)
#define PINCONF_SPI_SCK (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_3)
#define PINCONF_SPI_SSEL (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_8)
#define PINCONF_SSP0_MISO_1 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_7)
#define PINCONF_SSP0_MISO_2 (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_2)
#define PINCONF_SSP0_MISO_3 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_1)
#define PINCONF_SSP0_MISO_4 (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_6)
#define PINCONF_SSP0_MISO_5 (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_1)
#define PINCONF_SSP0_MOSI_1 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_8)
#define PINCONF_SSP0_MOSI_2 (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_3)
#define PINCONF_SSP0_MOSI_3 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_2)
#define PINCONF_SSP0_MOSI_4 (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_7)
#define PINCONF_SSP0_MOSI_5 (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_2)
#define PINCONF_SSP0_SCK_1 (PINCONF_FUNC0|PINCONF_PINSF|PINCONF_PIN_0)
#define PINCONF_SSP0_SCK_2 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_3)
#define PINCONF_SSP0_SCK_3 (PINCONF_FUNC4|PINCONF_PINS3|PINCONF_PIN_0)
#define PINCONF_SSP0_SSEL_1 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_6)
#define PINCONF_SSP0_SSEL_2 (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_1)
#define PINCONF_SSP0_SSEL_3 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_0)
#define PINCONF_SSP0_SSEL_4 (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_8)
#define PINCONF_SSP0_SSEL_5 (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_0)
#define PINCONF_SSP1_MISO_1 (PINCONF_FUNC1|PINCONF_PINS0|PINCONF_PIN_0)
#define PINCONF_SSP1_MISO_2 (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_6)
#define PINCONF_SSP1_MISO_3 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_3)
#define PINCONF_SSP1_MOSI_1 (PINCONF_FUNC1|PINCONF_PINS0|PINCONF_PIN_1)
#define PINCONF_SSP1_MOSI_2 (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_7)
#define PINCONF_SSP1_MOSI_3 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_4)
#define PINCONF_SSP1_SCK_1 (PINCONF_FUNC0|PINCONF_PINSF|PINCONF_PIN_4)
#define PINCONF_SSP1_SCK_2 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_19)
#define PINCONF_SSP1_SSEL_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_20)
#define PINCONF_SSP1_SSEL_2 (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_5)
#define PINCONF_SSP1_SSEL_3 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_5)
#define PINCONF_T0_CAP0_1 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_13)
#define PINCONF_T0_CAP0_2 (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_4)
#define PINCONF_T0_CAP1_1 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_12)
#define PINCONF_T0_CAP1_2 (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_5)
#define PINCONF_T0_CAP2_1 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_20)
#define PINCONF_T0_CAP2_2 (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_6)
#define PINCONF_T0_CAP3_1 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_17)
#define PINCONF_T0_CAP3_2 (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_7)
#define PINCONF_T0_MAT0_1 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_16)
#define PINCONF_T0_MAT0_2 (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_0)
#define PINCONF_T0_MAT1_1 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_15)
#define PINCONF_T0_MAT1_2 (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_1)
#define PINCONF_T0_MAT2_1 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_14)
#define PINCONF_T0_MAT2_2 (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_2)
#define PINCONF_T0_MAT3_1 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_18)
#define PINCONF_T0_MAT3_2 (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_3)
#define PINCONF_T1_CAP0 (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_0)
#define PINCONF_T1_CAP1 (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_1)
#define PINCONF_T1_CAP2 (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_2)
#define PINCONF_T1_CAP3 (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_3)
#define PINCONF_T1_MAT0 (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_4)
#define PINCONF_T1_MAT1 (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_5)
#define PINCONF_T1_MAT2 (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_6)
#define PINCONF_T1_MAT3 (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_7)
#define PINCONF_T2_CAP0 (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_1)
#define PINCONF_T2_CAP1 (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_2)
#define PINCONF_T2_CAP2 (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_3)
#define PINCONF_T2_CAP3 (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_6)
#define PINCONF_T2_MAT0 (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_7)
#define PINCONF_T2_MAT1 (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_8)
#define PINCONF_T2_MAT2 (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_9)
#define PINCONF_T2_MAT3 (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_11)
#define PINCONF_T3_CAP0_1 (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_0)
#define PINCONF_T3_CAP0_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_1)
#define PINCONF_T3_CAP1_1 (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_1)
#define PINCONF_T3_CAP1_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_4)
#define PINCONF_T3_CAP2_1 (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_2)
#define PINCONF_T3_CAP2_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_5)
#define PINCONF_T3_CAP3_1 (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_6)
#define PINCONF_T3_CAP3_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_6)
#define PINCONF_T3_MAT0_1 (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_3)
#define PINCONF_T3_MAT0_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_7)
#define PINCONF_T3_MAT1_1 (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_4)
#define PINCONF_T3_MAT1_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_8)
#define PINCONF_T3_MAT2_1 (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_5)
#define PINCONF_T3_MAT2_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_9)
#define PINCONF_T3_MAT3_1 (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_7)
#define PINCONF_T3_MAT3_2 (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_10)
#define PINCONF_TRACECLK (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_4)
#define PINCONF_TRACEDATA0_1 (PINCONF_FUNC3|PINCONF_PINSF|PINCONF_PIN_5)
#define PINCONF_TRACEDATA0_2 (PINCONF_FUNC5|PINCONF_PINS7|PINCONF_PIN_4)
#define PINCONF_TRACEDATA1_1 (PINCONF_FUNC3|PINCONF_PINSF|PINCONF_PIN_6)
#define PINCONF_TRACEDATA1_2 (PINCONF_FUNC5|PINCONF_PINS7|PINCONF_PIN_5)
#define PINCONF_TRACEDATA2_1 (PINCONF_FUNC3|PINCONF_PINSF|PINCONF_PIN_7)
#define PINCONF_TRACEDATA2_2 (PINCONF_FUNC5|PINCONF_PINS7|PINCONF_PIN_6)
#define PINCONF_TRACEDATA3_1 (PINCONF_FUNC3|PINCONF_PINSF|PINCONF_PIN_8)
#define PINCONF_TRACEDATA3_2 (PINCONF_FUNC5|PINCONF_PINS7|PINCONF_PIN_7)
#define PINCONF_U0_DIR_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_6)
#define PINCONF_U0_DIR_2 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_9)
#define PINCONF_U0_DIR_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_2)
#define PINCONF_U0_RXD_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_1)
#define PINCONF_U0_RXD_2 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_11)
#define PINCONF_U0_RXD_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_5)
#define PINCONF_U0_RXD_4 (PINCONF_FUNC7|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_6)
#define PINCONF_U0_TXD_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_0)
#define PINCONF_U0_TXD_2 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_10)
#define PINCONF_U0_TXD_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_4)
#define PINCONF_U0_TXD_4 (PINCONF_FUNC7|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_5)
#define PINCONF_U0_UCLK_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_2)
#define PINCONF_U0_UCLK_2 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_8)
#define PINCONF_U0_UCLK_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_1)
#define PINCONF_U1_CTS_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_11)
#define PINCONF_U1_CTS_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_2)
#define PINCONF_U1_CTS_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_7)
#define PINCONF_U1_CTS_4 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_4)
#define PINCONF_U1_DCD_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_12)
#define PINCONF_U1_DCD_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_11)
#define PINCONF_U1_DCD_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_9)
#define PINCONF_U1_DCD_4 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_5)
#define PINCONF_U1_DSR_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_7)
#define PINCONF_U1_DSR_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_10)
#define PINCONF_U1_DSR_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_8)
#define PINCONF_U1_DSR_4 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_0)
#define PINCONF_U1_DTR_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_8)
#define PINCONF_U1_DTR_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_12)
#define PINCONF_U1_DTR_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_10)
#define PINCONF_U1_DTR_4 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_1)
#define PINCONF_U1_RI_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_10)
#define PINCONF_U1_RI_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_1)
#define PINCONF_U1_RI_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_6)
#define PINCONF_U1_RI_4 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_3)
#define PINCONF_U1_RTS_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_9)
#define PINCONF_U1_RTS_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_3)
#define PINCONF_U1_RTS_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_5)
#define PINCONF_U1_RTS_4 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_2)
#define PINCONF_U1_RXD_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_14)
#define PINCONF_U1_RXD_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_14)
#define PINCONF_U1_RXD_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_12)
#define PINCONF_U1_RXD_4 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_5)
#define PINCONF_U1_RXD_5 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_7)
#define PINCONF_U1_TXD_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_13)
#define PINCONF_U1_TXD_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_13)
#define PINCONF_U1_TXD_3 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_11)
#define PINCONF_U1_TXD_4 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_4)
#define PINCONF_U1_TXD_5 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_6)
#define PINCONF_U2_DIR_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_18)
#define PINCONF_U2_DIR_2 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_13)
#define PINCONF_U2_RXD_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_16)
#define PINCONF_U2_RXD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_11)
#define PINCONF_U2_RXD_3 (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_2)
#define PINCONF_U2_RXD_4 (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_2)
#define PINCONF_U2_TXD_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_15)
#define PINCONF_U2_TXD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_10)
#define PINCONF_U2_TXD_3 (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_1)
#define PINCONF_U2_TXD_4 (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_1)
#define PINCONF_U2_UCLK_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_17)
#define PINCONF_U2_UCLK_2 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_12)
#define PINCONF_U3_BAUD_1 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_7)
#define PINCONF_U3_BAUD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_9)
#define PINCONF_U3_BAUD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_3)
#define PINCONF_U3_DIR_1 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_6)
#define PINCONF_U3_DIR_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_8)
#define PINCONF_U3_DIR_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_4)
#define PINCONF_U3_RXD_1 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_3)
#define PINCONF_U3_RXD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_4)
#define PINCONF_U3_RXD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_2)
#define PINCONF_U3_RXD_4 (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_4)
#define PINCONF_U3_TXD_1 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_2)
#define PINCONF_U3_TXD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_3)
#define PINCONF_U3_TXD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_1)
#define PINCONF_U3_TXD_4 (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_3)
#define PINCONF_U3_UCLK_1 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_5)
#define PINCONF_U3_UCLK_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_7)
#define PINCONF_U3_UCLK_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_0)
#define PINCONF_USB0_IND0_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_2)
#define PINCONF_USB0_IND0_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_6)
#define PINCONF_USB0_IND0_3 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_8)
#define PINCONF_USB0_IND0_4 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_4)
#define PINCONF_USB0_IND0_5 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_5)
#define PINCONF_USB0_IND1_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_1)
#define PINCONF_USB0_IND1_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_2)
#define PINCONF_USB0_IND1_3 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_7)
#define PINCONF_USB0_IND1_4 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_3)
#define PINCONF_USB0_PPWR_1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_3)
#define PINCONF_USB0_PPWR_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_0)
#define PINCONF_USB0_PPWR_3 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_7)
#define PINCONF_USB0_PPWR_4 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_3)
#define PINCONF_USB0_PWR_FAULT_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_0)
#define PINCONF_USB0_PWR_FAULT_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_1)
#define PINCONF_USB0_PWR_FAULT_3 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_6)
#define PINCONF_USB0_PWR_FAULT_4 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_5)
#define PINCONF_USB0_PWR_FAULT_5 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_4)
#define PINCONF_USB1_IND0_1 (PINCONF_FUNC2|PINCONF_PINS9|PINCONF_PIN_4)
#define PINCONF_USB1_IND0_2 (PINCONF_FUNC3|PINCONF_PINS3|PINCONF_PIN_2)
#define PINCONF_USB1_IND1_1 (PINCONF_FUNC2|PINCONF_PINS9|PINCONF_PIN_3)
#define PINCONF_USB1_IND1_2 (PINCONF_FUNC3|PINCONF_PINS3|PINCONF_PIN_1)
#define PINCONF_USB1_PPWR (PINCONF_FUNC2|PINCONF_PINS9|PINCONF_PIN_5)
#define PINCONF_USB1_PWR_FAULT (PINCONF_FUNC2|PINCONF_PINS9|PINCONF_PIN_6)
#define PINCONF_USB1_ULPI_CLK_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_8)
#define PINCONF_USB1_ULPI_CLK_2 (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_0)
#define PINCONF_USB1_ULPI_D0_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_5)
#define PINCONF_USB1_ULPI_D0_2 (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_8)
#define PINCONF_USB1_ULPI_D0_3 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_11)
#define PINCONF_USB1_ULPI_D1_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_4)
#define PINCONF_USB1_ULPI_D1_2 (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_7)
#define PINCONF_USB1_ULPI_D2_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_3)
#define PINCONF_USB1_ULPI_D2_2 (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_6)
#define PINCONF_USB1_ULPI_D3_1 (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_6)
#define PINCONF_USB1_ULPI_D3_2 (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_5)
#define PINCONF_USB1_ULPI_D4_1 (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_5)
#define PINCONF_USB1_ULPI_D4_2 (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_4)
#define PINCONF_USB1_ULPI_D5_1 (PINCONF_FUNC0|PINCONF_PINSC|PINCONF_PIN_3)
#define PINCONF_USB1_ULPI_D5_2 (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_4)
#define PINCONF_USB1_ULPI_D6_1 (PINCONF_FUNC0|PINCONF_PINSC|PINCONF_PIN_2)
#define PINCONF_USB1_ULPI_D6_2 (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_3)
#define PINCONF_USB1_ULPI_D7_1 (PINCONF_FUNC0|PINCONF_PINSC|PINCONF_PIN_1)
#define PINCONF_USB1_ULPI_D7_2 (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_2)
#define PINCONF_USB1_ULPI_DIR_1 (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_1)
#define PINCONF_USB1_ULPI_DIR_2 (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_11)
#define PINCONF_USB1_ULPI_NXT_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_6)
#define PINCONF_USB1_ULPI_NXT_2 (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_9)
#define PINCONF_USB1_ULPI_STP_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_7)
#define PINCONF_USB1_ULPI_STP_2 (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_10)
#define PINCONF_USB1_VBUS (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_5)
#define CLKCONF_CGU_OUT0 (PINCONFIG_DIGITAL|PINCONF_FUNC5|PINCONF_CLK1)
#define CLKCONF_CGU_OUT1 (PINCONFIG_DIGITAL|PINCONF_FUNC5|PINCONF_CLK3)
#define CLKCONF_CLKOUT_1 (PINCONFIG_DIGITAL|PINCONF_FUNC1|PINCONF_CLK0)
#define CLKCONF_CLKOUT_2 (PINCONFIG_DIGITAL|PINCONF_FUNC1|PINCONF_CLK1)
#define CLKCONF_CLKOUT_3 (PINCONFIG_DIGITAL|PINCONF_FUNC1|PINCONF_CLK2)
#define CLKCONF_CLKOUT_4 (PINCONFIG_DIGITAL|PINCONF_FUNC1|PINCONF_CLK3)
#define CLKCONF_EMC_CLK0 (PINCONFIG_DIGITAL|PINCONF_FUNC0|PINCONF_CLK0)
#define CLKCONF_EMC_CLK01 (PINCONFIG_DIGITAL|PINCONF_FUNC5|PINCONF_CLK0)
#define CLKCONF_EMC_CLK1 (PINCONFIG_DIGITAL|PINCONF_FUNC0|PINCONF_CLK1)
#define CLKCONF_EMC_CLK2 (PINCONFIG_DIGITAL|PINCONF_FUNC0|PINCONF_CLK3)
#define CLKCONF_EMC_CLK23 (PINCONFIG_DIGITAL|PINCONF_FUNC5|PINCONF_CLK2)
#define CLKCONF_EMC_CLK3 (PINCONFIG_DIGITAL|PINCONF_FUNC0|PINCONF_CLK2)
#define CLKCONF_ENET_REF_CLK (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK0)
#define CLKCONF_ENET_TX_CLK (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK0)
#define CLKCONF_I2S0_TX_MCLK (PINCONFIG_DIGITAL|PINCONF_FUNC6|PINCONF_CLK2)
#define CLKCONF_I2S1_RX_SCK_1 (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK2)
#define CLKCONF_I2S1_RX_SCK_2 (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK3)
#define CLKCONF_I2S1_TX_MCLK (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK1)
#define CLKCONF_SD_CLK_1 (PINCONFIG_DIGITAL|PINCONF_FUNC4|PINCONF_CLK0)
#define CLKCONF_SD_CLK_2 (PINCONFIG_DIGITAL|PINCONF_FUNC4|PINCONF_CLK2)
#define CLKCONF_SSP1_SCK (PINCONFIG_DIGITAL|PINCONF_FUNC6|PINCONF_CLK0)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4337JET100_PINCONF_H */

22
arch/arm/src/lpc43xx/chip/lpc43_aes.h
View file

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/lpc43xx/chip/lpc43_aes.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -45,6 +45,7 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* The AES is controlled through a set of simple API calls located in the LPC43xx
* ROM. This value holds the pointer to the AES driver table.
*/
@ -86,17 +87,32 @@ struct lpc43_aes_s
/* Loads 128-bit AES software defined user key (16 bytes) */
void (*aes_LoadKeySW)(unsigned char *key);
void (*aes_LoadKeySW)(const unsigned char *key);
/* Loads 128-bit AES initialization vector (16 bytes) */
void (*aes_LoadIV_SW)(unsigned char *iv);
void (*aes_LoadIV_SW)(const unsigned char *iv);
/* Loads 128-bit AES IC specific initialization vector, which is used to decrypt
* a boot image.
*/
void (*aes_LoadIV_IC)(void);
/* Process data */
unsigned int (*aes_Operate)(unsigned char* out, const unsigned char* in, unsigned blocks);
};
enum lpc43_aes_errorcodes_e
{
AES_API_ERR_BASE = 0x30000,
AES_API_ERR_WRONG_CMD,
AES_API_ERR_NOT_SUPPORTED,
AES_API_ERR_KEY_ALREADY_PROGRAMMED,
AES_API_ERR_DMA_CHANNEL_CFG,
AES_API_ERR_DMA_MUX_CFG,
AES_API_ERR_DMA_BUSY
};
/************************************************************************************

41
arch/arm/src/lpc43xx/lpc43_adc.c
View file

@ -7,8 +7,9 @@
* Ported from from the LPC17 version:
*
* Copyright(C) 2011 Li Zhuoyi. All rights reserved.
* Copyright(C) 2016 Gregory Nutt. All rights reserved.
* Author: Li Zhuoyi <lzyy.cn@gmail.com>
* History: 0.1 2011-08-05 initial version
* Gregory Nutt
*
* This file is a part of NuttX:
*
@ -55,6 +56,7 @@
#include <stdbool.h>
#include <semaphore.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
@ -112,6 +114,7 @@
struct up_dev_s
{
FAR const struct adc_callback_s *cb;
uint8_t mask;
uint8_t mask_int;
uint32_t freq;
@ -126,6 +129,8 @@ struct up_dev_s
/* ADC methods */
static int adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback);
static void adc_reset(FAR struct adc_dev_s *dev);
static int adc_setup(FAR struct adc_dev_s *dev);
static void adc_shutdown(FAR struct adc_dev_s *dev);
@ -139,6 +144,7 @@ static int adc_interrupt(int irq, void *context);
static const struct adc_ops_s g_adcops =
{
.ao_bind = adc_bind,
.ao_reset = adc_reset,
.ao_setup = adc_setup,
.ao_shutdown = adc_shutdown,
@ -166,6 +172,25 @@ static struct adc_dev_s g_adcdev =
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: adc_bind
*
* Description:
* Bind the upper-half driver callbacks to the lower-half implementation. This
* must be called early in order to receive ADC event notifications.
*
****************************************************************************/
static int adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback)
{
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
DEBUGASSERT(priv != NULL);
priv->cb = callback;
return OK;
}
/****************************************************************************
* Name: adc_reset
*
@ -454,8 +479,20 @@ static int adc_interrupt(int irq, void *context)
{
if (priv->mask & (1 << i))
{
int32_t data;
regval = getreg32(LPC43_ADC0_DR(i));
adc_receive(&g_adcdev, i,(regval&ADC_DR_VVREF_MASK)>>ADC_DR_VVREF_SHIFT);
data = (regval & ADC_DR_VVREF_MASK) >> ADC_DR_VVREF_SHIFT;
/* Verify that the upper-half driver has bound its callback functions */
if (priv->cb != NULL)
{
/* Perform the data received callback */
DEBUGASSERT(priv->cb->au_receive != NULL);
priv->cb->au_receive(&g_adcdev, i, data);
}
}
}

209
arch/arm/src/lpc43xx/lpc43_aes.c Normal file
View file

@ -0,0 +1,209 @@
/****************************************************************************
* arch/arm/src/lpc43xx/lpc43_aes.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Alexander Vasiljev <alexvasiljev@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#include <semaphore.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/crypto/crypto.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "up_internal.h"
#include "up_arch.h"
#include "chip.h"
#include <chip/lpc43_aes.h>
#define AES_BLOCK_SIZE 16
/****************************************************************************
* Private Data
****************************************************************************/
static struct lpc43_aes_s *g_aes;
/****************************************************************************
* Public Functions
****************************************************************************/
int aes_cypher(void *out, const void *in, uint32_t size, const void *iv,
const void *key, uint32_t keysize, int mode, int encrypt)
{
unsigned int ret = 0;
uint32_t outl = size;
ret = aes_init(iv, key, keysize, mode, encrypt);
if (ret != OK)
{
return ret;
}
return aes_update(out, &outl, in, size);
}
int up_aesreset(void)
{
return OK;
}
int aes_init(FAR const void *iv, FAR const void *key, uint32_t keysize,
int mode, int encrypt)
{
unsigned int cmd = 0;
unsigned int ret = 0;
if (g_aes == NULL)
{
return -ENOSYS;
}
/* The LPC43 aes engine can load two keys from otp and one random
* generated key. This behavior doesn't fit current api. So if
* key == NULL, we will usr keysize as identifier of the special key.
*/
if (keysize != 16 && key)
{
return -EINVAL;
}
if (mode != AES_MODE_ECB && mode != AES_MODE_CBC)
{
return -EINVAL;
}
if (encrypt == CYPHER_ENCRYPT)
{
cmd = mode == AES_MODE_ECB ? AES_API_CMD_ENCODE_ECB : AES_API_CMD_ENCODE_CBC;
}
else
{
cmd = mode == AES_MODE_ECB ? AES_API_CMD_DECODE_ECB : AES_API_CMD_DECODE_CBC;
}
g_aes->aes_Init();
if (key != NULL)
{
g_aes->aes_LoadKeySW(key);
}
else
{
switch (keysize)
{
case 0:
g_aes->aes_LoadKey1();
break;
case 1:
g_aes->aes_LoadKey2();
break;
case 2:
g_aes->aes_LoadKeyRNG();
break;
}
}
g_aes->aes_LoadIV_SW((const unsigned char*)iv);
ret = g_aes->aes_SetMode(cmd);
switch (ret)
{
case AES_API_ERR_WRONG_CMD:
case AES_API_ERR_NOT_SUPPORTED:
case AES_API_ERR_KEY_ALREADY_PROGRAMMED:
ret = -EINVAL;
break;
case AES_API_ERR_DMA_CHANNEL_CFG:
case AES_API_ERR_DMA_MUX_CFG:
case AES_API_ERR_DMA_BUSY:
ret = -EBUSY;
break;
}
return 0;
}
int aes_update(FAR const void *out, uint32_t *outl, FAR const void *in,
uint32_t inl)
{
if (g_aes == NULL)
{
return -ENOSYS;
}
if ((inl & (AES_BLOCK_SIZE-1)) != 0)
{
return -EINVAL;
}
if (inl > *outl)
{
return -EINVAL;
}
return g_aes->aes_Operate((unsigned char*)out,
(unsigned char*)in, inl / 16);
}
int up_aesinitialize(void)
{
g_aes = (struct lpc43_g_aes*)*((uint32_t*)LPC43_ROM_AES_DRIVER_TABLE);
if (g_aes != NULL)
{
return OK;
}
return -ENOSYS;
}
int up_aesuninitialize(void)
{
return OK;
}

6
arch/arm/src/nuc1xx/Kconfig
View file

@ -314,20 +314,20 @@ config NUC_PWM7
config NUC_UART0
bool "UART0"
default y
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config NUC_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config NUC_UART2
bool "UART2"
default n
depends on NUC_HAVE_UART2
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config NUC_USBD

15
arch/arm/src/sam34/Kconfig
View file

@ -453,7 +453,7 @@ config SAM34_PICOUART
bool "PicoUART"
default n
depends on ARCH_CHIP_SAM4L
select ARCH_HAVE_UART
select UART_SERIALDRIVER
config SAM34_PWM
bool "Pulse Width Modulation (PWM) Controller"
@ -609,14 +609,14 @@ config SAM34_UART0
bool "UART 0"
default y
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_UART1
bool "UART 1"
default n
depends on ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
if SAM34_UART1 && ARCH_CHIP_SAM4CM
@ -651,27 +651,27 @@ config SAM34_USBC
config SAM34_USART0
bool "USART 0"
default n
select ARCH_HAVE_USART0
select USART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_USART1
bool "USART 1"
default n
select ARCH_HAVE_USART1
select USART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_USART2
bool "USART 2"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4L
select ARCH_HAVE_USART2
select USART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_USART3
bool "USART 3"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4L
select ARCH_HAVE_USART3
select USART3_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAM34_WDT
@ -1060,6 +1060,7 @@ config SAM34_TC5_TIOB
config SAM34_ONESHOT
bool "TC one-shot wrapper"
depends on SAM34_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---

67
arch/arm/src/sam34/sam4cm_oneshot.c
View file

@ -58,6 +58,7 @@
#include <nuttx/clock.h>
#include "sam4cm_oneshot.h"
#include "sam4cm_freerun.h"
#ifdef CONFIG_SAM34_ONESHOT
@ -106,10 +107,11 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
/* Forward the event, clearing out any vestiges */
oneshot_handler = (oneshot_handler_t)oneshot->handler;
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
oneshot_handler = (oneshot_handler_t)oneshot->handler;
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
oneshot->start_count = 0;
oneshot_handler(oneshot_arg);
}
@ -206,10 +208,11 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
* success.
*/
oneshot->chan = chan;
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
oneshot->chan = chan;
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
oneshot->start_count = 0;
return OK;
}
@ -248,8 +251,8 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
void *arg, const struct timespec *ts)
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@ -267,7 +270,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
/* Yes.. then cancel it */
tcvdbg("Already running... cancelling\n");
(void)sam_oneshot_cancel(oneshot, NULL);
(void)sam_oneshot_cancel(oneshot, freerun, NULL);
}
/* Save the new handler and its argument */
@ -306,6 +309,26 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
sam_tc_start(oneshot->tch);
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
* software trigger, which starts the clock and sets the counter
* register to zero. This reset is performed with the next valid edge
* of the selected clock. Thus it can take up USEC_PER_TICK microseconds
* until the counter register becomes zero.
*
* If the timer is canceled within this period the counter register holds
* the counter value for the last timer/counter run. To circumvent this
* the counter value of the freerun timer/counter is stored at each start
* of the oneshot timer/counter.
*
* The function up_timer_gettime() could also be used for this but it takes
* too long. If up_timer_gettime() is called within this function the problem
* vanishes at least if compiled with no optimisation.
*/
oneshot->start_count = sam_tc_getcounter(freerun->tch);
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
*/
@ -340,7 +363,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts)
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@ -381,6 +405,17 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts)
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
/* Now we can disable the interrupt and stop the timer. */
sam_tc_attach(oneshot->tch, NULL, NULL, 0);
@ -429,6 +464,14 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts)
usec = (((uint64_t)(rc - count)) * USEC_PER_SEC) /
sam_tc_divfreq(oneshot->tch);
/* Each time the timer/counter is canceled the time calculated from
* the two registers (counter and REGC) is accurate up to an error
* between 0 and USEC_PER_TICK microseconds. To correct this error
* one tick which means USEC_PER_TICK microseconds are subtracted.
*/
usec = usec > USEC_PER_TICK ? usec - USEC_PER_TICK : 0;
/* Return the time remaining in the correct form */
sec = usec / USEC_PER_SEC;

19
arch/arm/src/sam34/sam4cm_oneshot.h
View file

@ -46,6 +46,7 @@
#include <time.h>
#include "sam4cm_tc.h"
#include "sam4cm_freerun.h"
#ifdef CONFIG_SAM34_ONESHOT
@ -82,6 +83,11 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
};
/****************************************************************************
@ -136,6 +142,9 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@ -146,8 +155,8 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
void *arg, const struct timespec *ts);
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@ -162,6 +171,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@ -173,7 +185,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts);
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus

6
arch/arm/src/sam34/sam4cm_tickless.c
View file

@ -365,8 +365,8 @@ int up_timer_gettime(FAR struct timespec *ts)
int up_timer_cancel(FAR struct timespec *ts)
{
return ONESHOT_INITIALIZED(&g_tickless.oneshot) ?
sam_oneshot_cancel(&g_tickless.oneshot, ts) :
return ONESHOT_INITIALIZED(&g_tickless.oneshot) && FREERUN_INITIALIZED(&g_tickless.freerun) ?
sam_oneshot_cancel(&g_tickless.oneshot, &g_tickless.freerun, ts) :
-EAGAIN;
}
@ -398,7 +398,7 @@ int up_timer_cancel(FAR struct timespec *ts)
int up_timer_start(FAR const struct timespec *ts)
{
return ONESHOT_INITIALIZED(&g_tickless.oneshot) ?
sam_oneshot_start(&g_tickless.oneshot, sam_oneshot_handler, NULL, ts) :
sam_oneshot_start(&g_tickless.oneshot, &g_tickless.freerun, sam_oneshot_handler, NULL, ts) :
-EAGAIN;
}
#endif /* CONFIG_SCHED_TICKLESS */

8
arch/arm/src/sam34/sam_lowputc.c
View file

@ -75,16 +75,16 @@
* for our purposes.
*/
#ifndef CONFIG_USART0_ISUART
#ifndef CONFIG_USART0_SERIALDRIVER
# undef CONFIG_SAM34_USART0
#endif
#ifndef CONFIG_USART1_ISUART
#ifndef CONFIG_USART1_SERIALDRIVER
# undef CONFIG_SAM34_USART1
#endif
#ifndef CONFIG_USART2_ISUART
#ifndef CONFIG_USART2_SERIALDRIVER
# undef CONFIG_SAM34_USART2
#endif
#ifndef CONFIG_USART3_ISUART
#ifndef CONFIG_USART3_SERIALDRIVER
# undef CONFIG_SAM34_USART3
#endif

8
arch/arm/src/sam34/sam_serial.c
View file

@ -84,16 +84,16 @@
* for our purposes.
*/
#ifndef CONFIG_USART0_ISUART
#ifndef CONFIG_USART0_SERIALDRIVER
# undef CONFIG_SAM34_USART0
#endif
#ifndef CONFIG_USART1_ISUART
#ifndef CONFIG_USART1_SERIALDRIVER
# undef CONFIG_SAM34_USART1
#endif
#ifndef CONFIG_USART2_ISUART
#ifndef CONFIG_USART2_SERIALDRIVER
# undef CONFIG_SAM34_USART2
#endif
#ifndef CONFIG_USART3_ISUART
#ifndef CONFIG_USART3_SERIALDRIVER
# undef CONFIG_SAM34_USART3
#endif

1
arch/arm/src/sam34/sam_twi.c
View file

@ -901,6 +901,7 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
/* Set the initial TWI data transfer frequency */
priv->i2cfreq = 0;
twi_setfrequency(priv, frequency);
}

33
arch/arm/src/sama5/Kconfig
View file

@ -387,7 +387,7 @@ config SAMA5_AESB
config SAMA5_DBGU
bool "Debug Unit (DBGU)"
default n
select ARCH_HAVE_OTHER_UART
select OTHER_UART_SERIALDRIVER
config SAMA5_PIT
bool "Periodic Interval Timer (PIT)"
@ -432,70 +432,70 @@ config SAMA5_UART0
bool "UART 0"
default y
depends on SAMA5_HAVE_UART0
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_UART1
bool "UART 1"
default n
depends on SAMA5_HAVE_UART1
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_UART2
bool "UART 2"
default n
depends on SAMA5_HAVE_UART2
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_UART3
bool "UART 3"
default n
depends on SAMA5_HAVE_UART3
select ARCH_HAVE_UART3
select UART3_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_UART4
bool "UART 4"
default n
depends on SAMA5_HAVE_UART4
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_USART0
bool "USART 0"
default n
depends on SAMA5_HAVE_USART0
select ARCH_HAVE_USART0
select USART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_USART1
bool "USART 1"
default n
depends on SAMA5_HAVE_USART1
select ARCH_HAVE_USART1
select USART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_USART2
bool "USART 2"
default n
depends on SAMA5_HAVE_USART2
select ARCH_HAVE_USART2
select USART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_USART3
bool "USART 3"
default n
depends on SAMA5_HAVE_USART3
select ARCH_HAVE_USART3
select USART3_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_USART4
bool "USART 4"
default n
depends on SAMA5_HAVE_USART4
select ARCH_HAVE_USART4
select USART4_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_FLEXCOM0
@ -786,7 +786,7 @@ choice
config SAMA5_FLEXCOM0_USART
bool "USART"
select SAMA5_FLEXCOM_USART
select ARCH_HAVE_USART0
select USART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_FLEXCOM0_SPI
@ -807,7 +807,7 @@ choice
config SAMA5_FLEXCOM1_USART
bool "USART"
select SAMA5_FLEXCOM_USART
select ARCH_HAVE_USART1
select USART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_FLEXCOM1_SPI
@ -828,7 +828,7 @@ choice
config SAMA5_FLEXCOM2_USART
bool "USART"
select SAMA5_FLEXCOM_USART
select ARCH_HAVE_USART2
select USART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_FLEXCOM2_SPI
@ -853,7 +853,7 @@ config SAMA5_FLEXCOM3_USART
config SAMA5_FLEXCOM3_SPI
bool "SPI"
select SAMA5_FLEXCOM_SPI
select ARCH_HAVE_USART3
select USART3_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_FLEXCOM3_SPI
@ -870,7 +870,7 @@ choice
config SAMA5_FLEXCOM4_USART
bool "USART"
select SAMA5_FLEXCOM_USART
select ARCH_HAVE_USART4
select USART4_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMA5_FLEXCOM4_SPI
@ -3866,6 +3866,7 @@ endif # SAMA5_TC2
config SAMA5_ONESHOT
bool "TC one-shot wrapper"
depends on SAMA5_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---

48
arch/arm/src/sama5/sam_adc.c
View file

@ -57,6 +57,7 @@
#include <stdbool.h>
#include <semaphore.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
@ -378,6 +379,7 @@
struct sam_adc_s
{
FAR const struct adc_callback_s *cb;
sem_t exclsem; /* Supports exclusive access to the ADC interface */
bool initialized; /* The ADC driver is already initialized */
uint32_t frequency; /* ADC clock frequency */
@ -446,6 +448,8 @@ static int sam_adc_interrupt(int irq, void *context);
/* ADC methods */
#ifdef SAMA5_ADC_HAVE_CHANNELS
static int sam_adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback);
static void sam_adc_reset(struct adc_dev_s *dev);
static int sam_adc_setup(struct adc_dev_s *dev);
static void sam_adc_shutdown(struct adc_dev_s *dev);
@ -477,6 +481,7 @@ static void sam_adc_channels(struct sam_adc_s *priv);
static const struct adc_ops_s g_adcops =
{
.ao_bind = sam_adc_bind,
.ao_reset = sam_adc_reset,
.ao_setup = sam_adc_setup,
.ao_shutdown = sam_adc_shutdown,
@ -664,9 +669,15 @@ static void sam_adc_dmadone(void *arg)
chan = (int)((*buffer & ADC_LCDR_CHANB_MASK) >> ADC_LCDR_CHANB_SHIFT);
sample = ((*buffer & ADC_LCDR_DATA_MASK) >> ADC_LCDR_DATA_SHIFT);
/* And give the sample data to the ADC upper half */
/* Verify that the upper-half driver has bound its callback functions */
(void)adc_receive(priv->dev, chan, sample);
if (priv->cb != NULL)
{
/* Give the sample data to the ADC upper half */
DEBUGASSERT(priv->cb->au_receive != NULL);
priv->cb->au_receive(priv->dev, chan, sample);
}
}
}
@ -858,7 +869,17 @@ static void sam_adc_endconversion(void *arg)
/* Read the ADC sample and pass it to the upper half */
regval = sam_adc_getreg(priv, SAM_ADC_CDR(chan));
(void)adc_receive(priv->dev, chan, regval & ADC_CDR_DATA_MASK);
/* Verify that the upper-half driver has bound its callback functions */
if (priv->cb != NULL)
{
/* Perform the data received callback */
DEBUGASSERT(priv->cb->au_receive != NULL);
priv->cb->au_receive(priv->dev, chan, regval & ADC_CDR_DATA_MASK);
}
pending &= ~bit;
}
}
@ -954,6 +975,26 @@ static int sam_adc_interrupt(int irq, void *context)
/****************************************************************************
* ADC methods
****************************************************************************/
/****************************************************************************
* Name: sam_adc_bind
*
* Description:
* Bind the upper-half driver callbacks to the lower-half implementation. This
* must be called early in order to receive ADC event notifications.
*
****************************************************************************/
static int sam_adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback)
{
struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
DEBUGASSERT(priv != NULL);
priv->cb = callback;
return OK;
}
/****************************************************************************
* Name: sam_adc_reset
*
@ -1980,6 +2021,7 @@ struct adc_dev_s *sam_adc_initialize(void)
/* Initialize the private ADC device data structure */
sem_init(&priv->exclsem, 0, 1);
priv->cb = NULL;
priv->dev = &g_adcdev;
#ifdef CONFIG_SAMA5_ADC_DMA

20
arch/arm/src/sama5/sam_config.h
View file

@ -52,27 +52,27 @@
* for our purposes.
*/
#ifndef CONFIG_USART0_ISUART
#ifndef CONFIG_USART0_SERIALDRIVER
# undef CONFIG_SAMA5_USART0
# undef CONFIG_SAMA5_FLEXCOM0_USART
# undef CONFIG_USART0_SERIAL_CONSOLE
#endif
#ifndef CONFIG_USART1_ISUART
#ifndef CONFIG_USART1_SERIALDRIVER
# undef CONFIG_SAMA5_USART1
# undef CONFIG_SAMA5_FLEXCOM1_USART
# undef CONFIG_USART1_SERIAL_CONSOLE
#endif
#ifndef CONFIG_USART2_ISUART
#ifndef CONFIG_USART2_SERIALDRIVER
# undef CONFIG_SAMA5_USART2
# undef CONFIG_SAMA5_FLEXCOM2_USART
# undef CONFIG_USART2_SERIAL_CONSOLE
#endif
#ifndef CONFIG_USART3_ISUART
#ifndef CONFIG_USART3_SERIALDRIVER
# undef CONFIG_SAMA5_USART3
# undef CONFIG_SAMA5_FLEXCOM3_USART
# undef CONFIG_USART3_SERIAL_CONSOLE
#endif
#ifndef CONFIG_USART4_ISUART
#ifndef CONFIG_USART4_SERIALDRIVER
# undef CONFIG_SAMA5_USART4
# undef CONFIG_SAMA5_FLEXCOM4_USART
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -212,7 +212,7 @@
# define SAMA5_HAVE_UART_CONSOLE 1
# undef SAMA5_HAVE_USART_CONSOLE
# undef SAMA5_HAVE_FLEXCOM_CONSOLE
#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_USART0_ISUART)
#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_USART0_SERIALDRIVER)
# undef CONFIG_SAMA5_DBGU_CONSOLE
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
@ -227,7 +227,7 @@
# undef SAMA5_HAVE_UART_CONSOLE
# define SAMA5_HAVE_USART_CONSOLE 1
# undef SAMA5_HAVE_FLEXCOM_CONSOLE
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_ISUART)
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_SERIALDRIVER)
# undef CONFIG_SAMA5_DBGU_CONSOLE
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
@ -242,7 +242,7 @@
# undef SAMA5_HAVE_UART_CONSOLE
# define SAMA5_HAVE_USART_CONSOLE 1
# undef SAMA5_HAVE_FLEXCOM_CONSOLE
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_ISUART)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_SERIALDRIVER)
# undef CONFIG_SAMA5_DBGU_CONSOLE
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
@ -257,7 +257,7 @@
# undef SAMA5_HAVE_UART_CONSOLE
# define SAMA5_HAVE_USART_CONSOLE 1
# undef SAMA5_HAVE_FLEXCOM_CONSOLE
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_ISUART)
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_SERIALDRIVER)
# undef CONFIG_SAMA5_DBGU_CONSOLE
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
@ -272,7 +272,7 @@
# undef SAMA5_HAVE_UART_CONSOLE
# define SAMA5_HAVE_USART_CONSOLE 1
# undef SAMA5_HAVE_FLEXCOM_CONSOLE
#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_USART4_ISUART)
#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_USART4_SERIALDRIVER)
# undef CONFIG_SAMA5_DBGU_CONSOLE
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE

78
arch/arm/src/sama5/sam_flexcom_serial.c
View file

@ -120,19 +120,19 @@
# define FLEXUS4_ASSIGNED 1
#else
# undef CONSOLE_DEV /* No console */
# if defined(CONFIG_USART0_ISUART)
# if defined(CONFIG_USART0_SERIALDRIVER)
# define TTYFC0_DEV g_flexus0port /* FLEXUS0 is ttyFC0 */
# define FLEXUS0_ASSIGNED 1
# elif defined(CONFIG_USART1_ISUART)
# elif defined(CONFIG_USART1_SERIALDRIVER)
# define TTYFC0_DEV g_flexus1port /* FLEXUS1 is ttyFC0 */
# define FLEXUS1_ASSIGNED 1
# elif defined(CONFIG_USART2_ISUART)
# elif defined(CONFIG_USART2_SERIALDRIVER)
# define TTYFC0_DEV g_flexus2port /* FLEXUS2 is ttyFC0 */
# define FLEXUS2_ASSIGNED 1
# elif defined(CONFIG_USART3_ISUART)
# elif defined(CONFIG_USART3_SERIALDRIVER)
# define TTYFC0_DEV g_flexus3port /* FLEXUS3 is ttyFC0 */
# define FLEXUS3_ASSIGNED 1
# elif defined(CONFIG_USART4_ISUART)
# elif defined(CONFIG_USART4_SERIALDRIVER)
# define TTYFC0_DEV g_flexus4port /* FLEXUS4 is ttyFC0 */
# define FLEXUS4_ASSIGNED 4
# endif
@ -140,19 +140,19 @@
/* Pick ttyFC1. This could be any of USART0-4 excluding the console UART. */
#if defined(CONFIG_USART0_ISUART) && !defined(FLEXUS0_ASSIGNED)
#if defined(CONFIG_USART0_SERIALDRIVER) && !defined(FLEXUS0_ASSIGNED)
# define TTYFC1_DEV g_flexus0port /* FLEXUS0 is ttyFC1 */
# define FLEXUS0_ASSIGNED 1
#elif defined(CONFIG_USART1_ISUART) && !defined(FLEXUS1_ASSIGNED)
#elif defined(CONFIG_USART1_SERIALDRIVER) && !defined(FLEXUS1_ASSIGNED)
# define TTYFC1_DEV g_flexus1port /* FLEXUS1 is ttyFC1 */
# define FLEXUS1_ASSIGNED 1
#elif defined(CONFIG_USART2_ISUART) && !defined(FLEXUS2_ASSIGNED)
#elif defined(CONFIG_USART2_SERIALDRIVER) && !defined(FLEXUS2_ASSIGNED)
# define TTYFC1_DEV g_flexus2port /* FLEXUS2 is ttyFC1 */
# define FLEXUS2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(FLEXUS3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(FLEXUS3_ASSIGNED)
# define TTYFC1_DEV g_flexus3port /* FLEXUS3 is ttyFC1 */
# define FLEXUS3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(FLEXUS4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(FLEXUS4_ASSIGNED)
# define TTYFC1_DEV g_flexus4port /* FLEXUS4 is ttyFC1 */
# define FLEXUS4_ASSIGNED 1
#endif
@ -162,16 +162,16 @@
* could also be the console.
*/
#if defined(CONFIG_USART1_ISUART) && !defined(FLEXUS1_ASSIGNED)
#if defined(CONFIG_USART1_SERIALDRIVER) && !defined(FLEXUS1_ASSIGNED)
# define TTYFC2_DEV g_flexus1port /* FLEXUS1 is ttyFC2 */
# define FLEXUS1_ASSIGNED 1
#elif defined(CONFIG_USART2_ISUART) && !defined(FLEXUS2_ASSIGNED)
#elif defined(CONFIG_USART2_SERIALDRIVER) && !defined(FLEXUS2_ASSIGNED)
# define TTYFC2_DEV g_flexus2port /* FLEXUS2 is ttyFC2 */
# define FLEXUS2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(FLEXUS3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(FLEXUS3_ASSIGNED)
# define TTYFC2_DEV g_flexus3port /* FLEXUS3 is ttyFC2 */
# define FLEXUS3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYFC2_DEV g_flexus4port /* FLEXUS4 is ttyFC2 */
# define FLEXUS4_ASSIGNED 1
#endif
@ -181,13 +181,13 @@
* FLEXUS2-4 could also be the console.
*/
#if defined(CONFIG_USART2_ISUART) && !defined(FLEXUS2_ASSIGNED)
#if defined(CONFIG_USART2_SERIALDRIVER) && !defined(FLEXUS2_ASSIGNED)
# define TTYFC3_DEV g_flexus2port /* FLEXUS2 is ttyFC3 */
# define FLEXUS2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(FLEXUS3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(FLEXUS3_ASSIGNED)
# define TTYFC3_DEV g_flexus3port /* FLEXUS3 is ttyFC3 */
# define FLEXUS3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(FLEXUS4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(FLEXUS4_ASSIGNED)
# define TTYFC3_DEV g_flexus4port /* FLEXUS4 is ttyFC3 */
# define FLEXUS4_ASSIGNED 1
#endif
@ -197,10 +197,10 @@
* USART3-4 could also be the console.
*/
#if defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#if defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYFC4_DEV g_flexus3port /* USART3 is ttyFC4 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYFC4_DEV g_flexus4port /* USART4 is ttyFC4 */
# define USART4_ASSIGNED 1
#endif
@ -234,19 +234,19 @@ struct flexus_dev_s
****************************************************************************/
static int flexus_interrupt(struct uart_dev_s *dev);
#ifdef CONFIG_USART0_ISUART
#ifdef CONFIG_USART0_SERIALDRIVER
static int flexus0_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_USART1_ISUART
#ifdef CONFIG_USART1_SERIALDRIVER
static int flexus1_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_USART2_ISUART
#ifdef CONFIG_USART2_SERIALDRIVER
static int flexus2_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_USART3_ISUART
#ifdef CONFIG_USART3_SERIALDRIVER
static int flexus3_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_USART4_ISUART
#ifdef CONFIG_USART4_SERIALDRIVER
static int flexus4_interrupt(int irq, void *context);
#endif
@ -288,30 +288,30 @@ static const struct uart_ops_s g_flexus_ops =
/* I/O buffers */
#ifdef CONFIG_USART0_ISUART
#ifdef CONFIG_USART0_SERIALDRIVER
static char g_flexus0rxbuffer[CONFIG_USART0_RXBUFSIZE];
static char g_flexus0txbuffer[CONFIG_USART0_TXBUFSIZE];
#endif
#ifdef CONFIG_USART1_ISUART
#ifdef CONFIG_USART1_SERIALDRIVER
static char g_flexus1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_flexus1txbuffer[CONFIG_USART1_TXBUFSIZE];
#endif
#ifdef CONFIG_USART2_ISUART
#ifdef CONFIG_USART2_SERIALDRIVER
static char g_flexus2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_flexus2txbuffer[CONFIG_USART2_TXBUFSIZE];
#endif
#ifdef CONFIG_USART3_ISUART
#ifdef CONFIG_USART3_SERIALDRIVER
static char g_flexus3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_flexus3txbuffer[CONFIG_USART3_TXBUFSIZE];
#endif
#ifdef CONFIG_USART4_ISUART
#ifdef CONFIG_USART4_SERIALDRIVER
static char g_flexus4rxbuffer[CONFIG_USART4_RXBUFSIZE];
static char g_flexus4txbuffer[CONFIG_USART4_TXBUFSIZE];
#endif
/* This describes the state of the USART0 port. */
#ifdef CONFIG_USART0_ISUART
#ifdef CONFIG_USART0_SERIALDRIVER
static struct flexus_dev_s g_flexus0priv =
{
.handler = flexus0_interrupt,
@ -345,7 +345,7 @@ static uart_dev_t g_flexus0port =
/* This describes the state of the USART1 port. */
#ifdef CONFIG_USART1_ISUART
#ifdef CONFIG_USART1_SERIALDRIVER
static struct flexus_dev_s g_flexus1priv =
{
.handler = flexus1_interrupt,
@ -379,7 +379,7 @@ static uart_dev_t g_flexus1port =
/* This describes the state of the USART2 port. */
#ifdef CONFIG_USART2_ISUART
#ifdef CONFIG_USART2_SERIALDRIVER
static struct flexus_dev_s g_flexus2priv =
{
.handler = flexus2_interrupt,
@ -413,7 +413,7 @@ static uart_dev_t g_flexus2port =
/* This describes the state of the USART3 port. */
#ifdef CONFIG_USART3_ISUART
#ifdef CONFIG_USART3_SERIALDRIVER
static struct flexus_dev_s g_flexus3priv =
{
.handler = flexus3_interrupt,
@ -447,7 +447,7 @@ static uart_dev_t g_flexus3port =
/* This describes the state of the USART4 port. */
#ifdef CONFIG_USART4_ISUART
#ifdef CONFIG_USART4_SERIALDRIVER
static struct flexus_dev_s g_flexus4priv =
{
.handler = flexus4_interrupt,
@ -613,31 +613,31 @@ static int flexus_interrupt(struct uart_dev_s *dev)
*
****************************************************************************/
#ifdef CONFIG_USART0_ISUART
#ifdef CONFIG_USART0_SERIALDRIVER
static int flexus0_interrupt(int irq, void *context)
{
return flexus_interrupt(&g_flexus0port);
}
#endif
#ifdef CONFIG_USART1_ISUART
#ifdef CONFIG_USART1_SERIALDRIVER
static int flexus1_interrupt(int irq, void *context)
{
return flexus_interrupt(&g_flexus1port);
}
#endif
#ifdef CONFIG_USART2_ISUART
#ifdef CONFIG_USART2_SERIALDRIVER
static int flexus2_interrupt(int irq, void *context)
{
return flexus_interrupt(&g_flexus2port);
}
#endif
#ifdef CONFIG_USART3_ISUART
#ifdef CONFIG_USART3_SERIALDRIVER
static int flexus3_interrupt(int irq, void *context)
{
return flexus_interrupt(&g_flexus3port);
}
#endif
#ifdef CONFIG_USART4_ISUART
#ifdef CONFIG_USART4_SERIALDRIVER
static int flexus4_interrupt(int irq, void *context)
{
return flexus_interrupt(&g_flexus4port);

22
arch/arm/src/sama5/sam_lowputc.c
View file

@ -379,7 +379,7 @@ void sam_lowsetup(void)
#ifdef CONFIG_SAMA5_UART4
sam_uart4_enableclk();
#endif
#ifdef CONFIG_USART0_ISUART
#ifdef CONFIG_USART0_SERIALDRIVER
sam_usart0_enableclk();
#endif
#ifdef CONFIG_SAMA5_USART1
@ -436,7 +436,7 @@ void sam_lowsetup(void)
(void)sam_configpio(PIO_UART4_TXD);
#endif
#if defined(CONFIG_USART0_ISUART) && defined(CONFIG_SAMA5_USART0)
#if defined(CONFIG_USART0_SERIALDRIVER) && defined(CONFIG_SAMA5_USART0)
(void)sam_configpio(PIO_USART0_RXD);
(void)sam_configpio(PIO_USART0_TXD);
#ifdef CONFIG_USART0_OFLOWCONTROL
@ -447,7 +447,7 @@ void sam_lowsetup(void)
#endif
#endif
#if defined(CONFIG_USART1_ISUART) && defined(CONFIG_SAMA5_USART1)
#if defined(CONFIG_USART1_SERIALDRIVER) && defined(CONFIG_SAMA5_USART1)
(void)sam_configpio(PIO_USART1_RXD);
(void)sam_configpio(PIO_USART1_TXD);
#ifdef CONFIG_USART1_OFLOWCONTROL
@ -458,7 +458,7 @@ void sam_lowsetup(void)
#endif
#endif
#if defined(CONFIG_USART2_ISUART) && defined(CONFIG_SAMA5_USART2)
#if defined(CONFIG_USART2_SERIALDRIVER) && defined(CONFIG_SAMA5_USART2)
(void)sam_configpio(PIO_USART2_RXD);
(void)sam_configpio(PIO_USART2_TXD);
#ifdef CONFIG_USART2_OFLOWCONTROL
@ -469,7 +469,7 @@ void sam_lowsetup(void)
#endif
#endif
#if defined(CONFIG_USART3_ISUART) && defined(CONFIG_SAMA5_USART3)
#if defined(CONFIG_USART3_SERIALDRIVER) && defined(CONFIG_SAMA5_USART3)
(void)sam_configpio(PIO_USART3_RXD);
(void)sam_configpio(PIO_USART3_TXD);
#ifdef CONFIG_USART3_OFLOWCONTROL
@ -480,7 +480,7 @@ void sam_lowsetup(void)
#endif
#endif
#if defined(CONFIG_USART4_ISUART) && defined(CONFIG_SAMA5_USART4)
#if defined(CONFIG_USART4_SERIALDRIVER) && defined(CONFIG_SAMA5_USART4)
(void)sam_configpio(PIO_USART4_RXD);
(void)sam_configpio(PIO_USART4_TXD);
#ifdef CONFIG_USART4_OFLOWCONTROL
@ -500,7 +500,7 @@ void sam_lowsetup(void)
* FLEXCOM_IO4 = RTS
*/
#if defined(CONFIG_USART0_ISUART) && defined(CONFIG_SAMA5_FLEXCOM0_USART)
#if defined(CONFIG_USART0_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM0_USART)
(void)sam_configpio(PIO_FLEXCOM0_IO0);
(void)sam_configpio(PIO_FLEXCOM0_IO1);
#ifdef CONFIG_USART0_OFLOWCONTROL
@ -511,7 +511,7 @@ void sam_lowsetup(void)
#endif
#endif
#if defined(CONFIG_USART1_ISUART) && defined(CONFIG_SAMA5_FLEXCOM1_USART)
#if defined(CONFIG_USART1_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM1_USART)
(void)sam_configpio(PIO_FLEXCOM1_IO0);
(void)sam_configpio(PIO_FLEXCOM1_IO1);
#ifdef CONFIG_USART1_OFLOWCONTROL
@ -522,7 +522,7 @@ void sam_lowsetup(void)
#endif
#endif
#if defined(CONFIG_USART2_ISUART) && defined(CONFIG_SAMA5_FLEXCOM2_USART)
#if defined(CONFIG_USART2_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM2_USART)
(void)sam_configpio(PIO_FLEXCOM2_IO0);
(void)sam_configpio(PIO_FLEXCOM2_IO1);
#ifdef CONFIG_USART2_OFLOWCONTROL
@ -533,7 +533,7 @@ void sam_lowsetup(void)
#endif
#endif
#if defined(CONFIG_USART3_ISUART) && defined(CONFIG_SAMA5_FLEXCOM3_USART)
#if defined(CONFIG_USART3_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM3_USART)
(void)sam_configpio(PIO_FLEXCOM3_IO0);
(void)sam_configpio(PIO_FLEXCOM3_IO1);
#ifdef CONFIG_USART3_OFLOWCONTROL
@ -544,7 +544,7 @@ void sam_lowsetup(void)
#endif
#endif
#if defined(CONFIG_USART4_ISUART) && defined(CONFIG_SAMA5_FLEXCOM4_USART)
#if defined(CONFIG_USART4_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM4_USART)
(void)sam_configpio(PIO_FLEXCOM4_IO0);
(void)sam_configpio(PIO_FLEXCOM4_IO1);
#ifdef CONFIG_USART4_OFLOWCONTROL

67
arch/arm/src/sama5/sam_oneshot.c
View file

@ -59,6 +59,7 @@
#include <nuttx/clock.h>
#include "sam_oneshot.h"
#include "sam_freerun.h"
#ifdef CONFIG_SAMA5_ONESHOT
@ -123,10 +124,11 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
/* Forward the event, clearing out any vestiges */
oneshot_handler = (oneshot_handler_t)oneshot->handler;
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
oneshot_handler = (oneshot_handler_t)oneshot->handler;
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
oneshot->start_count = 0;
oneshot_handler(oneshot_arg);
}
@ -223,10 +225,11 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
* success.
*/
oneshot->chan = chan;
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
oneshot->chan = chan;
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
oneshot->start_count = 0;
return OK;
}
@ -250,8 +253,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
void *arg, const struct timespec *ts)
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@ -269,7 +272,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
/* Yes.. then cancel it */
tcvdbg("Already running... cancelling\n");
(void)sam_oneshot_cancel(oneshot, NULL);
(void)sam_oneshot_cancel(oneshot, freerun, NULL);
}
/* Save the new handler and its argument */
@ -308,6 +311,26 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
sam_tc_start(oneshot->tch);
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
* software trigger, which starts the clock and sets the counter
* register to zero. This reset is performed with the next valid edge
* of the selected clock. Thus it can take up USEC_PER_TICK microseconds
* until the counter register becomes zero.
*
* If the timer is canceled within this period the counter register holds
* the counter value for the last timer/counter run. To circumvent this
* the counter value of the freerun timer/counter is stored at each start
* of the oneshot timer/counter.
*
* The function up_timer_gettime() could also be used for this but it takes
* too long. If up_timer_gettime() is called within this function the problem
* vanishes at least if compiled with no optimisation.
*/
oneshot->start_count = sam_tc_getcounter(freerun->tch);
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
*/
@ -342,7 +365,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts)
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@ -383,6 +407,17 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts)
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
/* Now we can disable the interrupt and stop the timer. */
sam_tc_attach(oneshot->tch, NULL, NULL, 0);
@ -431,6 +466,14 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts)
usec = (((uint64_t)(rc - count)) * USEC_PER_SEC) /
sam_tc_divfreq(oneshot->tch);
/* Each time the timer/counter is canceled the time calculated from
* the two registers (counter and REGC) is accurate up to an error
* between 0 and USEC_PER_TICK microseconds. To correct this error
* one tick which means USEC_PER_TICK microseconds are subtracted.
*/
usec = usec > USEC_PER_TICK ? usec - USEC_PER_TICK : 0;
/* Return the time remaining in the correct form */
sec = usec / USEC_PER_SEC;

19
arch/arm/src/sama5/sam_oneshot.h
View file

@ -46,6 +46,7 @@
#include <time.h>
#include "sam_tc.h"
#include "sam_freerun.h"
#ifdef CONFIG_SAMA5_ONESHOT
@ -82,6 +83,11 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
};
/****************************************************************************
@ -134,6 +140,9 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@ -144,8 +153,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
void *arg, const struct timespec *ts);
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@ -160,6 +169,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
* sam_freerun_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@ -171,7 +183,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts);
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus

128
arch/arm/src/sama5/sam_serial.c
View file

@ -167,19 +167,19 @@
# elif defined(CONFIG_SAMA5_UART4)
# define TTYS0_DEV g_uart1port /* UART4 is ttyS0 */
# define UART4_ASSIGNED 1
# elif defined(CONFIG_USART0_ISUART)
# elif defined(CONFIG_USART0_SERIALDRIVER)
# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */
# define USART0_ASSIGNED 1
# elif defined(CONFIG_USART1_ISUART)
# elif defined(CONFIG_USART1_SERIALDRIVER)
# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */
# define USART1_ASSIGNED 1
# elif defined(CONFIG_USART2_ISUART)
# elif defined(CONFIG_USART2_SERIALDRIVER)
# define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */
# define USART2_ASSIGNED 1
# elif defined(CONFIG_USART3_ISUART)
# elif defined(CONFIG_USART3_SERIALDRIVER)
# define TTYS0_DEV g_usart3port /* USART3 is ttyS0 */
# define USART3_ASSIGNED 1
# elif defined(CONFIG_USART4_ISUART)
# elif defined(CONFIG_USART4_SERIALDRIVER)
# define TTYS0_DEV g_usart4port /* USART4 is ttyS0 */
# define USART4_ASSIGNED 4
# endif
@ -202,19 +202,19 @@
#elif defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED)
# define TTYS1_DEV g_uart1port /* UART4 is ttyS1 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_USART0_ISUART) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_USART0_SERIALDRIVER) && !defined(USART0_ASSIGNED)
# define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_USART1_ISUART) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_USART1_SERIALDRIVER) && !defined(USART1_ASSIGNED)
# define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_USART2_ISUART) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_USART2_SERIALDRIVER) && !defined(USART2_ASSIGNED)
# define TTYS1_DEV g_usart2port /* USART2 is ttyS1 */
# define USART2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYS1_DEV g_usart3port /* USART3 is ttyS1 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYS1_DEV g_usart4port /* USART4 is ttyS1 */
# define USART4_ASSIGNED 1
#endif
@ -236,19 +236,19 @@
#elif defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED)
# define TTYS2_DEV g_uart1port /* UART4 is ttyS2 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_USART0_ISUART) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_USART0_SERIALDRIVER) && !defined(USART0_ASSIGNED)
# define TTYS2_DEV g_usart0port /* USART0 is ttyS2 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_USART1_ISUART) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_USART1_SERIALDRIVER) && !defined(USART1_ASSIGNED)
# define TTYS2_DEV g_usart1port /* USART1 is ttyS2 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_USART2_ISUART) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_USART2_SERIALDRIVER) && !defined(USART2_ASSIGNED)
# define TTYS2_DEV g_usart2port /* USART2 is ttyS2 */
# define USART2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYS2_DEV g_usart3port /* USART3 is ttyS2 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYS2_DEV g_usart4port /* USART4 is ttyS2 */
# define USART4_ASSIGNED 1
#endif
@ -267,19 +267,19 @@
#elif defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED)
# define TTYS3_DEV g_uart1port /* UART4 is ttyS3 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_USART0_ISUART) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_USART0_SERIALDRIVER) && !defined(USART0_ASSIGNED)
# define TTYS3_DEV g_usart0port /* USART0 is ttyS3 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_USART1_ISUART) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_USART1_SERIALDRIVER) && !defined(USART1_ASSIGNED)
# define TTYS3_DEV g_usart1port /* USART1 is ttyS3 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_USART2_ISUART) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_USART2_SERIALDRIVER) && !defined(USART2_ASSIGNED)
# define TTYS3_DEV g_usart2port /* USART2 is ttyS3 */
# define USART2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYS3_DEV g_usart3port /* USART3 is ttyS3 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYS3_DEV g_usart4port /* USART4 is ttyS3 */
# define USART4_ASSIGNED 1
#endif
@ -295,19 +295,19 @@
#elif defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED)
# define TTYS4_DEV g_uart1port /* UART4 is ttyS4 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_USART0_ISUART) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_USART0_SERIALDRIVER) && !defined(USART0_ASSIGNED)
# define TTYS4_DEV g_usart0port /* USART0 is ttyS4 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_USART1_ISUART) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_USART1_SERIALDRIVER) && !defined(USART1_ASSIGNED)
# define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_USART2_ISUART) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_USART2_SERIALDRIVER) && !defined(USART2_ASSIGNED)
# define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */
# define USART2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYS4_DEV g_usart3port /* USART3 is ttyS4 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYS4_DEV g_usart4port /* USART4 is ttyS4 */
# define USART4_ASSIGNED 1
#endif
@ -320,19 +320,19 @@
#if defined(CONFIG_SAMA5_UART4) && !defined(UART4_ASSIGNED)
# define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */
# define UART1_ASSIGNED 1
#elif defined(CONFIG_USART0_ISUART) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_USART0_SERIALDRIVER) && !defined(USART0_ASSIGNED)
# define TTYS5_DEV g_usart0port /* USART0 is ttyS5 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_USART1_ISUART) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_USART1_SERIALDRIVER) && !defined(USART1_ASSIGNED)
# define TTYS5_DEV g_usart1port /* USART1 is ttyS5 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_USART2_ISUART) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_USART2_SERIALDRIVER) && !defined(USART2_ASSIGNED)
# define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */
# define USART2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYS5_DEV g_usart3port /* USART3 is ttyS5 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYS5_DEV g_usart4port /* USART4 is ttyS5 */
# define USART4_ASSIGNED 1
#endif
@ -342,19 +342,19 @@
* could also be the console.
*/
#if defined(CONFIG_USART0_ISUART) && !defined(USART0_ASSIGNED)
#if defined(CONFIG_USART0_SERIALDRIVER) && !defined(USART0_ASSIGNED)
# define TTYS6_DEV g_usart0port /* USART0 is ttyS6 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_USART1_ISUART) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_USART1_SERIALDRIVER) && !defined(USART1_ASSIGNED)
# define TTYS6_DEV g_usart1port /* USART1 is ttyS6 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_USART2_ISUART) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_USART2_SERIALDRIVER) && !defined(USART2_ASSIGNED)
# define TTYS6_DEV g_usart2port /* USART2 is ttyS6 */
# define USART2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYS6_DEV g_usart3port /* USART3 is ttyS6 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYS6_DEV g_usart4port /* USART4 is ttyS6 */
# define USART4_ASSIGNED 1
#endif
@ -364,16 +364,16 @@
* USART1-4 could also be the console.
*/
#if defined(CONFIG_USART1_ISUART) && !defined(USART1_ASSIGNED)
#if defined(CONFIG_USART1_SERIALDRIVER) && !defined(USART1_ASSIGNED)
# define TTYS7_DEV g_usart1port /* USART1 is ttyS7 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_USART2_ISUART) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_USART2_SERIALDRIVER) && !defined(USART2_ASSIGNED)
# define TTYS7_DEV g_usart2port /* USART2 is ttyS7 */
# define USART2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYS7_DEV g_usart3port /* USART3 is ttyS7 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYS7_DEV g_usart4port /* USART4 is ttyS7 */
# define USART4_ASSIGNED 1
#endif
@ -383,13 +383,13 @@
* USART2-4 could also be the console.
*/
#if defined(CONFIG_USART2_ISUART) && !defined(USART2_ASSIGNED)
#if defined(CONFIG_USART2_SERIALDRIVER) && !defined(USART2_ASSIGNED)
# define TTYS8_DEV g_usart2port /* USART2 is ttyS8 */
# define USART2_ASSIGNED 1
#elif defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#elif defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYS8_DEV g_usart3port /* USART3 is ttyS8 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYS8_DEV g_usart4port /* USART4 is ttyS8 */
# define USART4_ASSIGNED 1
#endif
@ -399,10 +399,10 @@
* USART3-4 could also be the console.
*/
#if defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED)
#if defined(CONFIG_USART3_SERIALDRIVER) && !defined(USART3_ASSIGNED)
# define TTYS9_DEV g_usart3port /* USART3 is ttyS9 */
# define USART3_ASSIGNED 1
#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED)
#elif defined(CONFIG_USART4_SERIALDRIVER) && !defined(USART4_ASSIGNED)
# define TTYS9_DEV g_usart4port /* USART4 is ttyS9 */
# define USART4_ASSIGNED 1
#endif
@ -451,19 +451,19 @@ static int up_uart3_interrupt(int irq, void *context);
#ifdef CONFIG_SAMA5_UART4
static int up_uart4_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_USART0_ISUART
#ifdef CONFIG_USART0_SERIALDRIVER
static int up_usart0_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_USART1_ISUART
#ifdef CONFIG_USART1_SERIALDRIVER
static int up_usart1_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_USART2_ISUART
#ifdef CONFIG_USART2_SERIALDRIVER
static int up_usart2_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_USART3_ISUART
#ifdef CONFIG_USART3_SERIALDRIVER
static int up_usart3_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_USART4_ISUART
#ifdef CONFIG_USART4_SERIALDRIVER
static int up_usart4_interrupt(int irq, void *context);
#endif
@ -525,23 +525,23 @@ static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
#endif
#ifdef CONFIG_USART0_ISUART
#ifdef CONFIG_USART0_SERIALDRIVER
static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE];
static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE];
#endif
#ifdef CONFIG_USART1_ISUART
#ifdef CONFIG_USART1_SERIALDRIVER
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
#endif
#ifdef CONFIG_USART2_ISUART
#ifdef CONFIG_USART2_SERIALDRIVER
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
#endif
#ifdef CONFIG_USART3_ISUART
#ifdef CONFIG_USART3_SERIALDRIVER
static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
#endif
#ifdef CONFIG_USART4_ISUART
#ifdef CONFIG_USART4_SERIALDRIVER
static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE];
static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE];
#endif
@ -753,7 +753,7 @@ static uart_dev_t g_uart4port =
/* This describes the state of the USART0 port. */
#ifdef CONFIG_USART0_ISUART
#ifdef CONFIG_USART0_SERIALDRIVER
static struct up_dev_s g_usart0priv =
{
.handler = up_usart0_interrupt,
@ -787,7 +787,7 @@ static uart_dev_t g_usart0port =
/* This describes the state of the USART1 port. */
#ifdef CONFIG_USART1_ISUART
#ifdef CONFIG_USART1_SERIALDRIVER
static struct up_dev_s g_usart1priv =
{
.handler = up_usart1_interrupt,
@ -821,7 +821,7 @@ static uart_dev_t g_usart1port =
/* This describes the state of the USART2 port. */
#ifdef CONFIG_USART2_ISUART
#ifdef CONFIG_USART2_SERIALDRIVER
static struct up_dev_s g_usart2priv =
{
.handler = up_usart2_interrupt,
@ -855,7 +855,7 @@ static uart_dev_t g_usart2port =
/* This describes the state of the USART3 port. */
#ifdef CONFIG_USART3_ISUART
#ifdef CONFIG_USART3_SERIALDRIVER
static struct up_dev_s g_usart3priv =
{
.handler = up_usart3_interrupt,
@ -889,7 +889,7 @@ static uart_dev_t g_usart3port =
/* This describes the state of the USART4 port. */
#ifdef CONFIG_USART4_ISUART
#ifdef CONFIG_USART4_SERIALDRIVER
static struct up_dev_s g_usart4priv =
{
.handler = up_usart4_interrupt,
@ -1073,31 +1073,31 @@ static int up_uart4_interrupt(int irq, void *context)
return up_interrupt(&g_uart4port);
}
#endif
#ifdef CONFIG_USART0_ISUART
#ifdef CONFIG_USART0_SERIALDRIVER
static int up_usart0_interrupt(int irq, void *context)
{
return up_interrupt(&g_usart0port);
}
#endif
#ifdef CONFIG_USART1_ISUART
#ifdef CONFIG_USART1_SERIALDRIVER
static int up_usart1_interrupt(int irq, void *context)
{
return up_interrupt(&g_usart1port);
}
#endif
#ifdef CONFIG_USART2_ISUART
#ifdef CONFIG_USART2_SERIALDRIVER
static int up_usart2_interrupt(int irq, void *context)
{
return up_interrupt(&g_usart2port);
}
#endif
#ifdef CONFIG_USART3_ISUART
#ifdef CONFIG_USART3_SERIALDRIVER
static int up_usart3_interrupt(int irq, void *context)
{
return up_interrupt(&g_usart3port);
}
#endif
#ifdef CONFIG_USART4_ISUART
#ifdef CONFIG_USART4_SERIALDRIVER
static int up_usart4_interrupt(int irq, void *context)
{
return up_interrupt(&g_usart4port);

6
arch/arm/src/sama5/sam_tickless.c
View file

@ -377,8 +377,8 @@ int up_timer_gettime(FAR struct timespec *ts)
int up_timer_cancel(FAR struct timespec *ts)
{
return ONESHOT_INITIALIZED(&g_tickless.oneshot) ?
sam_oneshot_cancel(&g_tickless.oneshot, ts) :
return ONESHOT_INITIALIZED(&g_tickless.oneshot) && FREERUN_INITIALIZED(&g_tickless.freerun) ?
sam_oneshot_cancel(&g_tickless.oneshot, &g_tickless.freerun, ts) :
-EAGAIN;
}
@ -410,7 +410,7 @@ int up_timer_cancel(FAR struct timespec *ts)
int up_timer_start(FAR const struct timespec *ts)
{
return ONESHOT_INITIALIZED(&g_tickless.oneshot) ?
sam_oneshot_start(&g_tickless.oneshot, sam_oneshot_handler, NULL, ts) :
sam_oneshot_start(&g_tickless.oneshot, &g_tickless.freerun, sam_oneshot_handler, NULL, ts) :
-EAGAIN;
}
#endif /* CONFIG_SCHED_TICKLESS */

1
arch/arm/src/sama5/sam_twi.c
View file

@ -1200,6 +1200,7 @@ static void twi_hw_initialize(struct twi_dev_s *priv, uint32_t frequency)
/* Set the initial TWI data transfer frequency */
priv->frequency = 0;
twi_setfrequency(priv, frequency);
/* Enable Interrupts */

4
arch/arm/src/sama5/sam_wdt.c
View file

@ -648,7 +648,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
****************************************************************************/
/****************************************************************************
* Name: up_wdginitialize
* Name: sam_wdt_initialize
*
* Description:
* Initialize the WDT watchdog time. The watchdog timer is initialized and
@ -663,7 +663,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
*
****************************************************************************/
int up_wdginitialize(void)
int sam_wdt_initialize(void)
{
FAR struct sam_lowerhalf_s *priv = &g_wdtdev;

22
arch/arm/src/sama5/sam_wdt.h
View file

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/sama5/sam_wdt.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -66,6 +66,26 @@ extern "C"
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_wdt_initialize()
*
* Description:
* Perform architecture-specific initialization of the Watchdog hardware.
* This interface should be provided by all configurations using
* to avoid exposed platform-dependent logic.
*
* At a minimum, this function should call watchdog_register().
*
* Input parameters:
* None
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
int sam_wdt_initialize(void);
#undef EXTERN
#if defined(__cplusplus)
}

18
arch/arm/src/samdl/Kconfig
View file

@ -589,8 +589,7 @@ config SAMDL_SERCOM0_ISSPI
config SAMDL_SERCOM0_ISUSART
bool "USART"
select ARCH_HAVE_USART0
select USART0_ISUART
select USART0_SERIALDRIVER
endchoice
@ -623,8 +622,7 @@ config SAMDL_SERCOM1_ISSPI
config SAMDL_SERCOM1_ISUSART
bool "USART"
select ARCH_HAVE_USART1
select USART1_ISUART
select USART1_SERIALDRIVER
endchoice
@ -643,8 +641,7 @@ config SAMDL_SERCOM2_ISSPI
config SAMDL_SERCOM2_ISUSART
bool "USART"
select ARCH_HAVE_USART2
select USART2_ISUART
select USART2_SERIALDRIVER
endchoice
@ -663,8 +660,7 @@ config SAMDL_SERCOM3_ISSPI
config SAMDL_SERCOM3_ISUSART
bool "USART"
select ARCH_HAVE_USART3
select USART3_ISUART
select USART3_SERIALDRIVER
endchoice
@ -683,8 +679,7 @@ config SAMDL_SERCOM4_ISSPI
config SAMDL_SERCOM4_ISUSART
bool "USART"
select ARCH_HAVE_USART4
select USART4_ISUART
select USART4_SERIALDRIVER
endchoice
@ -703,8 +698,7 @@ config SAMDL_SERCOM5_ISSPI
config SAMDL_SERCOM5_ISUSART
bool "USART"
select ARCH_HAVE_USART5
select USART5_ISUART
select USART5_SERIALDRIVER
endchoice

12
arch/arm/src/samdl/sam_config.h
View file

@ -56,7 +56,7 @@
#define SAMDL_HAVE_USART5 1
#if !defined(CONFIG_SAMDL_SERCOM0) || !defined(CONFIG_SAMDL_SERCOM0_ISUSART) || \
!defined(CONFIG_USART0_ISUART)
!defined(CONFIG_USART0_SERIALDRIVER)
# undef SAMDL_HAVE_USART0
# undef CONFIG_SAMDL_SERCOM0_ISUSART
# undef CONFIG_USART0_SERIAL_CONSOLE
@ -66,7 +66,7 @@
#endif
#if !defined(CONFIG_SAMDL_SERCOM1) || !defined(CONFIG_SAMDL_SERCOM1_ISUSART) || \
!defined(CONFIG_USART1_ISUART)
!defined(CONFIG_USART1_SERIALDRIVER)
# undef SAMDL_HAVE_USART1
# undef CONFIG_SAMDL_SERCOM1_ISUSART
# undef CONFIG_USART1_SERIAL_CONSOLE
@ -76,7 +76,7 @@
#endif
#if !defined(CONFIG_SAMDL_SERCOM2) || !defined(CONFIG_SAMDL_SERCOM2_ISUSART) || \
!defined(CONFIG_USART2_ISUART)
!defined(CONFIG_USART2_SERIALDRIVER)
# undef SAMDL_HAVE_USART2
# undef CONFIG_SAMDL_SERCOM2_ISUSART
# undef CONFIG_USART2_SERIAL_CONSOLE
@ -86,7 +86,7 @@
#endif
#if !defined(CONFIG_SAMDL_SERCOM3) || !defined(CONFIG_SAMDL_SERCOM3_ISUSART) || \
!defined(CONFIG_USART3_ISUART)
!defined(CONFIG_USART3_SERIALDRIVER)
# undef SAMDL_HAVE_USART3
# undef CONFIG_SAMDL_SERCOM3_ISUSART
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -96,7 +96,7 @@
#endif
#if !defined(CONFIG_SAMDL_SERCOM4) || !defined(CONFIG_SAMDL_SERCOM4_ISUSART) || \
!defined(CONFIG_USART4_ISUART)
!defined(CONFIG_USART4_SERIALDRIVER)
# undef SAMDL_HAVE_USART4
# undef CONFIG_SAMDL_SERCOM4_ISUSART
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -106,7 +106,7 @@
#endif
#if !defined(CONFIG_SAMDL_SERCOM5) || !defined(CONFIG_SAMDL_SERCOM5_ISUSART) || \
!defined(CONFIG_USART5_ISUART)
!defined(CONFIG_USART5_SERIALDRIVER)
# undef SAMDL_HAVE_USART5
# undef CONFIG_SAMDL_SERCOM5_ISUSART
# undef CONFIG_USART5_SERIAL_CONSOLE

108
arch/arm/src/samv7/Kconfig
View file

@ -465,31 +465,31 @@ config SAMV7_TWIHS2
config SAMV7_UART0
bool "UART 0"
default y
select ARCH_HAVE_UART0
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMV7_UART1
bool "UART 1"
default n
select ARCH_HAVE_UART1
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMV7_UART2
bool "UART 2"
default y
select ARCH_HAVE_UART2
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMV7_UART3
bool "UART 3"
default n
select ARCH_HAVE_UART3
select UART3_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMV7_UART4
bool "UART 4"
default y
select ARCH_HAVE_UART4
select UART4_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMV7_USBDEVFS
@ -520,21 +520,21 @@ config SAMV7_USART0
bool "USART 0"
default n
depends on SAMV7_HAVE_USART0
select ARCH_HAVE_USART0
select USART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMV7_USART1
bool "USART 1"
default n
depends on SAMV7_HAVE_USART1
select ARCH_HAVE_USART1
select USART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMV7_USART2
bool "USART 2"
default n
depends on SAMV7_HAVE_USART2
select ARCH_HAVE_USART2
select USART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config SAMV7_WDT
@ -549,6 +549,97 @@ config SAMV7_RSWDT
endmenu # SAMV7 Peripheral Selection
choice
prompt "JTAG IO Configuration"
default SAMV7_JTAG_FULL_ENABLE
---help---
JTAG Enable settings (by default the IO for JTAG-DP and SW-DP are
enabled)
config SAMV7_JTAG_DISABLE
bool "Disable all JTAG IO"
---help---
JTAG Enable settings (by default the IO for JTAG-DP and SW-DP are
enabled)
When JTAG is disabled PB4-BP7 is assigned as a GPIO and can be
configured for use as GPIO or a Peripheral
config SAMV7_JTAG_FULL_ENABLE
bool "Enable full JTAG IO to use JTAG-DP + SW-DP"
---help---
The JTAG IO is configured for both JTAG-DP + SW-DP"
PB4 is TDI
PB5 is TDO/TRACESWO
PB6 is TMS/SWDIO
PB7 is TCK/SWCLK
config SAMV7_JTAG_FULL_SW_ENABLE
bool "Set JTAG-DP IO disabled and Full SW-DP IO enabled"
---help---
JTAG IO is configured for SW-DP with Trace"
PB5 is TDO/TRACESWO
PB6 is TMS/SWDIO
PB7 is TCK/SWCLK
config SAMV7_JTAG_SW_ENABLE
bool "Set JTAG-DP IO disabled and SW-DP IO enabled"
---help---
JTAG IO is configured for SW-DP without Trace "
PB6 is TMS/SWDIO
PB7 is TCK/SWCLK
endchoice # JTAG IO Configuration
choice
prompt "ERASE Pin Configuration"
default SAMV7_ERASE_ENABLE
---help---
ERASE Pin Enable settings (by default ERASE pin is enabled)
config SAMV7_ERASE_DISABLE
bool "Disable ERASE Pin"
---help---
ERASE Pin Enable settings (by default ERASE pin is enabled)
When the ERASE pin is disabled PB12 is assigned as a GPIO and can be
configured for use as GPIO or a Peripheral.
N.B. a low level must be ensured at startup to prevent Flash erase before
the user application sets PB12 into PIO mode,
config SAMV7_ERASE_ENABLE
bool "Enable ERASE Pin"
---help---
The ERASE pin is configured to reinitialize the Flash content.
endchoice
menuconfig SAMV7_SYSTEMRESET
bool "Enable System Reset"
select ARCH_HAVE_RESET
---help---
Enable up_systemreset
if SAMV7_SYSTEMRESET
config SAMV7_EXTRESET_ERST
int "Drive External nRST duration"
default 0
range 0 16
---help---
Define if the external reset (nRST) will be generated in up_systemreset
and for how long:
- A value of 0 will not drive the external reset
- A value of 1-6 will drive the external reset for 2^SAMV7_EXTRESET_ERST
slow clock cycles.
endif # SAMV7_SYSTEMRESET
menuconfig SAMV7_GPIO_IRQ
bool "GPIO pin interrupts"
---help---
@ -1423,6 +1514,7 @@ endif # SAMV7_TC3
config SAMV7_ONESHOT
bool "TC one-shot wrapper"
depends on SAMV7_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---

4
arch/arm/src/samv7/Make.defs
View file

@ -150,6 +150,10 @@ ifeq ($(CONFIG_SAMV7_RSWDT),y)
CHIP_CSRCS += sam_rswdt.c
endif
ifeq ($(CONFIG_SAMV7_SYSTEMRESET),y)
CHIP_CSRCS += sam_systemreset.c
endif
ifeq ($(CONFIG_SAMV7_SPI_MASTER),y)
CHIP_CSRCS += sam_spi.c
endif

6
arch/arm/src/samv7/sam_config.h
View file

@ -113,19 +113,19 @@
* enabled for our purposes.
*/
#if !defined(CONFIG_USART0_ISUART) && !defined(CONFIG_USART0_ISSPI)
#if !defined(CONFIG_USART0_SERIALDRIVER) && !defined(CONFIG_USART0_ISSPI)
# undef CONFIG_SAMV7_USART0
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART0_IFLOWCONTROL
#endif
#if !defined(CONFIG_USART1_ISUART) && !defined(CONFIG_USART1_ISSPI)
#if !defined(CONFIG_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_ISSPI)
# undef CONFIG_SAMV7_USART1
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART1_IFLOWCONTROL
#endif
#if !defined(CONFIG_USART2_ISUART) && !defined(CONFIG_USART2_ISSPI)
#if !defined(CONFIG_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_ISSPI)
# undef CONFIG_SAMV7_USART2
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART2_IFLOWCONTROL

54
arch/arm/src/samv7/sam_gpio.c
View file

@ -54,14 +54,33 @@
#include "sam_gpio.h"
#include "chip/sam_pio.h"
#include "chip/sam_matrix.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \
!defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
# if defined(CONFIG_SAMV7_ERASE_DISABLE)
# define SYSIO_ERASE_BIT MATRIX_CCFG_SYSIO_SYSIO12
# else
# define SYSIO_ERASE_BIT 0
# endif
# if defined(CONFIG_SAMV7_JTAG_DISABLE)
# define SYSIO_BITS (MATRIX_CCFG_SYSIO_SYSIO4 | MATRIX_CCFG_SYSIO_SYSIO5 | \
MATRIX_CCFG_SYSIO_SYSIO6 | MATRIX_CCFG_SYSIO_SYSIO7)
# endif
# if defined(CONFIG_SAMV7_JTAG_FULL_SW_ENABLE)
# define SYSIO_BITS MATRIX_CCFG_SYSIO_SYSIO4
# endif
# if defined(CONFIG_SAMV7_JTAG_SW_ENABLE)
# define SYSIO_BITS (MATRIX_CCFG_SYSIO_SYSIO4 | MATRIX_CCFG_SYSIO_SYSIO5)
# endif
#endif
#if !defined(SYSIO_BITS)
# define SYSIO_BITS 0
#endif
/****************************************************************************
* Private Data
@ -70,7 +89,7 @@
#ifdef CONFIG_DEBUG_GPIO
static const char g_portchar[SAMV7_NPIO] =
{
'A'
'A'
#if SAMV7_NPIO > 1
, 'B'
#endif
@ -402,6 +421,33 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: sam_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Configures the CCFG_SYSIO bits.
*
* Typically called from sam_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
* no mutual exlusion is necessary.
*
****************************************************************************/
#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \
!defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
void sam_gpioinit(void)
{
uint32_t regval;
regval = getreg32(SAM_MATRIX_CCFG_SYSIO);
regval |= (SYSIO_ERASE_BIT | SYSIO_BITS);
putreg32(regval, SAM_MATRIX_CCFG_SYSIO);
}
#endif
/****************************************************************************
* Name: sam_configgpio
*

18
arch/arm/src/samv7/sam_gpio.h
View file

@ -265,6 +265,24 @@ static inline int sam_gpio_pinmask(gpio_pinset_t cfgset)
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Function: sam_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions for GPIO.
*
* Typically called from sam_start().
*
************************************************************************************/
#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \
!defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
void sam_gpioinit(void);
#else
# define sam_gpioinit()
#endif
/************************************************************************************
* Name: sam_gpioirqinitialize
*

17
arch/arm/src/samv7/sam_lowputc.c
View file

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samv7/sam_lowputc.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -348,19 +348,26 @@ void sam_lowsetup(void)
#ifdef CONFIG_SAMV7_USART1
(void)sam_configgpio(GPIO_USART1_RXD);
(void)sam_configgpio(GPIO_USART1_TXD);
#ifdef CONFIG_USART1_OFLOWCONTROL
# ifdef CONFIG_USART1_OFLOWCONTROL
(void)sam_configgpio(GPIO_USART1_CTS);
#endif
#ifdef CONFIG_USART1_IFLOWCONTROL
# endif
# ifdef CONFIG_USART1_IFLOWCONTROL
(void)sam_configgpio(GPIO_USART1_RTS);
#endif
# endif
/* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4
* instead of TDI
*/
# if defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
# warning CONFIG_SAMV7_JTAG_FULL_ENABLE is incompatible with CONFIG_SAMV7_USART1.
# warning The SYSIO Pin4 must be bound to PB4 to use USART1
# endif
uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO);
sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4;
putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO);
#endif
#ifdef CONFIG_SAMV7_USART2

67
arch/arm/src/samv7/sam_oneshot.c
View file

@ -60,6 +60,7 @@
#include <nuttx/clock.h>
#include "sam_oneshot.h"
#include "sam_freerun.h"
#ifdef CONFIG_SAMV7_ONESHOT
@ -124,10 +125,11 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
/* Forward the event, clearing out any vestiges */
oneshot_handler = (oneshot_handler_t)oneshot->handler;
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
oneshot_handler = (oneshot_handler_t)oneshot->handler;
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
oneshot->start_count = 0;
oneshot_handler(oneshot_arg);
}
@ -224,10 +226,11 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
* success.
*/
oneshot->chan = chan;
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
oneshot->chan = chan;
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
oneshot->start_count = 0;
return OK;
}
@ -251,8 +254,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
void *arg, const struct timespec *ts)
int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
oneshot_handler_t handler, void *arg, const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@ -270,7 +273,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
/* Yes.. then cancel it */
tcvdbg("Already running... cancelling\n");
(void)sam_oneshot_cancel(oneshot, NULL);
(void)sam_oneshot_cancel(oneshot, freerun, NULL);
}
/* Save the new handler and its argument */
@ -309,6 +312,26 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
sam_tc_start(oneshot->tch);
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
* software trigger, which starts the clock and sets the counter
* register to zero. This reset is performed with the next valid edge
* of the selected clock. Thus it can take up USEC_PER_TICK microseconds
* until the counter register becomes zero.
*
* If the timer is canceled within this period the counter register holds
* the counter value for the last timer/counter run. To circumvent this
* the counter value of the freerun timer/counter is stored at each start
* of the oneshot timer/counter.
*
* The function up_timer_gettime() could also be used for this but it takes
* too long. If up_timer_gettime() is called within this function the problem
* vanishes at least if compiled with no optimisation.
*/
oneshot->start_count = sam_tc_getcounter(freerun->tch);
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
*/
@ -343,7 +366,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, oneshot_handler_t handler,
*
****************************************************************************/
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts)
int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@ -384,6 +408,17 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts)
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
/* Now we can disable the interrupt and stop the timer. */
sam_tc_attach(oneshot->tch, NULL, NULL, 0);
@ -432,6 +467,14 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct timespec *ts)
usec = (((uint64_t)(rc - count)) * USEC_PER_SEC) /
sam_tc_divfreq(oneshot->tch);
/* Each time the timer/counter is canceled the time calculated from
* the two registers (counter and REGC) is accurate up to an error
* between 0 and USEC_PER_TICK microseconds. To correct this error
* one tick which means USEC_PER_TICK microseconds are subtracted.
*/
usec = usec > USEC_PER_TICK ? usec - USEC_PER_TICK : 0;
/* Return the time remaining in the correct form */
sec = usec / USEC_PER_SEC;

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