diff --git a/arch/arm/src/bcm2708/bcm_gpio.c b/arch/arm/src/bcm2708/bcm_gpio.c index bb367fcbc0d..63b6625aee9 100644 --- a/arch/arm/src/bcm2708/bcm_gpio.c +++ b/arch/arm/src/bcm2708/bcm_gpio.c @@ -39,9 +39,120 @@ #include +#include + +#include + +#include "up_arch.h" #include "bcm_config.h" +#include "chip/bcm2708_gpio.h" #include "bcm_gpio.h" +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Function: bcm_gpio_fsel + * + * Description: + * Set the FSEL field for the given pin. + * + ************************************************************************************/ + +static void bcm_gpio_fsel(unsigned int pin, uint8_t mode) +{ + uintptr_t regaddr = BCM_GPIO_GPFSEL(pin); + uint32_t clrbits = BCM_GPIO_GPFSEL_FSEL_MASK(pin); + uint32_t setbits = BCM_GPIO_GPFSEL_FSEL(pin, mode); + + modifyreg32(regaddr, clrbits, setbits); +} + +/************************************************************************************ + * Function: bcm_gpio_pudclk + * + * Description: + * Clocks the value written into the pud to the GPIO pin. + * + ************************************************************************************/ + +static void bcm_gpio_pudclk(unsigned int pin, bool enable) +{ + uintptr_t regaddr = BCM_GPIO_GPPUDCLK(pin); + uint32_t mask = BCM_GPIO_GPPUD_PUDCLK_MASK(pin); + + if (enable) + { + modifyreg32(regaddr, 0, mask); + } + else + { + modifyreg32(regaddr, mask, 0); + } +} + +/************************************************************************************ + * Function: bcm_gpio_configpud + * + * Description: + * "The GPIO Pull-up/down Clock Registers control the actuation of internal + * pull-downs on the respective GPIO pins. These registers must be used in + * conjunction with the GPPUD register to effect GPIO Pull-up/down changes. The + * following sequence of events is required: + * + * "1. Write to GPPUD to set the required control signal (i.e. Pull-up or Pull- + * Down or neither to remove the current Pull-up/down) + * "2. Wait 150 cycles – this provides the required set-up time for the control + * signal + * "3. Write to GPPUDCLK0/1 to clock the control signal into the GPIO pads you + * wish to modify – NOTE only the pads which receive a clock will be modified, + * all others will retain their previous state. + * "4. Wait 150 cycles – this provides the required hold time for the control + * signal + * "5. Write to GPPUD to remove the control signal + * "6. Write to GPPUDCLK0/1 to remove the clock" + * + ************************************************************************************/ + +static void bcm_gpio_configpud(unsigned int pin, gpio_pinset_t pinset) +{ + uint32_t pud = (pinset & GPIO_PUD_MASK) >> GPIO_PUD_SHIFT; + + /* "1. Write to GPPUD to set the required control signal (i.e. Pull-up or Pull- + * Down or neither to remove the current Pull-up/down) + */ + + putreg32(pud, BCM_GPIO_GPPUD); + + /* "2. Wait 150 cycles – this provides the required set-up time for the control + * signal + */ + + up_udelay(10); + + /* "3. Write to GPPUDCLK0/1 to clock the control signal into the GPIO pads you + * wish to modify – NOTE only the pads which receive a clock will be modified, + * all others will retain their previous state. + */ + + bcm_gpio_pudclk(pin, true); + + /* "4. Wait 150 cycles – this provides the required hold time for the control + * signal + */ + + up_udelay(10); + + /* "5. Write to GPPUD to remove the control signal */ + + putreg32(BCM_GPIO_GPPUD_PUD_OFF, BCM_GPIO_GPPUD); + + /* "6. Write to GPPUDCLK0/1 to remove the clock" */ + + bcm_gpio_pudclk(pin, false); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -59,46 +170,89 @@ void bcm_gpio_initialize(void) { -#warning Missing logic + /* Nothing to be done */ } /************************************************************************************ - * Name: bcm_configgpio + * Name: bcm_gpio_config * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * ************************************************************************************/ -int bcm_configgpio(gpio_pinset_t cfgset) +int bcm_gpio_config(gpio_pinset_t pinset) { -#warning Missing logic - return -ENOSYS; + unsigned int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint8_t mode; + + /* First, force the pin into an innocuous input state */ + + bcm_gpio_fsel(pin, BCM_GPIO_GPFSEL_FSEL_INPUT); + +#ifdef CONFIG_BCM2708_GPIO_IRQ + /* Make sure that interrupts are disabled */ + + bcm_gpio_irqconfig(pinset & ~GPIO_INT_MASK); +#endif + + /* Configure the pin pull-ups or pull-downs */ + + bcm_gpio_configpud(pin, pinset); + + /* If the the pin is an output, set the correct output state */ + + mode = (pinset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT; + if (mode == BCM_GPIO_GPFSEL_FSEL_OUTPUT) + { + bool value = (pinset & GPIO_OUTPUT_MASK) != GPIO_OUTPUT_CLEAR; + bcm_gpio_write(pinset, value); + } + + /* Finally configure the correct mode */ + + bcm_gpio_fsel(pin, mode); + return OK; } /************************************************************************************ - * Name: bcm_gpiowrite + * Name: bcm_gpio_write * * Description: * Write one or zero to the selected GPIO pin * ************************************************************************************/ -void bcm_gpiowrite(gpio_pinset_t pinset, bool value) +void bcm_gpio_write(gpio_pinset_t pinset, bool value) { -#warning Missing logic + unsigned int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uintptr_t regaddr; + + if (value) + { + regaddr = BCM_GPIO_GPSET(pin); + } + else + { + regaddr = BCM_GPIO_GPCLR(pin); + } + + putreg32(BCM_GPIO_GPSET0_SET(pin), regaddr); } /************************************************************************************ - * Name: bcm_gpioread + * Name: bcm_gpio_read * * Description: * Read one or zero from the selected GPIO pin * ************************************************************************************/ -bool bcm_gpioread(gpio_pinset_t pinset) +bool bcm_gpio_read(gpio_pinset_t pinset) { -#warning Missing logic - return false; + unsigned int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uintptr_t regaddr = BCM_GPIO_GPLEV(pin); + uint32_t mask = BCM_GPIO_GPLEV0_LEV(pin); + + return (getreg32(regaddr) & mask) != 0; } diff --git a/arch/arm/src/bcm2708/bcm_gpio.h b/arch/arm/src/bcm2708/bcm_gpio.h index c73c7c85ecb..8e5e24728a0 100644 --- a/arch/arm/src/bcm2708/bcm_gpio.h +++ b/arch/arm/src/bcm2708/bcm_gpio.h @@ -50,7 +50,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* Bit-encoded input to bcm_configgpio() ********************************************/ +/* Bit-encoded input to bcm_gpio_config() ********************************************/ /* 32-bit Encoding: * @@ -76,6 +76,8 @@ /* These bits set the pull up/down configuration of the pin: * * .... .... .... .... PP.. .... .... .... + * + * NOTE: The shifted values match the values of the GPPUD egister. */ #define GPIO_PUD_SHIFT (14) /* Bits 14-16: GPIO configuration bits */ @@ -109,8 +111,9 @@ * .... .... .... .... .... .... V... .... */ -#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Initial value of output */ -#define GPIO_OUTPUT_CLEAR (0) +#define GPIO_OUTPUT_MASK (1 << 7) /* Bit 7: Initial value of output */ +# define GPIO_OUTPUT_CLEAR (0) +# define GPIO_OUTPUT_SET (1 << 7) /* This identifies the GPIO pin: * @@ -229,37 +232,37 @@ void bcm_gpio_irqinitialize(void); #endif /************************************************************************************ - * Name: bcm_configgpio + * Name: bcm_gpio_config * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * ************************************************************************************/ -int bcm_configgpio(gpio_pinset_t cfgset); +int bcm_gpio_config(gpio_pinset_t pinset); /************************************************************************************ - * Name: bcm_gpiowrite + * Name: bcm_gpio_write * * Description: * Write one or zero to the selected GPIO pin * ************************************************************************************/ -void bcm_gpiowrite(gpio_pinset_t pinset, bool value); +void bcm_gpio_write(gpio_pinset_t pinset, bool value); /************************************************************************************ - * Name: bcm_gpioread + * Name: bcm_gpio_read * * Description: * Read one or zero from the selected GPIO pin * ************************************************************************************/ -bool bcm_gpioread(gpio_pinset_t pinset); +bool bcm_gpio_read(gpio_pinset_t pinset); /************************************************************************************ - * Name: bcm_gpioirq + * Name: bcm_gpio_irqconfig * * Description: * Configure an interrupt for the specified GPIO pin. @@ -267,13 +270,13 @@ bool bcm_gpioread(gpio_pinset_t pinset); ************************************************************************************/ #ifdef CONFIG_BCM2708_GPIO_IRQ -void bcm_gpioirq(gpio_pinset_t pinset); +void bcm_gpio_irqconfig(gpio_pinset_t pinset); #else -# define bcm_gpioirq(pinset) +# define bcm_gpio_irqconfig(pinset) #endif /************************************************************************************ - * Name: bcm_gpioirqenable + * Name: bcm_gpio_irqenable * * Description: * Enable the interrupt for specified GPIO IRQ @@ -281,13 +284,13 @@ void bcm_gpioirq(gpio_pinset_t pinset); ************************************************************************************/ #ifdef CONFIG_BCM2708_GPIO_IRQ -void bcm_gpioirqenable(int irq); +void bcm_gpio_irqenable(int irq); #else -# define bcm_gpioirqenable(irq) +# define bcm_gpio_irqenable(irq) #endif /************************************************************************************ - * Name: bcm_gpioirqdisable + * Name: bcm_gpio_irqdisable * * Description: * Disable the interrupt for specified GPIO IRQ @@ -295,9 +298,9 @@ void bcm_gpioirqenable(int irq); ************************************************************************************/ #ifdef CONFIG_BCM2708_GPIO_IRQ -void bcm_gpioirqdisable(int irq); +void bcm_gpio_irqdisable(int irq); #else -# define bcm_gpioirqdisable(irq) +# define bcm_gpio_irqdisable(irq) #endif #undef EXTERN diff --git a/arch/arm/src/bcm2708/bcm_gpioint.c b/arch/arm/src/bcm2708/bcm_gpioint.c index 055e7ab3691..9c25032de25 100644 --- a/arch/arm/src/bcm2708/bcm_gpioint.c +++ b/arch/arm/src/bcm2708/bcm_gpioint.c @@ -62,40 +62,40 @@ void bcm_gpio_irqinitialize(void) } /************************************************************************************ - * Name: bcm_gpioirq + * Name: bcm_gpio_irqconfig * * Description: * Configure an interrupt for the specified GPIO pin. * ************************************************************************************/ -void bcm_gpioirq(gpio_pinset_t pinset) +void bcm_gpio_irqconfig(gpio_pinset_t pinset) { #warning Missing Logic } /************************************************************************************ - * Name: bcm_gpioirqenable + * Name: bcm_gpio_irqenable * * Description: * Enable the interrupt for specified GPIO IRQ * ************************************************************************************/ -void bcm_gpioirqenable(int irq) +void bcm_gpio_irqenable(int irq) { #warning Missing Logic } /************************************************************************************ - * Name: bcm_gpioirqdisable + * Name: bcm_gpio_irqdisable * * Description: * Disable the interrupt for specified GPIO IRQ * ************************************************************************************/ -void bcm_gpioirqdisable(int irq) +void bcm_gpio_irqdisable(int irq) { #warning Missing Logic } diff --git a/arch/arm/src/bcm2708/chip/bcm2708_gpio.h b/arch/arm/src/bcm2708/chip/bcm2708_gpio.h index 74bdf0dbb72..d52df50e4d0 100644 --- a/arch/arm/src/bcm2708/chip/bcm2708_gpio.h +++ b/arch/arm/src/bcm2708/chip/bcm2708_gpio.h @@ -50,70 +50,109 @@ /* GPIO Register Offsets ************************************************************/ -#define BCM_GPIO_GPFSEL0_OFFSET 0x0000 /* GPIO Function Select 0 */ -#define BCM_GPIO_GPFSEL1_OFFSET 0x0004 /* GPIO Function Select 1 */ -#define BCM_GPIO_GPFSEL2_OFFSET 0x0008 /* GPIO Function Select 2 */ -#define BCM_GPIO_GPFSEL3_OFFSET 0x000c /* GPIO Function Select 3 */ -#define BCM_GPIO_GPFSEL4_OFFSET 0x0010 /* GPIO Function Select 4 */ -#define BCM_GPIO_GPFSEL5_OFFSET 0x0014 /* GPIO Function Select 5 */ -#define BCM_GPIO_GPSET0_OFFSET 0x001c /* GPIO Pin Output Set 0 */ -#define BCM_GPIO_GPSET1_OFFSET 0x0020 /* GPIO Pin Output Set 1 */ -#define BCM_GPIO_GPCLR0_OFFSET 0x0028 /* GPIO Pin Output Clear 0 */ -#define BCM_GPIO_GPCLR1_OFFSET 0x002c /* GPIO Pin Output Clear 1 */ -#define BCM_GPIO_GPLEV0_OFFSET 0x0034 /* GPIO Pin Level 0 */ -#define BCM_GPIO_GPLEV1_OFFSET 0x0038 /* GPIO Pin Level 1 */ -#define BCM_GPIO_GPEDS0_OFFSET 0x0040 /* GPIO Pin Event Detect Status 0 */ -#define BCM_GPIO_GPEDS1_OFFSET 0x0044 /* GPIO Pin Event Detect Status 1 */ -#define BCM_GPIO_GPREN0_OFFSET 0x004c /* GPIO Pin Rising Edge Detect Enable 0 */ -#define BCM_GPIO_GPREN1_OFFSET 0x0050 /* GPIO Pin Rising Edge Detect Enable 1 */ -#define BCM_GPIO_GPFEN0_OFFSET 0x0058 /* GPIO Pin Falling Edge Detect Enable 0 */ -#define BCM_GPIO_GPFEN1_OFFSET 0x005c /* GPIO Pin Falling Edge Detect Enable 1 */ -#define BCM_GPIO_GPHEN0_OFFSET 0x0064 /* GPIO Pin High Detect Enable 0 */ -#define BCM_GPIO_GPHEN1_OFFSET 0x0068 /* GPIO Pin High Detect Enable 1 */ -#define BCM_GPIO_GPLEN0_OFFSET 0x0070 /* GPIO Pin Low Detect Enable 0 */ -#define BCM_GPIO_GPLEN1_OFFSET 0x0074 /* GPIO Pin Low Detect Enable 1 */ -#define BCM_GPIO_GPAREN0_OFFSET 0x007c /* GPIO Pin Async. Rising Edge Detect 0 */ -#define BCM_GPIO_GPAREN1_OFFSET 0x0080 /* GPIO Pin Async. Rising Edge Detect 1 */ -#define BCM_GPIO_GPAFEN0_OFFSET 0x0088 /* GPIO Pin Async. Falling Edge Detect 0 */ -#define BCM_GPIO_GPAFEN1_OFFSET 0x008c /* GPIO Pin Async. Falling Edge Detect 1 */ +#define BCM_GPIO_GPFSEL_INDEX(n) ((n) / 10) +#define BCM_GPIO_GPFSEL_FIELD(n) ((n) % 10) + +#define BCM_GPIO_GPFSEL_OFFSET(n) (0x0000 + (BCM_GPIO_GPFSEL_INDEX(n) << 2)) +# define BCM_GPIO_GPFSEL0_OFFSET 0x0000 /* GPIO Function Select 0 */ +# define BCM_GPIO_GPFSEL1_OFFSET 0x0004 /* GPIO Function Select 1 */ +# define BCM_GPIO_GPFSEL2_OFFSET 0x0008 /* GPIO Function Select 2 */ +# define BCM_GPIO_GPFSEL3_OFFSET 0x000c /* GPIO Function Select 3 */ +# define BCM_GPIO_GPFSEL4_OFFSET 0x0010 /* GPIO Function Select 4 */ +# define BCM_GPIO_GPFSEL5_OFFSET 0x0014 /* GPIO Function Select 5 */ +#define BCM_GPIO_GPSET_OFFSET(n) (0x001c + (((n) >> 5) << 2)) +# define BCM_GPIO_GPSET0_OFFSET 0x001c /* GPIO Pin Output Set 0 */ +# define BCM_GPIO_GPSET1_OFFSET 0x0020 /* GPIO Pin Output Set 1 */ +#define BCM_GPIO_GPCLR_OFFSET(n) (0x0028 + (((n) >> 5) << 2)) +# define BCM_GPIO_GPCLR0_OFFSET 0x0028 /* GPIO Pin Output Clear 0 */ +# define BCM_GPIO_GPCLR1_OFFSET 0x002c /* GPIO Pin Output Clear 1 */ +#define BCM_GPIO_GPLEV_OFFSET(n) (0x0034 + (((n) >> 5) << 2)) +# define BCM_GPIO_GPLEV0_OFFSET 0x0034 /* GPIO Pin Level 0 */ +# define BCM_GPIO_GPLEV1_OFFSET 0x0038 /* GPIO Pin Level 1 */ +#define BCM_GPIO_GPEDS_OFFSET(n) (0x0040 + (((n) >> 5) << 2)) +# define BCM_GPIO_GPEDS0_OFFSET 0x0040 /* GPIO Pin Event Detect Status 0 */ +# define BCM_GPIO_GPEDS1_OFFSET 0x0044 /* GPIO Pin Event Detect Status 1 */ +#define BCM_GPIO_GPREN_OFFSET(n) (0x004c + (((n) >> 5) << 2)) +# define BCM_GPIO_GPREN0_OFFSET 0x004c /* GPIO Pin Rising Edge Detect Enable 0 */ +# define BCM_GPIO_GPREN1_OFFSET 0x0050 /* GPIO Pin Rising Edge Detect Enable 1 */ +#define BCM_GPIO_GPFEN_OFFSET(n) (0x0058 + (((n) >> 5) << 2)) +# define BCM_GPIO_GPFEN0_OFFSET 0x0058 /* GPIO Pin Falling Edge Detect Enable 0 */ +# define BCM_GPIO_GPFEN1_OFFSET 0x005c /* GPIO Pin Falling Edge Detect Enable 1 */ +#define BCM_GPIO_GPHEN_OFFSET(n) (0x0064 + (((n) >> 5) << 2)) +# define BCM_GPIO_GPHEN0_OFFSET 0x0064 /* GPIO Pin High Detect Enable 0 */ +# define BCM_GPIO_GPHEN1_OFFSET 0x0068 /* GPIO Pin High Detect Enable 1 */ +#define BCM_GPIO_GPLEN_OFFSET(n) (0x0070 + (((n) >> 5) << 2)) +# define BCM_GPIO_GPLEN0_OFFSET 0x0070 /* GPIO Pin Low Detect Enable 0 */ +# define BCM_GPIO_GPLEN1_OFFSET 0x0074 /* GPIO Pin Low Detect Enable 1 */ +#define BCM_GPIO_GPAREN_OFFSET(n) (0x007c + (((n) >> 5) << 2)) +# define BCM_GPIO_GPAREN0_OFFSET 0x007c /* GPIO Pin Async. Rising Edge Detect 0 */ +# define BCM_GPIO_GPAREN1_OFFSET 0x0080 /* GPIO Pin Async. Rising Edge Detect 1 */ +#define BCM_GPIO_GPAFEN_OFFSET(n) (0x0088 + (((n) >> 5) << 2)) +# define BCM_GPIO_GPAFEN0_OFFSET 0x0088 /* GPIO Pin Async. Falling Edge Detect 0 */ +# define BCM_GPIO_GPAFEN1_OFFSET 0x008c /* GPIO Pin Async. Falling Edge Detect 1 */ #define BCM_GPIO_GPPUD_OFFSET 0x0094 /* GPIO Pin Pull-up/down Enable */ -#define BCM_GPIO_GPPUDCLK0_OFFSET 0x0098 /* GPIO Pin Pull-up/down Enable Clock 0 */ -#define BCM_GPIO_GPPUDCLK1_OFFSET 0x009c /* GPIO Pin Pull-up/down Enable Clock 1 */ +#define BCM_GPIO_GPPUDCLK_OFFSET(n) (0x0098 + (((n) >> 5) << 2)) +# define BCM_GPIO_GPPUDCLK0_OFFSET 0x0098 /* GPIO Pin Pull-up/down Enable Clock 0 */ +# define BCM_GPIO_GPPUDCLK1_OFFSET 0x009c /* GPIO Pin Pull-up/down Enable Clock 1 */ /* GPIO Register Addresses **********************************************************/ -#define BCM_GPIO_GPFSEL0 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL0_OFFSET) -#define BCM_GPIO_GPFSEL1 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL1_OFFSET) -#define BCM_GPIO_GPFSEL2 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL2_OFFSET) -#define BCM_GPIO_GPFSEL3 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL3_OFFSET) -#define BCM_GPIO_GPFSEL4 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL4_OFFSET) -#define BCM_GPIO_GPFSEL5 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL5_OFFSET) -#define BCM_GPIO_GPSET0 (BCM_GPIO_VBASE+BCM_BCM_GPIO_GPSET0_OFFSET) -#define BCM_GPIO_GPSET1 (BCM_GPIO_VBASE+BCM_BCM_GPIO_GPSET1_OFFSET) -#define BCM_GPIO_GPCLR0 (BCM_GPIO_VBASE+BCM_GPIO_GPCLR0_OFFSET) -#define BCM_GPIO_GPCLR1 (BCM_GPIO_VBASE+BCM_GPIO_GPCLR1_OFFSET) -#define BCM_GPIO_GPLEV0 (BCM_GPIO_VBASE+BCM_GPIO_GPLEV0_OFFSET) -#define BCM_GPIO_GPLEV1 (BCM_GPIO_VBASE+BCM_GPIO_GPLEV1_OFFSET) -#define BCM_GPIO_GPEDS0 (BCM_GPIO_VBASE+BCM_GPIO_GPEDS0_OFFSET) -#define BCM_GPIO_GPEDS1 (BCM_GPIO_VBASE+BCM_GPIO_GPEDS1_OFFSET) -#define BCM_GPIO_GPREN0 (BCM_GPIO_VBASE+BCM_GPIO_GPREN0_OFFSET) -#define BCM_GPIO_GPREN1 (BCM_GPIO_VBASE+BCM_GPIO_GPREN1_OFFSET) -#define BCM_GPIO_GPFEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPFEN0_OFFSET) -#define BCM_GPIO_GPFEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPFEN1_OFFSET) -#define BCM_GPIO_GPHEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPHEN0_OFFSET) -#define BCM_GPIO_GPHEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPHEN1_OFFSET) -#define BCM_GPIO_GPLEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPLEN0_OFFSET) -#define BCM_GPIO_GPLEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPLEN1_OFFSET) -#define BCM_GPIO_GPAREN0 (BCM_GPIO_VBASE+BCM_GPIO_GPAREN0_OFFSET) -#define BCM_GPIO_GPAREN1 (BCM_GPIO_VBASE+BCM_GPIO_GPAREN1_OFFSET) -#define BCM_GPIO_GPAFEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN0_OFFSET) -#define BCM_GPIO_GPAFEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN1_OFFSET) +#define BCM_GPIO_GPFSEL(n) (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL_OFFSET(n)) +# define BCM_GPIO_GPFSEL0 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL0_OFFSET) +# define BCM_GPIO_GPFSEL1 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL1_OFFSET) +# define BCM_GPIO_GPFSEL2 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL2_OFFSET) +# define BCM_GPIO_GPFSEL3 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL3_OFFSET) +# define BCM_GPIO_GPFSEL4 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL4_OFFSET) +# define BCM_GPIO_GPFSEL5 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL5_OFFSET) +#define BCM_GPIO_GPSET(n) (BCM_GPIO_VBASE+BCM_GPIO_GPSET_OFFSET(n)) +# define BCM_GPIO_GPSET0 (BCM_GPIO_VBASE+BCM_BCM_GPIO_GPSET0_OFFSET) +# define BCM_GPIO_GPSET1 (BCM_GPIO_VBASE+BCM_BCM_GPIO_GPSET1_OFFSET) +#define BCM_GPIO_GPCLR(n) (BCM_GPIO_VBASE+BCM_GPIO_GPCLR_OFFSET(n)) +# define BCM_GPIO_GPCLR0 (BCM_GPIO_VBASE+BCM_GPIO_GPCLR0_OFFSET) +# define BCM_GPIO_GPCLR1 (BCM_GPIO_VBASE+BCM_GPIO_GPCLR1_OFFSET) +#define BCM_GPIO_GPLEV(n) (BCM_GPIO_VBASE+BCM_GPIO_GPLEV_OFFSET(n)) +# define BCM_GPIO_GPLEV0 (BCM_GPIO_VBASE+BCM_GPIO_GPLEV0_OFFSET) +# define BCM_GPIO_GPLEV1 (BCM_GPIO_VBASE+BCM_GPIO_GPLEV1_OFFSET) +#define BCM_GPIO_GPEDS(n) (BCM_GPIO_VBASE+BCM_GPIO_GPEDS_OFFSET(n)) +# define BCM_GPIO_GPEDS0 (BCM_GPIO_VBASE+BCM_GPIO_GPEDS0_OFFSET) +# define BCM_GPIO_GPEDS1 (BCM_GPIO_VBASE+BCM_GPIO_GPEDS1_OFFSET) +#define BCM_GPIO_GPREN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPREN_OFFSET(n)) +# define BCM_GPIO_GPREN0 (BCM_GPIO_VBASE+BCM_GPIO_GPREN0_OFFSET) +# define BCM_GPIO_GPREN1 (BCM_GPIO_VBASE+BCM_GPIO_GPREN1_OFFSET) +#define BCM_GPIO_GPFEN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPFEN_OFFSET(n)) +# define BCM_GPIO_GPFEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPFEN0_OFFSET) +# define BCM_GPIO_GPFEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPFEN1_OFFSET) +#define BCM_GPIO_GPHEN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPHEN_OFFSET(n)) +# define BCM_GPIO_GPHEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPHEN0_OFFSET) +# define BCM_GPIO_GPHEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPHEN1_OFFSET) +#define BCM_GPIO_GPLEN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPLEN_OFFSET(n)) +# define BCM_GPIO_GPLEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPLEN0_OFFSET) +# define BCM_GPIO_GPLEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPLEN1_OFFSET) +#define BCM_GPIO_GPAREN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPAREN_OFFSET(n)) +# define BCM_GPIO_GPAREN0 (BCM_GPIO_VBASE+BCM_GPIO_GPAREN0_OFFSET) +# define BCM_GPIO_GPAREN1 (BCM_GPIO_VBASE+BCM_GPIO_GPAREN1_OFFSET) +#define BCM_GPIO_GPAFEN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN_OFFSET(n)) +# define BCM_GPIO_GPAFEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN0_OFFSET) +# define BCM_GPIO_GPAFEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN1_OFFSET) #define BCM_GPIO_GPPUD (BCM_GPIO_VBASE+BCM_GPIO_GPPUD_OFFSET) -#define BCM_GPIO_GPPUDCLK0 (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK0_OFFSET) -#define BCM_GPIO_GPPUDCLK1 (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK1_OFFSET) +#define BCM_GPIO_GPPUDCLK(n) (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK_OFFSET(n)) +# define BCM_GPIO_GPPUDCLK0 (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK0_OFFSET) +# define BCM_GPIO_GPPUDCLK1 (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK1_OFFSET) /* GPIO Register Bit Definitions ****************************************************/ +#define BCM_GPIO_GPFSEL_FSEL_SHIFT(n) (3 * BCM_GPIO_GPFSEL_FIELD(n)) +#define BCM_GPIO_GPFSEL_FSEL_MASK(n) (7 << BCM_GPIO_GPFSEL_FSEL_SHIFT(n)) +# define BCM_GPIO_GPFSEL_FSEL(n,f) ((uint32_t)(f) << BCM_GPIO_GPFSEL_FSEL_SHIFT(n)) +# define BCM_GPIO_GPFSEL_FSEL_INPUT (0) +# define BCM_GPIO_GPFSEL_FSEL_OUTPUT (1) +# define BCM_GPIO_GPFSEL_FSEL_ALT0 (4) +# define BCM_GPIO_GPFSEL_FSEL_ALT1 (5) +# define BCM_GPIO_GPFSEL_FSEL_ALT2 (6) +# define BCM_GPIO_GPFSEL_FSEL_ALT3 (7) +# define BCM_GPIO_GPFSEL_FSEL_ALT4 (3) +# define BCM_GPIO_GPFSEL_FSEL_ALT5 (2) + #define BCM_GPIO_GPFSEL_FSELx0_SHIFT 0 #define BCM_GPIO_GPFSEL_FSELx0_MASK (7 << BCM_GPIO_GPFSEL_FSELx0_SHIFT) # define BCM_GPIO_GPFSEL_FSELx0_INPUT (0 << BCM_GPIO_GPFSEL_FSELx0_SHIFT) @@ -215,41 +254,25 @@ # define BCM_GPIO_GPFSEL_FSELx9_ALT4 (3 << BCM_GPIO_GPFSEL_FSELx9_SHIFT) # define BCM_GPIO_GPFSEL_FSELx9_ALT5 (2 << BCM_GPIO_GPFSEL_FSELx9_SHIFT) -#define BCM_GPIO_GPSET0_SET(n) (1 << n) /* Set GPIO pin n 0-31 */ -#define BCM_GPIO_GPSET1_SET(n) (1 << (n-32)) /* Set GPIO pin n 32-53 */ - -#define BCM_GPIO_GPCLR0_CLR(n) (1 << n) /* Clear GPIO pin n 0-31 */ -#define BCM_GPIO_GPCLR1_CLR(n) (1 << (n-32)) /* Clear GPIO pin n 32-53 */ - -#define BCM_GPIO_GPLEV0_LEV(n) (1 << n) /* Level of pin n 0-31 */ -#define BCM_GPIO_GPLEV1_LEV(n) (1 << (n-32)) /* Level of pin n 32-53 */ - -#define BCM_GPIO_GPEDS0_EDS(n) (1 << n) /* Event detected in pin n 0-31 */ -#define BCM_GPIO_GPEDS1_EDS(n) (1 << (n-32)) /* Event detected in pin n 32-53 */ - -#define BCM_GPIO_GPREN0_REN(n) (1 << n) /* Rising Edge Enable pin n 0-31 */ -#define BCM_GPIO_GPREN1_REN(n) (1 << (n-32)) /* Rising Edge Enable pin n 32-53 */ - -#define BCM_GPIO_GPFEN0_FEN(n) (1 << n) /* Falling Edge Enable pin n 0-31 */ -#define BCM_GPIO_GPFEN0_FEN(n) (1 << (n-32)) /* Falling Edge Enable pin n 32-53 */ - -#define BCM_GPIO_GPHEN0_HEN(n) (1 << n) /* High Detect Enable pin n 0-31 */ -#define BCM_GPIO_GPHEN1_HEN(n) (1 << (n-32)) /* High Detect Enable pin n 32-53 */ - -#define BCM_GPIO_GPLEN0_LEN(n) (1 << n) /* Low Detect Enable pin n 0-31 */ -#define BCM_GPIO_GPLEN1_LEN(n) (1 << (n-32)) /* Low Detect Enable pin n 32-53 */ - -#define BCM_GPIO_GPAREN0_AREN(n) (1 << n) /* Asynchronous Rising Edge Detect Enable n 0-31 */ -#define BCM_GPIO_GPAREN1_AREN(n) (1 << (n-32) /* Asynchronous Rising Edge Detect Enable n 32-53 */ - -#define BCM_GPIO_GPAFEN0_AFEN(n) (1 << n) /* Asynchronous Falling Edge Detect Enable n 0-31 */ -#define BCM_GPIO_GPAFEN1_AFEN(n) (1 << (n-32) /* Asynchronous Falling Edge Detect Enable n 32-53 */ +#define BCM_GPIO_GPSET0_SET(n) (1 << ((n) & 0x1f)) +#define BCM_GPIO_GPCLR0_CLR(n) (1 << ((n) & 0x1f)) +#define BCM_GPIO_GPLEV0_LEV(n) (1 << ((n) & 0x1f)) +#define BCM_GPIO_GPEDS0_EDS(n) (1 << ((n) & 0x1f)) +#define BCM_GPIO_GPREN0_REN(n) (1 << ((n) & 0x1f)) +#define BCM_GPIO_GPFEN0_FEN(n) (1 << ((n) & 0x1f)) +#define BCM_GPIO_GPHEN0_HEN(n) (1 << ((n) & 0x1f)) +#define BCM_GPIO_GPLEN0_LEN(n) (1 << ((n) & 0x1f)) +#define BCM_GPIO_GPAREN0_AREN(n) (1 << ((n) & 0x1f)) +#define BCM_GPIO_GPAFEN0_AFEN(n) (1 << ((n) & 0x1f)) #define BCM_GPIO_GPPUD_PUD_SHIFT 0 /* bit 0-1: Pull-up/down register */ #define BCM_GPIO_GPPUD_PUD_MASK (3 << BCM_GPIO_GPPUD_PUD_SHIFT) -#define BCM_GPIO_GPPUD_PUD_OFF (0 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Disable Pull-up/down */ -#define BCM_GPIO_GPPUD_PUD_PD (1 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Enable Pull-down */ -#define BCM_GPIO_GPPUD_PUD_PU (2 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Enable Pull-up */ +# define BCM_GPIO_GPPUD_PUD_OFF (0 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Disable Pull-up/down */ +# define BCM_GPIO_GPPUD_PUD_PD (1 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Enable Pull-down */ +# define BCM_GPIO_GPPUD_PUD_PU (2 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Enable Pull-up */ + +#define BCM_GPIO_GPPUD_PUDCLK_SHIFT(n) ((n) & 0x1f) +# define BCM_GPIO_GPPUD_PUDCLK_MASK(n) (1 << BCM_GPIO_GPPUD_PUDCLK_SHIFT(n)) +# define BCM_GPIO_GPPUD_PUDCLK(n,v) ((uint32_t)(v) << BCM_GPIO_GPPUD_PUDCLK_SHIFT(n)) #endif /* __ARCH_ARM_SRC_BCM2708_CHIP_BCM2708_GPIO_H */ -