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SAMA5: Add HSMCI memory card driver support

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This commit is contained in:
Gregory Nutt 2013-08-05 16:21:24 -06:00
parent 8c88dcd0c7
commit 369bf26b20
15 changed files with 4208 additions and 82 deletions
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10
ChangeLog
View file

@ -5297,3 +5297,13 @@
SPI driver while testing the SAMA5 SPI driver: If CONFIG_SPI_OWNBUS
is not set, the driver will not configure the SPI mode correctly
(2013-8-5).
* configs/sama5d3x-ek/src/sam_at25.c: Move AT25 initialization logic
out of sam_nsh.c and into a separate file where it can be better
shared (2013-8-5).
* arch/arm/src/sama5/sam_hsmci.c, sam_hsmci.h, and chip.sam_hsmci.h:
Add register definitions and a driver for the (3) HSMCI memory card
interfaces provided by the SAMA5. Leveraged from the SAM3/4 and
untested on initial commit (2013-8-5).
* nuttx/configs/sama5d3x-ek/src/sam_hsmci.c and sam_nsh.c: Add support
for the (2) SD card slots provided on the SAMA5D3x-EK boards.
Untested on initial commit (2013-8-5).

8
Documentation/NuttX.html
View file

@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: July 31, 2013</p>
<p>Last Updated: August 5, 2013</p>
</td>
</tr>
</table>
@ -1992,12 +1992,14 @@
<ul>
<p>
<b>STATUS</b>.
Initial support for the NUC120 was released in NuttX-6.29.
Initial support for the SAMA5D3x-EK was released in NuttX-6.29.
This initial support is very minimal:
There are simple test configurations that run out of internal SRAM and two configurations that run out of the on-boar NOR FLASH:
(1) An OS test configuration that verifies the correct port of NuttX to the part and
(2) a NuttShell (<a href="NuttShell.html">NSH</a>) configuration that might be the basis for further application development.
As of this writing, more device drivers are needed to make this a more complete port.
Develop continues.
Drivers for DMA, SPI, AT25 Serial Flash, and HSMCI memory cards included in NuttX-6.30.
More device drivers are needed to make this a more complete port, particularly USB and networking.
Refer to the NuttX board <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/sama5d3x-ek/README.txt">README</a> file for further information.
</p>
<b>Development Environments:</b>

37
arch/arm/src/sama5/Kconfig
View file

@ -96,14 +96,17 @@ config SAMA5_TWI2
config SAMA5_HSMCI0
bool "High Speed Multimedia Card Interface 0 (HSMCI0)"
default n
select ARCH_HAVE_SDIO
config SAMA5_HSMCI1
bool "High Speed Multimedia Card Interface 1 (HSMCI1)"
default n
select ARCH_HAVE_SDIO
config SAMA5_HSMCI2
bool "High Speed Multimedia Card Interface 2 (HSMCI2)"
default n
select ARCH_HAVE_SDIO
config SAMA5_SPI0
bool "Serial Peripheral Interface 0 (SPI0)"
@ -238,16 +241,48 @@ config PIOE_IRQ
endif # PIO_IRQ
if SAMA5_SPI0 || SAMA5_SPI1
menu "SPI device driver options"
config SAMA5_SPI_REGDEBUG
bool "SPI Register level debug"
depends on (SAMA5_SPI0 || SAMA5_SPI1) && DEBUG
depends on DEBUG
default n
---help---
Output detailed register-level SPI device debug information. Requires also DEBUG.
endmenu # SPI device driver options
endif # SAMA5_SPI0 || SAMA5_SPI1
if SAMA5_HSMCI0 || SAMA5_HSMCI1 || SAMA5_HSMCI2
menu "HSMCI device driver options"
config SAMA5_HSMCI_RDPROOF
bool "Read Proof Enable"
default n
---help---
Enabling Read Proof allows to stop the HSMCI Clock during read
access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
config SAMA5_HSMCI_WRPROOF
bool " Write Proof Enable"
default n
---help---
Enabling Write Proof allows to stop the HSMCI Clock during write
access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
config SAMA5_HSMCI_REGDEBUG
bool "SPI Register level debug"
depends on DEBUG
default n
---help---
Output detailed register-level HSCMI device debug information. Requires also DEBUG.
endmenu # HSMCI device driver options
endif # SAMA5_HSMCI0 || SAMA5_HSMCI1 || SAMA5_HSMCI2
menu "External Memory Configuration"

13
arch/arm/src/sama5/Make.defs
View file

@ -99,7 +99,6 @@ CHIP_CSRCS += sam_dmac.c
else
ifeq ($(CONFIG_SAMA5_DMAC1),y)
CHIP_CSRCS += sam_dmac.c
else
endif
endif
@ -111,3 +110,15 @@ CHIP_CSRCS += sam_spi.c
else
endif
endif
ifeq ($(CONFIG_SAMA5_HSMCI0),y)
CHIP_CSRCS += sam_hsmci.c
else
ifeq ($(CONFIG_SAMA5_HSMCI1),y)
CHIP_CSRCS += sam_hsmci.c
else
ifeq ($(CONFIG_SAMA5_HSMCI2),y)
CHIP_CSRCS += sam_hsmci.c
endif
endif
endif

364
arch/arm/src/sama5/chip/sam_hsmci.h Normal file
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@ -0,0 +1,364 @@
/****************************************************************************************
* arch/arm/src/sama5/chip/sam_hsmci.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMCI_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMCI_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* HSMCI register offsets ***************************************************************/
#define SAM_HSMCI_CR_OFFSET 0x0000 /* Control Register */
#define SAM_HSMCI_MR_OFFSET 0x0004 /* Mode Register */
#define SAM_HSMCI_DTOR_OFFSET 0x0008 /* Data Timeout Register */
#define SAM_HSMCI_SDCR_OFFSET 0x000c /* SD/SDIO Card Register */
#define SAM_HSMCI_ARGR_OFFSET 0x0010 /* Argument Register */
#define SAM_HSMCI_CMDR_OFFSET 0x0014 /* Command Register */
#define SAM_HSMCI_BLKR_OFFSET 0x0018 /* Block Register */
#define SAM_HSMCI_CSTOR_OFFSET 0x001c /* Completion Signal Timeout Register */
#define SAM_HSMCI_RSPR0_OFFSET 0x0020 /* Response Register 0 */
#define SAM_HSMCI_RSPR1_OFFSET 0x0024 /* Response Register 1 */
#define SAM_HSMCI_RSPR2_OFFSET 0x0028 /* Response Register 2 */
#define SAM_HSMCI_RSPR3_OFFSET 0x002c /* Response Register 3 */
#define SAM_HSMCI_RDR_OFFSET 0x0030 /* Receive Data Register */
#define SAM_HSMCI_TDR_OFFSET 0x0034 /* Transmit Data Register */
/* 0x0038-0x003c: Reserved */
#define SAM_HSMCI_SR_OFFSET 0x0040 /* Status Register */
#define SAM_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */
#define SAM_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */
#define SAM_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */
#define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */
#define SAM_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */
/* 0x0058-0x00e0: Reserved */
#define SAM_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */
#define SAM_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
/* 0x00ec-0x00fc: Reserved */
/* 0x0100-0x0124: Reserved for PCD registers */
#define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x05fc FIFO Memory Aperture */
/* HSMCI register adresses **************************************************************/
#define SAM_HSMCI0_CR (SAM_HSMCI0_VBASE+SAM_HSMCI_CR_OFFSET)
#define SAM_HSMCI0_MR (SAM_HSMCI0_VBASE+SAM_HSMCI_MR_OFFSET)
#define SAM_HSMCI0_DTOR (SAM_HSMCI0_VBASE+SAM_HSMCI_DTOR_OFFSET)
#define SAM_HSMCI0_SDCR (SAM_HSMCI0_VBASE+SAM_HSMCI_SDCR_OFFSET)
#define SAM_HSMCI0_ARGR (SAM_HSMCI0_VBASE+SAM_HSMCI_ARGR_OFFSET)
#define SAM_HSMCI0_CMDR (SAM_HSMCI0_VBASE+SAM_HSMCI_CMDR_OFFSET)
#define SAM_HSMCI0_BLKR (SAM_HSMCI0_VBASE+SAM_HSMCI_BLKR_OFFSET)
#define SAM_HSMCI0_CSTOR (SAM_HSMCI0_VBASE+SAM_HSMCI_CSTOR_OFFSET)
#define SAM_HSMCI0_RSPR0 (SAM_HSMCI0_VBASE+SAM_HSMCI_RSPR0_OFFSET)
#define SAM_HSMCI0_RSPR1 (SAM_HSMCI0_VBASE+SAM_HSMCI_RSPR1_OFFSET)
#define SAM_HSMCI0_RSPR2 (SAM_HSMCI0_VBASE+SAM_HSMCI_RSPR2_OFFSET)
#define SAM_HSMCI0_RSPR3 (SAM_HSMCI0_VBASE+SAM_HSMCI_RSPR3_OFFSET)
#define SAM_HSMCI0_RDR (SAM_HSMCI0_VBASE+SAM_HSMCI_RDR_OFFSET)
#define SAM_HSMCI0_TDR (SAM_HSMCI0_VBASE+SAM_HSMCI_TDR_OFFSET)
#define SAM_HSMCI0_SR (SAM_HSMCI0_VBASE+SAM_HSMCI_SR_OFFSET)
#define SAM_HSMCI0_IER (SAM_HSMCI0_VBASE+SAM_HSMCI_IER_OFFSET)
#define SAM_HSMCI0_IDR (SAM_HSMCI0_VBASE+SAM_HSMCI_IDR_OFFSET)
#define SAM_HSMCI0_IMR (SAM_HSMCI0_VBASE+SAM_HSMCI_IMR_OFFSET)
#define SAM_HSMCI0_DMA (SAM_HSMCI0_VBASE+SAM_HSMCI_DMA_OFFSET)
#define SAM_HSMCI0_CFG (SAM_HSMCI0_VBASE+SAM_HSMCI_CFG_OFFSET)
#define SAM_HSMCI0_WPMR (SAM_HSMCI0_VBASE+SAM_HSMCI_WPMR_OFFSET)
#define SAM_HSMCI0_WPSR (SAM_HSMCI0_VBASE+SAM_HSMCI_WPSR_OFFSET)
#define SAM_HSMCI0_FIFO (SAM_HSMCI0_VBASE+SAM_HSMCI_FIFO_OFFSET)
#define SAM_HSMCI1_CR (SAM_HSMCI1_VBASE+SAM_HSMCI_CR_OFFSET)
#define SAM_HSMCI1_MR (SAM_HSMCI1_VBASE+SAM_HSMCI_MR_OFFSET)
#define SAM_HSMCI1_DTOR (SAM_HSMCI1_VBASE+SAM_HSMCI_DTOR_OFFSET)
#define SAM_HSMCI1_SDCR (SAM_HSMCI1_VBASE+SAM_HSMCI_SDCR_OFFSET)
#define SAM_HSMCI1_ARGR (SAM_HSMCI1_VBASE+SAM_HSMCI_ARGR_OFFSET)
#define SAM_HSMCI1_CMDR (SAM_HSMCI1_VBASE+SAM_HSMCI_CMDR_OFFSET)
#define SAM_HSMCI1_BLKR (SAM_HSMCI1_VBASE+SAM_HSMCI_BLKR_OFFSET)
#define SAM_HSMCI1_CSTOR (SAM_HSMCI1_VBASE+SAM_HSMCI_CSTOR_OFFSET)
#define SAM_HSMCI1_RSPR0 (SAM_HSMCI1_VBASE+SAM_HSMCI_RSPR0_OFFSET)
#define SAM_HSMCI1_RSPR1 (SAM_HSMCI1_VBASE+SAM_HSMCI_RSPR1_OFFSET)
#define SAM_HSMCI1_RSPR2 (SAM_HSMCI1_VBASE+SAM_HSMCI_RSPR2_OFFSET)
#define SAM_HSMCI1_RSPR3 (SAM_HSMCI1_VBASE+SAM_HSMCI_RSPR3_OFFSET)
#define SAM_HSMCI1_RDR (SAM_HSMCI1_VBASE+SAM_HSMCI_RDR_OFFSET)
#define SAM_HSMCI1_TDR (SAM_HSMCI1_VBASE+SAM_HSMCI_TDR_OFFSET)
#define SAM_HSMCI1_SR (SAM_HSMCI1_VBASE+SAM_HSMCI_SR_OFFSET)
#define SAM_HSMCI1_IER (SAM_HSMCI1_VBASE+SAM_HSMCI_IER_OFFSET)
#define SAM_HSMCI1_IDR (SAM_HSMCI1_VBASE+SAM_HSMCI_IDR_OFFSET)
#define SAM_HSMCI1_IMR (SAM_HSMCI1_VBASE+SAM_HSMCI_IMR_OFFSET)
#define SAM_HSMCI1_DMA (SAM_HSMCI1_VBASE+SAM_HSMCI_DMA_OFFSET)
#define SAM_HSMCI1_CFG (SAM_HSMCI1_VBASE+SAM_HSMCI_CFG_OFFSET)
#define SAM_HSMCI1_WPMR (SAM_HSMCI1_VBASE+SAM_HSMCI_WPMR_OFFSET)
#define SAM_HSMCI1_WPSR (SAM_HSMCI1_VBASE+SAM_HSMCI_WPSR_OFFSET)
#define SAM_HSMCI1_FIFO (SAM_HSMCI1_VBASE+SAM_HSMCI_FIFO_OFFSET)
#define SAM_HSMCI2_CR (SAM_HSMCI2_VBASE+SAM_HSMCI_CR_OFFSET)
#define SAM_HSMCI2_MR (SAM_HSMCI2_VBASE+SAM_HSMCI_MR_OFFSET)
#define SAM_HSMCI2_DTOR (SAM_HSMCI2_VBASE+SAM_HSMCI_DTOR_OFFSET)
#define SAM_HSMCI2_SDCR (SAM_HSMCI2_VBASE+SAM_HSMCI_SDCR_OFFSET)
#define SAM_HSMCI2_ARGR (SAM_HSMCI2_VBASE+SAM_HSMCI_ARGR_OFFSET)
#define SAM_HSMCI2_CMDR (SAM_HSMCI2_VBASE+SAM_HSMCI_CMDR_OFFSET)
#define SAM_HSMCI2_BLKR (SAM_HSMCI2_VBASE+SAM_HSMCI_BLKR_OFFSET)
#define SAM_HSMCI2_CSTOR (SAM_HSMCI2_VBASE+SAM_HSMCI_CSTOR_OFFSET)
#define SAM_HSMCI2_RSPR0 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR0_OFFSET)
#define SAM_HSMCI2_RSPR1 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR1_OFFSET)
#define SAM_HSMCI2_RSPR2 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR2_OFFSET)
#define SAM_HSMCI2_RSPR3 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR3_OFFSET)
#define SAM_HSMCI2_RDR (SAM_HSMCI2_VBASE+SAM_HSMCI_RDR_OFFSET)
#define SAM_HSMCI2_TDR (SAM_HSMCI2_VBASE+SAM_HSMCI_TDR_OFFSET)
#define SAM_HSMCI2_SR (SAM_HSMCI2_VBASE+SAM_HSMCI_SR_OFFSET)
#define SAM_HSMCI2_IER (SAM_HSMCI2_VBASE+SAM_HSMCI_IER_OFFSET)
#define SAM_HSMCI2_IDR (SAM_HSMCI2_VBASE+SAM_HSMCI_IDR_OFFSET)
#define SAM_HSMCI2_IMR (SAM_HSMCI2_VBASE+SAM_HSMCI_IMR_OFFSET)
#define SAM_HSMCI2_DMA (SAM_HSMCI2_VBASE+SAM_HSMCI_DMA_OFFSET)
#define SAM_HSMCI2_CFG (SAM_HSMCI2_VBASE+SAM_HSMCI_CFG_OFFSET)
#define SAM_HSMCI2_WPMR (SAM_HSMCI2_VBASE+SAM_HSMCI_WPMR_OFFSET)
#define SAM_HSMCI2_WPSR (SAM_HSMCI2_VBASE+SAM_HSMCI_WPSR_OFFSET)
#define SAM_HSMCI2_FIFO (SAM_HSMCI2_VBASE+SAM_HSMCI_FIFO_OFFSET)
/* HSMCI register bit definitions *******************************************************/
/* HSMCI Control Register */
#define HSMCI_CR_MCIEN (1 << 0) /* Bit 0: Multi-Media Interface Enable */
#define HSMCI_CR_MCIDIS (1 << 1) /* Bit 1: Multi-Media Interface Disable */
#define HSMCI_CR_PWSEN (1 << 2) /* Bit 2: Power Save Mode Enable */
#define HSMCI_CR_PWSDIS (1 << 3) /* Bit 3: Power Save Mode Disable */
#define HSMCI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */
/* HSMCI Mode Register */
#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */
#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT)
#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */
#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT)
# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT)
#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */
#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */
#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */
#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */
#define HSMCI_MR_CLKODD (1 << 15) /* Bit 15: Clock divider is odd */
/* HSMCI Data Timeout Register */
#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */
#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT)
# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT)
#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */
#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_1 (0 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_16 (1 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_128 (2 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_256 (3 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_1024 (4 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_4096 (5 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_65536 (6 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_1048576 (7 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_MAX (7 << HSMCI_DTOR_DTOMUL_SHIFT)
/* HSMCI SDCard/SDIO Register */
#define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */
#define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT) /* Slot A is selected */
# define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */
# define HSMCI_SDCR_SDCSEL_SLOTB (1 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */
# define HSMCI_SDCR_SDCSEL_SLOTC (2 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */
# define HSMCI_SDCR_SDCSEL_SLOTD (3 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */
#define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */
#define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT)
# define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT)
# define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT)
# define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT)
/* HSMCI Argument Register (32-bit value) */
/* HSMCI Command Register */
#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */
#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT)
#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */
#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT)
# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */
# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */
# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */
# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */
#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */
#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT)
# define HSMCI_CMDR_SPCMD_STD (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */
# define HSMCI_CMDR_SPCMD_INIT (1 << HSMCI_CMDR_SPCMD_SHIFT) /* Initialization CMD */
# define HSMCI_CMDR_SPCMD_SYNC (2 << HSMCI_CMDR_SPCMD_SHIFT) /* Synchronized CMD */
# define HSMCI_CMDR_SPCMD_CEATAC (3 << HSMCI_CMDR_SPCMD_SHIFT) /* CE-ATA Completion Signal disable CMD */
# define HSMCI_CMDR_SPCMD_ITCMD (4 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt command */
# define HSMCI_CMDR_SPCMD_ITRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */
# define HSMCI_CMDR_SPCMD_BOR (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */
# define HSMCI_CMDR_SPCMD_EBO (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */
#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */
#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */
#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */
#define HSMCI_CMDR_TRCMD_MASK (3 << HSMCI_CMDR_TRCMD_SHIFT)
# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */
# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */
# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */
#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */
# define HSMCI_CMDR_TRDIR_WRITE (0 << 18)
# define HSMCI_CMDR_TRDIR_READ (1 << 18)
#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */
#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT)
# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */
# define HSMCI_CMDR_TRTYP_MULTIPLE (1 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Multiple Block */
# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */
# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */
# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */
#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */
#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT)
# define HSMCI_CMDR_IOSPCMD_STD (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */
# define HSMCI_CMDR_IOSPCMD_SUSPEND (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */
# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */
#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */
#define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */
/* HSMCI Block Register */
#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */
#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT)
#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT)
/* HSMCI Completion Signal Timeout Register */
#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */
#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT)
#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */
#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_16 (1 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_128 (2 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_256 (3 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_1024 (4 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_4096 (5 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
/* HSMCI Response Registers (32-bit data) */
/* HSMCI Receive Data Registers (32-bit data) */
/* HSMCI Transmit Data Registers (32-bit data) */
/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable
* Register, and HSMCI Interrupt Mask Register common bit-field definitions
*/
#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */
#define HSMCI_INT_RXRDY (1 << 1) /* Bit 1: Receiver Ready */
#define HSMCI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Ready */
#define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */
#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */
#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */
#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */
#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */
#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */
#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */
#define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */
#define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */
#define HSMCI_INT_RENDE (1 << 19) /* Bit 19: Response End Bit Error */
#define HSMCI_INT_RTOE (1 << 20) /* Bit 20: Response Time-out */
#define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */
#define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */
#define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */
#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */
#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */
#define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */
#define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */
#define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */
#define HSMCI_INT_ACKRCVE (1 << 29) /* Bit 29: Boot Operation Acknowledge Error */
#define HSMCI_INT_OVRE (1 << 30) /* Bit 30: Overrun */
#define HSMCI_INT_UNRE (1 << 31) /* Bit 31: Underrun */
/* HSMCI DMA Configuration Register */
#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */
#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT)
#define HSMCI_DMA_CHKSIZE_SHIFT (4) /* Bits 4-6: DMA Channel Read and Write Chunk Size */
# define HSMCI_DMA_CHKSIZE_1 (0 << HSMCI_DMA_CHKSIZE_SHIFT) /* 1 data available */
# define HSMCI_DMA_CHKSIZE_4 (1 << HSMCI_DMA_CHKSIZE_SHIFT) /* 4 data available */
# define HSMCI_DMA_CHKSIZE_8 (2 << HSMCI_DMA_CHKSIZE_SHIFT) /* 8 data available */
# define HSMCI_DMA_CHKSIZE_16 (3 << HSMCI_DMA_CHKSIZE_SHIFT) /* 16 data available */
# define HSMCI_DMA_CHKSIZE_32 (4 << HSMCI_DMA_CHKSIZE_SHIFT) /* 32 data available */
#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */
#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */
/* HSMCI Configuration Register */
#define HSMCI_CFG_FIFOMODE (1 << 0) /* Bit 0: HSMCI Internal FIFO control mode */
#define HSMCI_CFG_FERRCTRL (1 << 4) /* Bit 4: Flow Error flag reset control mode */
#define HSMCI_CFG_HSMODE (1 << 8) /* Bit 8: High Speed Mode */
#define HSMCI_CFG_LSYNC (1 << 12) /* Bit 12: Synchronize on the last block */
/* HSMCI Write Protect Mode Register */
#define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */
#define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */
#define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT)
# define HSMCI_WPMR_WP_KEY (0x004d4349 << HSMCI_WPMR_WP_KEY_SHIFT)
/* HSMCI Write Protect Status Register */
#define HSMCI_WPSR_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
#define HSMCI_WPSR_VS_MASK (15 << HSMCI_WPSR_VS_SHIFT)
# define HSMCI_WPSR_VS_NONE (0 << HSMCI_WPSR_VS_SHIFT)
# define HSMCI_WPSR_VS_WRITE (1 << HSMCI_WPSR_VS_SHIFT)
# define HSMCI_WPSR_VS_RESET (2 << HSMCI_WPSR_VS_SHIFT)
# define HSMCI_WPSR_VS_BOTH (3 << HSMCI_WPSR_VS_SHIFT)
#define HSMCI_WPSR_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define HSMCI_WPSR_VSRC_MASK (0xffff << HSMCI_WPSR_VSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMCI_H */

27
arch/arm/src/sama5/sam_dmac.c
View file

@ -1535,7 +1535,7 @@ void weak_function up_dmainitialize(void)
*
****************************************************************************/
DMA_HANDLE sam_dmachannel(uint32_t chflags)
DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags)
{
struct sam_dmac_s *dmac;
struct sam_dmach_s *dmach;
@ -1543,21 +1543,26 @@ DMA_HANDLE sam_dmachannel(uint32_t chflags)
/* Pick the DMA controller */
if ((chflags & DMACH_FLAG_DMAC) == DMACH_FLAG_DMAC0)
{
#ifdef CONFIG_SAMA5_DMAC0
if (dmacno == 0)
{
dmac = &g_dmac0;
#else
return NULL;
#endif
}
else
{
#ifdef CONFIG_SAMA5_DMAC1
dmac = &g_dmac1;
#else
return NULL;
#endif
#ifdef CONFIG_SAMA5_DMAC0
if (dmacno == 1)
{
dmac = &g_dmac1;
}
else
#endif
{
fdbg("Bad DMAC number: %d\n", dmacno);
DEBUGPANIC();
return (DMA_HANDLE)NULL;
}
/* Search for an available DMA channel with at least the requested FIFO

41
arch/arm/src/sama5/sam_dmac.h
View file

@ -58,24 +58,19 @@
/* DMA ******************************************************************************/
/* Flags used to characterize the desired DMA channel. The naming convention is that
* one side is the peripheral and the other is memory (however, the interface could still
* be used if, for example, both sides were memory although the naming would be awkward)
/* Flags used to characterize the DMA channel. The naming convention is that one
* side is the peripheral and the other is memory (however, the interface could still
* be used if, for example, both sides were memory although the naming would be
* awkward)
*/
/* Select the DMA controller */
#define DMACH_FLAG_DMAC (1 << 0) /* 0=DMAC0, 1=DMAC1 */
# define DMACH_FLAG_DMAC0 (0) /* DMAC0 */
# define DMACH_FLAG_DMAC1 (1 << 0) /* DMAC1 */
/* Configurable properties of the channel */
#define DMACH_FLAG_BURST_LARGEST 0 /* Largest length AHB burst */
#define DMACH_FLAG_BURST_HALF 1 /* Half FIFO size */
#define DMACH_FLAG_BURST_SINGLE 2 /* Single AHB access */
#define DMACH_FLAG_FIFOCFG_SHIFT (1) /* Bits 1-2: FIFO configuration */
#define DMACH_FLAG_FIFOCFG_SHIFT (0) /* Bits 0-1: FIFO configuration */
#define DMACH_FLAG_FIFOCFG_MASK (3 << DMACH_FLAG_FIFOCFG_SHIFT)
# define DMACH_FLAG_FIFOCFG_LARGEST (DMACH_FLAG_BURST_LARGEST << DMACH_FLAG_FIFOCFG_SHIFT)
# define DMACH_FLAG_FIFOCFG_HALF (DMACH_FLAG_BURST_HALF << DMACH_FLAG_FIFOCFG_SHIFT)
@ -83,35 +78,35 @@
/* Peripheral endpoint characteristics */
#define DMACH_FLAG_PERIPHPID_SHIFT (3) /* Bits 3-6: Peripheral PID */
#define DMACH_FLAG_PERIPHPID_SHIFT (2) /* Bits 2-5: Peripheral PID */
#define DMACH_FLAG_PERIPHPID_MASK (15 << DMACH_FLAG_PERIPHPID_SHIFT)
#define DMACH_FLAG_PERIPHH2SEL (1 << 7) /* Bits 7: HW handshaking */
#define DMACH_FLAG_PERIPHISPERIPH (1 << 8) /* Bits 8: 0=memory; 1=peripheral */
#define DMACH_FLAG_PERIPHWIDTH_SHIFT (9) /* Bits 9-10: Peripheral width */
#define DMACH_FLAG_PERIPHH2SEL (1 << 6) /* Bits 6: HW handshaking */
#define DMACH_FLAG_PERIPHISPERIPH (1 << 7) /* Bits 7: 0=memory; 1=peripheral */
#define DMACH_FLAG_PERIPHWIDTH_SHIFT (8) /* Bits 8-9: Peripheral width */
#define DMACH_FLAG_PERIPHWIDTH_MASK (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT)
# define DMACH_FLAG_PERIPHWIDTH_8BITS (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */
# define DMACH_FLAG_PERIPHWIDTH_16BITS (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */
# define DMACH_FLAG_PERIPHWIDTH_32BITS (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */
# define DMACH_FLAG_PERIPHWIDTH_64BITS (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 64 bits */
#define DMACH_FLAG_PERIPHINCREMENT (1 << 11) /* Bit 11: Autoincrement peripheral address */
#define DMACH_FLAG_PERIPHCHUNKSIZE (1 << 12) /* Bit 12: Peripheral chunk size */
#define DMACH_FLAG_PERIPHINCREMENT (1 << 10) /* Bit 10: Autoincrement peripheral address */
#define DMACH_FLAG_PERIPHCHUNKSIZE (1 << 11) /* Bit 11: Peripheral chunk size */
# define DMACH_FLAG_PERIPHCHUNKSIZE_1 (0) /* Peripheral chunksize = 1 */
# define DMACH_FLAG_PERIPHCHUNKSIZE_4 DMACH_FLAG_PERIPHCHUNKSIZE /* Peripheral chunksize = 4 */
/* Memory endpoint characteristics */
#define DMACH_FLAG_MEMPID_SHIFT (13) /* Bits 13-14: Memory PID */
#define DMACH_FLAG_MEMPID_SHIFT (12) /* Bits 12-15: Memory PID */
#define DMACH_FLAG_MEMPID_MASK (15 << DMACH_FLAG_PERIPHPID_SHIFT)
#define DMACH_FLAG_MEMH2SEL (1 << 15) /* Bits 15: HW handshaking */
#define DMACH_FLAG_MEMISPERIPH (1 << 16) /* Bits 16: 0=memory; 1=peripheral */
#define DMACH_FLAG_MEMWIDTH_SHIFT (17) /* Bits 17-18: Memory width */
#define DMACH_FLAG_MEMH2SEL (1 << 16) /* Bits 16: HW handshaking */
#define DMACH_FLAG_MEMISPERIPH (1 << 17) /* Bits 17: 0=memory; 1=peripheral */
#define DMACH_FLAG_MEMWIDTH_SHIFT (18) /* Bits 18-19: Memory width */
#define DMACH_FLAG_MEMWIDTH_MASK (3 << DMACH_FLAG_MEMWIDTH_SHIFT)
# define DMACH_FLAG_MEMWIDTH_8BITS (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */
# define DMACH_FLAG_MEMWIDTH_16BITS (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */
# define DMACH_FLAG_MEMWIDTH_32BITS (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */
# define DMACH_FLAG_MEMWIDTH_64BITS (3 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 64 bits */
#define DMACH_FLAG_MEMINCREMENT (1 << 19) /* Bit 19: Autoincrement memory address */
#define DMACH_FLAG_MEMCHUNKSIZE (1 << 20) /* Bit 20: Memory chunk size */
#define DMACH_FLAG_MEMINCREMENT (1 << 20) /* Bit 20: Autoincrement memory address */
#define DMACH_FLAG_MEMCHUNKSIZE (1 << 21) /* Bit 21: Memory chunk size */
# define DMACH_FLAG_MEMCHUNKSIZE_1 (0) /* Memory chunksize = 1 */
# define DMACH_FLAG_MEMCHUNKSIZE_4 DMACH_FLAG_MEMCHUNKSIZE /* Memory chunksize = 4 */
@ -196,7 +191,7 @@ extern "C"
*
****************************************************************************/
DMA_HANDLE sam_dmachannel(uint32_t dmach_flags);
DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t dmach_flags);
/****************************************************************************
* Name: sam_dmafree

2918
arch/arm/src/sama5/sam_hsmci.c Normal file
View file

File diff suppressed because it is too large Load diff

143
arch/arm/src/sama5/sam_hsmci.h Normal file
View file

@ -0,0 +1,143 @@
/************************************************************************************
* arch/arm/src/sama5/sam_hsmci.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_HSMCI_H
#define __ARCH_ARM_SRC_SAMA5_SAM_HSMCI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip.h"
/************************************************************************************
* Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/****************************************************************************
* Name: sdio_initialize
*
* Description:
* Initialize SDIO for operation.
*
* Input Parameters:
* slotno - Not used.
*
* Returned Values:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
struct sdio_dev_s; /* See include/nuttx/sdio.h */
FAR struct sdio_dev_s *sdio_initialize(int slotno);
/****************************************************************************
* Name: sdio_mediachange
*
* Description:
* Called by board-specific logic -- posssible from an interrupt handler --
* in order to signal to the driver that a card has been inserted or
* removed from the slot
*
* Input Parameters:
* dev - An instance of the SDIO driver device state structure.
* cardinslot - true is a card has been detected in the slot; false if a
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
* Returned Values:
* None
*
****************************************************************************/
void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
/****************************************************************************
* Name: sdio_wrprotect
*
* Description:
* Called by board-specific logic to report if the card in the slot is
* mechanically write protected.
*
* Input Parameters:
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
* Returned Values:
* None
*
****************************************************************************/
void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_HSMCI_H */

62
configs/sama5d3x-ek/README.txt
View file

@ -74,6 +74,7 @@ Contents
- Buttons and LEDs
- Serial Consoles
- Serial FLASH
- HSMCI Card Slots
- SAMA5D3x-EK Configuration Options
- Configurations
@ -527,6 +528,42 @@ Serial FLASH
PD13; on the Ronetix schematic, JP11 seems only to bypass a resistor (may
not be populated?). I think closing JP1 is correct in either case.
HSMCI Card Slots
================
The SAMA5D3x-EK provides a two SD memory card slots: (1) a full size SD
card slot (J7 labeled MCI0), and (2) a microSD memory card slot (J6
labeled MCI1).
The full size SD card slot connects via HSMCI0. The card detect discrete
is available on PB17 (pulled high). The write protect descrete is tied to
ground (via PP6) and not available to software. The slot supports 8-bit
wide transfer mode, but the NuttX driver currently uses only the 4-bit
wide transfer mode
PD17 MCI0_CD
PD1 MCI0_DA0
PD2 MCI0_DA1
PD3 MCI0_DA2
PD4 MCI0_DA3
PD5 MCI0_DA4
PD6 MCI0_DA5
PD7 MCI0_DA6
PD8 MCI0_DA7
PD9 MCI0_CK
PD0 MCI0_CDA
The microSD connects vi HSMCI1. The card detect discrete is available on
PB18 (pulled high):
PD18 MCI1_CD
PB20 MCI1_DA0
PB21 MCI1_DA1
PB22 MCI1_DA2
PB23 MCI1_DA3
PB24 MCI1_CK
PB19 MCI1_CDA
SAMA5D3x-EK Configuration Options
=================================
@ -968,6 +1005,31 @@ Configurations
nsh> cat /mnt/sdcard/atest.txt
This is a test
9. Enabling HSMCI support. The SAMA5D3x-EK provides a two SD memory card
slots: (1) a full size SD card slot (J7 labeled MCI0), and (2) a
microSD memory card slot (J6 labeled MCI1). The full size SD card
slot connects via HSMCI0; the microSD connects vi HSMCI1. Support
for both SD slots can be enabled with the following settings:
System Type->ATSAMA5 Peripheral Support
CONFIG_SAMA5_HSMCI0=y : Enable HSMCI0 support
CONFIG_SAMA5_HSMCI1=y : Enable HSMCI1 support
CONFIG_SAMA5_DMAC0=y : DMAC0 is needed by HSMCI0
CONFIG_SAMA5_DMAC1=y : DMAC1 is needed by HSMCI1
Device Drivers ->
CONFIG_MMCSD=y : Enable MMC/SD support
CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance
CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support
CONFIG_SDIO_DMA=y : Use SDIO DMA
CONFIG_SDIO_BLOCKSETUP=y : Needs to know block sizes
Library Routines
CONFIG_SCHED_WORKQUEUE=y : Driver needs work queue support
Application Configuration -> NSH Library
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
STATUS:
2013-7-19: This configuration (as do the others) run at 396MHz.
The SAMA5D3 can run at 536MHz. I still need to figure out the

12
configs/sama5d3x-ek/src/Makefile
View file

@ -66,6 +66,18 @@ ifeq ($(CONFIG_SAMA5_NOR_MAIN),y)
CSRCS += nor_main.c
endif
ifeq ($(CONFIG_MTD_AT25),y)
CSRCS += sam_at25.c
endif
ifeq ($(CONFIG_SAMA5_HSMCI0),y)
CSRCS += sam_hsmci.c
else
ifeq ($(CONFIG_SAMA5_HSMCI1),y)
CSRCS += sam_hsmci.c
endif
endif
ifeq ($(CONFIG_NSH_ARCHINIT),y)
CSRCS += sam_nsh.c
endif

166
configs/sama5d3x-ek/src/sam_at25.c Normal file
View file

@ -0,0 +1,166 @@
/****************************************************************************
* config/sama5d3x-ek/src/sam_at25.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/mount.h>
#include <stdbool.h>
#include <stdio.h>
#include <errno.h>
#include <debug.h>
#ifdef CONFIG_SAMA5_SPI0
# include <nuttx/spi/spi.h>
# include <nuttx/mtd.h>
# include <nuttx/fs/nxffs.h>
# include "sam_spi.h"
#endif
#include "sama5d3x-ek.h"
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Can't support the AT25 device if it SPI0 or AT25 support are not enabled */
#define HAVE_AT25 1
#if !defined(CONFIG_SAMA5_SPI0) || !defined(CONFIG_MTD_AT25)
# undef HAVE_AT25
#endif
/* Can't support AT25 features if mountpoints are disabled or if we were not
* asked to mount the AT25 part
*/
#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_SAMA5_AT25_AUTOMOUNT)
# undef HAVE_AT25
#endif
/* If we are going to mount the AT25, then they user must also have told
* us what to do with it by setting one of these.
*/
#if !defined(CONFIG_SAMA5_AT25_FTL) && !defined(CONFIG_SAMA5_AT25_NXFFS)
# undef HAVE_AT25
#endif
#if defined(CONFIG_SAMA5_AT25_FTL) && defined(CONFIG_SAMA5_AT25_NXFFS)
# warning Both CONFIG_SAMA5_AT25_FTL and CONFIG_SAMA5_AT25_NXFFS are set
# warning Ignoring CONFIG_SAMA5_AT25_NXFFS
# undef CONFIG_SAMA5_AT25_NXFFS
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_at25_initialize
*
* Description:
* Initialize and configure the AT25 SPI Flash
*
****************************************************************************/
#ifdef CONFIG_MTD_AT25
int sam_at25_initialize(int minor)
{
#ifdef HAVE_AT25
FAR struct spi_dev_s *spi;
FAR struct mtd_dev_s *mtd;
int ret;
/* Get the SPI port driver */
spi = up_spiinitialize(AT25_PORT);
if (!spi)
{
fdbg("ERROR: Failed to initialize SPI port %d\n", AT25_PORT);
return -ENODEV;
}
/* Now bind the SPI interface to the AT25 SPI FLASH driver */
mtd = at25_initialize(spi);
if (!mtd)
{
fdbg("ERROR: Failed to bind SPI port %d to the AT25 FLASH driver\n");
return -ENODEV;
}
#if defined(CONFIG_SAMA5_AT25_FTL)
/* And finally, use the FTL layer to wrap the MTD driver as a block driver */
ret = ftl_initialize(CONFIG_NSH_MMCSDMINOR, mtd);
if (ret < 0)
{
fdbg("ERROR: Initialize the FTL layer\n");
return ret;
}
#elif defined(CONFIG_SAMA5_AT25_NXFFS)
/* Initialize to provide NXFFS on the MTD interface */
ret = nxffs_initialize(mtd);
if (ret < 0)
{
fdbg("ERROR: NXFFS initialization failed: %d\n", -ret);
return ret;
}
/* Mount the file system at /mnt/at25 */
ret = mount(NULL, "/mnt/at25", "nxffs", 0, NULL);
if (ret < 0)
{
fdbg("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
return ret;
}
#endif
#endif
return OK;
}
#endif

296
configs/sama5d3x-ek/src/sam_hsmci.c Normal file
View file

@ -0,0 +1,296 @@
/****************************************************************************
* config/sama5d3x-ek/src/sam_hsmci.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The SAMA5D3x-EK provides a two SD memory card slots: (1) a full size SD card
* slot (J7 labeled MCI0), and (2) a microSD memory card slot (J6 labeled MCI1).
*
* The full size SD card slot connects via HSMCI0. The card detect discrete
* is available on PB17 (pulled high). The write protect descrete is tied to
* ground (via PP6) and not available to software. The slot supports 8-bit
* wide transfer mode, but the NuttX driver currently uses only the 4-bit
* wide transfer mode
*
* PD17 MCI0_CD
* PD1 MCI0_DA0
* PD2 MCI0_DA1
* PD3 MCI0_DA2
* PD4 MCI0_DA3
* PD5 MCI0_DA4
* PD6 MCI0_DA5
* PD7 MCI0_DA6
* PD8 MCI0_DA7
* PD9 MCI0_CK
* PD0 MCI0_CDA
*
* The microSD connects vi HSMCI1. The card detect discrete is available on
* PB18 (pulled high):
*
* PD18 MCI1_CD
* PB20 MCI1_DA0
* PB21 MCI1_DA1
* PB22 MCI1_DA2
* PB23 MCI1_DA3
* PB24 MCI1_CK
* PB19 MCI1_CDA
*/
/* SPI Chip Selects *****************************************************************/
/* Both the Ronetix and Embest versions of the SAMAD3x CPU modules include an
* Atmel AT25DF321A, 32-megabit, 2.7-volt SPI serial flash. The SPI
* connection is as follows:
*
* AT25DF321A SAMA5
* --------------- -----------------------------------------------
* SI PD11 SPI0_MOSI
* SO PD10 SPI0_MIS0
* SCK PD12 SPI0_SPCK
* /CS PD13 via NL17SZ126 if JP1 is closed (See below)
*
* JP1 and JP2 seem to related to /CS on the Ronetix board, but the usage is
* less clear. For the Embest module, JP1 must be closed to connect /CS to
* PD13; on the Ronetix schematic, JP11 seems only to bypass a resistor (may
* not be populated?). I think closing JP1 is correct in either case.
*/
#define GPIO_AT25_NPCS0 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \
GPIO_PORT_PIOD | GPIO_PIN13)
#define AT25_PORT SPI0_CS0
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/sdio.h>
#include <nuttx/mmcsd.h>
#include "sam_hsmci.h"
#include "sama5d3x-ek.h"
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* This needs to be extended. The card detect GPIO must be configured as an
* interrupt. When the interrupt indicating that a card has been inserted
* or removed is received, this function must call sio_mediachange() to
* handle that event.
*/
#warning "Card detect interrupt handling needed"
/* Configuration ************************************************************/
#define HAVE_MMCSD 1
/* Can't support MMC/SD if the card interface(s) are not enable */
#if !defined(CONFIG_SAMA5_HSMCI0) && !defined(CONFIG_SAMA5_HSMCI0)
# undef HAVE_MMCSD
#endif
/* Can't support MMC/SD features if mountpoints are disabled */
#if defined(CONFIG_DISABLE_MOUNTPOINT)
# undef HAVE_MMCSD
#endif
#ifdef HAVE_MMCSD
# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0
# undef CONFIG_NSH_MMCSDSLOTNO
# endif
# ifndef CONFIG_NSH_MMCSDMINOR
# define CONFIG_NSH_MMCSDMINOR 0
# endif
# ifndef CONFIG_NSH_MMCSDSLOTNO
# define CONFIG_NSH_MMCSDSLOTNO 0
# endif
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/************************************************************************************
* Name: sam_hsmci_gpioinit
*
* Description:
* Initialize HSMCI support. This function is called very early in board
* initialization.
*
************************************************************************************/
#ifdef HAVE_MMCSD
static void sam_hsmci_gpioinit(int slotno)
{
#ifdef CONFIG_SAMA5_HSMCI0
#ifdef CONFIG_SAMA5_HSMCI1
if (slotno == 0)
#endif
{
sam_configgpio(GPIO_MCI0_CD);
}
#ifdef CONFIG_SAMA5_HSMCI1
else
#endif
#endif
#ifdef CONFIG_SAMA5_HSMCI1
{
sam_configgpio(GPIO_MCI1_CD);
}
#endif
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_hsmci_initialize
*
* Description:
* Perform architecture specific initialization
*
****************************************************************************/
#if defined(CONFIG_SAMA5_HSMCI0) || defined(CONFIG_SAMA5_HSMCI1)
int sam_hsmci_initialize(int slotno, int minor)
{
#ifdef HAVE_MMCSD
FAR struct sdio_dev_s *sdio;
int ret;
/* Initialize card-detect and write-protect GPIOs */
sam_hsmci_gpioinit(slotno);
/* Mount the SDIO-based MMC/SD block driver */
/* First, get an instance of the SDIO interface */
sdio = sdio_initialize(slotno);
if (!sdio)
{
fdbg("Failed to initialize SDIO slot %d\n", slotno);
return -ENODEV;
}
/* Now bind the SDIO interface to the MMC/SD driver */
ret = mmcsd_slotinitialize(minor, sdio);
if (ret != OK)
{
fdbg("Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
return ret;
}
/* Then inform the HSMCI driver if there is or is not a card in the slot. */
sdio_mediachange(sdio, sam_cardinserted(slotno));
#endif
return OK;
}
/************************************************************************************
* Name: sam_cardinserted
*
* Description:
* Check if a card is inserted into the selected HSMCI slot
*
************************************************************************************/
#if defined(CONFIG_SAMA5_HSMCI0) || defined(CONFIG_SAMA5_HSMCI1)
bool sam_cardinserted(int slotno)
{
#ifdef HAVE_MMCSD
#ifdef CONFIG_SAMA5_HSMCI0
#ifdef CONFIG_SAMA5_HSMCI1
if (slotno == 0)
#endif /* CONFIG_SAMA5_HSMCI1 */
{
bool inserted = sam_gpioread(GPIO_MCI0_CD);
fvdbg("Slot 0 inserted: %s\n", inserted ? "NO" : "YES");
return !inserted;
}
#ifdef CONFIG_SAMA5_HSMCI1
else
#endif /* CONFIG_SAMA5_HSMCI1 */
#endif /* CONFIG_SAMA5_HSMCI0 */
#ifdef CONFIG_SAMA5_HSMCI1
{
bool inserted = sam_gpioread(GPIO_MCI1_CD);
fvdbg("Slot 1 inserted: %s\n", inserted ? "NO" : "YES");
return !inserted;
}
#endif /* CONFIG_SAMA5_HSMCI1 */
#else /* HAVE_MMCSD */
return false;
#endif /* HAVE_MMCSD */
}
#endif /* CONFIG_SAMA5_HSMCIO || CONFIG_SAMA5_HSMCI1 */
/************************************************************************************
* Name: sam_writeprotected
*
* Description:
* Check if a card is inserted into the selected HSMCI slot
*
************************************************************************************/
#if defined(CONFIG_SAMA5_HSMCI0) || defined(CONFIG_SAMA5_HSMCI1)
bool sam_writeprotected(int slotno)
{
/* There are no write protect pins */
return false;
}
#endif
#endif /* CONFIG_SAMA5_HSMCI0 || CONFIG_SAMA5_HSMCI1 */

102
configs/sama5d3x-ek/src/sam_nsh.c
View file

@ -61,9 +61,12 @@
****************************************************************************/
/* Configuration ************************************************************/
/* Can't support the AT25 device if it SPI0 or AT25 support are not enabled */
#define HAVE_AT25 1
#define HAVE_MMCSD 1
/* Can't support the AT25 device if it SPI0 or AT25 support are not enabled */
#if !defined(CONFIG_SAMA5_SPI0) || !defined(CONFIG_MTD_AT25)
# undef HAVE_AT25
#endif
@ -84,18 +87,50 @@
# undef HAVE_AT25
#endif
#if defined(CONFIG_SAMA5_AT25_FTL) && defined(CONFIG_SAMA5_AT25_NXFFS)
# warning Both CONFIG_SAMA5_AT25_FTL and CONFIG_SAMA5_AT25_NXFFS are set
# warning Ignoring CONFIG_SAMA5_AT25_NXFFS
# undef CONFIG_SAMA5_AT25_NXFFS
#endif
/* Use minor device number 0 is not is provided */
#ifndef CONFIG_NSH_MMCSDMINOR
# define CONFIG_NSH_MMCSDMINOR 0
#endif
/* Can't support MMC/SD if the card interface(s) are not enable */
#if !defined(CONFIG_SAMA5_HSMCI0) && !defined(CONFIG_SAMA5_HSMCI0)
# undef HAVE_MMCSD
#endif
/* Can't support MMC/SD features if mountpoints are disabled */
#if defined(CONFIG_DISABLE_MOUNTPOINT)
# undef HAVE_MMCSD
#endif
/* Assign minor device numbers. We basically ignore more of the NSH
* configuration here (NSH SLOTNO ignored completely; NSH minor extended
* to handle more devices.
*/
#ifndef CONFIG_NSH_MMCSDMINOR
# define CONFIG_NSH_MMCSDMINOR 0
#endif
#ifdef HAVE_MMCSD
# define HSMCI0_SLOTNO 0
# define HSMCI1_SLOTNO 1
# ifdef CONFIG_SAMA5_HSMCI0
# define HSMCI0_MINOR CONFIG_NSH_MMCSDMINOR
# define HSMCI1_MINOR (CONFIG_NSH_MMCSDMINOR+1)
# define AT25_MINOR (CONFIG_NSH_MMCSDMINOR+2)
# else
# define HSMCI1_MINOR CONFIG_NSH_MMCSDMINOR
# define AT25_MINOR (CONFIG_NSH_MMCSDMINOR+1)
# endif
#else
# define AT25_MINOR CONFIG_NSH_MMCSDMINOR
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -110,58 +145,39 @@
int nsh_archinitialize(void)
{
#ifdef HAVE_AT25
FAR struct spi_dev_s *spi;
FAR struct mtd_dev_s *mtd;
#if defined(HAVE_AT25) || defined(HAVE_MMCSD)
int ret;
#endif
/* Get the SPI port driver */
/* Initialize the AT25 driver */
spi = up_spiinitialize(AT25_PORT);
if (!spi)
{
fdbg("ERROR: Failed to initialize SPI port %d\n", AT25_PORT);
return -ENODEV;
}
/* Now bind the SPI interface to the AT25 SPI FLASH driver */
mtd = at25_initialize(spi);
if (!mtd)
{
fdbg("ERROR: Failed to bind SPI port %d to the AT25 FLASH driver\n");
return -ENODEV;
}
#if defined(CONFIG_SAMA5_AT25_FTL)
/* And finally, use the FTL layer to wrap the MTD driver as a block driver */
ret = ftl_initialize(CONFIG_NSH_MMCSDMINOR, mtd);
#ifdef HAVE_AT25
ret = sam_at25_initialize(AT25_MINOR);
if (ret < 0)
{
fdbg("ERROR: Initialize the FTL layer\n");
fdbg("ERROR: sam_at25_initialize failed: %d\n", ret);
return ret;
}
#endif
#elif defined(CONFIG_SAMA5_AT25_NXFFS)
/* Initialize to provide NXFFS on the MTD interface */
ret = nxffs_initialize(mtd);
#ifdef HAVE_MMCSD
#ifdef CONFIG_SAMA5_HSMCI0
ret = sam_hsmci_initialize(HSMCI0_SLOTNO, HSMCI0_MINOR);
if (ret < 0)
{
fdbg("ERROR: NXFFS initialization failed: %d\n", -ret);
fdbg("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
HSMCI0_SLOTNO, HSMCI0_MINOR, ret);
return ret;
}
#endif
/* Mount the file system at /mnt/at25 */
ret = mount(NULL, "/mnt/at25", "nxffs", 0, NULL);
#ifdef CONFIG_SAMA5_HSMCI0
ret = sam_hsmci_initialize(HSMCI1_SLOTNO, HSMCI1_MINOR);
if (ret < 0)
{
fdbg("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
fdbg("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
HSMCI1_SLOTNO, HSMCI1_MINOR, ret);
return ret;
}
#endif
#endif

91
configs/sama5d3x-ek/src/sama5d3x-ek.h
View file

@ -94,6 +94,49 @@
GPIO_INT_BOTHEDGES | GPIO_PORT_PIOE | GPIO_PIN27)
#define IRQ_USER1 SAM_IRQ_PE27
/* HSMCI Card Slots *****************************************************************/
/* The SAMA5D3x-EK provides a two SD memory card slots: (1) a full size SD card
* slot (J7 labeled MCI0), and (2) a microSD memory card slot (J6 labeled MCI1).
*
* The full size SD card slot connects via HSMCI0. The card detect discrete
* is available on PB17 (pulled high). The write protect descrete is tied to
* ground (via PP6) and not available to software. The slot supports 8-bit
* wide transfer mode, but the NuttX driver currently uses only the 4-bit
* wide transfer mode
*
* PD17 MCI0_CD
* PD1 MCI0_DA0
* PD2 MCI0_DA1
* PD3 MCI0_DA2
* PD4 MCI0_DA3
* PD5 MCI0_DA4
* PD6 MCI0_DA5
* PD7 MCI0_DA6
* PD8 MCI0_DA7
* PD9 MCI0_CK
* PD0 MCI0_CDA
*/
#define GPIO_MCI0_CD (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_CFG_DEGLITCH | \
GPIO_INT_BOTHEDGES | GPIO_PORT_PIOD | GPIO_PIN17)
#define IRQ_MCI0_CD SAM_IRQ_PD17
/* The microSD connects vi HSMCI1. The card detect discrete is available on
* PB18 (pulled high):
*
* PD18 MCI1_CD
* PB20 MCI1_DA0
* PB21 MCI1_DA1
* PB22 MCI1_DA2
* PB23 MCI1_DA3
* PB24 MCI1_CK
* PB19 MCI1_CDA
*/
#define GPIO_MCI1_CD (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_CFG_DEGLITCH | \
GPIO_INT_BOTHEDGES | GPIO_PORT_PIOD | GPIO_PIN18)
#define IRQ_MCI1_CD SAM_IRQ_PD18
/* SPI Chip Selects *****************************************************************/
/* Both the Ronetix and Embest versions of the SAMAD3x CPU modules include an
* Atmel AT25DF321A, 32-megabit, 2.7-volt SPI serial flash. The SPI
@ -178,6 +221,54 @@ void sam_sdram_config(void);
# define board_sdram_config(t)
#endif
/****************************************************************************
* Name: sam_at25_initialize
*
* Description:
* Initialize and configure the AT25 SPI Flash
*
****************************************************************************/
#ifdef CONFIG_MTD_AT25
int sam_at25_initialize(int minor);
#endif
/****************************************************************************
* Name: sam_hsmci_initialize
*
* Description:
* Initialize and configure one HSMCI slot
*
****************************************************************************/
#if defined(CONFIG_SAMA5_HSMCI0) || defined(CONFIG_SAMA5_HSMCI1)
int sam_hsmci_initialize(int slotno, int minor);
#endif
/************************************************************************************
* Name: sam_cardinserted
*
* Description:
* Check if a card is inserted into the selected HSMCI slot
*
************************************************************************************/
#if defined(CONFIG_SAMA5_HSMCI0) || defined(CONFIG_SAMA5_HSMCI1)
bool sam_cardinserted(int slotno);
#endif
/************************************************************************************
* Name: sam_writeprotected
*
* Description:
* Check if a card is inserted into the selected HSMCI slot
*
************************************************************************************/
#ifdef HAVE_MMCSD
bool sam_writeprotected(int slotno);
#endif
/************************************************************************************
* Name: up_ledinit
************************************************************************************/